src/gen6_vme.c

   1 /*
   2  * Copyright © 2010-2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Zhou Chang <chang.zhou@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <assert.h>
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_driver.h"
  36
  37 #include "i965_defines.h"
  38 #include "i965_drv_video.h"
  39 #include "i965_encoder.h"
  40 #include "gen6_vme.h"
  41
  42 #define SURFACE_STATE_PADDED_SIZE_0_GEN7        ALIGN(sizeof(struct gen7_surface_state), 32)
  43 #define SURFACE_STATE_PADDED_SIZE_1_GEN7        ALIGN(sizeof(struct gen7_surface_state2), 32)
  44 #define SURFACE_STATE_PADDED_SIZE_GEN7          MAX(SURFACE_STATE_PADDED_SIZE_0_GEN7, SURFACE_STATE_PADDED_SIZE_1_GEN7)
  45
  46 #define SURFACE_STATE_PADDED_SIZE_0_GEN6        ALIGN(sizeof(struct i965_surface_state), 32)
  47 #define SURFACE_STATE_PADDED_SIZE_1_GEN6        ALIGN(sizeof(struct i965_surface_state2), 32)
  48 #define SURFACE_STATE_PADDED_SIZE_GEN6          MAX(SURFACE_STATE_PADDED_SIZE_0_GEN6, SURFACE_STATE_PADDED_SIZE_1_GEN6)
  49
  50 #define SURFACE_STATE_PADDED_SIZE               MAX(SURFACE_STATE_PADDED_SIZE_GEN6, SURFACE_STATE_PADDED_SIZE_GEN7)
  51 #define SURFACE_STATE_OFFSET(index)             (SURFACE_STATE_PADDED_SIZE * index)
  52 #define BINDING_TABLE_OFFSET                    SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6)
  53
  54 #define VME_INTRA_SHADER        0
  55 #define VME_INTER_SHADER        1
  56 #define VME_BATCHBUFFER         2
  57
  58 #define CURBE_ALLOCATION_SIZE   37              /* in 256-bit */
  59 #define CURBE_TOTAL_DATA_LENGTH (4 * 32)        /* in byte, it should be less than or equal to CURBE_ALLOCATION_SIZE * 32 */
  60 #define CURBE_URB_ENTRY_LENGTH  4               /* in 256-bit, it should be less than or equal to CURBE_TOTAL_DATA_LENGTH / 32 */
  61
  62 static const uint32_t gen6_vme_intra_frame[][4] = {
  63 #include "shaders/vme/intra_frame.g6b"
  64 };
  65
  66 static const uint32_t gen6_vme_inter_frame[][4] = {
  67 #include "shaders/vme/inter_frame.g6b"
  68 };
  69
  70 static const uint32_t gen6_vme_batchbuffer[][4] = {
  71 #include "shaders/vme/batchbuffer.g6b"
  72 };
  73
  74 static struct i965_kernel gen6_vme_kernels[] = {
  75     {
  76         "VME Intra Frame",
  77         VME_INTRA_SHADER,                                                                               /*index*/
  78         gen6_vme_intra_frame,
  79         sizeof(gen6_vme_intra_frame),
  80         NULL
  81     },
  82     {
  83         "VME inter Frame",
  84         VME_INTER_SHADER,
  85         gen6_vme_inter_frame,
  86         sizeof(gen6_vme_inter_frame),
  87         NULL
  88     },
  89     {
  90         "VME BATCHBUFFER",
  91         VME_BATCHBUFFER,
  92         gen6_vme_batchbuffer,
  93         sizeof(gen6_vme_batchbuffer),
  94         NULL
  95     },
  96 };
  97
  98 static const uint32_t gen7_vme_intra_frame[][4] = {
  99 #include "shaders/vme/intra_frame.g7b"
 100 };
 101
 102 static const uint32_t gen7_vme_inter_frame[][4] = {
 103 #include "shaders/vme/inter_frame.g7b"
 104 };
 105
 106 static const uint32_t gen7_vme_batchbuffer[][4] = {
 107 #include "shaders/vme/batchbuffer.g7b"
 108 };
 109
 110 static struct i965_kernel gen7_vme_kernels[] = {
 111     {
 112         "VME Intra Frame",
 113         VME_INTRA_SHADER,                                                                               /*index*/
 114         gen7_vme_intra_frame,
 115         sizeof(gen7_vme_intra_frame),
 116         NULL
 117     },
 118     {
 119         "VME inter Frame",
 120         VME_INTER_SHADER,
 121         gen7_vme_inter_frame,
 122         sizeof(gen7_vme_inter_frame),
 123         NULL
 124     },
 125     {
 126         "VME BATCHBUFFER",
 127         VME_BATCHBUFFER,
 128         gen7_vme_batchbuffer,
 129         sizeof(gen7_vme_batchbuffer),
 130         NULL
 131     },
 132 };
 133
 134 static void
 135 gen6_vme_set_common_surface_tiling(struct i965_surface_state *ss, unsigned int tiling)
 136 {
 137     switch (tiling) {
 138     case I915_TILING_NONE:
 139         ss->ss3.tiled_surface = 0;
 140         ss->ss3.tile_walk = 0;
 141         break;
 142     case I915_TILING_X:
 143         ss->ss3.tiled_surface = 1;
 144         ss->ss3.tile_walk = I965_TILEWALK_XMAJOR;
 145         break;
 146     case I915_TILING_Y:
 147         ss->ss3.tiled_surface = 1;
 148         ss->ss3.tile_walk = I965_TILEWALK_YMAJOR;
 149         break;
 150     }
 151 }
 152
 153 static void
 154 gen6_vme_set_source_surface_tiling(struct i965_surface_state2 *ss, unsigned int tiling)
 155 {
 156     switch (tiling) {
 157     case I915_TILING_NONE:
 158         ss->ss2.tiled_surface = 0;
 159         ss->ss2.tile_walk = 0;
 160         break;
 161     case I915_TILING_X:
 162         ss->ss2.tiled_surface = 1;
 163         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
 164         break;
 165     case I915_TILING_Y:
 166         ss->ss2.tiled_surface = 1;
 167         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
 168         break;
 169     }
 170 }
 171
 172 /* only used for VME source surface state */
 173 static void gen6_vme_source_surface_state(VADriverContextP ctx,
 174                                           int index,
 175                                           struct object_surface *obj_surface,
 176                                           struct intel_encoder_context *encoder_context)
 177 {
 178     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 179     struct i965_surface_state2 *ss;
 180     dri_bo *bo;
 181     int w, h, w_pitch, h_pitch;
 182     unsigned int tiling, swizzle;
 183
 184     assert(obj_surface->bo);
 185     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
 186
 187     w = obj_surface->orig_width;
 188     h = obj_surface->orig_height;
 189     w_pitch = obj_surface->width;
 190     h_pitch = obj_surface->height;
 191
 192     bo = vme_context->surface_state_binding_table.bo;
 193     dri_bo_map(bo, 1);
 194     assert(bo->virtual);
 195
 196     ss = (struct i965_surface_state2 *)((char *)bo->virtual + SURFACE_STATE_OFFSET(index));
 197     memset(ss, 0, sizeof(*ss));
 198
 199     ss->ss0.surface_base_address = obj_surface->bo->offset;
 200
 201     ss->ss1.cbcr_pixel_offset_v_direction = 2;
 202     ss->ss1.width = w - 1;
 203     ss->ss1.height = h - 1;
 204
 205     ss->ss2.surface_format = MFX_SURFACE_PLANAR_420_8;
 206     ss->ss2.interleave_chroma = 1;
 207     ss->ss2.pitch = w_pitch - 1;
 208     ss->ss2.half_pitch_for_chroma = 0;
 209
 210     gen6_vme_set_source_surface_tiling(ss, tiling);
 211
 212     /* UV offset for interleave mode */
 213     ss->ss3.x_offset_for_cb = 0;
 214     ss->ss3.y_offset_for_cb = h_pitch;
 215
 216     dri_bo_emit_reloc(bo,
 217                       I915_GEM_DOMAIN_RENDER, 0,
 218                       0,
 219                       SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state2, ss0),
 220                       obj_surface->bo);
 221
 222     ((unsigned int *)((char *)bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
 223     dri_bo_unmap(bo);
 224 }
 225
 226 static void
 227 gen6_vme_media_source_surface_state(VADriverContextP ctx,
 228                                     int index,
 229                                     struct object_surface *obj_surface,
 230                                     struct intel_encoder_context *encoder_context)
 231 {
 232     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 233     struct i965_surface_state *ss;
 234     dri_bo *bo;
 235     int w, h, w_pitch;
 236     unsigned int tiling, swizzle;
 237
 238     w = obj_surface->orig_width;
 239     h = obj_surface->orig_height;
 240     w_pitch = obj_surface->width;
 241
 242     /* Y plane */
 243     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
 244
 245     bo = vme_context->surface_state_binding_table.bo;
 246     dri_bo_map(bo, True);
 247     assert(bo->virtual);
 248
 249     ss = (struct i965_surface_state *)((char *)bo->virtual + SURFACE_STATE_OFFSET(index));
 250     memset(ss, 0, sizeof(*ss));
 251     ss->ss0.surface_type = I965_SURFACE_2D;
 252     ss->ss0.surface_format = I965_SURFACEFORMAT_R8_UNORM;
 253     ss->ss1.base_addr = obj_surface->bo->offset;
 254     ss->ss2.width = w / 4 - 1;
 255     ss->ss2.height = h - 1;
 256     ss->ss3.pitch = w_pitch - 1;
 257     gen6_vme_set_common_surface_tiling(ss, tiling);
 258     dri_bo_emit_reloc(bo,
 259                       I915_GEM_DOMAIN_RENDER,
 260                       0,
 261                       0,
 262                       SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
 263                       obj_surface->bo);
 264
 265     ((unsigned int *)((char *)bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
 266     dri_bo_unmap(bo);
 267 }
 268
 269 static VAStatus
 270 gen6_vme_output_buffer_setup(VADriverContextP ctx,
 271                              struct encode_state *encode_state,
 272                              int index,
 273                              struct intel_encoder_context *encoder_context)
 274
 275 {
 276     struct i965_driver_data *i965 = i965_driver_data(ctx);
 277     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 278     struct i965_surface_state *ss;
 279     dri_bo *bo;
 280     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 281     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
 282     int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
 283     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 284     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 285     int num_entries;
 286
 287     if ( is_intra ) {
 288         vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs;
 289     } else {
 290         vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs * 4;
 291     }
 292     vme_context->vme_output.size_block = 16; /* an OWORD */
 293     vme_context->vme_output.pitch = ALIGN(vme_context->vme_output.size_block, 16);
 294     bo = dri_bo_alloc(i965->intel.bufmgr,
 295                       "VME output buffer",
 296                       vme_context->vme_output.num_blocks * vme_context->vme_output.pitch,
 297                       0x1000);
 298     assert(bo);
 299     vme_context->vme_output.bo = bo;
 300
 301     bo = vme_context->surface_state_binding_table.bo;
 302     dri_bo_map(bo, 1);
 303     assert(bo->virtual);
 304
 305     ss = (struct i965_surface_state *)((char *)bo->virtual + SURFACE_STATE_OFFSET(index));
 306     memset(ss, 0, sizeof(*ss));
 307
 308     /* always use 16 bytes as pitch on Sandy Bridge */
 309     num_entries = vme_context->vme_output.num_blocks * vme_context->vme_output.pitch / 16;
 310     ss->ss0.render_cache_read_mode = 1;
 311     ss->ss0.surface_type = I965_SURFACE_BUFFER;
 312     ss->ss1.base_addr = vme_context->vme_output.bo->offset;
 313     ss->ss2.width = ((num_entries - 1) & 0x7f);
 314     ss->ss2.height = (((num_entries - 1) >> 7) & 0x1fff);
 315     ss->ss3.depth = (((num_entries - 1) >> 20) & 0x7f);
 316     ss->ss3.pitch = vme_context->vme_output.pitch - 1;
 317     dri_bo_emit_reloc(bo,
 318                       I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 319                       0,
 320                       SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
 321                       vme_context->vme_output.bo);
 322
 323
 324     ((unsigned int *)((char *)bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
 325     dri_bo_unmap(bo);
 326     return VA_STATUS_SUCCESS;
 327 }
 328
 329 static VAStatus
 330 gen6_vme_output_vme_batchbuffer_setup(VADriverContextP ctx,
 331                                       struct encode_state *encode_state,
 332                                       int index,
 333                                       struct intel_encoder_context *encoder_context)
 334
 335 {
 336     struct i965_driver_data *i965 = i965_driver_data(ctx);
 337     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 338     struct i965_surface_state *ss;
 339     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 340     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 341     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 342     int num_entries;
 343     dri_bo *bo;
 344
 345     vme_context->vme_batchbuffer.num_blocks = width_in_mbs * height_in_mbs + 1;
 346     vme_context->vme_batchbuffer.size_block = 32; /* 2 OWORDs */
 347     vme_context->vme_batchbuffer.pitch = 16;
 348     bo = dri_bo_alloc(i965->intel.bufmgr,
 349                       "VME batchbuffer",
 350                       vme_context->vme_batchbuffer.num_blocks * vme_context->vme_batchbuffer.size_block,
 351                       0x1000);
 352     assert(bo);
 353     vme_context->vme_batchbuffer.bo = bo;
 354
 355     bo = vme_context->surface_state_binding_table.bo;
 356     dri_bo_map(bo, 1);
 357     assert(bo->virtual);
 358
 359     ss = (struct i965_surface_state *)((char *)bo->virtual + SURFACE_STATE_OFFSET(index));
 360     memset(ss, 0, sizeof(*ss));
 361
 362     num_entries = vme_context->vme_batchbuffer.num_blocks * vme_context->vme_batchbuffer.size_block / vme_context->vme_batchbuffer.pitch;
 363
 364     ss->ss0.render_cache_read_mode = 1;
 365     ss->ss0.surface_type = I965_SURFACE_BUFFER;
 366
 367     ss->ss1.base_addr = vme_context->vme_batchbuffer.bo->offset;
 368
 369     ss->ss2.width = ((num_entries - 1) & 0x7f);
 370     ss->ss2.height = (((num_entries - 1) >> 7) & 0x1fff);
 371     ss->ss3.depth = (((num_entries - 1) >> 20) & 0x7f);
 372
 373     dri_bo_emit_reloc(bo,
 374                       I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 375                       0,
 376                       SURFACE_STATE_OFFSET(index) + offsetof(struct i965_surface_state, ss1),
 377                       vme_context->vme_batchbuffer.bo);
 378
 379     ((unsigned int *)((char *)bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
 380     dri_bo_unmap(bo);
 381
 382     return VA_STATUS_SUCCESS;
 383 }
 384
 385 static VAStatus gen6_vme_surface_setup(VADriverContextP ctx,
 386                                        struct encode_state *encode_state,
 387                                        int is_intra,
 388                                        struct intel_encoder_context *encoder_context)
 389 {
 390     struct i965_driver_data *i965 = i965_driver_data(ctx);
 391     struct object_surface *obj_surface;
 392     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 393
 394     /*Setup surfaces state*/
 395     /* current picture for encoding */
 396     obj_surface = SURFACE(encoder_context->input_yuv_surface);
 397     assert(obj_surface);
 398     gen6_vme_source_surface_state(ctx, 0, obj_surface, encoder_context);
 399     gen6_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context);
 400
 401     if ( ! is_intra ) {
 402         /* reference 0 */
 403         obj_surface = SURFACE(pPicParameter->ReferenceFrames[0].picture_id);
 404         assert(obj_surface);
 405                 if ( obj_surface->bo != NULL)
 406                         gen6_vme_source_surface_state(ctx, 1, obj_surface, encoder_context);
 407                 /* reference 1 */
 408                 obj_surface = SURFACE(pPicParameter->ReferenceFrames[1].picture_id);
 409                 assert(obj_surface);
 410                 if ( obj_surface->bo != NULL )
 411                         gen6_vme_source_surface_state(ctx, 2, obj_surface, encoder_context);
 412     }
 413
 414     /* VME output */
 415     gen6_vme_output_buffer_setup(ctx, encode_state, 3, encoder_context);
 416     gen6_vme_output_vme_batchbuffer_setup(ctx, encode_state, 5, encoder_context);
 417
 418     return VA_STATUS_SUCCESS;
 419 }
 420
 421 /*
 422  * Surface state for IvyBridge
 423  */
 424 static void
 425 gen7_vme_set_common_surface_tiling(struct gen7_surface_state *ss, unsigned int tiling)
 426 {
 427     switch (tiling) {
 428     case I915_TILING_NONE:
 429         ss->ss0.tiled_surface = 0;
 430         ss->ss0.tile_walk = 0;
 431         break;
 432     case I915_TILING_X:
 433         ss->ss0.tiled_surface = 1;
 434         ss->ss0.tile_walk = I965_TILEWALK_XMAJOR;
 435         break;
 436     case I915_TILING_Y:
 437         ss->ss0.tiled_surface = 1;
 438         ss->ss0.tile_walk = I965_TILEWALK_YMAJOR;
 439         break;
 440     }
 441 }
 442
 443 static void
 444 gen7_vme_set_source_surface_tiling(struct gen7_surface_state2 *ss, unsigned int tiling)
 445 {
 446     switch (tiling) {
 447     case I915_TILING_NONE:
 448         ss->ss2.tiled_surface = 0;
 449         ss->ss2.tile_walk = 0;
 450         break;
 451     case I915_TILING_X:
 452         ss->ss2.tiled_surface = 1;
 453         ss->ss2.tile_walk = I965_TILEWALK_XMAJOR;
 454         break;
 455     case I915_TILING_Y:
 456         ss->ss2.tiled_surface = 1;
 457         ss->ss2.tile_walk = I965_TILEWALK_YMAJOR;
 458         break;
 459     }
 460 }
 461
 462 /* only used for VME source surface state */
 463 static void gen7_vme_source_surface_state(VADriverContextP ctx,
 464                                           int index,
 465                                           struct object_surface *obj_surface,
 466                                           struct intel_encoder_context *encoder_context)
 467 {
 468     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 469     struct gen7_surface_state2 *ss;
 470     dri_bo *bo;
 471     int w, h, w_pitch, h_pitch;
 472     unsigned int tiling, swizzle;
 473
 474     assert(obj_surface->bo);
 475
 476     w = obj_surface->orig_width;
 477     h = obj_surface->orig_height;
 478     w_pitch = obj_surface->width;
 479     h_pitch = obj_surface->height;
 480
 481     bo = vme_context->surface_state_binding_table.bo;
 482     dri_bo_map(bo, 1);
 483     assert(bo->virtual);
 484
 485     ss = (struct gen7_surface_state2 *)((char *)bo->virtual + SURFACE_STATE_OFFSET(index));
 486     memset(ss, 0, sizeof(*ss));
 487
 488     ss->ss0.surface_base_address = obj_surface->bo->offset;
 489
 490     ss->ss1.cbcr_pixel_offset_v_direction = 2;
 491     ss->ss1.width = w - 1;
 492     ss->ss1.height = h - 1;
 493
 494     ss->ss2.surface_format = MFX_SURFACE_PLANAR_420_8;
 495     ss->ss2.interleave_chroma = 1;
 496     ss->ss2.pitch = w_pitch - 1;
 497     ss->ss2.half_pitch_for_chroma = 0;
 498
 499     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
 500     gen7_vme_set_source_surface_tiling(ss, tiling);
 501
 502     /* UV offset for interleave mode */
 503     ss->ss3.x_offset_for_cb = 0;
 504     ss->ss3.y_offset_for_cb = h_pitch;
 505
 506     dri_bo_emit_reloc(bo,
 507                       I915_GEM_DOMAIN_RENDER, 0,
 508                       0,
 509                       SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state2, ss0),
 510                       obj_surface->bo);
 511
 512     ((unsigned int *)((char *)bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
 513     dri_bo_unmap(bo);
 514 }
 515
 516 static void
 517 gen7_vme_media_source_surface_state(VADriverContextP ctx,
 518                                     int index,
 519                                     struct object_surface *obj_surface,
 520                                     struct intel_encoder_context *encoder_context)
 521 {
 522     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 523     struct gen7_surface_state *ss;
 524     dri_bo *bo;
 525     int w, h, w_pitch;
 526     unsigned int tiling, swizzle;
 527
 528     /* Y plane */
 529     w = obj_surface->orig_width;
 530     h = obj_surface->orig_height;
 531     w_pitch = obj_surface->width;
 532
 533     bo = vme_context->surface_state_binding_table.bo;
 534     dri_bo_map(bo, True);
 535     assert(bo->virtual);
 536
 537     ss = (struct gen7_surface_state *)((char *)bo->virtual + SURFACE_STATE_OFFSET(index));
 538     memset(ss, 0, sizeof(*ss));
 539
 540     ss->ss0.surface_type = I965_SURFACE_2D;
 541     ss->ss0.surface_format = I965_SURFACEFORMAT_R8_UNORM;
 542
 543     ss->ss1.base_addr = obj_surface->bo->offset;
 544
 545     ss->ss2.width = w / 4 - 1;
 546     ss->ss2.height = h - 1;
 547
 548     ss->ss3.pitch = w_pitch - 1;
 549
 550     dri_bo_get_tiling(obj_surface->bo, &tiling, &swizzle);
 551     gen7_vme_set_common_surface_tiling(ss, tiling);
 552
 553     dri_bo_emit_reloc(bo,
 554                       I915_GEM_DOMAIN_RENDER, 0,
 555                       0,
 556                       SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
 557                       obj_surface->bo);
 558
 559     ((unsigned int *)((char *)bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
 560     dri_bo_unmap(bo);
 561 }
 562
 563 static VAStatus
 564 gen7_vme_output_buffer_setup(VADriverContextP ctx,
 565                              struct encode_state *encode_state,
 566                              int index,
 567                              struct intel_encoder_context *encoder_context)
 568
 569 {
 570     struct i965_driver_data *i965 = i965_driver_data(ctx);
 571     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 572     struct gen7_surface_state *ss;
 573     dri_bo *bo;
 574     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 575     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
 576     int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
 577     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 578     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 579     int num_entries;
 580
 581     if ( is_intra ) {
 582         vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs;
 583     } else {
 584         vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs * 4;
 585     }
 586     vme_context->vme_output.size_block = 16; /* an OWORD */
 587     vme_context->vme_output.pitch = ALIGN(vme_context->vme_output.size_block, 16);
 588     bo = dri_bo_alloc(i965->intel.bufmgr,
 589                       "VME output buffer",
 590                       vme_context->vme_output.num_blocks * vme_context->vme_output.pitch,
 591                       0x1000);
 592     assert(bo);
 593     vme_context->vme_output.bo = bo;
 594
 595     bo = vme_context->surface_state_binding_table.bo;
 596     dri_bo_map(bo, 1);
 597     assert(bo->virtual);
 598
 599     ss = (struct gen7_surface_state *)((char *)bo->virtual + SURFACE_STATE_OFFSET(index));
 600     memset(ss, 0, sizeof(*ss));
 601
 602     /* always use 16 bytes as pitch on Sandy Bridge */
 603     num_entries = vme_context->vme_output.num_blocks * vme_context->vme_output.pitch / 16;
 604
 605     ss->ss0.surface_type = I965_SURFACE_BUFFER;
 606
 607     ss->ss1.base_addr = vme_context->vme_output.bo->offset;
 608
 609     ss->ss2.width = ((num_entries - 1) & 0x7f);
 610     ss->ss2.height = (((num_entries - 1) >> 7) & 0x3fff);
 611     ss->ss3.depth = (((num_entries - 1) >> 21) & 0x3f);
 612
 613     ss->ss3.pitch = vme_context->vme_output.pitch - 1;
 614
 615     dri_bo_emit_reloc(bo,
 616                       I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 617                       0,
 618                       SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
 619                       vme_context->vme_output.bo);
 620
 621     ((unsigned int *)((char *)bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
 622     dri_bo_unmap(bo);
 623
 624     return VA_STATUS_SUCCESS;
 625 }
 626
 627 static VAStatus
 628 gen7_vme_output_vme_batchbuffer_setup(VADriverContextP ctx,
 629                                       struct encode_state *encode_state,
 630                                       int index,
 631                                       struct intel_encoder_context *encoder_context)
 632
 633 {
 634     struct i965_driver_data *i965 = i965_driver_data(ctx);
 635     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 636     struct gen7_surface_state *ss;
 637     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 638     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 639     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 640     int num_entries;
 641     dri_bo *bo;
 642
 643     vme_context->vme_batchbuffer.num_blocks = width_in_mbs * height_in_mbs + 1;
 644     vme_context->vme_batchbuffer.size_block = 32; /* an OWORD */
 645     vme_context->vme_batchbuffer.pitch = 16;
 646     bo = dri_bo_alloc(i965->intel.bufmgr,
 647                       "VME batchbuffer",
 648                       vme_context->vme_batchbuffer.num_blocks * vme_context->vme_batchbuffer.size_block,
 649                       0x1000);
 650     assert(bo);
 651     vme_context->vme_batchbuffer.bo = bo;
 652
 653     bo = vme_context->surface_state_binding_table.bo;
 654     dri_bo_map(bo, 1);
 655     assert(bo->virtual);
 656
 657     ss = (struct gen7_surface_state *)((char *)bo->virtual + SURFACE_STATE_OFFSET(index));
 658     memset(ss, 0, sizeof(*ss));
 659
 660     num_entries = vme_context->vme_batchbuffer.num_blocks * vme_context->vme_batchbuffer.size_block / vme_context->vme_batchbuffer.pitch;
 661
 662     ss->ss0.render_cache_read_write = 1;
 663     ss->ss0.surface_type = I965_SURFACE_BUFFER;
 664
 665     ss->ss1.base_addr = vme_context->vme_batchbuffer.bo->offset;
 666
 667     ss->ss2.width = ((num_entries - 1) & 0x7f);
 668     ss->ss2.height = (((num_entries - 1) >> 7) & 0x3fff);
 669     ss->ss3.depth = (((num_entries - 1) >> 21) & 0x3f);
 670
 671     ss->ss3.pitch = vme_context->vme_batchbuffer.pitch - 1;
 672
 673     dri_bo_emit_reloc(bo,
 674                       I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
 675                       0,
 676                       SURFACE_STATE_OFFSET(index) + offsetof(struct gen7_surface_state, ss1),
 677                       vme_context->vme_batchbuffer.bo);
 678
 679     ((unsigned int *)((char *)bo->virtual + BINDING_TABLE_OFFSET))[index] = SURFACE_STATE_OFFSET(index);
 680     dri_bo_unmap(bo);
 681
 682     return VA_STATUS_SUCCESS;
 683 }
 684
 685 static VAStatus gen7_vme_surface_setup(VADriverContextP ctx,
 686                                        struct encode_state *encode_state,
 687                                        int is_intra,
 688                                        struct intel_encoder_context *encoder_context)
 689 {
 690     struct i965_driver_data *i965 = i965_driver_data(ctx);
 691     struct object_surface *obj_surface;
 692     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 693
 694     /*Setup surfaces state*/
 695     /* current picture for encoding */
 696     obj_surface = SURFACE(encoder_context->input_yuv_surface);
 697     assert(obj_surface);
 698     gen7_vme_source_surface_state(ctx, 0, obj_surface, encoder_context);
 699     gen7_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context);
 700
 701     if (!is_intra) {
 702         /* reference 0 */
 703         obj_surface = SURFACE(pPicParameter->ReferenceFrames[0].picture_id);
 704         assert(obj_surface);
 705         if ( obj_surface->bo != NULL)
 706             gen7_vme_source_surface_state(ctx, 1, obj_surface, encoder_context);
 707
 708         /* reference 1 */
 709         obj_surface = SURFACE(pPicParameter->ReferenceFrames[1].picture_id);
 710         assert(obj_surface);
 711         if ( obj_surface->bo != NULL )
 712             gen7_vme_source_surface_state(ctx, 2, obj_surface, encoder_context);
 713     }
 714
 715     /* VME output */
 716     gen7_vme_output_buffer_setup(ctx, encode_state, 3, encoder_context);
 717     gen7_vme_output_vme_batchbuffer_setup(ctx, encode_state, 5, encoder_context);
 718
 719     return VA_STATUS_SUCCESS;
 720 }
 721
 722 static VAStatus gen6_vme_interface_setup(VADriverContextP ctx,
 723                                          struct encode_state *encode_state,
 724                                          struct intel_encoder_context *encoder_context)
 725 {
 726     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 727     struct gen6_interface_descriptor_data *desc;
 728     int i;
 729     dri_bo *bo;
 730
 731     bo = vme_context->idrt.bo;
 732     dri_bo_map(bo, 1);
 733     assert(bo->virtual);
 734     desc = bo->virtual;
 735
 736     for (i = 0; i < GEN6_VME_KERNEL_NUMBER; i++) {
 737         struct i965_kernel *kernel;
 738         kernel = &vme_context->vme_kernels[i];
 739         assert(sizeof(*desc) == 32);
 740         /*Setup the descritor table*/
 741         memset(desc, 0, sizeof(*desc));
 742         desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6);
 743         desc->desc2.sampler_count = 1; /* FIXME: */
 744         desc->desc2.sampler_state_pointer = (vme_context->vme_state.bo->offset >> 5);
 745         desc->desc3.binding_table_entry_count = 1; /* FIXME: */
 746         desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET >> 5);
 747         desc->desc4.constant_urb_entry_read_offset = 0;
 748         desc->desc4.constant_urb_entry_read_length = CURBE_URB_ENTRY_LENGTH;
 749
 750         /*kernel start*/
 751         dri_bo_emit_reloc(bo,
 752                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 753                           0,
 754                           i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0),
 755                           kernel->bo);
 756         /*Sampler State(VME state pointer)*/
 757         dri_bo_emit_reloc(bo,
 758                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 759                           (1 << 2),                                                                     //
 760                           i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc2),
 761                           vme_context->vme_state.bo);
 762         desc++;
 763     }
 764     dri_bo_unmap(bo);
 765
 766     return VA_STATUS_SUCCESS;
 767 }
 768
 769 static VAStatus gen6_vme_constant_setup(VADriverContextP ctx,
 770                                         struct encode_state *encode_state,
 771                                         struct intel_encoder_context *encoder_context)
 772 {
 773     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 774     // unsigned char *constant_buffer;
 775
 776     dri_bo_map(vme_context->curbe.bo, 1);
 777     assert(vme_context->curbe.bo->virtual);
 778     // constant_buffer = vme_context->curbe.bo->virtual;
 779
 780     /*TODO copy buffer into CURB*/
 781
 782     dri_bo_unmap( vme_context->curbe.bo);
 783
 784     return VA_STATUS_SUCCESS;
 785 }
 786
 787 static VAStatus gen6_vme_vme_state_setup(VADriverContextP ctx,
 788                                          struct encode_state *encode_state,
 789                                          int is_intra,
 790                                          struct intel_encoder_context *encoder_context)
 791 {
 792     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 793     unsigned int *vme_state_message;
 794     int i;
 795
 796     //building VME state message
 797     dri_bo_map(vme_context->vme_state.bo, 1);
 798     assert(vme_context->vme_state.bo->virtual);
 799     vme_state_message = (unsigned int *)vme_context->vme_state.bo->virtual;
 800
 801         vme_state_message[0] = 0x01010101;
 802         vme_state_message[1] = 0x01010110;
 803         vme_state_message[2] = 0x0F0F0F0F;
 804         vme_state_message[3] = 0x0F0F0F10;
 805         vme_state_message[4] = 0x01010101;
 806         vme_state_message[5] = 0x01010110;
 807         vme_state_message[6] = 0x0F0F0F0F;
 808         vme_state_message[7] = 0x0F0F0F10;
 809         vme_state_message[8] = 0x01010101;
 810         vme_state_message[9] = 0x01010110;
 811     vme_state_message[10] = 0x0F0F0F0F;
 812     vme_state_message[11] = 0x0F0F0F10;
 813     vme_state_message[12] = 0x01010101;
 814     vme_state_message[13] = 0x01010100;
 815
 816     for(i = 14; i < 32; i++) {
 817         vme_state_message[i] = 0x00000000;
 818     }
 819
 820     //vme_state_message[16] = 0x42424242;                       //cost function LUT set 0 for Intra
 821
 822     dri_bo_unmap( vme_context->vme_state.bo);
 823     return VA_STATUS_SUCCESS;
 824 }
 825
 826 static void gen6_vme_pipeline_select(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 827 {
 828     struct intel_batchbuffer *batch = encoder_context->base.batch;
 829
 830     BEGIN_BATCH(batch, 1);
 831     OUT_BATCH(batch, CMD_PIPELINE_SELECT | PIPELINE_SELECT_MEDIA);
 832     ADVANCE_BATCH(batch);
 833 }
 834
 835 static void gen6_vme_state_base_address(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 836 {
 837     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 838     struct intel_batchbuffer *batch = encoder_context->base.batch;
 839
 840     BEGIN_BATCH(batch, 10);
 841
 842     OUT_BATCH(batch, CMD_STATE_BASE_ADDRESS | 8);
 843
 844     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);                          //General State Base Address
 845     OUT_RELOC(batch, vme_context->surface_state_binding_table.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
 846     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);                          //Dynamic State Base Address
 847     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);                          //Indirect Object Base Address
 848     OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);                          //Instruction Base Address
 849
 850     OUT_BATCH(batch, 0xFFFFF000 | BASE_ADDRESS_MODIFY);         //General State Access Upper Bound
 851     OUT_BATCH(batch, 0xFFFFF000 | BASE_ADDRESS_MODIFY);         //Dynamic State Access Upper Bound
 852     OUT_BATCH(batch, 0xFFFFF000 | BASE_ADDRESS_MODIFY);         //Indirect Object Access Upper Bound
 853     OUT_BATCH(batch, 0xFFFFF000 | BASE_ADDRESS_MODIFY);         //Instruction Access Upper Bound
 854
 855     /*
 856       OUT_BATCH(batch, 0 | BASE_ADDRESS_MODIFY);                                //LLC Coherent Base Address
 857       OUT_BATCH(batch, 0xFFFFF000 | BASE_ADDRESS_MODIFY );              //LLC Coherent Upper Bound
 858     */
 859
 860     ADVANCE_BATCH(batch);
 861 }
 862
 863 static void gen6_vme_vfe_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 864 {
 865     struct intel_batchbuffer *batch = encoder_context->base.batch;
 866     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 867
 868     BEGIN_BATCH(batch, 8);
 869
 870     OUT_BATCH(batch, CMD_MEDIA_VFE_STATE | 6);                                  /*Gen6 CMD_MEDIA_STATE_POINTERS = CMD_MEDIA_STATE */
 871     OUT_BATCH(batch, 0);                                                                                                /*Scratch Space Base Pointer and Space*/
 872     OUT_BATCH(batch, (vme_context->vfe_state.max_num_threads << 16)
 873               | (vme_context->vfe_state.num_urb_entries << 8)
 874               | (vme_context->vfe_state.gpgpu_mode << 2) );     /*Maximum Number of Threads , Number of URB Entries, MEDIA Mode*/
 875     OUT_BATCH(batch, 0);                                                                                                /*Debug: Object ID*/
 876     OUT_BATCH(batch, (vme_context->vfe_state.urb_entry_size << 16)
 877               | vme_context->vfe_state.curbe_allocation_size);                          /*URB Entry Allocation Size , CURBE Allocation Size*/
 878     OUT_BATCH(batch, 0);                                                                                        /*Disable Scoreboard*/
 879     OUT_BATCH(batch, 0);                                                                                        /*Disable Scoreboard*/
 880     OUT_BATCH(batch, 0);                                                                                        /*Disable Scoreboard*/
 881
 882     ADVANCE_BATCH(batch);
 883
 884 }
 885
 886 static void gen6_vme_curbe_load(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 887 {
 888     struct intel_batchbuffer *batch = encoder_context->base.batch;
 889     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 890
 891     BEGIN_BATCH(batch, 4);
 892
 893     OUT_BATCH(batch, CMD_MEDIA_CURBE_LOAD | 2);
 894     OUT_BATCH(batch, 0);
 895
 896     OUT_BATCH(batch, CURBE_TOTAL_DATA_LENGTH);
 897     OUT_RELOC(batch, vme_context->curbe.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 898
 899     ADVANCE_BATCH(batch);
 900 }
 901
 902 static void gen6_vme_idrt(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 903 {
 904     struct intel_batchbuffer *batch = encoder_context->base.batch;
 905     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 906
 907     BEGIN_BATCH(batch, 4);
 908
 909     OUT_BATCH(batch, CMD_MEDIA_INTERFACE_LOAD | 2);
 910     OUT_BATCH(batch, 0);
 911     OUT_BATCH(batch, GEN6_VME_KERNEL_NUMBER * sizeof(struct gen6_interface_descriptor_data));
 912     OUT_RELOC(batch, vme_context->idrt.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 913
 914     ADVANCE_BATCH(batch);
 915 }
 916
 917 static void
 918 gen6_vme_fill_vme_batchbuffer(VADriverContextP ctx,
 919                               struct encode_state *encode_state,
 920                               int mb_width, int mb_height,
 921                               int kernel,
 922                               int transform_8x8_mode_flag,
 923                               struct intel_encoder_context *encoder_context)
 924 {
 925     struct intel_batchbuffer *batch = encoder_context->base.batch;
 926     int mb_x, mb_y, i;
 927     int total_mbs = mb_width * mb_height;
 928     int number_mb_cmds = 512;
 929     int starting_mb = 0;
 930     int last_object = 0;
 931
 932     for (i = 0; i < total_mbs / number_mb_cmds; i++) {
 933         mb_x = starting_mb % mb_width;
 934         mb_y = starting_mb / mb_width;
 935         last_object = (total_mbs - starting_mb) == number_mb_cmds;
 936         starting_mb += number_mb_cmds;
 937
 938         BEGIN_BATCH(batch, 9);
 939
 940         OUT_BATCH(batch, CMD_MEDIA_OBJECT | (9 - 2));
 941         OUT_BATCH(batch, VME_BATCHBUFFER);
 942         OUT_BATCH(batch, 0);
 943         OUT_BATCH(batch, 0);
 944         OUT_BATCH(batch, 0);
 945         OUT_BATCH(batch, 0);
 946
 947         /*inline data */
 948         OUT_BATCH(batch,
 949                   kernel << 24 |
 950                   transform_8x8_mode_flag << 16 |
 951                   mb_width);
 952         OUT_BATCH(batch,
 953                   number_mb_cmds << 16 |
 954                   mb_y << 8 |
 955                   mb_x);
 956         OUT_BATCH(batch, last_object);
 957
 958         ADVANCE_BATCH(batch);
 959     }
 960
 961     if (!last_object) {
 962         number_mb_cmds = total_mbs % number_mb_cmds;
 963         mb_x = starting_mb % mb_width;
 964         mb_y = starting_mb / mb_width;
 965         last_object = 1;
 966         starting_mb += number_mb_cmds;
 967
 968         BEGIN_BATCH(batch, 9);
 969
 970         OUT_BATCH(batch, CMD_MEDIA_OBJECT | (9 - 2));
 971         OUT_BATCH(batch, VME_BATCHBUFFER);
 972         OUT_BATCH(batch, 0);
 973         OUT_BATCH(batch, 0);
 974         OUT_BATCH(batch, 0);
 975         OUT_BATCH(batch, 0);
 976
 977         /*inline data */
 978         OUT_BATCH(batch,
 979                   kernel << 24 |
 980                   transform_8x8_mode_flag << 16 |
 981                   mb_width);
 982         OUT_BATCH(batch,
 983                   number_mb_cmds << 16 |
 984                   mb_y << 8 |
 985                   mb_x);
 986         OUT_BATCH(batch, last_object);
 987
 988         ADVANCE_BATCH(batch);
 989     }
 990
 991 }
 992
 993 static void gen6_vme_media_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 994 {
 995     struct i965_driver_data *i965 = i965_driver_data(ctx);
 996     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 997     dri_bo *bo;
 998
 999     /* constant buffer */
1000     dri_bo_unreference(vme_context->curbe.bo);
1001     bo = dri_bo_alloc(i965->intel.bufmgr,
1002                       "Buffer",
1003                       CURBE_TOTAL_DATA_LENGTH, 64);
1004     assert(bo);
1005     vme_context->curbe.bo = bo;
1006
1007     dri_bo_unreference(vme_context->surface_state_binding_table.bo);
1008     bo = dri_bo_alloc(i965->intel.bufmgr,
1009                       "surface state & binding table",
1010                       (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6,
1011                       4096);
1012     assert(bo);
1013     vme_context->surface_state_binding_table.bo = bo;
1014
1015     /* interface descriptor remapping table */
1016     dri_bo_unreference(vme_context->idrt.bo);
1017     bo = dri_bo_alloc(i965->intel.bufmgr,
1018                       "Buffer",
1019                       MAX_INTERFACE_DESC_GEN6 * sizeof(struct gen6_interface_descriptor_data), 16);
1020     assert(bo);
1021     vme_context->idrt.bo = bo;
1022
1023     /* VME output buffer */
1024     dri_bo_unreference(vme_context->vme_output.bo);
1025     vme_context->vme_output.bo = NULL;
1026
1027     dri_bo_unreference(vme_context->vme_batchbuffer.bo);
1028     vme_context->vme_batchbuffer.bo = NULL;
1029
1030     /* VME state */
1031     dri_bo_unreference(vme_context->vme_state.bo);
1032     bo = dri_bo_alloc(i965->intel.bufmgr,
1033                       "Buffer",
1034                       1024*16, 64);
1035     assert(bo);
1036     vme_context->vme_state.bo = bo;
1037
1038     vme_context->vfe_state.max_num_threads = 60 - 1;
1039     vme_context->vfe_state.num_urb_entries = 16;
1040     vme_context->vfe_state.gpgpu_mode = 0;
1041     vme_context->vfe_state.urb_entry_size = 59 - 1;
1042     vme_context->vfe_state.curbe_allocation_size = CURBE_ALLOCATION_SIZE - 1;
1043 }
1044
1045 static void gen6_vme_pipeline_programing(VADriverContextP ctx,
1046                                          struct encode_state *encode_state,
1047                                          struct intel_encoder_context *encoder_context)
1048 {
1049     struct gen6_vme_context *vme_context = encoder_context->vme_context;
1050     struct intel_batchbuffer *batch = encoder_context->base.batch;
1051     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
1052     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
1053     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
1054     int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
1055     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
1056     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
1057
1058     intel_batchbuffer_start_atomic(batch, 0x1000);
1059
1060     intel_batchbuffer_emit_mi_flush(batch);
1061
1062     /*Step2: State command PIPELINE_SELECT*/
1063     gen6_vme_pipeline_select(ctx, encoder_context);
1064
1065     /*Step3: State commands configuring pipeline states*/
1066     gen6_vme_state_base_address(ctx, encoder_context);
1067     gen6_vme_vfe_state(ctx, encoder_context);
1068     gen6_vme_curbe_load(ctx, encoder_context);
1069     gen6_vme_idrt(ctx, encoder_context);
1070
1071     gen6_vme_fill_vme_batchbuffer(ctx,
1072                                   encode_state,
1073                                   width_in_mbs, height_in_mbs,
1074                                   is_intra ? VME_INTRA_SHADER : VME_INTER_SHADER,
1075                                   pPicParameter->pic_fields.bits.transform_8x8_mode_flag,
1076                                   encoder_context);
1077
1078     intel_batchbuffer_emit_mi_flush(batch);
1079
1080     gen6_vme_state_base_address(ctx, encoder_context);
1081     gen6_vme_vfe_state(ctx, encoder_context);
1082     gen6_vme_curbe_load(ctx, encoder_context);
1083     gen6_vme_idrt(ctx, encoder_context);
1084
1085     BEGIN_BATCH(batch, 2);
1086     OUT_BATCH(batch, MI_BATCH_BUFFER_START | (2 << 6));
1087     OUT_RELOC(batch,
1088               vme_context->vme_batchbuffer.bo,
1089               I915_GEM_DOMAIN_COMMAND, 0,
1090               0);
1091     ADVANCE_BATCH(batch);
1092
1093     intel_batchbuffer_end_atomic(batch);
1094 }
1095
1096 static VAStatus gen6_vme_prepare(VADriverContextP ctx,
1097                                  struct encode_state *encode_state,
1098                                  struct intel_encoder_context *encoder_context)
1099 {
1100     struct i965_driver_data *i965 = i965_driver_data(ctx);
1101     VAStatus vaStatus = VA_STATUS_SUCCESS;
1102     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
1103     int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
1104
1105     /*Setup all the memory object*/
1106     if (IS_GEN7(i965->intel.device_id))
1107         gen7_vme_surface_setup(ctx, encode_state, is_intra, encoder_context);
1108     else
1109         gen6_vme_surface_setup(ctx, encode_state, is_intra, encoder_context);
1110
1111     gen6_vme_interface_setup(ctx, encode_state, encoder_context);
1112     gen6_vme_constant_setup(ctx, encode_state, encoder_context);
1113     gen6_vme_vme_state_setup(ctx, encode_state, is_intra, encoder_context);
1114
1115     /*Programing media pipeline*/
1116     gen6_vme_pipeline_programing(ctx, encode_state, encoder_context);
1117
1118     return vaStatus;
1119 }
1120
1121 static VAStatus gen6_vme_run(VADriverContextP ctx,
1122                              struct encode_state *encode_state,
1123                              struct intel_encoder_context *encoder_context)
1124 {
1125     struct intel_batchbuffer *batch = encoder_context->base.batch;
1126
1127     intel_batchbuffer_flush(batch);
1128
1129     return VA_STATUS_SUCCESS;
1130 }
1131
1132 static VAStatus gen6_vme_stop(VADriverContextP ctx,
1133                               struct encode_state *encode_state,
1134                               struct intel_encoder_context *encoder_context)
1135 {
1136     return VA_STATUS_SUCCESS;
1137 }
1138
1139 static VAStatus
1140 gen6_vme_pipeline(VADriverContextP ctx,
1141                   VAProfile profile,
1142                   struct encode_state *encode_state,
1143                   struct intel_encoder_context *encoder_context)
1144 {
1145     gen6_vme_media_init(ctx, encoder_context);
1146     gen6_vme_prepare(ctx, encode_state, encoder_context);
1147     gen6_vme_run(ctx, encode_state, encoder_context);
1148     gen6_vme_stop(ctx, encode_state, encoder_context);
1149
1150     return VA_STATUS_SUCCESS;
1151 }
1152
1153 static void
1154 gen6_vme_context_destroy(void *context)
1155 {
1156     struct gen6_vme_context *vme_context = context;
1157     int i;
1158
1159     dri_bo_unreference(vme_context->idrt.bo);
1160     vme_context->idrt.bo = NULL;
1161
1162     dri_bo_unreference(vme_context->surface_state_binding_table.bo);
1163     vme_context->surface_state_binding_table.bo = NULL;
1164
1165     dri_bo_unreference(vme_context->curbe.bo);
1166     vme_context->curbe.bo = NULL;
1167
1168     dri_bo_unreference(vme_context->vme_output.bo);
1169     vme_context->vme_output.bo = NULL;
1170
1171     dri_bo_unreference(vme_context->vme_state.bo);
1172     vme_context->vme_state.bo = NULL;
1173
1174     for (i = 0; i < GEN6_VME_KERNEL_NUMBER; i++) {
1175         /*Load kernel into GPU memory*/
1176         struct i965_kernel *kernel = &vme_context->vme_kernels[i];
1177
1178         dri_bo_unreference(kernel->bo);
1179         kernel->bo = NULL;
1180     }
1181
1182     free(vme_context);
1183 }
1184
1185 Bool gen6_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
1186 {
1187     struct i965_driver_data *i965 = i965_driver_data(ctx);
1188     struct gen6_vme_context *vme_context = calloc(1, sizeof(struct gen6_vme_context));
1189     int i;
1190
1191     if (IS_GEN7(i965->intel.device_id))
1192         memcpy(vme_context->vme_kernels, gen7_vme_kernels, sizeof(vme_context->vme_kernels));
1193     else
1194         memcpy(vme_context->vme_kernels, gen6_vme_kernels, sizeof(vme_context->vme_kernels));
1195
1196     for (i = 0; i < GEN6_VME_KERNEL_NUMBER; i++) {
1197         /*Load kernel into GPU memory*/
1198         struct i965_kernel *kernel = &vme_context->vme_kernels[i];
1199
1200         kernel->bo = dri_bo_alloc(i965->intel.bufmgr,
1201                                   kernel->name,
1202                                   kernel->size,
1203                                   0x1000);
1204         assert(kernel->bo);
1205         dri_bo_subdata(kernel->bo, 0, kernel->size, kernel->bin);
1206     }
1207
1208     encoder_context->vme_context = vme_context;
1209     encoder_context->vme_context_destroy = gen6_vme_context_destroy;
1210     encoder_context->vme_pipeline = gen6_vme_pipeline;
1211
1212     return True;
1213 }