src/gen6_vme.c

   1 /*
   2  * Copyright © 2010-2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Zhou Chang <chang.zhou@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <assert.h>
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_driver.h"
  36
  37 #include "i965_defines.h"
  38 #include "i965_drv_video.h"
  39 #include "i965_encoder.h"
  40 #include "gen6_vme.h"
  41 #include "gen6_mfc.h"
  42
  43 #define SURFACE_STATE_PADDED_SIZE_0_GEN7        ALIGN(sizeof(struct gen7_surface_state), 32)
  44 #define SURFACE_STATE_PADDED_SIZE_1_GEN7        ALIGN(sizeof(struct gen7_surface_state2), 32)
  45 #define SURFACE_STATE_PADDED_SIZE_GEN7          MAX(SURFACE_STATE_PADDED_SIZE_0_GEN7, SURFACE_STATE_PADDED_SIZE_1_GEN7)
  46
  47 #define SURFACE_STATE_PADDED_SIZE_0_GEN6        ALIGN(sizeof(struct i965_surface_state), 32)
  48 #define SURFACE_STATE_PADDED_SIZE_1_GEN6        ALIGN(sizeof(struct i965_surface_state2), 32)
  49 #define SURFACE_STATE_PADDED_SIZE_GEN6          MAX(SURFACE_STATE_PADDED_SIZE_0_GEN6, SURFACE_STATE_PADDED_SIZE_1_GEN6)
  50
  51 #define SURFACE_STATE_PADDED_SIZE               MAX(SURFACE_STATE_PADDED_SIZE_GEN6, SURFACE_STATE_PADDED_SIZE_GEN7)
  52 #define SURFACE_STATE_OFFSET(index)             (SURFACE_STATE_PADDED_SIZE * index)
  53 #define BINDING_TABLE_OFFSET(index)             (SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * index)
  54
  55 #define VME_INTRA_SHADER        0
  56 #define VME_INTER_SHADER        1
  57 #define VME_BATCHBUFFER         2
  58
  59 #define CURBE_ALLOCATION_SIZE   37              /* in 256-bit */
  60 #define CURBE_TOTAL_DATA_LENGTH (4 * 32)        /* in byte, it should be less than or equal to CURBE_ALLOCATION_SIZE * 32 */
  61 #define CURBE_URB_ENTRY_LENGTH  4               /* in 256-bit, it should be less than or equal to CURBE_TOTAL_DATA_LENGTH / 32 */
  62
  63 static const uint32_t gen6_vme_intra_frame[][4] = {
  64 #include "shaders/vme/intra_frame.g6b"
  65 };
  66
  67 static const uint32_t gen6_vme_inter_frame[][4] = {
  68 #include "shaders/vme/inter_frame.g6b"
  69 };
  70
  71 static const uint32_t gen6_vme_batchbuffer[][4] = {
  72 #include "shaders/vme/batchbuffer.g6b"
  73 };
  74
  75 static struct i965_kernel gen6_vme_kernels[] = {
  76     {
  77         "VME Intra Frame",
  78         VME_INTRA_SHADER,                                                                               /*index*/
  79         gen6_vme_intra_frame,
  80         sizeof(gen6_vme_intra_frame),
  81         NULL
  82     },
  83     {
  84         "VME inter Frame",
  85         VME_INTER_SHADER,
  86         gen6_vme_inter_frame,
  87         sizeof(gen6_vme_inter_frame),
  88         NULL
  89     },
  90     {
  91         "VME BATCHBUFFER",
  92         VME_BATCHBUFFER,
  93         gen6_vme_batchbuffer,
  94         sizeof(gen6_vme_batchbuffer),
  95         NULL
  96     },
  97 };
  98
  99 static const uint32_t gen7_vme_intra_frame[][4] = {
 100 #include "shaders/vme/intra_frame.g7b"
 101 };
 102
 103 static const uint32_t gen7_vme_inter_frame[][4] = {
 104 #include "shaders/vme/inter_frame.g7b"
 105 };
 106
 107 static const uint32_t gen7_vme_batchbuffer[][4] = {
 108 #include "shaders/vme/batchbuffer.g7b"
 109 };
 110
 111 static struct i965_kernel gen7_vme_kernels[] = {
 112     {
 113         "VME Intra Frame",
 114         VME_INTRA_SHADER,                                                                               /*index*/
 115         gen7_vme_intra_frame,
 116         sizeof(gen7_vme_intra_frame),
 117         NULL
 118     },
 119     {
 120         "VME inter Frame",
 121         VME_INTER_SHADER,
 122         gen7_vme_inter_frame,
 123         sizeof(gen7_vme_inter_frame),
 124         NULL
 125     },
 126     {
 127         "VME BATCHBUFFER",
 128         VME_BATCHBUFFER,
 129         gen7_vme_batchbuffer,
 130         sizeof(gen7_vme_batchbuffer),
 131         NULL
 132     },
 133 };
 134
 135 /* only used for VME source surface state */
 136 static void
 137 gen6_vme_source_surface_state(VADriverContextP ctx,
 138                               int index,
 139                               struct object_surface *obj_surface,
 140                               struct intel_encoder_context *encoder_context)
 141 {
 142     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 143
 144     vme_context->vme_surface2_setup(ctx,
 145                                     &vme_context->gpe_context,
 146                                     obj_surface,
 147                                     BINDING_TABLE_OFFSET(index),
 148                                     SURFACE_STATE_OFFSET(index));
 149 }
 150
 151 static void
 152 gen6_vme_media_source_surface_state(VADriverContextP ctx,
 153                                     int index,
 154                                     struct object_surface *obj_surface,
 155                                     struct intel_encoder_context *encoder_context)
 156 {
 157     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 158
 159     vme_context->vme_media_rw_surface_setup(ctx,
 160                                             &vme_context->gpe_context,
 161                                             obj_surface,
 162                                             BINDING_TABLE_OFFSET(index),
 163                                             SURFACE_STATE_OFFSET(index));
 164 }
 165
 166 static void
 167 gen6_vme_output_buffer_setup(VADriverContextP ctx,
 168                              struct encode_state *encode_state,
 169                              int index,
 170                              struct intel_encoder_context *encoder_context)
 171
 172 {
 173     struct i965_driver_data *i965 = i965_driver_data(ctx);
 174     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 175     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 176     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
 177     int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
 178     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 179     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 180
 181     vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs;
 182     vme_context->vme_output.pitch = 16; /* in bytes, always 16 */
 183
 184     if (is_intra)
 185         vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES;
 186     else
 187         vme_context->vme_output.size_block = INTER_VME_OUTPUT_IN_BYTES;
 188
 189     vme_context->vme_output.bo = dri_bo_alloc(i965->intel.bufmgr,
 190                                               "VME output buffer",
 191                                               vme_context->vme_output.num_blocks * vme_context->vme_output.size_block,
 192                                               0x1000);
 193     assert(vme_context->vme_output.bo);
 194     vme_context->vme_buffer_suface_setup(ctx,
 195                                          &vme_context->gpe_context,
 196                                          &vme_context->vme_output,
 197                                          BINDING_TABLE_OFFSET(index),
 198                                          SURFACE_STATE_OFFSET(index));
 199 }
 200
 201 static void
 202 gen6_vme_output_vme_batchbuffer_setup(VADriverContextP ctx,
 203                                       struct encode_state *encode_state,
 204                                       int index,
 205                                       struct intel_encoder_context *encoder_context)
 206
 207 {
 208     struct i965_driver_data *i965 = i965_driver_data(ctx);
 209     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 210     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 211     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 212     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 213
 214     vme_context->vme_batchbuffer.num_blocks = width_in_mbs * height_in_mbs + 1;
 215     vme_context->vme_batchbuffer.size_block = 32; /* 2 OWORDs */
 216     vme_context->vme_batchbuffer.pitch = 16;
 217     vme_context->vme_batchbuffer.bo = dri_bo_alloc(i965->intel.bufmgr,
 218                                                    "VME batchbuffer",
 219                                                    vme_context->vme_batchbuffer.num_blocks * vme_context->vme_batchbuffer.size_block,
 220                                                    0x1000);
 221     vme_context->vme_buffer_suface_setup(ctx,
 222                                          &vme_context->gpe_context,
 223                                          &vme_context->vme_batchbuffer,
 224                                          BINDING_TABLE_OFFSET(index),
 225                                          SURFACE_STATE_OFFSET(index));
 226 }
 227
 228 static VAStatus
 229 gen6_vme_surface_setup(VADriverContextP ctx,
 230                        struct encode_state *encode_state,
 231                        int is_intra,
 232                        struct intel_encoder_context *encoder_context)
 233 {
 234     struct i965_driver_data *i965 = i965_driver_data(ctx);
 235     struct object_surface *obj_surface;
 236     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 237
 238     /*Setup surfaces state*/
 239     /* current picture for encoding */
 240     obj_surface = SURFACE(encoder_context->input_yuv_surface);
 241     assert(obj_surface);
 242     gen6_vme_source_surface_state(ctx, 0, obj_surface, encoder_context);
 243     gen6_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context);
 244
 245     if (!is_intra) {
 246         /* reference 0 */
 247         obj_surface = SURFACE(pPicParameter->ReferenceFrames[0].picture_id);
 248         assert(obj_surface);
 249         if ( obj_surface->bo != NULL)
 250             gen6_vme_source_surface_state(ctx, 1, obj_surface, encoder_context);
 251
 252         /* reference 1 */
 253         obj_surface = SURFACE(pPicParameter->ReferenceFrames[1].picture_id);
 254         assert(obj_surface);
 255         if ( obj_surface->bo != NULL )
 256             gen6_vme_source_surface_state(ctx, 2, obj_surface, encoder_context);
 257     }
 258
 259     /* VME output */
 260     gen6_vme_output_buffer_setup(ctx, encode_state, 3, encoder_context);
 261     gen6_vme_output_vme_batchbuffer_setup(ctx, encode_state, 5, encoder_context);
 262
 263     return VA_STATUS_SUCCESS;
 264 }
 265
 266 static VAStatus gen6_vme_interface_setup(VADriverContextP ctx,
 267                                          struct encode_state *encode_state,
 268                                          struct intel_encoder_context *encoder_context)
 269 {
 270     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 271     struct gen6_interface_descriptor_data *desc;
 272     int i;
 273     dri_bo *bo;
 274
 275     bo = vme_context->gpe_context.idrt.bo;
 276     dri_bo_map(bo, 1);
 277     assert(bo->virtual);
 278     desc = bo->virtual;
 279
 280     for (i = 0; i < GEN6_VME_KERNEL_NUMBER; i++) {
 281         struct i965_kernel *kernel;
 282         kernel = &vme_context->gpe_context.kernels[i];
 283         assert(sizeof(*desc) == 32);
 284         /*Setup the descritor table*/
 285         memset(desc, 0, sizeof(*desc));
 286         desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6);
 287         desc->desc2.sampler_count = 1; /* FIXME: */
 288         desc->desc2.sampler_state_pointer = (vme_context->vme_state.bo->offset >> 5);
 289         desc->desc3.binding_table_entry_count = 1; /* FIXME: */
 290         desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5);
 291         desc->desc4.constant_urb_entry_read_offset = 0;
 292         desc->desc4.constant_urb_entry_read_length = CURBE_URB_ENTRY_LENGTH;
 293
 294         /*kernel start*/
 295         dri_bo_emit_reloc(bo,
 296                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 297                           0,
 298                           i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0),
 299                           kernel->bo);
 300         /*Sampler State(VME state pointer)*/
 301         dri_bo_emit_reloc(bo,
 302                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 303                           (1 << 2),                                                                     //
 304                           i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc2),
 305                           vme_context->vme_state.bo);
 306         desc++;
 307     }
 308     dri_bo_unmap(bo);
 309
 310     return VA_STATUS_SUCCESS;
 311 }
 312
 313 static VAStatus gen6_vme_constant_setup(VADriverContextP ctx,
 314                                         struct encode_state *encode_state,
 315                                         struct intel_encoder_context *encoder_context)
 316 {
 317     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 318     // unsigned char *constant_buffer;
 319     unsigned int *vme_state_message;
 320     int mv_num = 32;
 321     if (vme_context->h264_level >= 30) {
 322         mv_num = 16;
 323         if (vme_context->h264_level >= 31)
 324                 mv_num = 8;
 325     }
 326
 327     dri_bo_map(vme_context->gpe_context.curbe.bo, 1);
 328     assert(vme_context->gpe_context.curbe.bo->virtual);
 329     // constant_buffer = vme_context->curbe.bo->virtual;
 330     vme_state_message = (unsigned int *)vme_context->gpe_context.curbe.bo->virtual;
 331     vme_state_message[31] = mv_num;
 332
 333     /*TODO copy buffer into CURB*/
 334
 335     dri_bo_unmap( vme_context->gpe_context.curbe.bo);
 336
 337     return VA_STATUS_SUCCESS;
 338 }
 339
 340 static const unsigned int intra_mb_mode_cost_table[] = {
 341     0x31110001, // for qp0
 342     0x09110001, // for qp1
 343     0x15030001, // for qp2
 344     0x0b030001, // for qp3
 345     0x0d030011, // for qp4
 346     0x17210011, // for qp5
 347     0x41210011, // for qp6
 348     0x19210011, // for qp7
 349     0x25050003, // for qp8
 350     0x1b130003, // for qp9
 351     0x1d130003, // for qp10
 352     0x27070021, // for qp11
 353     0x51310021, // for qp12
 354     0x29090021, // for qp13
 355     0x35150005, // for qp14
 356     0x2b0b0013, // for qp15
 357     0x2d0d0013, // for qp16
 358     0x37170007, // for qp17
 359     0x61410031, // for qp18
 360     0x39190009, // for qp19
 361     0x45250015, // for qp20
 362     0x3b1b000b, // for qp21
 363     0x3d1d000d, // for qp22
 364     0x47270017, // for qp23
 365     0x71510041, // for qp24 ! center for qp=0..30
 366     0x49290019, // for qp25
 367     0x55350025, // for qp26
 368     0x4b2b001b, // for qp27
 369     0x4d2d001d, // for qp28
 370     0x57370027, // for qp29
 371     0x81610051, // for qp30
 372     0x57270017, // for qp31
 373     0x81510041, // for qp32 ! center for qp=31..51
 374     0x59290019, // for qp33
 375     0x65350025, // for qp34
 376     0x5b2b001b, // for qp35
 377     0x5d2d001d, // for qp36
 378     0x67370027, // for qp37
 379     0x91610051, // for qp38
 380     0x69390029, // for qp39
 381     0x75450035, // for qp40
 382     0x6b3b002b, // for qp41
 383     0x6d3d002d, // for qp42
 384     0x77470037, // for qp43
 385     0xa1710061, // for qp44
 386     0x79490039, // for qp45
 387     0x85550045, // for qp46
 388     0x7b4b003b, // for qp47
 389     0x7d4d003d, // for qp48
 390     0x87570047, // for qp49
 391     0xb1810071, // for qp50
 392     0x89590049  // for qp51
 393 };
 394
 395 static void gen6_vme_state_setup_fixup(VADriverContextP ctx,
 396                                        struct encode_state *encode_state,
 397                                        struct intel_encoder_context *encoder_context,
 398                                        unsigned int *vme_state_message)
 399 {
 400     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 401     VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 402     VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
 403
 404     if (slice_param->slice_type != SLICE_TYPE_I &&
 405         slice_param->slice_type != SLICE_TYPE_SI)
 406         return;
 407     if (encoder_context->rate_control_mode == VA_RC_CQP)
 408         vme_state_message[16] = intra_mb_mode_cost_table[pic_param->pic_init_qp + slice_param->slice_qp_delta];
 409     else
 410         vme_state_message[16] = intra_mb_mode_cost_table[mfc_context->bit_rate_control_context[slice_param->slice_type].QpPrimeY];
 411 }
 412
 413 static VAStatus gen6_vme_vme_state_setup(VADriverContextP ctx,
 414                                          struct encode_state *encode_state,
 415                                          int is_intra,
 416                                          struct intel_encoder_context *encoder_context)
 417 {
 418     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 419     unsigned int *vme_state_message;
 420     int i;
 421
 422     //building VME state message
 423     dri_bo_map(vme_context->vme_state.bo, 1);
 424     assert(vme_context->vme_state.bo->virtual);
 425     vme_state_message = (unsigned int *)vme_context->vme_state.bo->virtual;
 426
 427     vme_state_message[0] = 0x01010101;
 428     vme_state_message[1] = 0x10010101;
 429     vme_state_message[2] = 0x0F0F0F0F;
 430     vme_state_message[3] = 0x100F0F0F;
 431     vme_state_message[4] = 0x01010101;
 432     vme_state_message[5] = 0x10010101;
 433     vme_state_message[6] = 0x0F0F0F0F;
 434     vme_state_message[7] = 0x100F0F0F;
 435     vme_state_message[8] = 0x01010101;
 436     vme_state_message[9] = 0x10010101;
 437     vme_state_message[10] = 0x0F0F0F0F;
 438     vme_state_message[11] = 0x000F0F0F;
 439     vme_state_message[12] = 0x00;
 440     vme_state_message[13] = 0x00;
 441
 442     vme_state_message[14] = 0x4a4a;
 443     vme_state_message[15] = 0x0;
 444     vme_state_message[16] = 0x4a4a4a4a;
 445     vme_state_message[17] = 0x4a4a4a4a;
 446     vme_state_message[18] = 0x21110100;
 447     vme_state_message[19] = 0x61514131;
 448
 449     for(i = 20; i < 32; i++) {
 450         vme_state_message[i] = 0;
 451     }
 452     //vme_state_message[16] = 0x42424242;                       //cost function LUT set 0 for Intra
 453
 454     gen6_vme_state_setup_fixup(ctx, encode_state, encoder_context, vme_state_message);
 455
 456     dri_bo_unmap( vme_context->vme_state.bo);
 457     return VA_STATUS_SUCCESS;
 458 }
 459
 460 static void
 461 gen6_vme_fill_vme_batchbuffer(VADriverContextP ctx,
 462                               struct encode_state *encode_state,
 463                               int mb_width, int mb_height,
 464                               int kernel,
 465                               int transform_8x8_mode_flag,
 466                               struct intel_encoder_context *encoder_context)
 467 {
 468     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 469     int number_mb_cmds;
 470     int mb_x = 0, mb_y = 0;
 471     int i, s;
 472     unsigned int *command_ptr;
 473
 474     dri_bo_map(vme_context->vme_batchbuffer.bo, 1);
 475     command_ptr = vme_context->vme_batchbuffer.bo->virtual;
 476
 477     for (s = 0; s < encode_state->num_slice_params_ext; s++) {
 478         VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[s]->buffer;
 479         int slice_mb_begin = pSliceParameter->macroblock_address;
 480         int slice_mb_number = pSliceParameter->num_macroblocks;
 481
 482         for (i = 0; i < slice_mb_number;  ) {
 483             int mb_count = i + slice_mb_begin;
 484             mb_x = mb_count % mb_width;
 485             mb_y = mb_count / mb_width;
 486             if( i == 0 ) {
 487                 number_mb_cmds = mb_width;          // we must mark the slice edge.
 488             } else if ( (i + 128 ) <= slice_mb_number) {
 489                 number_mb_cmds = 128;
 490             } else {
 491                 number_mb_cmds = slice_mb_number - i;
 492             }
 493
 494             *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
 495             *command_ptr++ = kernel;
 496             *command_ptr++ = 0;
 497             *command_ptr++ = 0;
 498             *command_ptr++ = 0;
 499             *command_ptr++ = 0;
 500
 501             /*inline data */
 502             *command_ptr++ = (mb_width << 16 | mb_y << 8 | mb_x);
 503             *command_ptr++ = (number_mb_cmds << 16 | transform_8x8_mode_flag | ((i==0) << 1));
 504
 505             i += number_mb_cmds;
 506         }
 507     }
 508
 509     *command_ptr++ = 0;
 510     *command_ptr++ = MI_BATCH_BUFFER_END;
 511
 512     dri_bo_unmap(vme_context->vme_batchbuffer.bo);
 513 }
 514
 515 static void gen6_vme_media_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 516 {
 517     struct i965_driver_data *i965 = i965_driver_data(ctx);
 518     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 519     dri_bo *bo;
 520
 521     i965_gpe_context_init(ctx, &vme_context->gpe_context);
 522
 523     /* VME output buffer */
 524     dri_bo_unreference(vme_context->vme_output.bo);
 525     vme_context->vme_output.bo = NULL;
 526
 527     dri_bo_unreference(vme_context->vme_batchbuffer.bo);
 528     vme_context->vme_batchbuffer.bo = NULL;
 529
 530     /* VME state */
 531     dri_bo_unreference(vme_context->vme_state.bo);
 532     bo = dri_bo_alloc(i965->intel.bufmgr,
 533                       "Buffer",
 534                       1024*16, 64);
 535     assert(bo);
 536     vme_context->vme_state.bo = bo;
 537 }
 538
 539 static void gen6_vme_pipeline_programing(VADriverContextP ctx,
 540                                          struct encode_state *encode_state,
 541                                          struct intel_encoder_context *encoder_context)
 542 {
 543     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 544     struct intel_batchbuffer *batch = encoder_context->base.batch;
 545     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 546     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
 547     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 548     int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
 549     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 550     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 551
 552     gen6_vme_fill_vme_batchbuffer(ctx,
 553                                   encode_state,
 554                                   width_in_mbs, height_in_mbs,
 555                                   is_intra ? VME_INTRA_SHADER : VME_INTER_SHADER,
 556                                   pPicParameter->pic_fields.bits.transform_8x8_mode_flag,
 557                                   encoder_context);
 558
 559     intel_batchbuffer_start_atomic(batch, 0x1000);
 560     gen6_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch);
 561     BEGIN_BATCH(batch, 2);
 562     OUT_BATCH(batch, MI_BATCH_BUFFER_START | (2 << 6));
 563     OUT_RELOC(batch,
 564               vme_context->vme_batchbuffer.bo,
 565               I915_GEM_DOMAIN_COMMAND, 0,
 566               0);
 567     ADVANCE_BATCH(batch);
 568
 569     intel_batchbuffer_end_atomic(batch);
 570 }
 571
 572 static VAStatus gen6_vme_prepare(VADriverContextP ctx,
 573                                  struct encode_state *encode_state,
 574                                  struct intel_encoder_context *encoder_context)
 575 {
 576     VAStatus vaStatus = VA_STATUS_SUCCESS;
 577     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
 578     int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
 579     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 580     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 581
 582     if (!vme_context->h264_level ||
 583                 (vme_context->h264_level != pSequenceParameter->level_idc)) {
 584         vme_context->h264_level = pSequenceParameter->level_idc;
 585     }
 586     /*Setup all the memory object*/
 587     gen6_vme_surface_setup(ctx, encode_state, is_intra, encoder_context);
 588     gen6_vme_interface_setup(ctx, encode_state, encoder_context);
 589     gen6_vme_constant_setup(ctx, encode_state, encoder_context);
 590     gen6_vme_vme_state_setup(ctx, encode_state, is_intra, encoder_context);
 591
 592     /*Programing media pipeline*/
 593     gen6_vme_pipeline_programing(ctx, encode_state, encoder_context);
 594
 595     return vaStatus;
 596 }
 597
 598 static VAStatus gen6_vme_run(VADriverContextP ctx,
 599                              struct encode_state *encode_state,
 600                              struct intel_encoder_context *encoder_context)
 601 {
 602     struct intel_batchbuffer *batch = encoder_context->base.batch;
 603
 604     intel_batchbuffer_flush(batch);
 605
 606     return VA_STATUS_SUCCESS;
 607 }
 608
 609 static VAStatus gen6_vme_stop(VADriverContextP ctx,
 610                               struct encode_state *encode_state,
 611                               struct intel_encoder_context *encoder_context)
 612 {
 613     return VA_STATUS_SUCCESS;
 614 }
 615
 616 static VAStatus
 617 gen6_vme_pipeline(VADriverContextP ctx,
 618                   VAProfile profile,
 619                   struct encode_state *encode_state,
 620                   struct intel_encoder_context *encoder_context)
 621 {
 622     gen6_vme_media_init(ctx, encoder_context);
 623     gen6_vme_prepare(ctx, encode_state, encoder_context);
 624     gen6_vme_run(ctx, encode_state, encoder_context);
 625     gen6_vme_stop(ctx, encode_state, encoder_context);
 626
 627     return VA_STATUS_SUCCESS;
 628 }
 629
 630 static void
 631 gen6_vme_context_destroy(void *context)
 632 {
 633     struct gen6_vme_context *vme_context = context;
 634
 635     i965_gpe_context_destroy(&vme_context->gpe_context);
 636
 637     dri_bo_unreference(vme_context->vme_output.bo);
 638     vme_context->vme_output.bo = NULL;
 639
 640     dri_bo_unreference(vme_context->vme_state.bo);
 641     vme_context->vme_state.bo = NULL;
 642
 643     dri_bo_unreference(vme_context->vme_batchbuffer.bo);
 644     vme_context->vme_batchbuffer.bo = NULL;
 645
 646     free(vme_context);
 647 }
 648
 649 Bool gen6_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 650 {
 651     struct i965_driver_data *i965 = i965_driver_data(ctx);
 652     struct gen6_vme_context *vme_context = calloc(1, sizeof(struct gen6_vme_context));
 653
 654     vme_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6;
 655
 656     vme_context->gpe_context.idrt.max_entries = MAX_INTERFACE_DESC_GEN6;
 657     vme_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data);
 658
 659     vme_context->gpe_context.curbe.length = CURBE_TOTAL_DATA_LENGTH;
 660
 661     vme_context->gpe_context.vfe_state.max_num_threads = 60 - 1;
 662     vme_context->gpe_context.vfe_state.num_urb_entries = 16;
 663     vme_context->gpe_context.vfe_state.gpgpu_mode = 0;
 664     vme_context->gpe_context.vfe_state.urb_entry_size = 59 - 1;
 665     vme_context->gpe_context.vfe_state.curbe_allocation_size = CURBE_ALLOCATION_SIZE - 1;
 666
 667     if (IS_GEN7(i965->intel.device_id)) {
 668         i965_gpe_load_kernels(ctx,
 669                               &vme_context->gpe_context,
 670                               gen7_vme_kernels,
 671                               GEN6_VME_KERNEL_NUMBER);
 672         vme_context->vme_surface2_setup = gen7_gpe_surface2_setup;
 673         vme_context->vme_media_rw_surface_setup = gen7_gpe_media_rw_surface_setup;
 674         vme_context->vme_buffer_suface_setup = gen7_gpe_buffer_suface_setup;
 675     } else {
 676         i965_gpe_load_kernels(ctx,
 677                               &vme_context->gpe_context,
 678                               gen6_vme_kernels,
 679                               GEN6_VME_KERNEL_NUMBER);
 680         vme_context->vme_surface2_setup = i965_gpe_surface2_setup;
 681         vme_context->vme_media_rw_surface_setup = i965_gpe_media_rw_surface_setup;
 682         vme_context->vme_buffer_suface_setup = i965_gpe_buffer_suface_setup;
 683     }
 684
 685     encoder_context->vme_context = vme_context;
 686     encoder_context->vme_context_destroy = gen6_vme_context_destroy;
 687     encoder_context->vme_pipeline = gen6_vme_pipeline;
 688
 689     return True;
 690 }