src/gen6_vme.c

   1 /*
   2  * Copyright © 2010-2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Zhou Chang <chang.zhou@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <assert.h>
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_driver.h"
  36
  37 #include "i965_defines.h"
  38 #include "i965_drv_video.h"
  39 #include "i965_encoder.h"
  40 #include "gen6_vme.h"
  41 #include "gen6_mfc.h"
  42
  43 #define SURFACE_STATE_PADDED_SIZE_0_GEN7        ALIGN(sizeof(struct gen7_surface_state), 32)
  44 #define SURFACE_STATE_PADDED_SIZE_1_GEN7        ALIGN(sizeof(struct gen7_surface_state2), 32)
  45 #define SURFACE_STATE_PADDED_SIZE_GEN7          MAX(SURFACE_STATE_PADDED_SIZE_0_GEN7, SURFACE_STATE_PADDED_SIZE_1_GEN7)
  46
  47 #define SURFACE_STATE_PADDED_SIZE_0_GEN6        ALIGN(sizeof(struct i965_surface_state), 32)
  48 #define SURFACE_STATE_PADDED_SIZE_1_GEN6        ALIGN(sizeof(struct i965_surface_state2), 32)
  49 #define SURFACE_STATE_PADDED_SIZE_GEN6          MAX(SURFACE_STATE_PADDED_SIZE_0_GEN6, SURFACE_STATE_PADDED_SIZE_1_GEN6)
  50
  51 #define SURFACE_STATE_PADDED_SIZE               MAX(SURFACE_STATE_PADDED_SIZE_GEN6, SURFACE_STATE_PADDED_SIZE_GEN7)
  52 #define SURFACE_STATE_OFFSET(index)             (SURFACE_STATE_PADDED_SIZE * index)
  53 #define BINDING_TABLE_OFFSET(index)             (SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * index)
  54
  55 #define CURBE_ALLOCATION_SIZE   37              /* in 256-bit */
  56 #define CURBE_TOTAL_DATA_LENGTH (4 * 32)        /* in byte, it should be less than or equal to CURBE_ALLOCATION_SIZE * 32 */
  57 #define CURBE_URB_ENTRY_LENGTH  4               /* in 256-bit, it should be less than or equal to CURBE_TOTAL_DATA_LENGTH / 32 */
  58
  59 enum VIDEO_CODING_TYPE{
  60     VIDEO_CODING_AVC = 0,
  61     VIDEO_CODING_SUM
  62 };
  63
  64 enum AVC_VME_KERNEL_TYPE{
  65     AVC_VME_INTRA_SHADER = 0,
  66     AVC_VME_INTER_SHADER,
  67     AVC_VME_BATCHBUFFER,
  68     AVC_VME_KERNEL_SUM
  69 };
  70
  71 static const uint32_t gen6_vme_intra_frame[][4] = {
  72 #include "shaders/vme/intra_frame.g6b"
  73 };
  74
  75 static const uint32_t gen6_vme_inter_frame[][4] = {
  76 #include "shaders/vme/inter_frame.g6b"
  77 };
  78
  79 static const uint32_t gen6_vme_batchbuffer[][4] = {
  80 #include "shaders/vme/batchbuffer.g6b"
  81 };
  82
  83 static struct i965_kernel gen6_vme_kernels[] = {
  84     {
  85         "AVC VME Intra Frame",
  86         AVC_VME_INTRA_SHADER,                   /*index*/
  87         gen6_vme_intra_frame,
  88         sizeof(gen6_vme_intra_frame),
  89         NULL
  90     },
  91     {
  92         "AVC VME inter Frame",
  93         AVC_VME_INTER_SHADER,
  94         gen6_vme_inter_frame,
  95         sizeof(gen6_vme_inter_frame),
  96         NULL
  97     },
  98     {
  99         "AVC VME BATCHBUFFER",
 100         AVC_VME_BATCHBUFFER,
 101         gen6_vme_batchbuffer,
 102         sizeof(gen6_vme_batchbuffer),
 103         NULL
 104     },
 105 };
 106
 107 /* only used for VME source surface state */
 108 static void
 109 gen6_vme_source_surface_state(VADriverContextP ctx,
 110                               int index,
 111                               struct object_surface *obj_surface,
 112                               struct intel_encoder_context *encoder_context)
 113 {
 114     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 115
 116     vme_context->vme_surface2_setup(ctx,
 117                                     &vme_context->gpe_context,
 118                                     obj_surface,
 119                                     BINDING_TABLE_OFFSET(index),
 120                                     SURFACE_STATE_OFFSET(index));
 121 }
 122
 123 static void
 124 gen6_vme_media_source_surface_state(VADriverContextP ctx,
 125                                     int index,
 126                                     struct object_surface *obj_surface,
 127                                     struct intel_encoder_context *encoder_context)
 128 {
 129     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 130
 131     vme_context->vme_media_rw_surface_setup(ctx,
 132                                             &vme_context->gpe_context,
 133                                             obj_surface,
 134                                             BINDING_TABLE_OFFSET(index),
 135                                             SURFACE_STATE_OFFSET(index));
 136 }
 137
 138 static void
 139 gen6_vme_output_buffer_setup(VADriverContextP ctx,
 140                              struct encode_state *encode_state,
 141                              int index,
 142                              struct intel_encoder_context *encoder_context)
 143
 144 {
 145     struct i965_driver_data *i965 = i965_driver_data(ctx);
 146     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 147     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 148     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
 149     int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
 150     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 151     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 152
 153     vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs;
 154     vme_context->vme_output.pitch = 16; /* in bytes, always 16 */
 155
 156     if (is_intra)
 157         vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES;
 158     else
 159         vme_context->vme_output.size_block = INTER_VME_OUTPUT_IN_BYTES;
 160
 161     vme_context->vme_output.bo = dri_bo_alloc(i965->intel.bufmgr,
 162                                               "VME output buffer",
 163                                               vme_context->vme_output.num_blocks * vme_context->vme_output.size_block,
 164                                               0x1000);
 165     assert(vme_context->vme_output.bo);
 166     vme_context->vme_buffer_suface_setup(ctx,
 167                                          &vme_context->gpe_context,
 168                                          &vme_context->vme_output,
 169                                          BINDING_TABLE_OFFSET(index),
 170                                          SURFACE_STATE_OFFSET(index));
 171 }
 172
 173 static void
 174 gen6_vme_output_vme_batchbuffer_setup(VADriverContextP ctx,
 175                                       struct encode_state *encode_state,
 176                                       int index,
 177                                       struct intel_encoder_context *encoder_context)
 178
 179 {
 180     struct i965_driver_data *i965 = i965_driver_data(ctx);
 181     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 182     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 183     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 184     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 185
 186     vme_context->vme_batchbuffer.num_blocks = width_in_mbs * height_in_mbs + 1;
 187     vme_context->vme_batchbuffer.size_block = 32; /* 2 OWORDs */
 188     vme_context->vme_batchbuffer.pitch = 16;
 189     vme_context->vme_batchbuffer.bo = dri_bo_alloc(i965->intel.bufmgr,
 190                                                    "VME batchbuffer",
 191                                                    vme_context->vme_batchbuffer.num_blocks * vme_context->vme_batchbuffer.size_block,
 192                                                    0x1000);
 193     vme_context->vme_buffer_suface_setup(ctx,
 194                                          &vme_context->gpe_context,
 195                                          &vme_context->vme_batchbuffer,
 196                                          BINDING_TABLE_OFFSET(index),
 197                                          SURFACE_STATE_OFFSET(index));
 198 }
 199
 200 static VAStatus
 201 gen6_vme_surface_setup(VADriverContextP ctx,
 202                        struct encode_state *encode_state,
 203                        int is_intra,
 204                        struct intel_encoder_context *encoder_context)
 205 {
 206     struct object_surface *obj_surface;
 207     struct i965_driver_data *i965 = i965_driver_data(ctx);
 208
 209     /*Setup surfaces state*/
 210     /* current picture for encoding */
 211     obj_surface = encode_state->input_yuv_object;
 212     gen6_vme_source_surface_state(ctx, 0, obj_surface, encoder_context);
 213     gen6_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context);
 214
 215     if (!is_intra) {
 216         VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
 217         int slice_type;
 218         struct object_surface *slice_obj_surface;
 219         int ref_surface_id;
 220
 221         slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
 222
 223         if (slice_type == SLICE_TYPE_P || slice_type == SLICE_TYPE_B) {
 224                 slice_obj_surface = NULL;
 225                 ref_surface_id = slice_param->RefPicList0[0].picture_id;
 226                 if (ref_surface_id != 0 && ref_surface_id != VA_INVALID_SURFACE) {
 227                         slice_obj_surface = SURFACE(ref_surface_id);
 228                 }
 229                 if (slice_obj_surface && slice_obj_surface->bo) {
 230                         obj_surface = slice_obj_surface;
 231                 } else {
 232                         obj_surface = encode_state->reference_objects[0];
 233                 }
 234                 /* reference 0 */
 235                 if (obj_surface && obj_surface->bo)
 236                     gen6_vme_source_surface_state(ctx, 1, obj_surface, encoder_context);
 237         }
 238         if (slice_type == SLICE_TYPE_B) {
 239                 /* reference 1 */
 240                 slice_obj_surface = NULL;
 241                 ref_surface_id = slice_param->RefPicList1[0].picture_id;
 242                 if (ref_surface_id != 0 && ref_surface_id != VA_INVALID_SURFACE) {
 243                         slice_obj_surface = SURFACE(ref_surface_id);
 244                 }
 245                 if (slice_obj_surface && slice_obj_surface->bo) {
 246                         obj_surface = slice_obj_surface;
 247                 } else {
 248                         obj_surface = encode_state->reference_objects[0];
 249                 }
 250
 251                 obj_surface = encode_state->reference_objects[1];
 252                 if (obj_surface && obj_surface->bo)
 253                         gen6_vme_source_surface_state(ctx, 2, obj_surface, encoder_context);
 254         }
 255     }
 256
 257     /* VME output */
 258     gen6_vme_output_buffer_setup(ctx, encode_state, 3, encoder_context);
 259     gen6_vme_output_vme_batchbuffer_setup(ctx, encode_state, 5, encoder_context);
 260
 261     return VA_STATUS_SUCCESS;
 262 }
 263
 264 static VAStatus gen6_vme_interface_setup(VADriverContextP ctx,
 265                                          struct encode_state *encode_state,
 266                                          struct intel_encoder_context *encoder_context)
 267 {
 268     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 269     struct gen6_interface_descriptor_data *desc;
 270     int i;
 271     dri_bo *bo;
 272
 273     bo = vme_context->gpe_context.idrt.bo;
 274     dri_bo_map(bo, 1);
 275     assert(bo->virtual);
 276     desc = bo->virtual;
 277
 278     for (i = 0; i < vme_context->vme_kernel_sum; i++) {
 279         struct i965_kernel *kernel;
 280         kernel = &vme_context->gpe_context.kernels[i];
 281         assert(sizeof(*desc) == 32);
 282         /*Setup the descritor table*/
 283         memset(desc, 0, sizeof(*desc));
 284         desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6);
 285         desc->desc2.sampler_count = 1; /* FIXME: */
 286         desc->desc2.sampler_state_pointer = (vme_context->vme_state.bo->offset >> 5);
 287         desc->desc3.binding_table_entry_count = 1; /* FIXME: */
 288         desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5);
 289         desc->desc4.constant_urb_entry_read_offset = 0;
 290         desc->desc4.constant_urb_entry_read_length = CURBE_URB_ENTRY_LENGTH;
 291
 292         /*kernel start*/
 293         dri_bo_emit_reloc(bo,
 294                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 295                           0,
 296                           i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0),
 297                           kernel->bo);
 298         /*Sampler State(VME state pointer)*/
 299         dri_bo_emit_reloc(bo,
 300                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 301                           (1 << 2),                                                                     //
 302                           i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc2),
 303                           vme_context->vme_state.bo);
 304         desc++;
 305     }
 306     dri_bo_unmap(bo);
 307
 308     return VA_STATUS_SUCCESS;
 309 }
 310
 311 static VAStatus gen6_vme_constant_setup(VADriverContextP ctx,
 312                                         struct encode_state *encode_state,
 313                                         struct intel_encoder_context *encoder_context)
 314 {
 315     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 316     // unsigned char *constant_buffer;
 317     unsigned int *vme_state_message;
 318     int mv_num = 32;
 319     if (vme_context->h264_level >= 30) {
 320         mv_num = 16;
 321         if (vme_context->h264_level >= 31)
 322                 mv_num = 8;
 323     }
 324
 325     dri_bo_map(vme_context->gpe_context.curbe.bo, 1);
 326     assert(vme_context->gpe_context.curbe.bo->virtual);
 327     // constant_buffer = vme_context->curbe.bo->virtual;
 328     vme_state_message = (unsigned int *)vme_context->gpe_context.curbe.bo->virtual;
 329     vme_state_message[31] = mv_num;
 330
 331     /*TODO copy buffer into CURB*/
 332
 333     dri_bo_unmap( vme_context->gpe_context.curbe.bo);
 334
 335     return VA_STATUS_SUCCESS;
 336 }
 337
 338 static const unsigned int intra_mb_mode_cost_table[] = {
 339     0x31110001, // for qp0
 340     0x09110001, // for qp1
 341     0x15030001, // for qp2
 342     0x0b030001, // for qp3
 343     0x0d030011, // for qp4
 344     0x17210011, // for qp5
 345     0x41210011, // for qp6
 346     0x19210011, // for qp7
 347     0x25050003, // for qp8
 348     0x1b130003, // for qp9
 349     0x1d130003, // for qp10
 350     0x27070021, // for qp11
 351     0x51310021, // for qp12
 352     0x29090021, // for qp13
 353     0x35150005, // for qp14
 354     0x2b0b0013, // for qp15
 355     0x2d0d0013, // for qp16
 356     0x37170007, // for qp17
 357     0x61410031, // for qp18
 358     0x39190009, // for qp19
 359     0x45250015, // for qp20
 360     0x3b1b000b, // for qp21
 361     0x3d1d000d, // for qp22
 362     0x47270017, // for qp23
 363     0x71510041, // for qp24 ! center for qp=0..30
 364     0x49290019, // for qp25
 365     0x55350025, // for qp26
 366     0x4b2b001b, // for qp27
 367     0x4d2d001d, // for qp28
 368     0x57370027, // for qp29
 369     0x81610051, // for qp30
 370     0x57270017, // for qp31
 371     0x81510041, // for qp32 ! center for qp=31..51
 372     0x59290019, // for qp33
 373     0x65350025, // for qp34
 374     0x5b2b001b, // for qp35
 375     0x5d2d001d, // for qp36
 376     0x67370027, // for qp37
 377     0x91610051, // for qp38
 378     0x69390029, // for qp39
 379     0x75450035, // for qp40
 380     0x6b3b002b, // for qp41
 381     0x6d3d002d, // for qp42
 382     0x77470037, // for qp43
 383     0xa1710061, // for qp44
 384     0x79490039, // for qp45
 385     0x85550045, // for qp46
 386     0x7b4b003b, // for qp47
 387     0x7d4d003d, // for qp48
 388     0x87570047, // for qp49
 389     0xb1810071, // for qp50
 390     0x89590049  // for qp51
 391 };
 392
 393 static void gen6_vme_state_setup_fixup(VADriverContextP ctx,
 394                                        struct encode_state *encode_state,
 395                                        struct intel_encoder_context *encoder_context,
 396                                        unsigned int *vme_state_message)
 397 {
 398     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 399     VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 400     VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
 401
 402     if (slice_param->slice_type != SLICE_TYPE_I &&
 403         slice_param->slice_type != SLICE_TYPE_SI)
 404         return;
 405
 406     if (encoder_context->rate_control_mode == VA_RC_CQP)
 407         vme_state_message[16] = intra_mb_mode_cost_table[pic_param->pic_init_qp + slice_param->slice_qp_delta];
 408     else
 409         vme_state_message[16] = intra_mb_mode_cost_table[mfc_context->bit_rate_control_context[SLICE_TYPE_I].QpPrimeY];
 410 }
 411
 412 static VAStatus gen6_vme_vme_state_setup(VADriverContextP ctx,
 413                                          struct encode_state *encode_state,
 414                                          int is_intra,
 415                                          struct intel_encoder_context *encoder_context)
 416 {
 417     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 418     unsigned int *vme_state_message;
 419     int i;
 420
 421     //building VME state message
 422     dri_bo_map(vme_context->vme_state.bo, 1);
 423     assert(vme_context->vme_state.bo->virtual);
 424     vme_state_message = (unsigned int *)vme_context->vme_state.bo->virtual;
 425
 426     vme_state_message[0] = 0x01010101;
 427     vme_state_message[1] = 0x10010101;
 428     vme_state_message[2] = 0x0F0F0F0F;
 429     vme_state_message[3] = 0x100F0F0F;
 430     vme_state_message[4] = 0x01010101;
 431     vme_state_message[5] = 0x10010101;
 432     vme_state_message[6] = 0x0F0F0F0F;
 433     vme_state_message[7] = 0x100F0F0F;
 434     vme_state_message[8] = 0x01010101;
 435     vme_state_message[9] = 0x10010101;
 436     vme_state_message[10] = 0x0F0F0F0F;
 437     vme_state_message[11] = 0x000F0F0F;
 438     vme_state_message[12] = 0x00;
 439     vme_state_message[13] = 0x00;
 440
 441     vme_state_message[14] = 0x4a4a;
 442     vme_state_message[15] = 0x0;
 443     vme_state_message[16] = 0x4a4a4a4a;
 444     vme_state_message[17] = 0x4a4a4a4a;
 445     vme_state_message[18] = 0x21110100;
 446     vme_state_message[19] = 0x61514131;
 447
 448     for(i = 20; i < 32; i++) {
 449         vme_state_message[i] = 0;
 450     }
 451     //vme_state_message[16] = 0x42424242;                       //cost function LUT set 0 for Intra
 452
 453     gen6_vme_state_setup_fixup(ctx, encode_state, encoder_context, vme_state_message);
 454
 455     dri_bo_unmap( vme_context->vme_state.bo);
 456     return VA_STATUS_SUCCESS;
 457 }
 458
 459 static void
 460 gen6_vme_fill_vme_batchbuffer(VADriverContextP ctx,
 461                               struct encode_state *encode_state,
 462                               int mb_width, int mb_height,
 463                               int kernel,
 464                               int transform_8x8_mode_flag,
 465                               struct intel_encoder_context *encoder_context)
 466 {
 467     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 468     int number_mb_cmds;
 469     int mb_x = 0, mb_y = 0;
 470     int i, s;
 471     unsigned int *command_ptr;
 472
 473     dri_bo_map(vme_context->vme_batchbuffer.bo, 1);
 474     command_ptr = vme_context->vme_batchbuffer.bo->virtual;
 475
 476     for (s = 0; s < encode_state->num_slice_params_ext; s++) {
 477         VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[s]->buffer;
 478         int slice_mb_begin = pSliceParameter->macroblock_address;
 479         int slice_mb_number = pSliceParameter->num_macroblocks;
 480
 481         for (i = 0; i < slice_mb_number;  ) {
 482             int mb_count = i + slice_mb_begin;
 483             mb_x = mb_count % mb_width;
 484             mb_y = mb_count / mb_width;
 485             if( i == 0 ) {
 486                 number_mb_cmds = mb_width;          // we must mark the slice edge.
 487             } else if ( (i + 128 ) <= slice_mb_number) {
 488                 number_mb_cmds = 128;
 489             } else {
 490                 number_mb_cmds = slice_mb_number - i;
 491             }
 492
 493             *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
 494             *command_ptr++ = kernel;
 495             *command_ptr++ = 0;
 496             *command_ptr++ = 0;
 497             *command_ptr++ = 0;
 498             *command_ptr++ = 0;
 499
 500             /*inline data */
 501             *command_ptr++ = (mb_width << 16 | mb_y << 8 | mb_x);
 502             *command_ptr++ = (number_mb_cmds << 16 | transform_8x8_mode_flag | ((i==0) << 1));
 503
 504             i += number_mb_cmds;
 505         }
 506     }
 507
 508     *command_ptr++ = 0;
 509     *command_ptr++ = MI_BATCH_BUFFER_END;
 510
 511     dri_bo_unmap(vme_context->vme_batchbuffer.bo);
 512 }
 513
 514 static void gen6_vme_media_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 515 {
 516     struct i965_driver_data *i965 = i965_driver_data(ctx);
 517     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 518     dri_bo *bo;
 519
 520     i965_gpe_context_init(ctx, &vme_context->gpe_context);
 521
 522     /* VME output buffer */
 523     dri_bo_unreference(vme_context->vme_output.bo);
 524     vme_context->vme_output.bo = NULL;
 525
 526     dri_bo_unreference(vme_context->vme_batchbuffer.bo);
 527     vme_context->vme_batchbuffer.bo = NULL;
 528
 529     /* VME state */
 530     dri_bo_unreference(vme_context->vme_state.bo);
 531     bo = dri_bo_alloc(i965->intel.bufmgr,
 532                       "Buffer",
 533                       1024*16, 64);
 534     assert(bo);
 535     vme_context->vme_state.bo = bo;
 536 }
 537
 538 static void gen6_vme_pipeline_programing(VADriverContextP ctx,
 539                                          struct encode_state *encode_state,
 540                                          struct intel_encoder_context *encoder_context)
 541 {
 542     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 543     struct intel_batchbuffer *batch = encoder_context->base.batch;
 544     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 545     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
 546     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 547     int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
 548     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 549     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 550
 551     gen6_vme_fill_vme_batchbuffer(ctx,
 552                                   encode_state,
 553                                   width_in_mbs, height_in_mbs,
 554                                   is_intra ? AVC_VME_INTRA_SHADER : AVC_VME_INTER_SHADER,
 555                                   pPicParameter->pic_fields.bits.transform_8x8_mode_flag,
 556                                   encoder_context);
 557
 558     intel_batchbuffer_start_atomic(batch, 0x1000);
 559     gen6_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch);
 560     BEGIN_BATCH(batch, 2);
 561     OUT_BATCH(batch, MI_BATCH_BUFFER_START | (2 << 6));
 562     OUT_RELOC(batch,
 563               vme_context->vme_batchbuffer.bo,
 564               I915_GEM_DOMAIN_COMMAND, 0,
 565               0);
 566     ADVANCE_BATCH(batch);
 567
 568     intel_batchbuffer_end_atomic(batch);
 569 }
 570
 571 static VAStatus gen6_vme_prepare(VADriverContextP ctx,
 572                                  struct encode_state *encode_state,
 573                                  struct intel_encoder_context *encoder_context)
 574 {
 575     VAStatus vaStatus = VA_STATUS_SUCCESS;
 576     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
 577     int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
 578     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 579     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 580
 581     if (!vme_context->h264_level ||
 582                 (vme_context->h264_level != pSequenceParameter->level_idc)) {
 583         vme_context->h264_level = pSequenceParameter->level_idc;
 584     }
 585     /*Setup all the memory object*/
 586     gen6_vme_surface_setup(ctx, encode_state, is_intra, encoder_context);
 587     gen6_vme_interface_setup(ctx, encode_state, encoder_context);
 588     gen6_vme_constant_setup(ctx, encode_state, encoder_context);
 589     gen6_vme_vme_state_setup(ctx, encode_state, is_intra, encoder_context);
 590
 591     /*Programing media pipeline*/
 592     gen6_vme_pipeline_programing(ctx, encode_state, encoder_context);
 593
 594     return vaStatus;
 595 }
 596
 597 static VAStatus gen6_vme_run(VADriverContextP ctx,
 598                              struct encode_state *encode_state,
 599                              struct intel_encoder_context *encoder_context)
 600 {
 601     struct intel_batchbuffer *batch = encoder_context->base.batch;
 602
 603     intel_batchbuffer_flush(batch);
 604
 605     return VA_STATUS_SUCCESS;
 606 }
 607
 608 static VAStatus gen6_vme_stop(VADriverContextP ctx,
 609                               struct encode_state *encode_state,
 610                               struct intel_encoder_context *encoder_context)
 611 {
 612     return VA_STATUS_SUCCESS;
 613 }
 614
 615 static VAStatus
 616 gen6_vme_pipeline(VADriverContextP ctx,
 617                   VAProfile profile,
 618                   struct encode_state *encode_state,
 619                   struct intel_encoder_context *encoder_context)
 620 {
 621     gen6_vme_media_init(ctx, encoder_context);
 622     gen6_vme_prepare(ctx, encode_state, encoder_context);
 623     gen6_vme_run(ctx, encode_state, encoder_context);
 624     gen6_vme_stop(ctx, encode_state, encoder_context);
 625
 626     return VA_STATUS_SUCCESS;
 627 }
 628
 629 static void
 630 gen6_vme_context_destroy(void *context)
 631 {
 632     struct gen6_vme_context *vme_context = context;
 633
 634     i965_gpe_context_destroy(&vme_context->gpe_context);
 635
 636     dri_bo_unreference(vme_context->vme_output.bo);
 637     vme_context->vme_output.bo = NULL;
 638
 639     dri_bo_unreference(vme_context->vme_state.bo);
 640     vme_context->vme_state.bo = NULL;
 641
 642     dri_bo_unreference(vme_context->vme_batchbuffer.bo);
 643     vme_context->vme_batchbuffer.bo = NULL;
 644
 645     free(vme_context);
 646 }
 647
 648 Bool gen6_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 649 {
 650     struct gen6_vme_context *vme_context = NULL;
 651
 652     if (encoder_context->profile != VAProfileH264Baseline &&
 653         encoder_context->profile != VAProfileH264Main     &&
 654         encoder_context->profile != VAProfileH264High) {
 655         /* Never get here */
 656         assert(0);
 657         return False;
 658     }
 659
 660     vme_context = calloc(1, sizeof(struct gen6_vme_context));
 661     vme_context->gpe_context.surface_state_binding_table.length =
 662               (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6;
 663
 664     vme_context->gpe_context.idrt.max_entries = MAX_INTERFACE_DESC_GEN6;
 665     vme_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data);
 666     vme_context->gpe_context.curbe.length = CURBE_TOTAL_DATA_LENGTH;
 667
 668     vme_context->gpe_context.vfe_state.max_num_threads = 60 - 1;
 669     vme_context->gpe_context.vfe_state.num_urb_entries = 16;
 670     vme_context->gpe_context.vfe_state.gpgpu_mode = 0;
 671     vme_context->gpe_context.vfe_state.urb_entry_size = 59 - 1;
 672     vme_context->gpe_context.vfe_state.curbe_allocation_size = CURBE_ALLOCATION_SIZE - 1;
 673
 674     vme_context->video_coding_type = VIDEO_CODING_AVC;
 675     vme_context->vme_kernel_sum = AVC_VME_KERNEL_SUM;
 676     i965_gpe_load_kernels(ctx,
 677                           &vme_context->gpe_context,
 678                           gen6_vme_kernels,
 679                           vme_context->vme_kernel_sum);
 680
 681     encoder_context->vme_pipeline = gen6_vme_pipeline;
 682     vme_context->vme_surface2_setup = i965_gpe_surface2_setup;
 683     vme_context->vme_media_rw_surface_setup = i965_gpe_media_rw_surface_setup;
 684     vme_context->vme_buffer_suface_setup = i965_gpe_buffer_suface_setup;
 685
 686     encoder_context->vme_context = vme_context;
 687     encoder_context->vme_context_destroy = gen6_vme_context_destroy;
 688
 689     return True;
 690 }