src/gen6_vme.c

   1 /*
   2  * Copyright © 2010-2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Zhou Chang <chang.zhou@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <assert.h>
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_driver.h"
  36
  37 #include "i965_defines.h"
  38 #include "i965_drv_video.h"
  39 #include "i965_encoder.h"
  40 #include "gen6_vme.h"
  41
  42 #define SURFACE_STATE_PADDED_SIZE_0_GEN7        ALIGN(sizeof(struct gen7_surface_state), 32)
  43 #define SURFACE_STATE_PADDED_SIZE_1_GEN7        ALIGN(sizeof(struct gen7_surface_state2), 32)
  44 #define SURFACE_STATE_PADDED_SIZE_GEN7          MAX(SURFACE_STATE_PADDED_SIZE_0_GEN7, SURFACE_STATE_PADDED_SIZE_1_GEN7)
  45
  46 #define SURFACE_STATE_PADDED_SIZE_0_GEN6        ALIGN(sizeof(struct i965_surface_state), 32)
  47 #define SURFACE_STATE_PADDED_SIZE_1_GEN6        ALIGN(sizeof(struct i965_surface_state2), 32)
  48 #define SURFACE_STATE_PADDED_SIZE_GEN6          MAX(SURFACE_STATE_PADDED_SIZE_0_GEN6, SURFACE_STATE_PADDED_SIZE_1_GEN6)
  49
  50 #define SURFACE_STATE_PADDED_SIZE               MAX(SURFACE_STATE_PADDED_SIZE_GEN6, SURFACE_STATE_PADDED_SIZE_GEN7)
  51 #define SURFACE_STATE_OFFSET(index)             (SURFACE_STATE_PADDED_SIZE * index)
  52 #define BINDING_TABLE_OFFSET(index)             (SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * index)
  53
  54 #define VME_INTRA_SHADER        0
  55 #define VME_INTER_SHADER        1
  56 #define VME_BATCHBUFFER         2
  57
  58 #define CURBE_ALLOCATION_SIZE   37              /* in 256-bit */
  59 #define CURBE_TOTAL_DATA_LENGTH (4 * 32)        /* in byte, it should be less than or equal to CURBE_ALLOCATION_SIZE * 32 */
  60 #define CURBE_URB_ENTRY_LENGTH  4               /* in 256-bit, it should be less than or equal to CURBE_TOTAL_DATA_LENGTH / 32 */
  61
  62 static const uint32_t gen6_vme_intra_frame[][4] = {
  63 #include "shaders/vme/intra_frame.g6b"
  64 };
  65
  66 static const uint32_t gen6_vme_inter_frame[][4] = {
  67 #include "shaders/vme/inter_frame.g6b"
  68 };
  69
  70 static const uint32_t gen6_vme_batchbuffer[][4] = {
  71 #include "shaders/vme/batchbuffer.g6b"
  72 };
  73
  74 static struct i965_kernel gen6_vme_kernels[] = {
  75     {
  76         "VME Intra Frame",
  77         VME_INTRA_SHADER,                                                                               /*index*/
  78         gen6_vme_intra_frame,
  79         sizeof(gen6_vme_intra_frame),
  80         NULL
  81     },
  82     {
  83         "VME inter Frame",
  84         VME_INTER_SHADER,
  85         gen6_vme_inter_frame,
  86         sizeof(gen6_vme_inter_frame),
  87         NULL
  88     },
  89     {
  90         "VME BATCHBUFFER",
  91         VME_BATCHBUFFER,
  92         gen6_vme_batchbuffer,
  93         sizeof(gen6_vme_batchbuffer),
  94         NULL
  95     },
  96 };
  97
  98 static const uint32_t gen7_vme_intra_frame[][4] = {
  99 #include "shaders/vme/intra_frame.g7b"
 100 };
 101
 102 static const uint32_t gen7_vme_inter_frame[][4] = {
 103 #include "shaders/vme/inter_frame.g7b"
 104 };
 105
 106 static const uint32_t gen7_vme_batchbuffer[][4] = {
 107 #include "shaders/vme/batchbuffer.g7b"
 108 };
 109
 110 static struct i965_kernel gen7_vme_kernels[] = {
 111     {
 112         "VME Intra Frame",
 113         VME_INTRA_SHADER,                                                                               /*index*/
 114         gen7_vme_intra_frame,
 115         sizeof(gen7_vme_intra_frame),
 116         NULL
 117     },
 118     {
 119         "VME inter Frame",
 120         VME_INTER_SHADER,
 121         gen7_vme_inter_frame,
 122         sizeof(gen7_vme_inter_frame),
 123         NULL
 124     },
 125     {
 126         "VME BATCHBUFFER",
 127         VME_BATCHBUFFER,
 128         gen7_vme_batchbuffer,
 129         sizeof(gen7_vme_batchbuffer),
 130         NULL
 131     },
 132 };
 133
 134 /* only used for VME source surface state */
 135 static void
 136 gen6_vme_source_surface_state(VADriverContextP ctx,
 137                               int index,
 138                               struct object_surface *obj_surface,
 139                               struct intel_encoder_context *encoder_context)
 140 {
 141     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 142
 143     vme_context->vme_surface2_setup(ctx,
 144                                     &vme_context->gpe_context,
 145                                     obj_surface,
 146                                     BINDING_TABLE_OFFSET(index),
 147                                     SURFACE_STATE_OFFSET(index));
 148 }
 149
 150 static void
 151 gen6_vme_media_source_surface_state(VADriverContextP ctx,
 152                                     int index,
 153                                     struct object_surface *obj_surface,
 154                                     struct intel_encoder_context *encoder_context)
 155 {
 156     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 157
 158     vme_context->vme_media_rw_surface_setup(ctx,
 159                                             &vme_context->gpe_context,
 160                                             obj_surface,
 161                                             BINDING_TABLE_OFFSET(index),
 162                                             SURFACE_STATE_OFFSET(index));
 163 }
 164
 165 static void
 166 gen6_vme_output_buffer_setup(VADriverContextP ctx,
 167                              struct encode_state *encode_state,
 168                              int index,
 169                              struct intel_encoder_context *encoder_context)
 170
 171 {
 172     struct i965_driver_data *i965 = i965_driver_data(ctx);
 173     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 174     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 175     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
 176     int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
 177     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 178     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 179
 180     vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs;
 181     vme_context->vme_output.pitch = 16; /* in bytes, always 16 */
 182
 183     if (is_intra)
 184         vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES;
 185     else
 186         vme_context->vme_output.size_block = INTER_VME_OUTPUT_IN_BYTES;
 187
 188     vme_context->vme_output.bo = dri_bo_alloc(i965->intel.bufmgr,
 189                                               "VME output buffer",
 190                                               vme_context->vme_output.num_blocks * vme_context->vme_output.size_block,
 191                                               0x1000);
 192     assert(vme_context->vme_output.bo);
 193     vme_context->vme_buffer_suface_setup(ctx,
 194                                          &vme_context->gpe_context,
 195                                          &vme_context->vme_output,
 196                                          BINDING_TABLE_OFFSET(index),
 197                                          SURFACE_STATE_OFFSET(index));
 198 }
 199
 200 static void
 201 gen6_vme_output_vme_batchbuffer_setup(VADriverContextP ctx,
 202                                       struct encode_state *encode_state,
 203                                       int index,
 204                                       struct intel_encoder_context *encoder_context)
 205
 206 {
 207     struct i965_driver_data *i965 = i965_driver_data(ctx);
 208     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 209     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 210     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 211     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 212
 213     vme_context->vme_batchbuffer.num_blocks = width_in_mbs * height_in_mbs + 1;
 214     vme_context->vme_batchbuffer.size_block = 32; /* 2 OWORDs */
 215     vme_context->vme_batchbuffer.pitch = 16;
 216     vme_context->vme_batchbuffer.bo = dri_bo_alloc(i965->intel.bufmgr,
 217                                                    "VME batchbuffer",
 218                                                    vme_context->vme_batchbuffer.num_blocks * vme_context->vme_batchbuffer.size_block,
 219                                                    0x1000);
 220     vme_context->vme_buffer_suface_setup(ctx,
 221                                          &vme_context->gpe_context,
 222                                          &vme_context->vme_batchbuffer,
 223                                          BINDING_TABLE_OFFSET(index),
 224                                          SURFACE_STATE_OFFSET(index));
 225 }
 226
 227 static VAStatus
 228 gen6_vme_surface_setup(VADriverContextP ctx,
 229                        struct encode_state *encode_state,
 230                        int is_intra,
 231                        struct intel_encoder_context *encoder_context)
 232 {
 233     struct i965_driver_data *i965 = i965_driver_data(ctx);
 234     struct object_surface *obj_surface;
 235     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 236
 237     /*Setup surfaces state*/
 238     /* current picture for encoding */
 239     obj_surface = SURFACE(encoder_context->input_yuv_surface);
 240     assert(obj_surface);
 241     gen6_vme_source_surface_state(ctx, 0, obj_surface, encoder_context);
 242     gen6_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context);
 243
 244     if (!is_intra) {
 245         /* reference 0 */
 246         obj_surface = SURFACE(pPicParameter->ReferenceFrames[0].picture_id);
 247         assert(obj_surface);
 248         if ( obj_surface->bo != NULL)
 249             gen6_vme_source_surface_state(ctx, 1, obj_surface, encoder_context);
 250
 251         /* reference 1 */
 252         obj_surface = SURFACE(pPicParameter->ReferenceFrames[1].picture_id);
 253         assert(obj_surface);
 254         if ( obj_surface->bo != NULL )
 255             gen6_vme_source_surface_state(ctx, 2, obj_surface, encoder_context);
 256     }
 257
 258     /* VME output */
 259     gen6_vme_output_buffer_setup(ctx, encode_state, 3, encoder_context);
 260     gen6_vme_output_vme_batchbuffer_setup(ctx, encode_state, 5, encoder_context);
 261
 262     return VA_STATUS_SUCCESS;
 263 }
 264
 265 static VAStatus gen6_vme_interface_setup(VADriverContextP ctx,
 266                                          struct encode_state *encode_state,
 267                                          struct intel_encoder_context *encoder_context)
 268 {
 269     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 270     struct gen6_interface_descriptor_data *desc;
 271     int i;
 272     dri_bo *bo;
 273
 274     bo = vme_context->gpe_context.idrt.bo;
 275     dri_bo_map(bo, 1);
 276     assert(bo->virtual);
 277     desc = bo->virtual;
 278
 279     for (i = 0; i < GEN6_VME_KERNEL_NUMBER; i++) {
 280         struct i965_kernel *kernel;
 281         kernel = &vme_context->gpe_context.kernels[i];
 282         assert(sizeof(*desc) == 32);
 283         /*Setup the descritor table*/
 284         memset(desc, 0, sizeof(*desc));
 285         desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6);
 286         desc->desc2.sampler_count = 1; /* FIXME: */
 287         desc->desc2.sampler_state_pointer = (vme_context->vme_state.bo->offset >> 5);
 288         desc->desc3.binding_table_entry_count = 1; /* FIXME: */
 289         desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5);
 290         desc->desc4.constant_urb_entry_read_offset = 0;
 291         desc->desc4.constant_urb_entry_read_length = CURBE_URB_ENTRY_LENGTH;
 292
 293         /*kernel start*/
 294         dri_bo_emit_reloc(bo,
 295                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 296                           0,
 297                           i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0),
 298                           kernel->bo);
 299         /*Sampler State(VME state pointer)*/
 300         dri_bo_emit_reloc(bo,
 301                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 302                           (1 << 2),                                                                     //
 303                           i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc2),
 304                           vme_context->vme_state.bo);
 305         desc++;
 306     }
 307     dri_bo_unmap(bo);
 308
 309     return VA_STATUS_SUCCESS;
 310 }
 311
 312 static VAStatus gen6_vme_constant_setup(VADriverContextP ctx,
 313                                         struct encode_state *encode_state,
 314                                         struct intel_encoder_context *encoder_context)
 315 {
 316     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 317     // unsigned char *constant_buffer;
 318
 319     dri_bo_map(vme_context->gpe_context.curbe.bo, 1);
 320     assert(vme_context->gpe_context.curbe.bo->virtual);
 321     // constant_buffer = vme_context->curbe.bo->virtual;
 322
 323     /*TODO copy buffer into CURB*/
 324
 325     dri_bo_unmap( vme_context->gpe_context.curbe.bo);
 326
 327     return VA_STATUS_SUCCESS;
 328 }
 329
 330 static VAStatus gen6_vme_vme_state_setup(VADriverContextP ctx,
 331                                          struct encode_state *encode_state,
 332                                          int is_intra,
 333                                          struct intel_encoder_context *encoder_context)
 334 {
 335     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 336     unsigned int *vme_state_message;
 337     int i;
 338
 339     //building VME state message
 340     dri_bo_map(vme_context->vme_state.bo, 1);
 341     assert(vme_context->vme_state.bo->virtual);
 342     vme_state_message = (unsigned int *)vme_context->vme_state.bo->virtual;
 343
 344         vme_state_message[0] = 0x01010101;
 345         vme_state_message[1] = 0x10010101;
 346         vme_state_message[2] = 0x0F0F0F0F;
 347         vme_state_message[3] = 0x100F0F0F;
 348         vme_state_message[4] = 0x01010101;
 349         vme_state_message[5] = 0x00010101;
 350         vme_state_message[6] = 0x01010101;
 351         vme_state_message[7] = 0x10010101;
 352         vme_state_message[8] = 0x0F0F0F0F;
 353         vme_state_message[9] = 0x100F0F0F;
 354         vme_state_message[10] = 0x01010101;
 355         vme_state_message[11] = 0x00010101;
 356         vme_state_message[12] = 0x00;
 357         vme_state_message[13] = 0x00;
 358
 359         vme_state_message[14] = 0x4a4a;
 360         vme_state_message[15] = 0x0;
 361         vme_state_message[16] = 0x4a4a4a4a;
 362         vme_state_message[17] = 0x4a4a4a4a;
 363         vme_state_message[18] = 0x22120200;
 364         vme_state_message[19] = 0x62524232;
 365
 366         for(i = 20; i < 32; i++) {
 367             vme_state_message[i] = 0;
 368         }
 369     //vme_state_message[16] = 0x42424242;                       //cost function LUT set 0 for Intra
 370
 371     dri_bo_unmap( vme_context->vme_state.bo);
 372     return VA_STATUS_SUCCESS;
 373 }
 374
 375 static void
 376 gen6_vme_fill_vme_batchbuffer(VADriverContextP ctx,
 377                               struct encode_state *encode_state,
 378                               int mb_width, int mb_height,
 379                               int kernel,
 380                               int transform_8x8_mode_flag,
 381                               struct intel_encoder_context *encoder_context)
 382 {
 383     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 384     int number_mb_cmds;
 385     int mb_x = 0, mb_y = 0;
 386     int i, s;
 387     unsigned int *command_ptr;
 388
 389     dri_bo_map(vme_context->vme_batchbuffer.bo, 1);
 390     command_ptr = vme_context->vme_batchbuffer.bo->virtual;
 391
 392     for (s = 0; s < encode_state->num_slice_params_ext; s++) {
 393         VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[s]->buffer;
 394         int slice_mb_begin = pSliceParameter->macroblock_address;
 395         int slice_mb_number = pSliceParameter->num_macroblocks;
 396
 397         for (i = 0; i < slice_mb_number;  ) {
 398             int mb_count = i + slice_mb_begin;
 399             mb_x = mb_count % mb_width;
 400             mb_y = mb_count / mb_width;
 401             if( i == 0 ) {
 402                 number_mb_cmds = mb_width;          // we must mark the slice edge.
 403             } else if ( (i + 128 ) <= slice_mb_number) {
 404                 number_mb_cmds = 128;
 405             } else {
 406                 number_mb_cmds = slice_mb_number - i;
 407             }
 408
 409             *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
 410             *command_ptr++ = kernel;
 411             *command_ptr++ = 0;
 412             *command_ptr++ = 0;
 413             *command_ptr++ = 0;
 414             *command_ptr++ = 0;
 415
 416             /*inline data */
 417             *command_ptr++ = (mb_width << 16 | mb_y << 8 | mb_x);
 418             *command_ptr++ = (number_mb_cmds << 16 | transform_8x8_mode_flag | ((i==0) << 1));
 419
 420             i += number_mb_cmds;
 421         }
 422     }
 423
 424     *command_ptr++ = 0;
 425     *command_ptr++ = MI_BATCH_BUFFER_END;
 426
 427     dri_bo_unmap(vme_context->vme_batchbuffer.bo);
 428 }
 429
 430 static void gen6_vme_media_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 431 {
 432     struct i965_driver_data *i965 = i965_driver_data(ctx);
 433     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 434     dri_bo *bo;
 435
 436     i965_gpe_context_init(ctx, &vme_context->gpe_context);
 437
 438     /* VME output buffer */
 439     dri_bo_unreference(vme_context->vme_output.bo);
 440     vme_context->vme_output.bo = NULL;
 441
 442     dri_bo_unreference(vme_context->vme_batchbuffer.bo);
 443     vme_context->vme_batchbuffer.bo = NULL;
 444
 445     /* VME state */
 446     dri_bo_unreference(vme_context->vme_state.bo);
 447     bo = dri_bo_alloc(i965->intel.bufmgr,
 448                       "Buffer",
 449                       1024*16, 64);
 450     assert(bo);
 451     vme_context->vme_state.bo = bo;
 452 }
 453
 454 static void gen6_vme_pipeline_programing(VADriverContextP ctx,
 455                                          struct encode_state *encode_state,
 456                                          struct intel_encoder_context *encoder_context)
 457 {
 458     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 459     struct intel_batchbuffer *batch = encoder_context->base.batch;
 460     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 461     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
 462     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 463     int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
 464     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 465     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 466
 467     gen6_vme_fill_vme_batchbuffer(ctx,
 468                                   encode_state,
 469                                   width_in_mbs, height_in_mbs,
 470                                   is_intra ? VME_INTRA_SHADER : VME_INTER_SHADER,
 471                                   pPicParameter->pic_fields.bits.transform_8x8_mode_flag,
 472                                   encoder_context);
 473
 474     intel_batchbuffer_start_atomic(batch, 0x1000);
 475     gen6_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch);
 476     BEGIN_BATCH(batch, 2);
 477     OUT_BATCH(batch, MI_BATCH_BUFFER_START | (2 << 6));
 478     OUT_RELOC(batch,
 479               vme_context->vme_batchbuffer.bo,
 480               I915_GEM_DOMAIN_COMMAND, 0,
 481               0);
 482     ADVANCE_BATCH(batch);
 483
 484     intel_batchbuffer_end_atomic(batch);
 485 }
 486
 487 static VAStatus gen6_vme_prepare(VADriverContextP ctx,
 488                                  struct encode_state *encode_state,
 489                                  struct intel_encoder_context *encoder_context)
 490 {
 491     VAStatus vaStatus = VA_STATUS_SUCCESS;
 492     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
 493     int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
 494
 495     /*Setup all the memory object*/
 496     gen6_vme_surface_setup(ctx, encode_state, is_intra, encoder_context);
 497     gen6_vme_interface_setup(ctx, encode_state, encoder_context);
 498     gen6_vme_constant_setup(ctx, encode_state, encoder_context);
 499     gen6_vme_vme_state_setup(ctx, encode_state, is_intra, encoder_context);
 500
 501     /*Programing media pipeline*/
 502     gen6_vme_pipeline_programing(ctx, encode_state, encoder_context);
 503
 504     return vaStatus;
 505 }
 506
 507 static VAStatus gen6_vme_run(VADriverContextP ctx,
 508                              struct encode_state *encode_state,
 509                              struct intel_encoder_context *encoder_context)
 510 {
 511     struct intel_batchbuffer *batch = encoder_context->base.batch;
 512
 513     intel_batchbuffer_flush(batch);
 514
 515     return VA_STATUS_SUCCESS;
 516 }
 517
 518 static VAStatus gen6_vme_stop(VADriverContextP ctx,
 519                               struct encode_state *encode_state,
 520                               struct intel_encoder_context *encoder_context)
 521 {
 522     return VA_STATUS_SUCCESS;
 523 }
 524
 525 static VAStatus
 526 gen6_vme_pipeline(VADriverContextP ctx,
 527                   VAProfile profile,
 528                   struct encode_state *encode_state,
 529                   struct intel_encoder_context *encoder_context)
 530 {
 531     gen6_vme_media_init(ctx, encoder_context);
 532     gen6_vme_prepare(ctx, encode_state, encoder_context);
 533     gen6_vme_run(ctx, encode_state, encoder_context);
 534     gen6_vme_stop(ctx, encode_state, encoder_context);
 535
 536     return VA_STATUS_SUCCESS;
 537 }
 538
 539 static void
 540 gen6_vme_context_destroy(void *context)
 541 {
 542     struct gen6_vme_context *vme_context = context;
 543
 544     i965_gpe_context_destroy(&vme_context->gpe_context);
 545
 546     dri_bo_unreference(vme_context->vme_output.bo);
 547     vme_context->vme_output.bo = NULL;
 548
 549     dri_bo_unreference(vme_context->vme_state.bo);
 550     vme_context->vme_state.bo = NULL;
 551
 552     dri_bo_unreference(vme_context->vme_batchbuffer.bo);
 553     vme_context->vme_batchbuffer.bo = NULL;
 554
 555     free(vme_context);
 556 }
 557
 558 Bool gen6_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 559 {
 560     struct i965_driver_data *i965 = i965_driver_data(ctx);
 561     struct gen6_vme_context *vme_context = calloc(1, sizeof(struct gen6_vme_context));
 562
 563     vme_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6;
 564
 565     vme_context->gpe_context.idrt.max_entries = MAX_INTERFACE_DESC_GEN6;
 566     vme_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data);
 567
 568     vme_context->gpe_context.curbe.length = CURBE_TOTAL_DATA_LENGTH;
 569
 570     vme_context->gpe_context.vfe_state.max_num_threads = 60 - 1;
 571     vme_context->gpe_context.vfe_state.num_urb_entries = 16;
 572     vme_context->gpe_context.vfe_state.gpgpu_mode = 0;
 573     vme_context->gpe_context.vfe_state.urb_entry_size = 59 - 1;
 574     vme_context->gpe_context.vfe_state.curbe_allocation_size = CURBE_ALLOCATION_SIZE - 1;
 575
 576     if (IS_GEN7(i965->intel.device_id)) {
 577         i965_gpe_load_kernels(ctx,
 578                               &vme_context->gpe_context,
 579                               gen7_vme_kernels,
 580                               GEN6_VME_KERNEL_NUMBER);
 581         vme_context->vme_surface2_setup = gen7_gpe_surface2_setup;
 582         vme_context->vme_media_rw_surface_setup = gen7_gpe_media_rw_surface_setup;
 583         vme_context->vme_buffer_suface_setup = gen7_gpe_buffer_suface_setup;
 584     } else {
 585         i965_gpe_load_kernels(ctx,
 586                               &vme_context->gpe_context,
 587                               gen6_vme_kernels,
 588                               GEN6_VME_KERNEL_NUMBER);
 589         vme_context->vme_surface2_setup = i965_gpe_surface2_setup;
 590         vme_context->vme_media_rw_surface_setup = i965_gpe_media_rw_surface_setup;
 591         vme_context->vme_buffer_suface_setup = i965_gpe_buffer_suface_setup;
 592     }
 593
 594     encoder_context->vme_context = vme_context;
 595     encoder_context->vme_context_destroy = gen6_vme_context_destroy;
 596     encoder_context->vme_pipeline = gen6_vme_pipeline;
 597
 598     return True;
 599 }