src/gen6_vme.c

   1 /*
   2  * Copyright © 2010-2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Zhou Chang <chang.zhou@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <assert.h>
  33
  34 #include "intel_batchbuffer.h"
  35 #include "intel_driver.h"
  36
  37 #include "i965_defines.h"
  38 #include "i965_drv_video.h"
  39 #include "i965_encoder.h"
  40 #include "gen6_vme.h"
  41 #include "gen6_mfc.h"
  42
  43 #define SURFACE_STATE_PADDED_SIZE_0_GEN7        ALIGN(sizeof(struct gen7_surface_state), 32)
  44 #define SURFACE_STATE_PADDED_SIZE_1_GEN7        ALIGN(sizeof(struct gen7_surface_state2), 32)
  45 #define SURFACE_STATE_PADDED_SIZE_GEN7          MAX(SURFACE_STATE_PADDED_SIZE_0_GEN7, SURFACE_STATE_PADDED_SIZE_1_GEN7)
  46
  47 #define SURFACE_STATE_PADDED_SIZE_0_GEN6        ALIGN(sizeof(struct i965_surface_state), 32)
  48 #define SURFACE_STATE_PADDED_SIZE_1_GEN6        ALIGN(sizeof(struct i965_surface_state2), 32)
  49 #define SURFACE_STATE_PADDED_SIZE_GEN6          MAX(SURFACE_STATE_PADDED_SIZE_0_GEN6, SURFACE_STATE_PADDED_SIZE_1_GEN6)
  50
  51 #define SURFACE_STATE_PADDED_SIZE               MAX(SURFACE_STATE_PADDED_SIZE_GEN6, SURFACE_STATE_PADDED_SIZE_GEN7)
  52 #define SURFACE_STATE_OFFSET(index)             (SURFACE_STATE_PADDED_SIZE * index)
  53 #define BINDING_TABLE_OFFSET(index)             (SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * index)
  54
  55 #define CURBE_ALLOCATION_SIZE   37              /* in 256-bit */
  56 #define CURBE_TOTAL_DATA_LENGTH (4 * 32)        /* in byte, it should be less than or equal to CURBE_ALLOCATION_SIZE * 32 */
  57 #define CURBE_URB_ENTRY_LENGTH  4               /* in 256-bit, it should be less than or equal to CURBE_TOTAL_DATA_LENGTH / 32 */
  58
  59 enum VIDEO_CODING_TYPE{
  60     VIDEO_CODING_AVC = 0,
  61     VIDEO_CODING_SUM
  62 };
  63
  64 enum AVC_VME_KERNEL_TYPE{
  65     AVC_VME_INTRA_SHADER = 0,
  66     AVC_VME_INTER_SHADER,
  67     AVC_VME_BATCHBUFFER,
  68     AVC_VME_KERNEL_SUM
  69 };
  70
  71 static const uint32_t gen6_vme_intra_frame[][4] = {
  72 #include "shaders/vme/intra_frame.g6b"
  73 };
  74
  75 static const uint32_t gen6_vme_inter_frame[][4] = {
  76 #include "shaders/vme/inter_frame.g6b"
  77 };
  78
  79 static const uint32_t gen6_vme_batchbuffer[][4] = {
  80 #include "shaders/vme/batchbuffer.g6b"
  81 };
  82
  83 static struct i965_kernel gen6_vme_kernels[] = {
  84     {
  85         "AVC VME Intra Frame",
  86         AVC_VME_INTRA_SHADER,                   /*index*/
  87         gen6_vme_intra_frame,
  88         sizeof(gen6_vme_intra_frame),
  89         NULL
  90     },
  91     {
  92         "AVC VME inter Frame",
  93         AVC_VME_INTER_SHADER,
  94         gen6_vme_inter_frame,
  95         sizeof(gen6_vme_inter_frame),
  96         NULL
  97     },
  98     {
  99         "AVC VME BATCHBUFFER",
 100         AVC_VME_BATCHBUFFER,
 101         gen6_vme_batchbuffer,
 102         sizeof(gen6_vme_batchbuffer),
 103         NULL
 104     },
 105 };
 106
 107 /* only used for VME source surface state */
 108 static void
 109 gen6_vme_source_surface_state(VADriverContextP ctx,
 110                               int index,
 111                               struct object_surface *obj_surface,
 112                               struct intel_encoder_context *encoder_context)
 113 {
 114     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 115
 116     vme_context->vme_surface2_setup(ctx,
 117                                     &vme_context->gpe_context,
 118                                     obj_surface,
 119                                     BINDING_TABLE_OFFSET(index),
 120                                     SURFACE_STATE_OFFSET(index));
 121 }
 122
 123 static void
 124 gen6_vme_media_source_surface_state(VADriverContextP ctx,
 125                                     int index,
 126                                     struct object_surface *obj_surface,
 127                                     struct intel_encoder_context *encoder_context)
 128 {
 129     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 130
 131     vme_context->vme_media_rw_surface_setup(ctx,
 132                                             &vme_context->gpe_context,
 133                                             obj_surface,
 134                                             BINDING_TABLE_OFFSET(index),
 135                                             SURFACE_STATE_OFFSET(index));
 136 }
 137
 138 static void
 139 gen6_vme_output_buffer_setup(VADriverContextP ctx,
 140                              struct encode_state *encode_state,
 141                              int index,
 142                              struct intel_encoder_context *encoder_context)
 143
 144 {
 145     struct i965_driver_data *i965 = i965_driver_data(ctx);
 146     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 147     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 148     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
 149     int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
 150     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 151     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 152
 153     vme_context->vme_output.num_blocks = width_in_mbs * height_in_mbs;
 154     vme_context->vme_output.pitch = 16; /* in bytes, always 16 */
 155
 156     if (is_intra)
 157         vme_context->vme_output.size_block = INTRA_VME_OUTPUT_IN_BYTES;
 158     else
 159         vme_context->vme_output.size_block = INTER_VME_OUTPUT_IN_BYTES;
 160
 161     vme_context->vme_output.bo = dri_bo_alloc(i965->intel.bufmgr,
 162                                               "VME output buffer",
 163                                               vme_context->vme_output.num_blocks * vme_context->vme_output.size_block,
 164                                               0x1000);
 165     assert(vme_context->vme_output.bo);
 166     vme_context->vme_buffer_suface_setup(ctx,
 167                                          &vme_context->gpe_context,
 168                                          &vme_context->vme_output,
 169                                          BINDING_TABLE_OFFSET(index),
 170                                          SURFACE_STATE_OFFSET(index));
 171 }
 172
 173 static void
 174 gen6_vme_output_vme_batchbuffer_setup(VADriverContextP ctx,
 175                                       struct encode_state *encode_state,
 176                                       int index,
 177                                       struct intel_encoder_context *encoder_context)
 178
 179 {
 180     struct i965_driver_data *i965 = i965_driver_data(ctx);
 181     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 182     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 183     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 184     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 185
 186     vme_context->vme_batchbuffer.num_blocks = width_in_mbs * height_in_mbs + 1;
 187     vme_context->vme_batchbuffer.size_block = 32; /* 2 OWORDs */
 188     vme_context->vme_batchbuffer.pitch = 16;
 189     vme_context->vme_batchbuffer.bo = dri_bo_alloc(i965->intel.bufmgr,
 190                                                    "VME batchbuffer",
 191                                                    vme_context->vme_batchbuffer.num_blocks * vme_context->vme_batchbuffer.size_block,
 192                                                    0x1000);
 193     vme_context->vme_buffer_suface_setup(ctx,
 194                                          &vme_context->gpe_context,
 195                                          &vme_context->vme_batchbuffer,
 196                                          BINDING_TABLE_OFFSET(index),
 197                                          SURFACE_STATE_OFFSET(index));
 198 }
 199
 200 static VAStatus
 201 gen6_vme_surface_setup(VADriverContextP ctx,
 202                        struct encode_state *encode_state,
 203                        int is_intra,
 204                        struct intel_encoder_context *encoder_context)
 205 {
 206     struct object_surface *obj_surface;
 207
 208     /*Setup surfaces state*/
 209     /* current picture for encoding */
 210     obj_surface = encode_state->input_yuv_object;
 211     gen6_vme_source_surface_state(ctx, 0, obj_surface, encoder_context);
 212     gen6_vme_media_source_surface_state(ctx, 4, obj_surface, encoder_context);
 213
 214     if (!is_intra) {
 215         /* reference 0 */
 216         obj_surface = encode_state->reference_objects[0];
 217
 218         if (obj_surface && obj_surface->bo)
 219             gen6_vme_source_surface_state(ctx, 1, obj_surface, encoder_context);
 220
 221         /* reference 1 */
 222         obj_surface = encode_state->reference_objects[1];
 223
 224         if (obj_surface && obj_surface->bo)
 225             gen6_vme_source_surface_state(ctx, 2, obj_surface, encoder_context);
 226     }
 227
 228     /* VME output */
 229     gen6_vme_output_buffer_setup(ctx, encode_state, 3, encoder_context);
 230     gen6_vme_output_vme_batchbuffer_setup(ctx, encode_state, 5, encoder_context);
 231
 232     return VA_STATUS_SUCCESS;
 233 }
 234
 235 static VAStatus gen6_vme_interface_setup(VADriverContextP ctx,
 236                                          struct encode_state *encode_state,
 237                                          struct intel_encoder_context *encoder_context)
 238 {
 239     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 240     struct gen6_interface_descriptor_data *desc;
 241     int i;
 242     dri_bo *bo;
 243
 244     bo = vme_context->gpe_context.idrt.bo;
 245     dri_bo_map(bo, 1);
 246     assert(bo->virtual);
 247     desc = bo->virtual;
 248
 249     for (i = 0; i < vme_context->vme_kernel_sum; i++) {
 250         struct i965_kernel *kernel;
 251         kernel = &vme_context->gpe_context.kernels[i];
 252         assert(sizeof(*desc) == 32);
 253         /*Setup the descritor table*/
 254         memset(desc, 0, sizeof(*desc));
 255         desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6);
 256         desc->desc2.sampler_count = 1; /* FIXME: */
 257         desc->desc2.sampler_state_pointer = (vme_context->vme_state.bo->offset >> 5);
 258         desc->desc3.binding_table_entry_count = 1; /* FIXME: */
 259         desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5);
 260         desc->desc4.constant_urb_entry_read_offset = 0;
 261         desc->desc4.constant_urb_entry_read_length = CURBE_URB_ENTRY_LENGTH;
 262
 263         /*kernel start*/
 264         dri_bo_emit_reloc(bo,
 265                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 266                           0,
 267                           i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0),
 268                           kernel->bo);
 269         /*Sampler State(VME state pointer)*/
 270         dri_bo_emit_reloc(bo,
 271                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 272                           (1 << 2),                                                                     //
 273                           i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc2),
 274                           vme_context->vme_state.bo);
 275         desc++;
 276     }
 277     dri_bo_unmap(bo);
 278
 279     return VA_STATUS_SUCCESS;
 280 }
 281
 282 static VAStatus gen6_vme_constant_setup(VADriverContextP ctx,
 283                                         struct encode_state *encode_state,
 284                                         struct intel_encoder_context *encoder_context)
 285 {
 286     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 287     // unsigned char *constant_buffer;
 288     unsigned int *vme_state_message;
 289     int mv_num = 32;
 290     if (vme_context->h264_level >= 30) {
 291         mv_num = 16;
 292         if (vme_context->h264_level >= 31)
 293                 mv_num = 8;
 294     }
 295
 296     dri_bo_map(vme_context->gpe_context.curbe.bo, 1);
 297     assert(vme_context->gpe_context.curbe.bo->virtual);
 298     // constant_buffer = vme_context->curbe.bo->virtual;
 299     vme_state_message = (unsigned int *)vme_context->gpe_context.curbe.bo->virtual;
 300     vme_state_message[31] = mv_num;
 301
 302     /*TODO copy buffer into CURB*/
 303
 304     dri_bo_unmap( vme_context->gpe_context.curbe.bo);
 305
 306     return VA_STATUS_SUCCESS;
 307 }
 308
 309 static const unsigned int intra_mb_mode_cost_table[] = {
 310     0x31110001, // for qp0
 311     0x09110001, // for qp1
 312     0x15030001, // for qp2
 313     0x0b030001, // for qp3
 314     0x0d030011, // for qp4
 315     0x17210011, // for qp5
 316     0x41210011, // for qp6
 317     0x19210011, // for qp7
 318     0x25050003, // for qp8
 319     0x1b130003, // for qp9
 320     0x1d130003, // for qp10
 321     0x27070021, // for qp11
 322     0x51310021, // for qp12
 323     0x29090021, // for qp13
 324     0x35150005, // for qp14
 325     0x2b0b0013, // for qp15
 326     0x2d0d0013, // for qp16
 327     0x37170007, // for qp17
 328     0x61410031, // for qp18
 329     0x39190009, // for qp19
 330     0x45250015, // for qp20
 331     0x3b1b000b, // for qp21
 332     0x3d1d000d, // for qp22
 333     0x47270017, // for qp23
 334     0x71510041, // for qp24 ! center for qp=0..30
 335     0x49290019, // for qp25
 336     0x55350025, // for qp26
 337     0x4b2b001b, // for qp27
 338     0x4d2d001d, // for qp28
 339     0x57370027, // for qp29
 340     0x81610051, // for qp30
 341     0x57270017, // for qp31
 342     0x81510041, // for qp32 ! center for qp=31..51
 343     0x59290019, // for qp33
 344     0x65350025, // for qp34
 345     0x5b2b001b, // for qp35
 346     0x5d2d001d, // for qp36
 347     0x67370027, // for qp37
 348     0x91610051, // for qp38
 349     0x69390029, // for qp39
 350     0x75450035, // for qp40
 351     0x6b3b002b, // for qp41
 352     0x6d3d002d, // for qp42
 353     0x77470037, // for qp43
 354     0xa1710061, // for qp44
 355     0x79490039, // for qp45
 356     0x85550045, // for qp46
 357     0x7b4b003b, // for qp47
 358     0x7d4d003d, // for qp48
 359     0x87570047, // for qp49
 360     0xb1810071, // for qp50
 361     0x89590049  // for qp51
 362 };
 363
 364 static void gen6_vme_state_setup_fixup(VADriverContextP ctx,
 365                                        struct encode_state *encode_state,
 366                                        struct intel_encoder_context *encoder_context,
 367                                        unsigned int *vme_state_message)
 368 {
 369     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 370     VAEncPictureParameterBufferH264 *pic_param = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 371     VAEncSliceParameterBufferH264 *slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
 372
 373     if (slice_param->slice_type != SLICE_TYPE_I &&
 374         slice_param->slice_type != SLICE_TYPE_SI)
 375         return;
 376
 377     if (encoder_context->rate_control_mode == VA_RC_CQP)
 378         vme_state_message[16] = intra_mb_mode_cost_table[pic_param->pic_init_qp + slice_param->slice_qp_delta];
 379     else
 380         vme_state_message[16] = intra_mb_mode_cost_table[mfc_context->bit_rate_control_context[SLICE_TYPE_I].QpPrimeY];
 381 }
 382
 383 static VAStatus gen6_vme_vme_state_setup(VADriverContextP ctx,
 384                                          struct encode_state *encode_state,
 385                                          int is_intra,
 386                                          struct intel_encoder_context *encoder_context)
 387 {
 388     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 389     unsigned int *vme_state_message;
 390     int i;
 391
 392     //building VME state message
 393     dri_bo_map(vme_context->vme_state.bo, 1);
 394     assert(vme_context->vme_state.bo->virtual);
 395     vme_state_message = (unsigned int *)vme_context->vme_state.bo->virtual;
 396
 397     vme_state_message[0] = 0x01010101;
 398     vme_state_message[1] = 0x10010101;
 399     vme_state_message[2] = 0x0F0F0F0F;
 400     vme_state_message[3] = 0x100F0F0F;
 401     vme_state_message[4] = 0x01010101;
 402     vme_state_message[5] = 0x10010101;
 403     vme_state_message[6] = 0x0F0F0F0F;
 404     vme_state_message[7] = 0x100F0F0F;
 405     vme_state_message[8] = 0x01010101;
 406     vme_state_message[9] = 0x10010101;
 407     vme_state_message[10] = 0x0F0F0F0F;
 408     vme_state_message[11] = 0x000F0F0F;
 409     vme_state_message[12] = 0x00;
 410     vme_state_message[13] = 0x00;
 411
 412     vme_state_message[14] = 0x4a4a;
 413     vme_state_message[15] = 0x0;
 414     vme_state_message[16] = 0x4a4a4a4a;
 415     vme_state_message[17] = 0x4a4a4a4a;
 416     vme_state_message[18] = 0x21110100;
 417     vme_state_message[19] = 0x61514131;
 418
 419     for(i = 20; i < 32; i++) {
 420         vme_state_message[i] = 0;
 421     }
 422     //vme_state_message[16] = 0x42424242;                       //cost function LUT set 0 for Intra
 423
 424     gen6_vme_state_setup_fixup(ctx, encode_state, encoder_context, vme_state_message);
 425
 426     dri_bo_unmap( vme_context->vme_state.bo);
 427     return VA_STATUS_SUCCESS;
 428 }
 429
 430 static void
 431 gen6_vme_fill_vme_batchbuffer(VADriverContextP ctx,
 432                               struct encode_state *encode_state,
 433                               int mb_width, int mb_height,
 434                               int kernel,
 435                               int transform_8x8_mode_flag,
 436                               struct intel_encoder_context *encoder_context)
 437 {
 438     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 439     int number_mb_cmds;
 440     int mb_x = 0, mb_y = 0;
 441     int i, s;
 442     unsigned int *command_ptr;
 443
 444     dri_bo_map(vme_context->vme_batchbuffer.bo, 1);
 445     command_ptr = vme_context->vme_batchbuffer.bo->virtual;
 446
 447     for (s = 0; s < encode_state->num_slice_params_ext; s++) {
 448         VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[s]->buffer;
 449         int slice_mb_begin = pSliceParameter->macroblock_address;
 450         int slice_mb_number = pSliceParameter->num_macroblocks;
 451
 452         for (i = 0; i < slice_mb_number;  ) {
 453             int mb_count = i + slice_mb_begin;
 454             mb_x = mb_count % mb_width;
 455             mb_y = mb_count / mb_width;
 456             if( i == 0 ) {
 457                 number_mb_cmds = mb_width;          // we must mark the slice edge.
 458             } else if ( (i + 128 ) <= slice_mb_number) {
 459                 number_mb_cmds = 128;
 460             } else {
 461                 number_mb_cmds = slice_mb_number - i;
 462             }
 463
 464             *command_ptr++ = (CMD_MEDIA_OBJECT | (8 - 2));
 465             *command_ptr++ = kernel;
 466             *command_ptr++ = 0;
 467             *command_ptr++ = 0;
 468             *command_ptr++ = 0;
 469             *command_ptr++ = 0;
 470
 471             /*inline data */
 472             *command_ptr++ = (mb_width << 16 | mb_y << 8 | mb_x);
 473             *command_ptr++ = (number_mb_cmds << 16 | transform_8x8_mode_flag | ((i==0) << 1));
 474
 475             i += number_mb_cmds;
 476         }
 477     }
 478
 479     *command_ptr++ = 0;
 480     *command_ptr++ = MI_BATCH_BUFFER_END;
 481
 482     dri_bo_unmap(vme_context->vme_batchbuffer.bo);
 483 }
 484
 485 static void gen6_vme_media_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 486 {
 487     struct i965_driver_data *i965 = i965_driver_data(ctx);
 488     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 489     dri_bo *bo;
 490
 491     i965_gpe_context_init(ctx, &vme_context->gpe_context);
 492
 493     /* VME output buffer */
 494     dri_bo_unreference(vme_context->vme_output.bo);
 495     vme_context->vme_output.bo = NULL;
 496
 497     dri_bo_unreference(vme_context->vme_batchbuffer.bo);
 498     vme_context->vme_batchbuffer.bo = NULL;
 499
 500     /* VME state */
 501     dri_bo_unreference(vme_context->vme_state.bo);
 502     bo = dri_bo_alloc(i965->intel.bufmgr,
 503                       "Buffer",
 504                       1024*16, 64);
 505     assert(bo);
 506     vme_context->vme_state.bo = bo;
 507 }
 508
 509 static void gen6_vme_pipeline_programing(VADriverContextP ctx,
 510                                          struct encode_state *encode_state,
 511                                          struct intel_encoder_context *encoder_context)
 512 {
 513     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 514     struct intel_batchbuffer *batch = encoder_context->base.batch;
 515     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 516     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
 517     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 518     int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
 519     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 520     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 521
 522     gen6_vme_fill_vme_batchbuffer(ctx,
 523                                   encode_state,
 524                                   width_in_mbs, height_in_mbs,
 525                                   is_intra ? AVC_VME_INTRA_SHADER : AVC_VME_INTER_SHADER,
 526                                   pPicParameter->pic_fields.bits.transform_8x8_mode_flag,
 527                                   encoder_context);
 528
 529     intel_batchbuffer_start_atomic(batch, 0x1000);
 530     gen6_gpe_pipeline_setup(ctx, &vme_context->gpe_context, batch);
 531     BEGIN_BATCH(batch, 2);
 532     OUT_BATCH(batch, MI_BATCH_BUFFER_START | (2 << 6));
 533     OUT_RELOC(batch,
 534               vme_context->vme_batchbuffer.bo,
 535               I915_GEM_DOMAIN_COMMAND, 0,
 536               0);
 537     ADVANCE_BATCH(batch);
 538
 539     intel_batchbuffer_end_atomic(batch);
 540 }
 541
 542 static VAStatus gen6_vme_prepare(VADriverContextP ctx,
 543                                  struct encode_state *encode_state,
 544                                  struct intel_encoder_context *encoder_context)
 545 {
 546     VAStatus vaStatus = VA_STATUS_SUCCESS;
 547     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
 548     int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
 549     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 550     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 551
 552     if (!vme_context->h264_level ||
 553                 (vme_context->h264_level != pSequenceParameter->level_idc)) {
 554         vme_context->h264_level = pSequenceParameter->level_idc;
 555     }
 556     /*Setup all the memory object*/
 557     gen6_vme_surface_setup(ctx, encode_state, is_intra, encoder_context);
 558     gen6_vme_interface_setup(ctx, encode_state, encoder_context);
 559     gen6_vme_constant_setup(ctx, encode_state, encoder_context);
 560     gen6_vme_vme_state_setup(ctx, encode_state, is_intra, encoder_context);
 561
 562     /*Programing media pipeline*/
 563     gen6_vme_pipeline_programing(ctx, encode_state, encoder_context);
 564
 565     return vaStatus;
 566 }
 567
 568 static VAStatus gen6_vme_run(VADriverContextP ctx,
 569                              struct encode_state *encode_state,
 570                              struct intel_encoder_context *encoder_context)
 571 {
 572     struct intel_batchbuffer *batch = encoder_context->base.batch;
 573
 574     intel_batchbuffer_flush(batch);
 575
 576     return VA_STATUS_SUCCESS;
 577 }
 578
 579 static VAStatus gen6_vme_stop(VADriverContextP ctx,
 580                               struct encode_state *encode_state,
 581                               struct intel_encoder_context *encoder_context)
 582 {
 583     return VA_STATUS_SUCCESS;
 584 }
 585
 586 static VAStatus
 587 gen6_vme_pipeline(VADriverContextP ctx,
 588                   VAProfile profile,
 589                   struct encode_state *encode_state,
 590                   struct intel_encoder_context *encoder_context)
 591 {
 592     gen6_vme_media_init(ctx, encoder_context);
 593     gen6_vme_prepare(ctx, encode_state, encoder_context);
 594     gen6_vme_run(ctx, encode_state, encoder_context);
 595     gen6_vme_stop(ctx, encode_state, encoder_context);
 596
 597     return VA_STATUS_SUCCESS;
 598 }
 599
 600 static void
 601 gen6_vme_context_destroy(void *context)
 602 {
 603     struct gen6_vme_context *vme_context = context;
 604
 605     i965_gpe_context_destroy(&vme_context->gpe_context);
 606
 607     dri_bo_unreference(vme_context->vme_output.bo);
 608     vme_context->vme_output.bo = NULL;
 609
 610     dri_bo_unreference(vme_context->vme_state.bo);
 611     vme_context->vme_state.bo = NULL;
 612
 613     dri_bo_unreference(vme_context->vme_batchbuffer.bo);
 614     vme_context->vme_batchbuffer.bo = NULL;
 615
 616     free(vme_context);
 617 }
 618
 619 Bool gen6_vme_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 620 {
 621     struct gen6_vme_context *vme_context = NULL;
 622
 623     if (encoder_context->profile != VAProfileH264Baseline &&
 624         encoder_context->profile != VAProfileH264Main     &&
 625         encoder_context->profile != VAProfileH264High) {
 626         /* Never get here */
 627         assert(0);
 628         return False;
 629     }
 630
 631     vme_context = calloc(1, sizeof(struct gen6_vme_context));
 632     vme_context->gpe_context.surface_state_binding_table.length =
 633               (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6;
 634
 635     vme_context->gpe_context.idrt.max_entries = MAX_INTERFACE_DESC_GEN6;
 636     vme_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data);
 637     vme_context->gpe_context.curbe.length = CURBE_TOTAL_DATA_LENGTH;
 638
 639     vme_context->gpe_context.vfe_state.max_num_threads = 60 - 1;
 640     vme_context->gpe_context.vfe_state.num_urb_entries = 16;
 641     vme_context->gpe_context.vfe_state.gpgpu_mode = 0;
 642     vme_context->gpe_context.vfe_state.urb_entry_size = 59 - 1;
 643     vme_context->gpe_context.vfe_state.curbe_allocation_size = CURBE_ALLOCATION_SIZE - 1;
 644
 645     vme_context->video_coding_type = VIDEO_CODING_AVC;
 646     vme_context->vme_kernel_sum = AVC_VME_KERNEL_SUM;
 647     i965_gpe_load_kernels(ctx,
 648                           &vme_context->gpe_context,
 649                           gen6_vme_kernels,
 650                           vme_context->vme_kernel_sum);
 651
 652     encoder_context->vme_pipeline = gen6_vme_pipeline;
 653     vme_context->vme_surface2_setup = i965_gpe_surface2_setup;
 654     vme_context->vme_media_rw_surface_setup = i965_gpe_media_rw_surface_setup;
 655     vme_context->vme_buffer_suface_setup = i965_gpe_buffer_suface_setup;
 656
 657     encoder_context->vme_context = vme_context;
 658     encoder_context->vme_context_destroy = gen6_vme_context_destroy;
 659
 660     return True;
 661 }