2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Xiang Haihao <haihao.xiang@intel.com>
34 #include "intel_batchbuffer.h"
35 #include "intel_driver.h"
37 #include "i965_defines.h"
38 #include "i965_drv_video.h"
39 #include "i965_decoder_utils.h"
42 #include "intel_media.h"
44 static const uint32_t zigzag_direct[64] = {
45 0, 1, 8, 16, 9, 2, 3, 10,
46 17, 24, 32, 25, 18, 11, 4, 5,
47 12, 19, 26, 33, 40, 48, 41, 34,
48 27, 20, 13, 6, 7, 14, 21, 28,
49 35, 42, 49, 56, 57, 50, 43, 36,
50 29, 22, 15, 23, 30, 37, 44, 51,
51 58, 59, 52, 45, 38, 31, 39, 46,
52 53, 60, 61, 54, 47, 55, 62, 63
56 gen6_mfd_avc_frame_store_index(VADriverContextP ctx,
57 VAPictureParameterBufferH264 *pic_param,
58 struct gen6_mfd_context *gen6_mfd_context)
60 struct i965_driver_data *i965 = i965_driver_data(ctx);
63 assert(ARRAY_ELEMS(gen6_mfd_context->reference_surface) == ARRAY_ELEMS(pic_param->ReferenceFrames));
65 for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) {
68 if (gen6_mfd_context->reference_surface[i].surface_id == VA_INVALID_ID)
71 for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) {
72 VAPictureH264 *ref_pic = &pic_param->ReferenceFrames[j];
73 if (ref_pic->flags & VA_PICTURE_H264_INVALID)
76 if (gen6_mfd_context->reference_surface[i].surface_id == ref_pic->picture_id) {
83 struct object_surface *obj_surface = SURFACE(gen6_mfd_context->reference_surface[i].surface_id);
84 obj_surface->flags &= ~SURFACE_REFERENCED;
86 if ((obj_surface->flags & SURFACE_ALL_MASK) == SURFACE_DISPLAYED) {
87 dri_bo_unreference(obj_surface->bo);
88 obj_surface->bo = NULL;
89 obj_surface->flags &= ~SURFACE_REF_DIS_MASK;
92 if (obj_surface->free_private_data)
93 obj_surface->free_private_data(&obj_surface->private_data);
95 gen6_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID;
96 gen6_mfd_context->reference_surface[i].frame_store_id = -1;
100 for (i = 0; i < ARRAY_ELEMS(pic_param->ReferenceFrames); i++) {
101 VAPictureH264 *ref_pic = &pic_param->ReferenceFrames[i];
104 if (ref_pic->flags & VA_PICTURE_H264_INVALID)
107 for (j = 0; j < ARRAY_ELEMS(gen6_mfd_context->reference_surface); j++) {
108 if (gen6_mfd_context->reference_surface[j].surface_id == VA_INVALID_ID)
111 if (gen6_mfd_context->reference_surface[j].surface_id == ref_pic->picture_id) {
119 struct object_surface *obj_surface = SURFACE(ref_pic->picture_id);
122 i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
124 for (frame_idx = 0; frame_idx < ARRAY_ELEMS(gen6_mfd_context->reference_surface); frame_idx++) {
125 for (j = 0; j < ARRAY_ELEMS(gen6_mfd_context->reference_surface); j++) {
126 if (gen6_mfd_context->reference_surface[j].surface_id == VA_INVALID_ID)
129 if (gen6_mfd_context->reference_surface[j].frame_store_id == frame_idx)
133 if (j == ARRAY_ELEMS(gen6_mfd_context->reference_surface))
137 assert(frame_idx < ARRAY_ELEMS(gen6_mfd_context->reference_surface));
139 for (j = 0; j < ARRAY_ELEMS(gen6_mfd_context->reference_surface); j++) {
140 if (gen6_mfd_context->reference_surface[j].surface_id == VA_INVALID_ID) {
141 gen6_mfd_context->reference_surface[j].surface_id = ref_pic->picture_id;
142 gen6_mfd_context->reference_surface[j].frame_store_id = frame_idx;
150 for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface) - 1; i++) {
151 if (gen6_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
152 gen6_mfd_context->reference_surface[i].frame_store_id == i)
155 for (j = i + 1; j < ARRAY_ELEMS(gen6_mfd_context->reference_surface); j++) {
156 if (gen6_mfd_context->reference_surface[j].surface_id != VA_INVALID_ID &&
157 gen6_mfd_context->reference_surface[j].frame_store_id == i) {
158 VASurfaceID id = gen6_mfd_context->reference_surface[i].surface_id;
159 int frame_idx = gen6_mfd_context->reference_surface[i].frame_store_id;
161 gen6_mfd_context->reference_surface[i].surface_id = gen6_mfd_context->reference_surface[j].surface_id;
162 gen6_mfd_context->reference_surface[i].frame_store_id = gen6_mfd_context->reference_surface[j].frame_store_id;
163 gen6_mfd_context->reference_surface[j].surface_id = id;
164 gen6_mfd_context->reference_surface[j].frame_store_id = frame_idx;
172 gen6_mfd_init_avc_surface(VADriverContextP ctx,
173 VAPictureParameterBufferH264 *pic_param,
174 struct object_surface *obj_surface)
176 struct i965_driver_data *i965 = i965_driver_data(ctx);
177 GenAvcSurface *gen6_avc_surface = obj_surface->private_data;
180 obj_surface->free_private_data = gen_free_avc_surface;
181 height_in_mbs = ((pic_param->picture_height_in_mbs_minus1 + 1) & 0xff); /* frame height */
183 if (!gen6_avc_surface) {
184 gen6_avc_surface = calloc(sizeof(GenAvcSurface), 1);
185 assert((obj_surface->size & 0x3f) == 0);
186 obj_surface->private_data = gen6_avc_surface;
189 gen6_avc_surface->dmv_bottom_flag = (pic_param->pic_fields.bits.field_pic_flag &&
190 !pic_param->seq_fields.bits.direct_8x8_inference_flag);
192 if (gen6_avc_surface->dmv_top == NULL) {
193 gen6_avc_surface->dmv_top = dri_bo_alloc(i965->intel.bufmgr,
194 "direct mv w/r buffer",
195 128 * height_in_mbs * 64, /* scalable with frame height */
199 if (gen6_avc_surface->dmv_bottom_flag &&
200 gen6_avc_surface->dmv_bottom == NULL) {
201 gen6_avc_surface->dmv_bottom = dri_bo_alloc(i965->intel.bufmgr,
202 "direct mv w/r buffer",
203 128 * height_in_mbs * 64, /* scalable with frame height */
209 gen6_mfd_pipe_mode_select(VADriverContextP ctx,
210 struct decode_state *decode_state,
212 struct gen6_mfd_context *gen6_mfd_context)
214 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
216 assert(standard_select == MFX_FORMAT_MPEG2 ||
217 standard_select == MFX_FORMAT_AVC ||
218 standard_select == MFX_FORMAT_VC1);
220 BEGIN_BCS_BATCH(batch, 4);
221 OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (4 - 2));
223 (MFD_MODE_VLD << 16) | /* VLD mode */
224 (0 << 10) | /* disable Stream-Out */
225 (gen6_mfd_context->post_deblocking_output.valid << 9) | /* Post Deblocking Output */
226 (gen6_mfd_context->pre_deblocking_output.valid << 8) | /* Pre Deblocking Output */
227 (0 << 7) | /* disable TLB prefectch */
228 (0 << 5) | /* not in stitch mode */
229 (MFX_CODEC_DECODE << 4) | /* decoding mode */
230 (standard_select << 0));
232 (0 << 20) | /* round flag in PB slice */
233 (0 << 19) | /* round flag in Intra8x8 */
234 (0 << 7) | /* expand NOA bus flag */
235 (1 << 6) | /* must be 1 */
236 (0 << 5) | /* disable clock gating for NOA */
237 (0 << 4) | /* terminate if AVC motion and POC table error occurs */
238 (0 << 3) | /* terminate if AVC mbdata error occurs */
239 (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */
240 (0 << 1) | /* AVC long field motion vector */
241 (1 << 0)); /* always calculate AVC ILDB boundary strength */
242 OUT_BCS_BATCH(batch, 0);
243 ADVANCE_BCS_BATCH(batch);
247 gen6_mfd_surface_state(VADriverContextP ctx,
248 struct decode_state *decode_state,
250 struct gen6_mfd_context *gen6_mfd_context)
252 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
253 struct i965_driver_data *i965 = i965_driver_data(ctx);
254 struct object_surface *obj_surface = SURFACE(decode_state->current_render_target);
257 BEGIN_BCS_BATCH(batch, 6);
258 OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
259 OUT_BCS_BATCH(batch, 0);
261 ((obj_surface->orig_height - 1) << 19) |
262 ((obj_surface->orig_width - 1) << 6));
264 (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
265 (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
266 (0 << 22) | /* surface object control state, FIXME??? */
267 ((obj_surface->width - 1) << 3) | /* pitch */
268 (0 << 2) | /* must be 0 for interleave U/V */
269 (1 << 1) | /* must be y-tiled */
270 (I965_TILEWALK_YMAJOR << 0)); /* tile walk, FIXME: must be 1 ??? */
272 (0 << 16) | /* must be 0 for interleave U/V */
273 (obj_surface->height)); /* y offset for U(cb) */
274 OUT_BCS_BATCH(batch, 0);
275 ADVANCE_BCS_BATCH(batch);
279 gen6_mfd_pipe_buf_addr_state(VADriverContextP ctx,
280 struct decode_state *decode_state,
282 struct gen6_mfd_context *gen6_mfd_context)
284 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
285 struct i965_driver_data *i965 = i965_driver_data(ctx);
288 BEGIN_BCS_BATCH(batch, 24);
289 OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
290 if (gen6_mfd_context->pre_deblocking_output.valid)
291 OUT_BCS_RELOC(batch, gen6_mfd_context->pre_deblocking_output.bo,
292 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
295 OUT_BCS_BATCH(batch, 0);
297 if (gen6_mfd_context->post_deblocking_output.valid)
298 OUT_BCS_RELOC(batch, gen6_mfd_context->post_deblocking_output.bo,
299 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
302 OUT_BCS_BATCH(batch, 0);
304 OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
305 OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
307 if (gen6_mfd_context->intra_row_store_scratch_buffer.valid)
308 OUT_BCS_RELOC(batch, gen6_mfd_context->intra_row_store_scratch_buffer.bo,
309 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
312 OUT_BCS_BATCH(batch, 0);
314 if (gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid)
315 OUT_BCS_RELOC(batch, gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo,
316 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
319 OUT_BCS_BATCH(batch, 0);
322 for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) {
323 struct object_surface *obj_surface;
325 if (gen6_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
326 obj_surface = SURFACE(gen6_mfd_context->reference_surface[i].surface_id);
327 assert(obj_surface && obj_surface->bo);
329 OUT_BCS_RELOC(batch, obj_surface->bo,
330 I915_GEM_DOMAIN_INSTRUCTION, 0,
333 OUT_BCS_BATCH(batch, 0);
337 OUT_BCS_BATCH(batch, 0); /* ignore DW23 for decoding */
338 ADVANCE_BCS_BATCH(batch);
342 gen6_mfd_ind_obj_base_addr_state(VADriverContextP ctx,
343 dri_bo *slice_data_bo,
345 struct gen6_mfd_context *gen6_mfd_context)
347 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
349 BEGIN_BCS_BATCH(batch, 11);
350 OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
351 OUT_BCS_RELOC(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */
352 OUT_BCS_BATCH(batch, 0);
353 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
354 OUT_BCS_BATCH(batch, 0);
355 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
356 OUT_BCS_BATCH(batch, 0);
357 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
358 OUT_BCS_BATCH(batch, 0);
359 OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
360 OUT_BCS_BATCH(batch, 0);
361 ADVANCE_BCS_BATCH(batch);
365 gen6_mfd_bsp_buf_base_addr_state(VADriverContextP ctx,
366 struct decode_state *decode_state,
368 struct gen6_mfd_context *gen6_mfd_context)
370 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
372 BEGIN_BCS_BATCH(batch, 4);
373 OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
375 if (gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid)
376 OUT_BCS_RELOC(batch, gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo,
377 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
380 OUT_BCS_BATCH(batch, 0);
382 if (gen6_mfd_context->mpr_row_store_scratch_buffer.valid)
383 OUT_BCS_RELOC(batch, gen6_mfd_context->mpr_row_store_scratch_buffer.bo,
384 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
387 OUT_BCS_BATCH(batch, 0);
389 if (gen6_mfd_context->bitplane_read_buffer.valid)
390 OUT_BCS_RELOC(batch, gen6_mfd_context->bitplane_read_buffer.bo,
391 I915_GEM_DOMAIN_INSTRUCTION, 0,
394 OUT_BCS_BATCH(batch, 0);
396 ADVANCE_BCS_BATCH(batch);
401 gen6_mfd_aes_state(VADriverContextP ctx,
402 struct decode_state *decode_state,
409 gen6_mfd_wait(VADriverContextP ctx,
410 struct decode_state *decode_state,
412 struct gen6_mfd_context *gen6_mfd_context)
414 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
416 BEGIN_BCS_BATCH(batch, 1);
417 OUT_BCS_BATCH(batch, MFX_WAIT | (1 << 8));
418 ADVANCE_BCS_BATCH(batch);
423 gen6_mfd_avc_img_state(VADriverContextP ctx,
424 struct decode_state *decode_state,
425 struct gen6_mfd_context *gen6_mfd_context)
427 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
430 int mbaff_frame_flag;
431 unsigned int width_in_mbs, height_in_mbs;
432 VAPictureParameterBufferH264 *pic_param;
434 assert(decode_state->pic_param && decode_state->pic_param->buffer);
435 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
436 assert(!(pic_param->CurrPic.flags & VA_PICTURE_H264_INVALID));
438 if (decode_state->iq_matrix && decode_state->iq_matrix->buffer)
441 qm_present_flag = 0; /* built-in QM matrices */
443 if (pic_param->CurrPic.flags & VA_PICTURE_H264_TOP_FIELD)
445 else if (pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD)
450 if ((img_struct & 0x1) == 0x1) {
451 assert(pic_param->pic_fields.bits.field_pic_flag == 0x1);
453 assert(pic_param->pic_fields.bits.field_pic_flag == 0x0);
456 if (pic_param->seq_fields.bits.frame_mbs_only_flag) { /* a frame containing only frame macroblocks */
457 assert(pic_param->seq_fields.bits.mb_adaptive_frame_field_flag == 0);
458 assert(pic_param->pic_fields.bits.field_pic_flag == 0);
460 assert(pic_param->seq_fields.bits.direct_8x8_inference_flag == 1); /* see H.264 spec */
463 mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag &&
464 !pic_param->pic_fields.bits.field_pic_flag);
466 width_in_mbs = ((pic_param->picture_width_in_mbs_minus1 + 1) & 0xff);
467 height_in_mbs = ((pic_param->picture_height_in_mbs_minus1 + 1) & 0xff); /* frame height */
468 assert(!((width_in_mbs * height_in_mbs) & 0x8000)); /* hardware requirement */
470 /* MFX unit doesn't support 4:2:2 and 4:4:4 picture */
471 assert(pic_param->seq_fields.bits.chroma_format_idc == 0 || /* monochrome picture */
472 pic_param->seq_fields.bits.chroma_format_idc == 1); /* 4:2:0 */
473 assert(pic_param->seq_fields.bits.residual_colour_transform_flag == 0); /* only available for 4:4:4 */
475 BEGIN_BCS_BATCH(batch, 13);
476 OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (13 - 2));
478 ((width_in_mbs * height_in_mbs) & 0x7fff));
480 (height_in_mbs << 16) |
481 (width_in_mbs << 0));
483 ((pic_param->second_chroma_qp_index_offset & 0x1f) << 24) |
484 ((pic_param->chroma_qp_index_offset & 0x1f) << 16) |
485 (0 << 14) | /* Max-bit conformance Intra flag ??? FIXME */
486 (0 << 13) | /* Max Macroblock size conformance Inter flag ??? FIXME */
487 (1 << 12) | /* always 1, hardware requirement */
488 (qm_present_flag << 10) |
492 (pic_param->seq_fields.bits.chroma_format_idc << 10) |
493 (pic_param->pic_fields.bits.entropy_coding_mode_flag << 7) |
494 ((!pic_param->pic_fields.bits.reference_pic_flag) << 6) |
495 (pic_param->pic_fields.bits.constrained_intra_pred_flag << 5) |
496 (pic_param->seq_fields.bits.direct_8x8_inference_flag << 4) |
497 (pic_param->pic_fields.bits.transform_8x8_mode_flag << 3) |
498 (pic_param->seq_fields.bits.frame_mbs_only_flag << 2) |
499 (mbaff_frame_flag << 1) |
500 (pic_param->pic_fields.bits.field_pic_flag << 0));
501 OUT_BCS_BATCH(batch, 0);
502 OUT_BCS_BATCH(batch, 0);
503 OUT_BCS_BATCH(batch, 0);
504 OUT_BCS_BATCH(batch, 0);
505 OUT_BCS_BATCH(batch, 0);
506 OUT_BCS_BATCH(batch, 0);
507 OUT_BCS_BATCH(batch, 0);
508 OUT_BCS_BATCH(batch, 0);
509 ADVANCE_BCS_BATCH(batch);
513 gen6_mfd_avc_qm_state(VADriverContextP ctx,
514 struct decode_state *decode_state,
515 struct gen6_mfd_context *gen6_mfd_context)
517 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
519 VAIQMatrixBufferH264 *iq_matrix;
520 VAPictureParameterBufferH264 *pic_param;
522 if (!decode_state->iq_matrix || !decode_state->iq_matrix->buffer)
525 iq_matrix = (VAIQMatrixBufferH264 *)decode_state->iq_matrix->buffer;
527 assert(decode_state->pic_param && decode_state->pic_param->buffer);
528 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
530 cmd_len = 2 + 6 * 4; /* always load six 4x4 scaling matrices */
532 if (pic_param->pic_fields.bits.transform_8x8_mode_flag)
533 cmd_len += 2 * 16; /* load two 8x8 scaling matrices */
535 BEGIN_BCS_BATCH(batch, cmd_len);
536 OUT_BCS_BATCH(batch, MFX_AVC_QM_STATE | (cmd_len - 2));
538 if (pic_param->pic_fields.bits.transform_8x8_mode_flag)
540 (0x0 << 8) | /* don't use default built-in matrices */
541 (0xff << 0)); /* six 4x4 and two 8x8 scaling matrices */
544 (0x0 << 8) | /* don't use default built-in matrices */
545 (0x3f << 0)); /* six 4x4 scaling matrices */
547 intel_batchbuffer_data(batch, &iq_matrix->ScalingList4x4[0][0], 6 * 4 * 4);
549 if (pic_param->pic_fields.bits.transform_8x8_mode_flag)
550 intel_batchbuffer_data(batch, &iq_matrix->ScalingList8x8[0][0], 2 * 16 * 4);
552 ADVANCE_BCS_BATCH(batch);
556 gen6_mfd_avc_directmode_state(VADriverContextP ctx,
557 VAPictureParameterBufferH264 *pic_param,
558 VASliceParameterBufferH264 *slice_param,
559 struct gen6_mfd_context *gen6_mfd_context)
561 struct i965_driver_data *i965 = i965_driver_data(ctx);
562 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
563 struct object_surface *obj_surface;
564 GenAvcSurface *gen6_avc_surface;
565 VAPictureH264 *va_pic;
568 BEGIN_BCS_BATCH(batch, 69);
569 OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
571 /* reference surfaces 0..15 */
572 for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) {
573 if (gen6_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
574 obj_surface = SURFACE(gen6_mfd_context->reference_surface[i].surface_id);
576 gen6_avc_surface = obj_surface->private_data;
578 if (gen6_avc_surface == NULL) {
579 OUT_BCS_BATCH(batch, 0);
580 OUT_BCS_BATCH(batch, 0);
582 OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top,
583 I915_GEM_DOMAIN_INSTRUCTION, 0,
586 if (gen6_avc_surface->dmv_bottom_flag == 1)
587 OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_bottom,
588 I915_GEM_DOMAIN_INSTRUCTION, 0,
591 OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top,
592 I915_GEM_DOMAIN_INSTRUCTION, 0,
596 OUT_BCS_BATCH(batch, 0);
597 OUT_BCS_BATCH(batch, 0);
601 /* the current decoding frame/field */
602 va_pic = &pic_param->CurrPic;
603 assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
604 obj_surface = SURFACE(va_pic->picture_id);
605 assert(obj_surface && obj_surface->bo && obj_surface->private_data);
606 gen6_avc_surface = obj_surface->private_data;
608 OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top,
609 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
612 if (gen6_avc_surface->dmv_bottom_flag == 1)
613 OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_bottom,
614 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
617 OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top,
618 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
622 for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) {
623 if (gen6_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
625 for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) {
626 va_pic = &pic_param->ReferenceFrames[j];
628 if (va_pic->flags & VA_PICTURE_H264_INVALID)
631 if (va_pic->picture_id == gen6_mfd_context->reference_surface[i].surface_id) {
638 assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
640 OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
641 OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
643 OUT_BCS_BATCH(batch, 0);
644 OUT_BCS_BATCH(batch, 0);
648 va_pic = &pic_param->CurrPic;
649 OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
650 OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
652 ADVANCE_BCS_BATCH(batch);
656 gen6_mfd_avc_slice_state(VADriverContextP ctx,
657 VAPictureParameterBufferH264 *pic_param,
658 VASliceParameterBufferH264 *slice_param,
659 VASliceParameterBufferH264 *next_slice_param,
660 struct gen6_mfd_context *gen6_mfd_context)
662 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
663 int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
664 int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1;
665 int slice_hor_pos, slice_ver_pos, next_slice_hor_pos, next_slice_ver_pos;
666 int num_ref_idx_l0, num_ref_idx_l1;
667 int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag &&
668 pic_param->seq_fields.bits.mb_adaptive_frame_field_flag);
669 int weighted_pred_idc = 0;
670 int first_mb_in_slice = 0, first_mb_in_next_slice = 0;
673 if (slice_param->slice_type == SLICE_TYPE_I ||
674 slice_param->slice_type == SLICE_TYPE_SI) {
675 slice_type = SLICE_TYPE_I;
676 } else if (slice_param->slice_type == SLICE_TYPE_P ||
677 slice_param->slice_type == SLICE_TYPE_SP) {
678 slice_type = SLICE_TYPE_P;
680 assert(slice_param->slice_type == SLICE_TYPE_B);
681 slice_type = SLICE_TYPE_B;
684 if (slice_type == SLICE_TYPE_I) {
685 assert(slice_param->num_ref_idx_l0_active_minus1 == 0);
686 assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
689 } else if (slice_type == SLICE_TYPE_P) {
690 assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
691 num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
693 weighted_pred_idc = (pic_param->pic_fields.bits.weighted_pred_flag == 1);
695 num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
696 num_ref_idx_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
697 weighted_pred_idc = (pic_param->pic_fields.bits.weighted_bipred_idc == 1);
700 first_mb_in_slice = slice_param->first_mb_in_slice << mbaff_picture;
701 slice_hor_pos = first_mb_in_slice % width_in_mbs;
702 slice_ver_pos = first_mb_in_slice / width_in_mbs;
704 if (next_slice_param) {
705 first_mb_in_next_slice = next_slice_param->first_mb_in_slice << mbaff_picture;
706 next_slice_hor_pos = first_mb_in_next_slice % width_in_mbs;
707 next_slice_ver_pos = first_mb_in_next_slice / width_in_mbs;
709 next_slice_hor_pos = 0;
710 next_slice_ver_pos = height_in_mbs;
713 BEGIN_BCS_BATCH(batch, 11); /* FIXME: is it 10??? */
714 OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
715 OUT_BCS_BATCH(batch, slice_type);
717 (num_ref_idx_l1 << 24) |
718 (num_ref_idx_l0 << 16) |
719 (slice_param->chroma_log2_weight_denom << 8) |
720 (slice_param->luma_log2_weight_denom << 0));
722 (weighted_pred_idc << 30) |
723 (slice_param->direct_spatial_mv_pred_flag << 29) |
724 (slice_param->disable_deblocking_filter_idc << 27) |
725 (slice_param->cabac_init_idc << 24) |
726 ((pic_param->pic_init_qp_minus26 + 26 + slice_param->slice_qp_delta) << 16) |
727 ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
728 ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
730 (slice_ver_pos << 24) |
731 (slice_hor_pos << 16) |
732 (first_mb_in_slice << 0));
734 (next_slice_ver_pos << 16) |
735 (next_slice_hor_pos << 0));
737 (next_slice_param == NULL) << 19); /* last slice flag */
738 OUT_BCS_BATCH(batch, 0);
739 OUT_BCS_BATCH(batch, 0);
740 OUT_BCS_BATCH(batch, 0);
741 OUT_BCS_BATCH(batch, 0);
742 ADVANCE_BCS_BATCH(batch);
746 gen6_mfd_avc_phantom_slice_state(VADriverContextP ctx,
747 VAPictureParameterBufferH264 *pic_param,
748 struct gen6_mfd_context *gen6_mfd_context)
750 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
751 int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
752 int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */
754 BEGIN_BCS_BATCH(batch, 11); /* FIXME: is it 10??? */
755 OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
756 OUT_BCS_BATCH(batch, 0);
757 OUT_BCS_BATCH(batch, 0);
758 OUT_BCS_BATCH(batch, 0);
760 height_in_mbs << 24 |
761 width_in_mbs * height_in_mbs / (1 + !!pic_param->pic_fields.bits.field_pic_flag));
762 OUT_BCS_BATCH(batch, 0);
763 OUT_BCS_BATCH(batch, 0);
764 OUT_BCS_BATCH(batch, 0);
765 OUT_BCS_BATCH(batch, 0);
766 OUT_BCS_BATCH(batch, 0);
767 OUT_BCS_BATCH(batch, 0);
768 ADVANCE_BCS_BATCH(batch);
772 gen6_mfd_avc_ref_idx_state(VADriverContextP ctx,
773 VAPictureParameterBufferH264 *pic_param,
774 VASliceParameterBufferH264 *slice_param,
775 struct gen6_mfd_context *gen6_mfd_context)
777 gen6_send_avc_ref_idx_state(
778 gen6_mfd_context->base.batch,
780 gen6_mfd_context->reference_surface
785 gen6_mfd_avc_weightoffset_state(VADriverContextP ctx,
786 VAPictureParameterBufferH264 *pic_param,
787 VASliceParameterBufferH264 *slice_param,
788 struct gen6_mfd_context *gen6_mfd_context)
790 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
791 int i, j, num_weight_offset_table = 0;
792 short weightoffsets[32 * 6];
794 if ((slice_param->slice_type == SLICE_TYPE_P ||
795 slice_param->slice_type == SLICE_TYPE_SP) &&
796 (pic_param->pic_fields.bits.weighted_pred_flag == 1)) {
797 num_weight_offset_table = 1;
800 if ((slice_param->slice_type == SLICE_TYPE_B) &&
801 (pic_param->pic_fields.bits.weighted_bipred_idc == 1)) {
802 num_weight_offset_table = 2;
805 for (i = 0; i < num_weight_offset_table; i++) {
806 BEGIN_BCS_BATCH(batch, 98);
807 OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2));
808 OUT_BCS_BATCH(batch, i);
811 for (j = 0; j < 32; j++) {
812 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l0[j];
813 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l0[j];
814 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l0[j][0];
815 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l0[j][0];
816 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l0[j][1];
817 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l0[j][1];
820 for (j = 0; j < 32; j++) {
821 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l1[j];
822 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l1[j];
823 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l1[j][0];
824 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l1[j][0];
825 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l1[j][1];
826 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l1[j][1];
830 intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
831 ADVANCE_BCS_BATCH(batch);
836 gen6_mfd_avc_bsd_object(VADriverContextP ctx,
837 VAPictureParameterBufferH264 *pic_param,
838 VASliceParameterBufferH264 *slice_param,
839 dri_bo *slice_data_bo,
840 struct gen6_mfd_context *gen6_mfd_context)
842 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
843 unsigned int slice_data_bit_offset;
845 slice_data_bit_offset = avc_get_first_mb_bit_offset(
848 pic_param->pic_fields.bits.entropy_coding_mode_flag
851 BEGIN_BCS_BATCH(batch, 6);
852 OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
854 (slice_param->slice_data_size - slice_param->slice_data_offset));
855 OUT_BCS_BATCH(batch, slice_param->slice_data_offset);
863 ((slice_data_bit_offset >> 3) << 16) |
865 ((0x7 - (slice_data_bit_offset & 0x7)) << 0));
866 OUT_BCS_BATCH(batch, 0);
867 ADVANCE_BCS_BATCH(batch);
871 gen6_mfd_avc_phantom_slice_bsd_object(VADriverContextP ctx,
872 VAPictureParameterBufferH264 *pic_param,
873 struct gen6_mfd_context *gen6_mfd_context)
875 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
877 BEGIN_BCS_BATCH(batch, 6);
878 OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
879 OUT_BCS_BATCH(batch, 0);
880 OUT_BCS_BATCH(batch, 0);
881 OUT_BCS_BATCH(batch, 0);
882 OUT_BCS_BATCH(batch, 0);
883 OUT_BCS_BATCH(batch, 0);
884 ADVANCE_BCS_BATCH(batch);
888 gen6_mfd_avc_phantom_slice(VADriverContextP ctx,
889 VAPictureParameterBufferH264 *pic_param,
890 struct gen6_mfd_context *gen6_mfd_context)
892 gen6_mfd_avc_phantom_slice_state(ctx, pic_param, gen6_mfd_context);
893 gen6_mfd_avc_phantom_slice_bsd_object(ctx, pic_param, gen6_mfd_context);
897 gen6_mfd_avc_decode_init(VADriverContextP ctx,
898 struct decode_state *decode_state,
899 struct gen6_mfd_context *gen6_mfd_context)
901 VAPictureParameterBufferH264 *pic_param;
902 VASliceParameterBufferH264 *slice_param;
903 VAPictureH264 *va_pic;
904 struct i965_driver_data *i965 = i965_driver_data(ctx);
905 struct object_surface *obj_surface;
907 int i, j, enable_avc_ildb = 0;
910 for (j = 0; j < decode_state->num_slice_params && enable_avc_ildb == 0; j++) {
911 assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
912 slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
914 for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
915 assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
916 assert((slice_param->slice_type == SLICE_TYPE_I) ||
917 (slice_param->slice_type == SLICE_TYPE_SI) ||
918 (slice_param->slice_type == SLICE_TYPE_P) ||
919 (slice_param->slice_type == SLICE_TYPE_SP) ||
920 (slice_param->slice_type == SLICE_TYPE_B));
922 if (slice_param->disable_deblocking_filter_idc != 1) {
931 assert(decode_state->pic_param && decode_state->pic_param->buffer);
932 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
933 gen6_mfd_avc_frame_store_index(ctx, pic_param, gen6_mfd_context);
934 width_in_mbs = ((pic_param->picture_width_in_mbs_minus1 + 1) & 0xff);
936 /* Current decoded picture */
937 va_pic = &pic_param->CurrPic;
938 assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
939 obj_surface = SURFACE(va_pic->picture_id);
941 obj_surface->flags &= ~SURFACE_REF_DIS_MASK;
942 obj_surface->flags |= (pic_param->pic_fields.bits.reference_pic_flag ? SURFACE_REFERENCED : 0);
943 i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
945 /* initial uv component for YUV400 case */
946 if (pic_param->seq_fields.bits.chroma_format_idc == 0) {
947 unsigned int uv_offset = obj_surface->width * obj_surface->height;
948 unsigned int uv_size = obj_surface->width * obj_surface->height / 2;
950 drm_intel_gem_bo_map_gtt(obj_surface->bo);
951 memset(obj_surface->bo->virtual + uv_offset, 0x80, uv_size);
952 drm_intel_gem_bo_unmap_gtt(obj_surface->bo);
955 gen6_mfd_init_avc_surface(ctx, pic_param, obj_surface);
957 dri_bo_unreference(gen6_mfd_context->post_deblocking_output.bo);
958 gen6_mfd_context->post_deblocking_output.bo = obj_surface->bo;
959 dri_bo_reference(gen6_mfd_context->post_deblocking_output.bo);
960 gen6_mfd_context->post_deblocking_output.valid = enable_avc_ildb;
962 dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo);
963 gen6_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
964 dri_bo_reference(gen6_mfd_context->pre_deblocking_output.bo);
965 gen6_mfd_context->pre_deblocking_output.valid = !enable_avc_ildb;
967 dri_bo_unreference(gen6_mfd_context->intra_row_store_scratch_buffer.bo);
968 bo = dri_bo_alloc(i965->intel.bufmgr,
973 gen6_mfd_context->intra_row_store_scratch_buffer.bo = bo;
974 gen6_mfd_context->intra_row_store_scratch_buffer.valid = 1;
976 dri_bo_unreference(gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
977 bo = dri_bo_alloc(i965->intel.bufmgr,
978 "deblocking filter row store",
979 width_in_mbs * 64 * 4,
982 gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
983 gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
985 dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
986 bo = dri_bo_alloc(i965->intel.bufmgr,
991 gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
992 gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
994 dri_bo_unreference(gen6_mfd_context->mpr_row_store_scratch_buffer.bo);
995 bo = dri_bo_alloc(i965->intel.bufmgr,
1000 gen6_mfd_context->mpr_row_store_scratch_buffer.bo = bo;
1001 gen6_mfd_context->mpr_row_store_scratch_buffer.valid = 1;
1003 gen6_mfd_context->bitplane_read_buffer.valid = 0;
1007 gen6_mfd_avc_decode_picture(VADriverContextP ctx,
1008 struct decode_state *decode_state,
1009 struct gen6_mfd_context *gen6_mfd_context)
1011 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1012 VAPictureParameterBufferH264 *pic_param;
1013 VASliceParameterBufferH264 *slice_param, *next_slice_param, *next_slice_group_param;
1014 dri_bo *slice_data_bo;
1017 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1018 pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
1019 gen6_mfd_avc_decode_init(ctx, decode_state, gen6_mfd_context);
1021 intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1022 intel_batchbuffer_emit_mi_flush(batch);
1023 gen6_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context);
1024 gen6_mfd_surface_state(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context);
1025 gen6_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context);
1026 gen6_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context);
1027 gen6_mfd_avc_img_state(ctx, decode_state, gen6_mfd_context);
1028 gen6_mfd_avc_qm_state(ctx, decode_state, gen6_mfd_context);
1030 for (j = 0; j < decode_state->num_slice_params; j++) {
1031 assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1032 slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
1033 slice_data_bo = decode_state->slice_datas[j]->bo;
1034 gen6_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_AVC, gen6_mfd_context);
1036 if (j == decode_state->num_slice_params - 1)
1037 next_slice_group_param = NULL;
1039 next_slice_group_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j + 1]->buffer;
1041 for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1042 assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1043 assert((slice_param->slice_type == SLICE_TYPE_I) ||
1044 (slice_param->slice_type == SLICE_TYPE_SI) ||
1045 (slice_param->slice_type == SLICE_TYPE_P) ||
1046 (slice_param->slice_type == SLICE_TYPE_SP) ||
1047 (slice_param->slice_type == SLICE_TYPE_B));
1049 if (i < decode_state->slice_params[j]->num_elements - 1)
1050 next_slice_param = slice_param + 1;
1052 next_slice_param = next_slice_group_param;
1054 gen6_mfd_avc_directmode_state(ctx, pic_param, slice_param, gen6_mfd_context);
1055 gen6_mfd_avc_slice_state(ctx, pic_param, slice_param, next_slice_param, gen6_mfd_context);
1056 gen6_mfd_avc_ref_idx_state(ctx, pic_param, slice_param, gen6_mfd_context);
1057 gen6_mfd_avc_weightoffset_state(ctx, pic_param, slice_param, gen6_mfd_context);
1058 gen6_mfd_avc_bsd_object(ctx, pic_param, slice_param, slice_data_bo, gen6_mfd_context);
1063 gen6_mfd_avc_phantom_slice(ctx, pic_param, gen6_mfd_context);
1064 intel_batchbuffer_end_atomic(batch);
1065 intel_batchbuffer_flush(batch);
1069 gen6_mfd_mpeg2_decode_init(VADriverContextP ctx,
1070 struct decode_state *decode_state,
1071 struct gen6_mfd_context *gen6_mfd_context)
1073 VAPictureParameterBufferMPEG2 *pic_param;
1074 struct i965_driver_data *i965 = i965_driver_data(ctx);
1075 struct object_surface *obj_surface;
1077 unsigned int width_in_mbs;
1079 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1080 pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1081 width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
1083 mpeg2_set_reference_surfaces(
1085 gen6_mfd_context->reference_surface,
1090 /* Current decoded picture */
1091 obj_surface = SURFACE(decode_state->current_render_target);
1092 assert(obj_surface);
1093 i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
1095 dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo);
1096 gen6_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1097 dri_bo_reference(gen6_mfd_context->pre_deblocking_output.bo);
1098 gen6_mfd_context->pre_deblocking_output.valid = 1;
1100 dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1101 bo = dri_bo_alloc(i965->intel.bufmgr,
1102 "bsd mpc row store",
1106 gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1107 gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1109 gen6_mfd_context->post_deblocking_output.valid = 0;
1110 gen6_mfd_context->intra_row_store_scratch_buffer.valid = 0;
1111 gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0;
1112 gen6_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1113 gen6_mfd_context->bitplane_read_buffer.valid = 0;
1117 gen6_mfd_mpeg2_pic_state(VADriverContextP ctx,
1118 struct decode_state *decode_state,
1119 struct gen6_mfd_context *gen6_mfd_context)
1121 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1122 VAPictureParameterBufferMPEG2 *pic_param;
1123 unsigned int tff, pic_structure;
1125 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1126 pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1128 pic_structure = pic_param->picture_coding_extension.bits.picture_structure;
1129 if (pic_structure == MPEG_FRAME)
1130 tff = pic_param->picture_coding_extension.bits.top_field_first;
1132 tff = !(pic_param->picture_coding_extension.bits.is_first_field ^
1133 (pic_structure & MPEG_TOP_FIELD));
1135 BEGIN_BCS_BATCH(batch, 4);
1136 OUT_BCS_BATCH(batch, MFX_MPEG2_PIC_STATE | (4 - 2));
1137 OUT_BCS_BATCH(batch,
1138 (pic_param->f_code & 0xf) << 28 | /* f_code[1][1] */
1139 ((pic_param->f_code >> 4) & 0xf) << 24 | /* f_code[1][0] */
1140 ((pic_param->f_code >> 8) & 0xf) << 20 | /* f_code[0][1] */
1141 ((pic_param->f_code >> 12) & 0xf) << 16 | /* f_code[0][0] */
1142 pic_param->picture_coding_extension.bits.intra_dc_precision << 14 |
1143 pic_param->picture_coding_extension.bits.picture_structure << 12 |
1145 pic_param->picture_coding_extension.bits.frame_pred_frame_dct << 10 |
1146 pic_param->picture_coding_extension.bits.concealment_motion_vectors << 9 |
1147 pic_param->picture_coding_extension.bits.q_scale_type << 8 |
1148 pic_param->picture_coding_extension.bits.intra_vlc_format << 7 |
1149 pic_param->picture_coding_extension.bits.alternate_scan << 6);
1150 OUT_BCS_BATCH(batch,
1151 pic_param->picture_coding_type << 9);
1152 OUT_BCS_BATCH(batch,
1153 (ALIGN(pic_param->vertical_size, 16) / 16) << 16 |
1154 (ALIGN(pic_param->horizontal_size, 16) / 16));
1155 ADVANCE_BCS_BATCH(batch);
1159 gen6_mfd_mpeg2_qm_state(VADriverContextP ctx,
1160 struct decode_state *decode_state,
1161 struct gen6_mfd_context *gen6_mfd_context)
1163 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1164 VAIQMatrixBufferMPEG2 * const gen_iq_matrix = &gen6_mfd_context->iq_matrix.mpeg2;
1167 /* Update internal QM state */
1168 if (decode_state->iq_matrix && decode_state->iq_matrix->buffer) {
1169 VAIQMatrixBufferMPEG2 * const iq_matrix =
1170 (VAIQMatrixBufferMPEG2 *)decode_state->iq_matrix->buffer;
1172 gen_iq_matrix->load_intra_quantiser_matrix =
1173 iq_matrix->load_intra_quantiser_matrix;
1174 if (iq_matrix->load_intra_quantiser_matrix) {
1175 for (j = 0; j < 64; j++)
1176 gen_iq_matrix->intra_quantiser_matrix[zigzag_direct[j]] =
1177 iq_matrix->intra_quantiser_matrix[j];
1180 gen_iq_matrix->load_non_intra_quantiser_matrix =
1181 iq_matrix->load_non_intra_quantiser_matrix;
1182 if (iq_matrix->load_non_intra_quantiser_matrix) {
1183 for (j = 0; j < 64; j++)
1184 gen_iq_matrix->non_intra_quantiser_matrix[zigzag_direct[j]] =
1185 iq_matrix->non_intra_quantiser_matrix[j];
1189 /* Commit QM state to HW */
1190 for (i = 0; i < 2; i++) {
1191 unsigned char *qm = NULL;
1194 if (gen_iq_matrix->load_intra_quantiser_matrix)
1195 qm = gen_iq_matrix->intra_quantiser_matrix;
1197 if (gen_iq_matrix->load_non_intra_quantiser_matrix)
1198 qm = gen_iq_matrix->non_intra_quantiser_matrix;
1204 BEGIN_BCS_BATCH(batch, 18);
1205 OUT_BCS_BATCH(batch, MFX_MPEG2_QM_STATE | (18 - 2));
1206 OUT_BCS_BATCH(batch, i);
1207 intel_batchbuffer_data(batch, qm, 64);
1208 ADVANCE_BCS_BATCH(batch);
1213 gen6_mfd_mpeg2_bsd_object(VADriverContextP ctx,
1214 VAPictureParameterBufferMPEG2 *pic_param,
1215 VASliceParameterBufferMPEG2 *slice_param,
1216 VASliceParameterBufferMPEG2 *next_slice_param,
1217 struct gen6_mfd_context *gen6_mfd_context)
1219 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1220 unsigned int width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
1221 int mb_count, vpos0, hpos0, vpos1, hpos1, is_field_pic_wa, is_field_pic = 0;
1223 if (pic_param->picture_coding_extension.bits.picture_structure == MPEG_TOP_FIELD ||
1224 pic_param->picture_coding_extension.bits.picture_structure == MPEG_BOTTOM_FIELD)
1226 is_field_pic_wa = is_field_pic &&
1227 gen6_mfd_context->wa_mpeg2_slice_vertical_position > 0;
1229 vpos0 = slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1230 hpos0 = slice_param->slice_horizontal_position;
1232 if (next_slice_param == NULL) {
1233 vpos1 = ALIGN(pic_param->vertical_size, 16) / 16 / (1 + is_field_pic);
1236 vpos1 = next_slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1237 hpos1 = next_slice_param->slice_horizontal_position;
1240 mb_count = (vpos1 * width_in_mbs + hpos1) - (vpos0 * width_in_mbs + hpos0);
1242 BEGIN_BCS_BATCH(batch, 5);
1243 OUT_BCS_BATCH(batch, MFD_MPEG2_BSD_OBJECT | (5 - 2));
1244 OUT_BCS_BATCH(batch,
1245 slice_param->slice_data_size - (slice_param->macroblock_offset >> 3));
1246 OUT_BCS_BATCH(batch,
1247 slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3));
1248 OUT_BCS_BATCH(batch,
1252 (next_slice_param == NULL) << 5 |
1253 (next_slice_param == NULL) << 3 |
1254 (slice_param->macroblock_offset & 0x7));
1255 OUT_BCS_BATCH(batch,
1256 slice_param->quantiser_scale_code << 24);
1257 ADVANCE_BCS_BATCH(batch);
1261 gen6_mfd_mpeg2_decode_picture(VADriverContextP ctx,
1262 struct decode_state *decode_state,
1263 struct gen6_mfd_context *gen6_mfd_context)
1265 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1266 VAPictureParameterBufferMPEG2 *pic_param;
1267 VASliceParameterBufferMPEG2 *slice_param, *next_slice_param, *next_slice_group_param;
1268 dri_bo *slice_data_bo;
1271 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1272 pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1274 gen6_mfd_mpeg2_decode_init(ctx, decode_state, gen6_mfd_context);
1275 intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1276 intel_batchbuffer_emit_mi_flush(batch);
1277 gen6_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context);
1278 gen6_mfd_surface_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context);
1279 gen6_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context);
1280 gen6_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context);
1281 gen6_mfd_mpeg2_pic_state(ctx, decode_state, gen6_mfd_context);
1282 gen6_mfd_mpeg2_qm_state(ctx, decode_state, gen6_mfd_context);
1284 if (gen6_mfd_context->wa_mpeg2_slice_vertical_position < 0)
1285 gen6_mfd_context->wa_mpeg2_slice_vertical_position =
1286 mpeg2_wa_slice_vertical_position(decode_state, pic_param);
1288 for (j = 0; j < decode_state->num_slice_params; j++) {
1289 assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1290 slice_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j]->buffer;
1291 slice_data_bo = decode_state->slice_datas[j]->bo;
1292 gen6_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_MPEG2, gen6_mfd_context);
1294 if (j == decode_state->num_slice_params - 1)
1295 next_slice_group_param = NULL;
1297 next_slice_group_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j + 1]->buffer;
1299 for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1300 assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1302 if (i < decode_state->slice_params[j]->num_elements - 1)
1303 next_slice_param = slice_param + 1;
1305 next_slice_param = next_slice_group_param;
1307 gen6_mfd_mpeg2_bsd_object(ctx, pic_param, slice_param, next_slice_param, gen6_mfd_context);
1312 intel_batchbuffer_end_atomic(batch);
1313 intel_batchbuffer_flush(batch);
1316 static const int va_to_gen6_vc1_pic_type[5] = {
1320 GEN6_VC1_BI_PICTURE,
1324 static const int va_to_gen6_vc1_mv[4] = {
1326 2, /* 1-MV half-pel */
1327 3, /* 1-MV half-pef bilinear */
1331 static const int b_picture_scale_factor[21] = {
1332 128, 85, 170, 64, 192,
1333 51, 102, 153, 204, 43,
1334 215, 37, 74, 111, 148,
1335 185, 222, 32, 96, 160,
1339 static const int va_to_gen6_vc1_condover[3] = {
1345 static const int va_to_gen6_vc1_profile[4] = {
1346 GEN6_VC1_SIMPLE_PROFILE,
1347 GEN6_VC1_MAIN_PROFILE,
1348 GEN6_VC1_RESERVED_PROFILE,
1349 GEN6_VC1_ADVANCED_PROFILE
1353 gen6_mfd_free_vc1_surface(void **data)
1355 struct gen6_vc1_surface *gen6_vc1_surface = *data;
1357 if (!gen6_vc1_surface)
1360 dri_bo_unreference(gen6_vc1_surface->dmv);
1361 free(gen6_vc1_surface);
1366 gen6_mfd_init_vc1_surface(VADriverContextP ctx,
1367 VAPictureParameterBufferVC1 *pic_param,
1368 struct object_surface *obj_surface)
1370 struct i965_driver_data *i965 = i965_driver_data(ctx);
1371 struct gen6_vc1_surface *gen6_vc1_surface = obj_surface->private_data;
1372 int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1374 obj_surface->free_private_data = gen6_mfd_free_vc1_surface;
1376 if (!gen6_vc1_surface) {
1377 gen6_vc1_surface = calloc(sizeof(struct gen6_vc1_surface), 1);
1378 assert((obj_surface->size & 0x3f) == 0);
1379 obj_surface->private_data = gen6_vc1_surface;
1382 gen6_vc1_surface->picture_type = pic_param->picture_fields.bits.picture_type;
1384 if (gen6_vc1_surface->dmv == NULL) {
1385 gen6_vc1_surface->dmv = dri_bo_alloc(i965->intel.bufmgr,
1386 "direct mv w/r buffer",
1387 128 * height_in_mbs * 64, /* scalable with frame height */
1393 gen6_mfd_vc1_decode_init(VADriverContextP ctx,
1394 struct decode_state *decode_state,
1395 struct gen6_mfd_context *gen6_mfd_context)
1397 VAPictureParameterBufferVC1 *pic_param;
1398 struct i965_driver_data *i965 = i965_driver_data(ctx);
1399 struct object_surface *obj_surface;
1405 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1406 pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1407 width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1408 picture_type = pic_param->picture_fields.bits.picture_type;
1410 /* reference picture */
1411 obj_surface = SURFACE(pic_param->forward_reference_picture);
1413 if (obj_surface && obj_surface->bo)
1414 gen6_mfd_context->reference_surface[0].surface_id = pic_param->forward_reference_picture;
1416 gen6_mfd_context->reference_surface[0].surface_id = VA_INVALID_ID;
1418 obj_surface = SURFACE(pic_param->backward_reference_picture);
1420 if (obj_surface && obj_surface->bo)
1421 gen6_mfd_context->reference_surface[1].surface_id = pic_param->backward_reference_picture;
1423 gen6_mfd_context->reference_surface[1].surface_id = pic_param->forward_reference_picture;
1425 /* must do so !!! */
1426 for (i = 2; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++)
1427 gen6_mfd_context->reference_surface[i].surface_id = gen6_mfd_context->reference_surface[i % 2].surface_id;
1429 /* Current decoded picture */
1430 obj_surface = SURFACE(decode_state->current_render_target);
1431 assert(obj_surface);
1432 i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
1433 gen6_mfd_init_vc1_surface(ctx, pic_param, obj_surface);
1435 dri_bo_unreference(gen6_mfd_context->post_deblocking_output.bo);
1436 gen6_mfd_context->post_deblocking_output.bo = obj_surface->bo;
1437 dri_bo_reference(gen6_mfd_context->post_deblocking_output.bo);
1438 gen6_mfd_context->post_deblocking_output.valid = pic_param->entrypoint_fields.bits.loopfilter;
1440 dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo);
1441 gen6_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1442 dri_bo_reference(gen6_mfd_context->pre_deblocking_output.bo);
1443 gen6_mfd_context->pre_deblocking_output.valid = !pic_param->entrypoint_fields.bits.loopfilter;
1445 dri_bo_unreference(gen6_mfd_context->intra_row_store_scratch_buffer.bo);
1446 bo = dri_bo_alloc(i965->intel.bufmgr,
1451 gen6_mfd_context->intra_row_store_scratch_buffer.bo = bo;
1452 gen6_mfd_context->intra_row_store_scratch_buffer.valid = 1;
1454 dri_bo_unreference(gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
1455 bo = dri_bo_alloc(i965->intel.bufmgr,
1456 "deblocking filter row store",
1457 width_in_mbs * 6 * 64,
1460 gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
1461 gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
1463 dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1464 bo = dri_bo_alloc(i965->intel.bufmgr,
1465 "bsd mpc row store",
1469 gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1470 gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1472 gen6_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1474 gen6_mfd_context->bitplane_read_buffer.valid = !!pic_param->bitplane_present.value;
1475 dri_bo_unreference(gen6_mfd_context->bitplane_read_buffer.bo);
1477 if (gen6_mfd_context->bitplane_read_buffer.valid) {
1478 int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1479 int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1480 int bitplane_width = ALIGN(width_in_mbs, 2) / 2;
1482 uint8_t *src = NULL, *dst = NULL;
1484 assert(decode_state->bit_plane->buffer);
1485 src = decode_state->bit_plane->buffer;
1487 bo = dri_bo_alloc(i965->intel.bufmgr,
1489 bitplane_width * height_in_mbs,
1492 gen6_mfd_context->bitplane_read_buffer.bo = bo;
1494 dri_bo_map(bo, True);
1495 assert(bo->virtual);
1498 for (src_h = 0; src_h < height_in_mbs; src_h++) {
1499 for(src_w = 0; src_w < width_in_mbs; src_w++) {
1500 int src_index, dst_index;
1504 src_index = (src_h * width_in_mbs + src_w) / 2;
1505 src_shift = !((src_h * width_in_mbs + src_w) & 1) * 4;
1506 src_value = ((src[src_index] >> src_shift) & 0xf);
1508 if (picture_type == GEN6_VC1_SKIPPED_PICTURE){
1512 dst_index = src_w / 2;
1513 dst[dst_index] = ((dst[dst_index] >> 4) | (src_value << 4));
1517 dst[src_w / 2] >>= 4;
1519 dst += bitplane_width;
1524 gen6_mfd_context->bitplane_read_buffer.bo = NULL;
1528 gen6_mfd_vc1_pic_state(VADriverContextP ctx,
1529 struct decode_state *decode_state,
1530 struct gen6_mfd_context *gen6_mfd_context)
1532 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1533 VAPictureParameterBufferVC1 *pic_param;
1534 struct i965_driver_data *i965 = i965_driver_data(ctx);
1535 struct object_surface *obj_surface;
1536 int alt_pquant_config = 0, alt_pquant_edge_mask = 0, alt_pq;
1537 int dquant, dquantfrm, dqprofile, dqdbedge, dqsbedge, dqbilevel;
1538 int unified_mv_mode;
1539 int ref_field_pic_polarity = 0;
1540 int scale_factor = 0;
1542 int dmv_surface_valid = 0;
1549 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1550 pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1552 profile = va_to_gen6_vc1_profile[pic_param->sequence_fields.bits.profile];
1553 dquant = pic_param->pic_quantizer_fields.bits.dquant;
1554 dquantfrm = pic_param->pic_quantizer_fields.bits.dq_frame;
1555 dqprofile = pic_param->pic_quantizer_fields.bits.dq_profile;
1556 dqdbedge = pic_param->pic_quantizer_fields.bits.dq_db_edge;
1557 dqsbedge = pic_param->pic_quantizer_fields.bits.dq_sb_edge;
1558 dqbilevel = pic_param->pic_quantizer_fields.bits.dq_binary_level;
1559 alt_pq = pic_param->pic_quantizer_fields.bits.alt_pic_quantizer;
1562 alt_pquant_config = 0;
1563 alt_pquant_edge_mask = 0;
1564 } else if (dquant == 2) {
1565 alt_pquant_config = 1;
1566 alt_pquant_edge_mask = 0xf;
1568 assert(dquant == 1);
1569 if (dquantfrm == 0) {
1570 alt_pquant_config = 0;
1571 alt_pquant_edge_mask = 0;
1574 assert(dquantfrm == 1);
1575 alt_pquant_config = 1;
1577 switch (dqprofile) {
1579 if (dqbilevel == 0) {
1580 alt_pquant_config = 2;
1581 alt_pquant_edge_mask = 0;
1583 assert(dqbilevel == 1);
1584 alt_pquant_config = 3;
1585 alt_pquant_edge_mask = 0;
1590 alt_pquant_edge_mask = 0xf;
1595 alt_pquant_edge_mask = 0x9;
1597 alt_pquant_edge_mask = (0x3 << dqdbedge);
1602 alt_pquant_edge_mask = (0x1 << dqsbedge);
1611 if (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation) {
1612 assert(pic_param->mv_fields.bits.mv_mode2 < 4);
1613 unified_mv_mode = va_to_gen6_vc1_mv[pic_param->mv_fields.bits.mv_mode2];
1615 assert(pic_param->mv_fields.bits.mv_mode < 4);
1616 unified_mv_mode = va_to_gen6_vc1_mv[pic_param->mv_fields.bits.mv_mode];
1619 if (pic_param->sequence_fields.bits.interlace == 1 &&
1620 pic_param->picture_fields.bits.frame_coding_mode != 0) { /* frame-interlace or field-interlace */
1621 /* FIXME: calculate reference field picture polarity */
1623 ref_field_pic_polarity = 0;
1626 if (pic_param->b_picture_fraction < 21)
1627 scale_factor = b_picture_scale_factor[pic_param->b_picture_fraction];
1629 picture_type = va_to_gen6_vc1_pic_type[pic_param->picture_fields.bits.picture_type];
1631 if (profile == GEN6_VC1_ADVANCED_PROFILE &&
1632 picture_type == GEN6_VC1_I_PICTURE)
1633 picture_type = GEN6_VC1_BI_PICTURE;
1635 if (picture_type == GEN6_VC1_I_PICTURE || picture_type == GEN6_VC1_BI_PICTURE) /* I picture */
1636 trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx2;
1638 trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx1;
1640 * 8.3.6.2.1 Transform Type Selection
1641 * If variable-sized transform coding is not enabled,
1642 * then the 8x8 transform shall be used for all blocks.
1643 * it is also MFX_VC1_PIC_STATE requirement.
1645 if (pic_param->transform_fields.bits.variable_sized_transform_flag == 0) {
1646 pic_param->transform_fields.bits.mb_level_transform_type_flag = 1;
1647 pic_param->transform_fields.bits.frame_level_transform_type = 0;
1651 if (picture_type == GEN6_VC1_B_PICTURE) {
1652 struct gen6_vc1_surface *gen6_vc1_surface = NULL;
1654 obj_surface = SURFACE(pic_param->backward_reference_picture);
1655 assert(obj_surface);
1656 gen6_vc1_surface = obj_surface->private_data;
1658 if (!gen6_vc1_surface ||
1659 (va_to_gen6_vc1_pic_type[gen6_vc1_surface->picture_type] == GEN6_VC1_I_PICTURE ||
1660 va_to_gen6_vc1_pic_type[gen6_vc1_surface->picture_type] == GEN6_VC1_BI_PICTURE))
1661 dmv_surface_valid = 0;
1663 dmv_surface_valid = 1;
1666 assert(pic_param->picture_fields.bits.frame_coding_mode < 3);
1668 if (pic_param->picture_fields.bits.frame_coding_mode < 2)
1669 fcm = pic_param->picture_fields.bits.frame_coding_mode;
1671 if (pic_param->picture_fields.bits.top_field_first)
1677 if (pic_param->picture_fields.bits.picture_type == GEN6_VC1_B_PICTURE) { /* B picture */
1678 brfd = pic_param->reference_fields.bits.reference_distance;
1679 brfd = (scale_factor * brfd) >> 8;
1680 brfd = pic_param->reference_fields.bits.reference_distance - brfd - 1;
1687 if (profile != GEN6_VC1_ADVANCED_PROFILE){
1688 if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9){
1692 if (pic_param->picture_fields.bits.picture_type == GEN6_VC1_P_PICTURE &&
1693 pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9){
1696 if (pic_param->picture_fields.bits.picture_type == GEN6_VC1_I_PICTURE ||
1697 pic_param->picture_fields.bits.picture_type == GEN6_VC1_BI_PICTURE){
1698 if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9){
1700 }else if(pic_param->conditional_overlap_flag == 2 ||
1701 pic_param->conditional_overlap_flag == 3){
1707 assert(pic_param->conditional_overlap_flag < 3);
1708 assert(pic_param->mv_fields.bits.mv_table < 4); /* FIXME: interlace mode */
1710 BEGIN_BCS_BATCH(batch, 6);
1711 OUT_BCS_BATCH(batch, MFX_VC1_PIC_STATE | (6 - 2));
1712 OUT_BCS_BATCH(batch,
1713 (ALIGN(pic_param->coded_height, 16) / 16) << 16 |
1714 (ALIGN(pic_param->coded_width, 16) / 16));
1715 OUT_BCS_BATCH(batch,
1716 pic_param->sequence_fields.bits.syncmarker << 31 |
1717 1 << 29 | /* concealment */
1719 pic_param->entrypoint_fields.bits.loopfilter << 23 |
1721 (pic_param->pic_quantizer_fields.bits.quantizer == 0) << 21 | /* implicit quantizer */
1722 pic_param->pic_quantizer_fields.bits.pic_quantizer_scale << 16 |
1723 alt_pquant_edge_mask << 12 |
1724 alt_pquant_config << 10 |
1725 pic_param->pic_quantizer_fields.bits.half_qp << 9 |
1726 pic_param->pic_quantizer_fields.bits.pic_quantizer_type << 8 |
1727 va_to_gen6_vc1_condover[pic_param->conditional_overlap_flag] << 6 |
1728 !pic_param->picture_fields.bits.is_first_field << 5 |
1731 OUT_BCS_BATCH(batch,
1732 !!pic_param->bitplane_present.value << 23 |
1733 !pic_param->bitplane_present.flags.bp_forward_mb << 22 |
1734 !pic_param->bitplane_present.flags.bp_mv_type_mb << 21 |
1735 !pic_param->bitplane_present.flags.bp_skip_mb << 20 |
1736 !pic_param->bitplane_present.flags.bp_direct_mb << 19 |
1737 !pic_param->bitplane_present.flags.bp_overflags << 18 |
1738 !pic_param->bitplane_present.flags.bp_ac_pred << 17 |
1739 !pic_param->bitplane_present.flags.bp_field_tx << 16 |
1740 pic_param->mv_fields.bits.extended_dmv_range << 14 |
1741 pic_param->mv_fields.bits.extended_mv_range << 12 |
1742 pic_param->mv_fields.bits.four_mv_switch << 11 |
1743 pic_param->fast_uvmc_flag << 10 |
1744 unified_mv_mode << 8 |
1745 ref_field_pic_polarity << 6 |
1746 pic_param->reference_fields.bits.num_reference_pictures << 5 |
1747 pic_param->reference_fields.bits.reference_distance << 0);
1748 OUT_BCS_BATCH(batch,
1749 scale_factor << 24 |
1750 pic_param->mv_fields.bits.mv_table << 20 |
1751 pic_param->mv_fields.bits.four_mv_block_pattern_table << 18 |
1752 pic_param->mv_fields.bits.two_mv_block_pattern_table << 16 |
1753 pic_param->transform_fields.bits.frame_level_transform_type << 12 |
1754 pic_param->transform_fields.bits.mb_level_transform_type_flag << 11 |
1755 pic_param->mb_mode_table << 8 |
1757 pic_param->transform_fields.bits.transform_ac_codingset_idx1 << 4 |
1758 pic_param->transform_fields.bits.intra_transform_dc_table << 3 |
1759 pic_param->cbp_table << 0);
1760 OUT_BCS_BATCH(batch,
1761 dmv_surface_valid << 13 |
1763 ((ALIGN(pic_param->coded_width, 16) / 16 + 1) / 2 - 1));
1764 ADVANCE_BCS_BATCH(batch);
1768 gen6_mfd_vc1_pred_pipe_state(VADriverContextP ctx,
1769 struct decode_state *decode_state,
1770 struct gen6_mfd_context *gen6_mfd_context)
1772 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1773 VAPictureParameterBufferVC1 *pic_param;
1774 int interpolation_mode = 0;
1775 int intensitycomp_single;
1777 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1778 pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1780 if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPelBilinear ||
1781 (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
1782 pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPelBilinear))
1783 interpolation_mode = 2; /* Half-pel bilinear */
1784 else if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPel ||
1785 (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
1786 pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPel))
1787 interpolation_mode = 0; /* Half-pel bicubic */
1789 interpolation_mode = 1; /* Quarter-pel bicubic */
1791 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1792 pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1793 intensitycomp_single = (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation);
1795 BEGIN_BCS_BATCH(batch, 7);
1796 OUT_BCS_BATCH(batch, MFX_VC1_PRED_PIPE_STATE | (7 - 2));
1797 OUT_BCS_BATCH(batch,
1798 0 << 8 | /* FIXME: interlace mode */
1799 pic_param->rounding_control << 4 |
1800 va_to_gen6_vc1_profile[pic_param->sequence_fields.bits.profile] << 2);
1801 OUT_BCS_BATCH(batch,
1802 pic_param->luma_shift << 16 |
1803 pic_param->luma_scale << 0); /* FIXME: Luma Scaling */
1804 OUT_BCS_BATCH(batch, 0);
1805 OUT_BCS_BATCH(batch, 0);
1806 OUT_BCS_BATCH(batch, 0);
1807 OUT_BCS_BATCH(batch,
1808 interpolation_mode << 19 |
1809 pic_param->fast_uvmc_flag << 18 |
1810 0 << 17 | /* FIXME: scale up or down ??? */
1811 pic_param->range_reduction_frame << 16 |
1812 0 << 6 | /* FIXME: double ??? */
1814 intensitycomp_single << 2 |
1815 intensitycomp_single << 0);
1816 ADVANCE_BCS_BATCH(batch);
1821 gen6_mfd_vc1_directmode_state(VADriverContextP ctx,
1822 struct decode_state *decode_state,
1823 struct gen6_mfd_context *gen6_mfd_context)
1825 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1826 VAPictureParameterBufferVC1 *pic_param;
1827 struct i965_driver_data *i965 = i965_driver_data(ctx);
1828 struct object_surface *obj_surface;
1829 dri_bo *dmv_read_buffer = NULL, *dmv_write_buffer = NULL;
1831 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1832 pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1834 obj_surface = SURFACE(decode_state->current_render_target);
1836 if (obj_surface && obj_surface->private_data) {
1837 dmv_write_buffer = ((struct gen6_vc1_surface *)(obj_surface->private_data))->dmv;
1840 obj_surface = SURFACE(pic_param->backward_reference_picture);
1842 if (obj_surface && obj_surface->private_data) {
1843 dmv_read_buffer = ((struct gen6_vc1_surface *)(obj_surface->private_data))->dmv;
1846 BEGIN_BCS_BATCH(batch, 3);
1847 OUT_BCS_BATCH(batch, MFX_VC1_DIRECTMODE_STATE | (3 - 2));
1849 if (dmv_write_buffer)
1850 OUT_BCS_RELOC(batch, dmv_write_buffer,
1851 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
1854 OUT_BCS_BATCH(batch, 0);
1856 if (dmv_read_buffer)
1857 OUT_BCS_RELOC(batch, dmv_read_buffer,
1858 I915_GEM_DOMAIN_INSTRUCTION, 0,
1861 OUT_BCS_BATCH(batch, 0);
1863 ADVANCE_BCS_BATCH(batch);
1867 gen6_mfd_vc1_get_macroblock_bit_offset(uint8_t *buf, int in_slice_data_bit_offset, int profile)
1869 int out_slice_data_bit_offset;
1870 int slice_header_size = in_slice_data_bit_offset / 8;
1874 out_slice_data_bit_offset = in_slice_data_bit_offset;
1876 for (i = 0, j = 0; i < slice_header_size; i++, j++) {
1877 if (!buf[j] && !buf[j + 1] && buf[j + 2] == 3 && buf[j + 3] < 4) {
1882 out_slice_data_bit_offset = 8 * j + in_slice_data_bit_offset % 8;
1885 return out_slice_data_bit_offset;
1889 gen6_mfd_vc1_bsd_object(VADriverContextP ctx,
1890 VAPictureParameterBufferVC1 *pic_param,
1891 VASliceParameterBufferVC1 *slice_param,
1892 VASliceParameterBufferVC1 *next_slice_param,
1893 dri_bo *slice_data_bo,
1894 struct gen6_mfd_context *gen6_mfd_context)
1896 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1897 int next_slice_start_vert_pos;
1898 int macroblock_offset;
1899 uint8_t *slice_data = NULL;
1901 dri_bo_map(slice_data_bo, 0);
1902 slice_data = (uint8_t *)(slice_data_bo->virtual + slice_param->slice_data_offset);
1903 macroblock_offset = gen6_mfd_vc1_get_macroblock_bit_offset(slice_data,
1904 slice_param->macroblock_offset,
1905 pic_param->sequence_fields.bits.profile);
1906 dri_bo_unmap(slice_data_bo);
1908 if (next_slice_param)
1909 next_slice_start_vert_pos = next_slice_param->slice_vertical_position;
1911 next_slice_start_vert_pos = ALIGN(pic_param->coded_height, 16) / 16;
1913 BEGIN_BCS_BATCH(batch, 4);
1914 OUT_BCS_BATCH(batch, MFD_VC1_BSD_OBJECT | (4 - 2));
1915 OUT_BCS_BATCH(batch,
1916 slice_param->slice_data_size - (macroblock_offset >> 3));
1917 OUT_BCS_BATCH(batch,
1918 slice_param->slice_data_offset + (macroblock_offset >> 3));
1919 OUT_BCS_BATCH(batch,
1920 slice_param->slice_vertical_position << 24 |
1921 next_slice_start_vert_pos << 16 |
1923 (macroblock_offset & 0x7));
1924 ADVANCE_BCS_BATCH(batch);
1928 gen6_mfd_vc1_decode_picture(VADriverContextP ctx,
1929 struct decode_state *decode_state,
1930 struct gen6_mfd_context *gen6_mfd_context)
1932 struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1933 VAPictureParameterBufferVC1 *pic_param;
1934 VASliceParameterBufferVC1 *slice_param, *next_slice_param, *next_slice_group_param;
1935 dri_bo *slice_data_bo;
1938 assert(decode_state->pic_param && decode_state->pic_param->buffer);
1939 pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1941 gen6_mfd_vc1_decode_init(ctx, decode_state, gen6_mfd_context);
1942 intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1943 intel_batchbuffer_emit_mi_flush(batch);
1944 gen6_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context);
1945 gen6_mfd_surface_state(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context);
1946 gen6_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context);
1947 gen6_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context);
1948 gen6_mfd_vc1_pic_state(ctx, decode_state, gen6_mfd_context);
1949 gen6_mfd_vc1_pred_pipe_state(ctx, decode_state, gen6_mfd_context);
1950 gen6_mfd_vc1_directmode_state(ctx, decode_state, gen6_mfd_context);
1952 for (j = 0; j < decode_state->num_slice_params; j++) {
1953 assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1954 slice_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j]->buffer;
1955 slice_data_bo = decode_state->slice_datas[j]->bo;
1956 gen6_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_VC1, gen6_mfd_context);
1958 if (j == decode_state->num_slice_params - 1)
1959 next_slice_group_param = NULL;
1961 next_slice_group_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j + 1]->buffer;
1963 for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1964 assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1966 if (i < decode_state->slice_params[j]->num_elements - 1)
1967 next_slice_param = slice_param + 1;
1969 next_slice_param = next_slice_group_param;
1971 gen6_mfd_vc1_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen6_mfd_context);
1976 intel_batchbuffer_end_atomic(batch);
1977 intel_batchbuffer_flush(batch);
1981 gen6_mfd_decode_picture(VADriverContextP ctx,
1983 union codec_state *codec_state,
1984 struct hw_context *hw_context)
1987 struct gen6_mfd_context *gen6_mfd_context = (struct gen6_mfd_context *)hw_context;
1988 struct decode_state *decode_state = &codec_state->decode;
1990 assert(gen6_mfd_context);
1993 case VAProfileMPEG2Simple:
1994 case VAProfileMPEG2Main:
1995 gen6_mfd_mpeg2_decode_picture(ctx, decode_state, gen6_mfd_context);
1998 case VAProfileH264Baseline:
1999 case VAProfileH264Main:
2000 case VAProfileH264High:
2001 gen6_mfd_avc_decode_picture(ctx, decode_state, gen6_mfd_context);
2004 case VAProfileVC1Simple:
2005 case VAProfileVC1Main:
2006 case VAProfileVC1Advanced:
2007 gen6_mfd_vc1_decode_picture(ctx, decode_state, gen6_mfd_context);
2017 gen6_mfd_context_destroy(void *hw_context)
2019 struct gen6_mfd_context *gen6_mfd_context = (struct gen6_mfd_context *)hw_context;
2021 dri_bo_unreference(gen6_mfd_context->post_deblocking_output.bo);
2022 gen6_mfd_context->post_deblocking_output.bo = NULL;
2024 dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo);
2025 gen6_mfd_context->pre_deblocking_output.bo = NULL;
2027 dri_bo_unreference(gen6_mfd_context->intra_row_store_scratch_buffer.bo);
2028 gen6_mfd_context->intra_row_store_scratch_buffer.bo = NULL;
2030 dri_bo_unreference(gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
2031 gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
2033 dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
2034 gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
2036 dri_bo_unreference(gen6_mfd_context->mpr_row_store_scratch_buffer.bo);
2037 gen6_mfd_context->mpr_row_store_scratch_buffer.bo = NULL;
2039 dri_bo_unreference(gen6_mfd_context->bitplane_read_buffer.bo);
2040 gen6_mfd_context->bitplane_read_buffer.bo = NULL;
2042 intel_batchbuffer_free(gen6_mfd_context->base.batch);
2043 free(gen6_mfd_context);
2047 gen6_dec_hw_context_init(VADriverContextP ctx, struct object_config *obj_config)
2049 struct intel_driver_data *intel = intel_driver_data(ctx);
2050 struct gen6_mfd_context *gen6_mfd_context = calloc(1, sizeof(struct gen6_mfd_context));
2053 gen6_mfd_context->base.destroy = gen6_mfd_context_destroy;
2054 gen6_mfd_context->base.run = gen6_mfd_decode_picture;
2055 gen6_mfd_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0);
2057 for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) {
2058 gen6_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID;
2059 gen6_mfd_context->reference_surface[i].frame_store_id = -1;
2062 gen6_mfd_context->wa_mpeg2_slice_vertical_position = -1;
2064 return (struct hw_context *)gen6_mfd_context;