src/gen6_mfd.c

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *
  27  */
  28
  29 #ifndef HAVE_GEN_AVC_SURFACE
  30 #define HAVE_GEN_AVC_SURFACE 1
  31 #endif
  32
  33 #include "sysdeps.h"
  34 #include "intel_batchbuffer.h"
  35 #include "intel_driver.h"
  36 #include "i965_defines.h"
  37 #include "i965_drv_video.h"
  38 #include "i965_decoder_utils.h"
  39
  40 #include "gen6_mfd.h"
  41
  42 static const uint32_t zigzag_direct[64] = {
  43     0,   1,  8, 16,  9,  2,  3, 10,
  44     17, 24, 32, 25, 18, 11,  4,  5,
  45     12, 19, 26, 33, 40, 48, 41, 34,
  46     27, 20, 13,  6,  7, 14, 21, 28,
  47     35, 42, 49, 56, 57, 50, 43, 36,
  48     29, 22, 15, 23, 30, 37, 44, 51,
  49     58, 59, 52, 45, 38, 31, 39, 46,
  50     53, 60, 61, 54, 47, 55, 62, 63
  51 };
  52
  53 static void
  54 gen6_mfd_avc_frame_store_index(VADriverContextP ctx,
  55                                VAPictureParameterBufferH264 *pic_param,
  56                                struct gen6_mfd_context *gen6_mfd_context)
  57 {
  58     struct i965_driver_data *i965 = i965_driver_data(ctx);
  59     int i, j;
  60
  61     assert(ARRAY_ELEMS(gen6_mfd_context->reference_surface) == ARRAY_ELEMS(pic_param->ReferenceFrames));
  62
  63     for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) {
  64         int found = 0;
  65
  66         if (gen6_mfd_context->reference_surface[i].surface_id == VA_INVALID_ID)
  67             continue;
  68
  69         for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) {
  70             VAPictureH264 *ref_pic = &pic_param->ReferenceFrames[j];
  71             if (ref_pic->flags & VA_PICTURE_H264_INVALID)
  72                 continue;
  73
  74             if (gen6_mfd_context->reference_surface[i].surface_id == ref_pic->picture_id) {
  75                 found = 1;
  76                 break;
  77             }
  78         }
  79
  80         if (!found) {
  81             struct object_surface *obj_surface = SURFACE(gen6_mfd_context->reference_surface[i].surface_id);
  82             obj_surface->flags &= ~SURFACE_REFERENCED;
  83
  84             if ((obj_surface->flags & SURFACE_ALL_MASK) == SURFACE_DISPLAYED) {
  85                 dri_bo_unreference(obj_surface->bo);
  86                 obj_surface->bo = NULL;
  87                 obj_surface->flags &= ~SURFACE_REF_DIS_MASK;
  88             }
  89
  90             if (obj_surface->free_private_data)
  91                 obj_surface->free_private_data(&obj_surface->private_data);
  92
  93             gen6_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID;
  94             gen6_mfd_context->reference_surface[i].frame_store_id = -1;
  95         }
  96     }
  97
  98     for (i = 0; i < ARRAY_ELEMS(pic_param->ReferenceFrames); i++) {
  99         VAPictureH264 *ref_pic = &pic_param->ReferenceFrames[i];
 100         int found = 0;
 101
 102         if (ref_pic->flags & VA_PICTURE_H264_INVALID)
 103             continue;
 104
 105         for (j = 0; j < ARRAY_ELEMS(gen6_mfd_context->reference_surface); j++) {
 106             if (gen6_mfd_context->reference_surface[j].surface_id == VA_INVALID_ID)
 107                 continue;
 108
 109             if (gen6_mfd_context->reference_surface[j].surface_id == ref_pic->picture_id) {
 110                 found = 1;
 111                 break;
 112             }
 113         }
 114
 115         if (!found) {
 116             int frame_idx;
 117             struct object_surface *obj_surface = SURFACE(ref_pic->picture_id);
 118
 119             assert(obj_surface);
 120             i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N', 'V', '1', '2'), SUBSAMPLE_YUV420);
 121
 122             for (frame_idx = 0; frame_idx < ARRAY_ELEMS(gen6_mfd_context->reference_surface); frame_idx++) {
 123                 for (j = 0; j < ARRAY_ELEMS(gen6_mfd_context->reference_surface); j++) {
 124                     if (gen6_mfd_context->reference_surface[j].surface_id == VA_INVALID_ID)
 125                         continue;
 126
 127                     if (gen6_mfd_context->reference_surface[j].frame_store_id == frame_idx)
 128                         break;
 129                 }
 130
 131                 if (j == ARRAY_ELEMS(gen6_mfd_context->reference_surface))
 132                     break;
 133             }
 134
 135             assert(frame_idx < ARRAY_ELEMS(gen6_mfd_context->reference_surface));
 136
 137             for (j = 0; j < ARRAY_ELEMS(gen6_mfd_context->reference_surface); j++) {
 138                 if (gen6_mfd_context->reference_surface[j].surface_id == VA_INVALID_ID) {
 139                     gen6_mfd_context->reference_surface[j].surface_id = ref_pic->picture_id;
 140                     gen6_mfd_context->reference_surface[j].frame_store_id = frame_idx;
 141                     break;
 142                 }
 143             }
 144         }
 145     }
 146
 147     /* sort */
 148     for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface) - 1; i++) {
 149         if (gen6_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
 150             gen6_mfd_context->reference_surface[i].frame_store_id == i)
 151             continue;
 152
 153         for (j = i + 1; j < ARRAY_ELEMS(gen6_mfd_context->reference_surface); j++) {
 154             if (gen6_mfd_context->reference_surface[j].surface_id != VA_INVALID_ID &&
 155                 gen6_mfd_context->reference_surface[j].frame_store_id == i) {
 156                 VASurfaceID id = gen6_mfd_context->reference_surface[i].surface_id;
 157                 int frame_idx = gen6_mfd_context->reference_surface[i].frame_store_id;
 158
 159                 gen6_mfd_context->reference_surface[i].surface_id = gen6_mfd_context->reference_surface[j].surface_id;
 160                 gen6_mfd_context->reference_surface[i].frame_store_id = gen6_mfd_context->reference_surface[j].frame_store_id;
 161                 gen6_mfd_context->reference_surface[j].surface_id = id;
 162                 gen6_mfd_context->reference_surface[j].frame_store_id = frame_idx;
 163                 break;
 164             }
 165         }
 166     }
 167 }
 168
 169 static void
 170 gen6_mfd_init_avc_surface(VADriverContextP ctx,
 171                           VAPictureParameterBufferH264 *pic_param,
 172                           struct object_surface *obj_surface)
 173 {
 174     struct i965_driver_data *i965 = i965_driver_data(ctx);
 175     GenAvcSurface *gen6_avc_surface = obj_surface->private_data;
 176     int height_in_mbs;
 177
 178     obj_surface->free_private_data = gen_free_avc_surface;
 179     height_in_mbs = ((pic_param->picture_height_in_mbs_minus1 + 1) & 0xff); /* frame height */
 180
 181     if (!gen6_avc_surface) {
 182         gen6_avc_surface = calloc(sizeof(GenAvcSurface), 1);
 183         assert((obj_surface->size & 0x3f) == 0);
 184         obj_surface->private_data = gen6_avc_surface;
 185     }
 186
 187     gen6_avc_surface->dmv_bottom_flag = (pic_param->pic_fields.bits.field_pic_flag &&
 188                                          !pic_param->seq_fields.bits.direct_8x8_inference_flag);
 189
 190     if (gen6_avc_surface->dmv_top == NULL) {
 191         gen6_avc_surface->dmv_top = dri_bo_alloc(i965->intel.bufmgr,
 192                                                  "direct mv w/r buffer",
 193                                                  128 * height_in_mbs * 64,      /* scalable with frame height */
 194                                                  0x1000);
 195     }
 196
 197     if (gen6_avc_surface->dmv_bottom_flag &&
 198         gen6_avc_surface->dmv_bottom == NULL) {
 199         gen6_avc_surface->dmv_bottom = dri_bo_alloc(i965->intel.bufmgr,
 200                                                     "direct mv w/r buffer",
 201                                                     128 * height_in_mbs * 64,   /* scalable with frame height */
 202                                                     0x1000);
 203     }
 204 }
 205
 206 static void
 207 gen6_mfd_pipe_mode_select(VADriverContextP ctx,
 208                           struct decode_state *decode_state,
 209                           int standard_select,
 210                           struct gen6_mfd_context *gen6_mfd_context)
 211 {
 212     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 213
 214     assert(standard_select == MFX_FORMAT_MPEG2 ||
 215            standard_select == MFX_FORMAT_AVC ||
 216            standard_select == MFX_FORMAT_VC1);
 217
 218     BEGIN_BCS_BATCH(batch, 4);
 219     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (4 - 2));
 220     OUT_BCS_BATCH(batch,
 221                   (MFD_MODE_VLD << 16) | /* VLD mode */
 222                   (0 << 10) | /* disable Stream-Out */
 223                   (gen6_mfd_context->post_deblocking_output.valid << 9)  | /* Post Deblocking Output */
 224                   (gen6_mfd_context->pre_deblocking_output.valid << 8)  | /* Pre Deblocking Output */
 225                   (0 << 7)  | /* disable TLB prefectch */
 226                   (0 << 5)  | /* not in stitch mode */
 227                   (MFX_CODEC_DECODE << 4)  | /* decoding mode */
 228                   (standard_select << 0));
 229     OUT_BCS_BATCH(batch,
 230                   (0 << 20) | /* round flag in PB slice */
 231                   (0 << 19) | /* round flag in Intra8x8 */
 232                   (0 << 7)  | /* expand NOA bus flag */
 233                   (1 << 6)  | /* must be 1 */
 234                   (0 << 5)  | /* disable clock gating for NOA */
 235                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
 236                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
 237                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
 238                   (0 << 1)  | /* AVC long field motion vector */
 239                   (1 << 0));  /* always calculate AVC ILDB boundary strength */
 240     OUT_BCS_BATCH(batch, 0);
 241     ADVANCE_BCS_BATCH(batch);
 242 }
 243
 244 static void
 245 gen6_mfd_surface_state(VADriverContextP ctx,
 246                        struct decode_state *decode_state,
 247                        int standard_select,
 248                        struct gen6_mfd_context *gen6_mfd_context)
 249 {
 250     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 251     struct i965_driver_data *i965 = i965_driver_data(ctx);
 252     struct object_surface *obj_surface = SURFACE(decode_state->current_render_target);
 253     assert(obj_surface);
 254
 255     BEGIN_BCS_BATCH(batch, 6);
 256     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
 257     OUT_BCS_BATCH(batch, 0);
 258     OUT_BCS_BATCH(batch,
 259                   ((obj_surface->orig_height - 1) << 19) |
 260                   ((obj_surface->orig_width - 1) << 6));
 261     OUT_BCS_BATCH(batch,
 262                   (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
 263                   (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
 264                   (0 << 22) | /* surface object control state, FIXME??? */
 265                   ((obj_surface->width - 1) << 3) | /* pitch */
 266                   (0 << 2)  | /* must be 0 for interleave U/V */
 267                   (1 << 1)  | /* must be y-tiled */
 268                   (I965_TILEWALK_YMAJOR << 0));  /* tile walk, FIXME: must be 1 ??? */
 269     OUT_BCS_BATCH(batch,
 270                   (0 << 16) | /* must be 0 for interleave U/V */
 271                   (obj_surface->height)); /* y offset for U(cb) */
 272     OUT_BCS_BATCH(batch, 0);
 273     ADVANCE_BCS_BATCH(batch);
 274 }
 275
 276 static void
 277 gen6_mfd_pipe_buf_addr_state(VADriverContextP ctx,
 278                              struct decode_state *decode_state,
 279                              int standard_select,
 280                              struct gen6_mfd_context *gen6_mfd_context)
 281 {
 282     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 283     struct i965_driver_data *i965 = i965_driver_data(ctx);
 284     int i;
 285
 286     BEGIN_BCS_BATCH(batch, 24);
 287     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
 288     if (gen6_mfd_context->pre_deblocking_output.valid)
 289         OUT_BCS_RELOC(batch, gen6_mfd_context->pre_deblocking_output.bo,
 290                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 291                       0);
 292     else
 293         OUT_BCS_BATCH(batch, 0);
 294
 295     if (gen6_mfd_context->post_deblocking_output.valid)
 296         OUT_BCS_RELOC(batch, gen6_mfd_context->post_deblocking_output.bo,
 297                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 298                       0);
 299     else
 300         OUT_BCS_BATCH(batch, 0);
 301
 302     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 303     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 304
 305     if (gen6_mfd_context->intra_row_store_scratch_buffer.valid)
 306         OUT_BCS_RELOC(batch, gen6_mfd_context->intra_row_store_scratch_buffer.bo,
 307                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 308                       0);
 309     else
 310         OUT_BCS_BATCH(batch, 0);
 311
 312     if (gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid)
 313         OUT_BCS_RELOC(batch, gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo,
 314                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 315                       0);
 316     else
 317         OUT_BCS_BATCH(batch, 0);
 318
 319     /* DW 7..22 */
 320     for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) {
 321         struct object_surface *obj_surface;
 322
 323         if (gen6_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
 324             obj_surface = SURFACE(gen6_mfd_context->reference_surface[i].surface_id);
 325             assert(obj_surface && obj_surface->bo);
 326
 327             OUT_BCS_RELOC(batch, obj_surface->bo,
 328                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 329                           0);
 330         } else {
 331             OUT_BCS_BATCH(batch, 0);
 332         }
 333     }
 334
 335     OUT_BCS_BATCH(batch, 0);   /* ignore DW23 for decoding */
 336     ADVANCE_BCS_BATCH(batch);
 337 }
 338
 339 static void
 340 gen6_mfd_ind_obj_base_addr_state(VADriverContextP ctx,
 341                                  dri_bo *slice_data_bo,
 342                                  int standard_select,
 343                                  struct gen6_mfd_context *gen6_mfd_context)
 344 {
 345     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 346
 347     BEGIN_BCS_BATCH(batch, 11);
 348     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
 349     OUT_BCS_RELOC(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */
 350     OUT_BCS_BATCH(batch, 0);
 351     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 352     OUT_BCS_BATCH(batch, 0);
 353     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 354     OUT_BCS_BATCH(batch, 0);
 355     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 356     OUT_BCS_BATCH(batch, 0);
 357     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 358     OUT_BCS_BATCH(batch, 0);
 359     ADVANCE_BCS_BATCH(batch);
 360 }
 361
 362 static void
 363 gen6_mfd_bsp_buf_base_addr_state(VADriverContextP ctx,
 364                                  struct decode_state *decode_state,
 365                                  int standard_select,
 366                                  struct gen6_mfd_context *gen6_mfd_context)
 367 {
 368     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 369
 370     BEGIN_BCS_BATCH(batch, 4);
 371     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
 372
 373     if (gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid)
 374         OUT_BCS_RELOC(batch, gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo,
 375                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 376                       0);
 377     else
 378         OUT_BCS_BATCH(batch, 0);
 379
 380     if (gen6_mfd_context->mpr_row_store_scratch_buffer.valid)
 381         OUT_BCS_RELOC(batch, gen6_mfd_context->mpr_row_store_scratch_buffer.bo,
 382                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 383                       0);
 384     else
 385         OUT_BCS_BATCH(batch, 0);
 386
 387     if (gen6_mfd_context->bitplane_read_buffer.valid)
 388         OUT_BCS_RELOC(batch, gen6_mfd_context->bitplane_read_buffer.bo,
 389                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 390                       0);
 391     else
 392         OUT_BCS_BATCH(batch, 0);
 393
 394     ADVANCE_BCS_BATCH(batch);
 395 }
 396
 397 static void
 398 gen6_mfd_avc_img_state(VADriverContextP ctx,
 399                        struct decode_state *decode_state,
 400                        struct gen6_mfd_context *gen6_mfd_context)
 401 {
 402     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 403     int qm_present_flag;
 404     int img_struct;
 405     int mbaff_frame_flag;
 406     unsigned int width_in_mbs, height_in_mbs;
 407     VAPictureParameterBufferH264 *pic_param;
 408
 409     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 410     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 411     assert(!(pic_param->CurrPic.flags & VA_PICTURE_H264_INVALID));
 412
 413     if (decode_state->iq_matrix && decode_state->iq_matrix->buffer)
 414         qm_present_flag = 1;
 415     else
 416         qm_present_flag = 0; /* built-in QM matrices */
 417
 418     if (pic_param->CurrPic.flags & VA_PICTURE_H264_TOP_FIELD)
 419         img_struct = 1;
 420     else if (pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD)
 421         img_struct = 3;
 422     else
 423         img_struct = 0;
 424
 425     if ((img_struct & 0x1) == 0x1) {
 426         assert(pic_param->pic_fields.bits.field_pic_flag == 0x1);
 427     } else {
 428         assert(pic_param->pic_fields.bits.field_pic_flag == 0x0);
 429     }
 430
 431     if (pic_param->seq_fields.bits.frame_mbs_only_flag) { /* a frame containing only frame macroblocks */
 432         assert(pic_param->seq_fields.bits.mb_adaptive_frame_field_flag == 0);
 433         assert(pic_param->pic_fields.bits.field_pic_flag == 0);
 434     } else {
 435         assert(pic_param->seq_fields.bits.direct_8x8_inference_flag == 1); /* see H.264 spec */
 436     }
 437
 438     mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag &&
 439                         !pic_param->pic_fields.bits.field_pic_flag);
 440
 441     width_in_mbs = ((pic_param->picture_width_in_mbs_minus1 + 1) & 0xff);
 442     height_in_mbs = ((pic_param->picture_height_in_mbs_minus1 + 1) & 0xff); /* frame height */
 443     assert(!((width_in_mbs * height_in_mbs) & 0x8000)); /* hardware requirement */
 444
 445     /* MFX unit doesn't support 4:2:2 and 4:4:4 picture */
 446     assert(pic_param->seq_fields.bits.chroma_format_idc == 0 || /* monochrome picture */
 447            pic_param->seq_fields.bits.chroma_format_idc == 1);  /* 4:2:0 */
 448     assert(pic_param->seq_fields.bits.residual_colour_transform_flag == 0); /* only available for 4:4:4 */
 449
 450     BEGIN_BCS_BATCH(batch, 13);
 451     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (13 - 2));
 452     OUT_BCS_BATCH(batch,
 453                   ((width_in_mbs * height_in_mbs) & 0x7fff));
 454     OUT_BCS_BATCH(batch,
 455                   (height_in_mbs << 16) |
 456                   (width_in_mbs << 0));
 457     OUT_BCS_BATCH(batch,
 458                   ((pic_param->second_chroma_qp_index_offset & 0x1f) << 24) |
 459                   ((pic_param->chroma_qp_index_offset & 0x1f) << 16) |
 460                   (0 << 14) | /* Max-bit conformance Intra flag ??? FIXME */
 461                   (0 << 13) | /* Max Macroblock size conformance Inter flag ??? FIXME */
 462                   (1 << 12) | /* always 1, hardware requirement */
 463                   (qm_present_flag << 10) |
 464                   (img_struct << 8) |
 465                   (16 << 0));
 466     OUT_BCS_BATCH(batch,
 467                   (pic_param->seq_fields.bits.chroma_format_idc << 10) |
 468                   (pic_param->pic_fields.bits.entropy_coding_mode_flag << 7) |
 469                   ((!pic_param->pic_fields.bits.reference_pic_flag) << 6) |
 470                   (pic_param->pic_fields.bits.constrained_intra_pred_flag << 5) |
 471                   (pic_param->seq_fields.bits.direct_8x8_inference_flag << 4) |
 472                   (pic_param->pic_fields.bits.transform_8x8_mode_flag << 3) |
 473                   (pic_param->seq_fields.bits.frame_mbs_only_flag << 2) |
 474                   (mbaff_frame_flag << 1) |
 475                   (pic_param->pic_fields.bits.field_pic_flag << 0));
 476     OUT_BCS_BATCH(batch, 0);
 477     OUT_BCS_BATCH(batch, 0);
 478     OUT_BCS_BATCH(batch, 0);
 479     OUT_BCS_BATCH(batch, 0);
 480     OUT_BCS_BATCH(batch, 0);
 481     OUT_BCS_BATCH(batch, 0);
 482     OUT_BCS_BATCH(batch, 0);
 483     OUT_BCS_BATCH(batch, 0);
 484     ADVANCE_BCS_BATCH(batch);
 485 }
 486
 487 static void
 488 gen6_mfd_avc_qm_state(VADriverContextP ctx,
 489                       struct decode_state *decode_state,
 490                       struct gen6_mfd_context *gen6_mfd_context)
 491 {
 492     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 493     int cmd_len;
 494     VAIQMatrixBufferH264 *iq_matrix;
 495     VAPictureParameterBufferH264 *pic_param;
 496
 497     if (!decode_state->iq_matrix || !decode_state->iq_matrix->buffer)
 498         return;
 499
 500     iq_matrix = (VAIQMatrixBufferH264 *)decode_state->iq_matrix->buffer;
 501
 502     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 503     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 504
 505     cmd_len = 2 + 6 * 4; /* always load six 4x4 scaling matrices */
 506
 507     if (pic_param->pic_fields.bits.transform_8x8_mode_flag)
 508         cmd_len += 2 * 16; /* load two 8x8 scaling matrices */
 509
 510     BEGIN_BCS_BATCH(batch, cmd_len);
 511     OUT_BCS_BATCH(batch, MFX_AVC_QM_STATE | (cmd_len - 2));
 512
 513     if (pic_param->pic_fields.bits.transform_8x8_mode_flag)
 514         OUT_BCS_BATCH(batch,
 515                       (0x0  << 8) | /* don't use default built-in matrices */
 516                       (0xff << 0)); /* six 4x4 and two 8x8 scaling matrices */
 517     else
 518         OUT_BCS_BATCH(batch,
 519                       (0x0  << 8) | /* don't use default built-in matrices */
 520                       (0x3f << 0)); /* six 4x4 scaling matrices */
 521
 522     intel_batchbuffer_data(batch, &iq_matrix->ScalingList4x4[0][0], 6 * 4 * 4);
 523
 524     if (pic_param->pic_fields.bits.transform_8x8_mode_flag)
 525         intel_batchbuffer_data(batch, &iq_matrix->ScalingList8x8[0][0], 2 * 16 * 4);
 526
 527     ADVANCE_BCS_BATCH(batch);
 528 }
 529
 530 static void
 531 gen6_mfd_avc_directmode_state(VADriverContextP ctx,
 532                               VAPictureParameterBufferH264 *pic_param,
 533                               VASliceParameterBufferH264 *slice_param,
 534                               struct gen6_mfd_context *gen6_mfd_context)
 535 {
 536     struct i965_driver_data *i965 = i965_driver_data(ctx);
 537     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 538     struct object_surface *obj_surface;
 539     GenAvcSurface *gen6_avc_surface;
 540     VAPictureH264 *va_pic;
 541     int i, j;
 542
 543     BEGIN_BCS_BATCH(batch, 69);
 544     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
 545
 546     /* reference surfaces 0..15 */
 547     for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) {
 548         if (gen6_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
 549             obj_surface = SURFACE(gen6_mfd_context->reference_surface[i].surface_id);
 550             assert(obj_surface);
 551             gen6_avc_surface = obj_surface->private_data;
 552
 553             if (gen6_avc_surface == NULL) {
 554                 OUT_BCS_BATCH(batch, 0);
 555                 OUT_BCS_BATCH(batch, 0);
 556             } else {
 557                 OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top,
 558                               I915_GEM_DOMAIN_INSTRUCTION, 0,
 559                               0);
 560
 561                 if (gen6_avc_surface->dmv_bottom_flag == 1)
 562                     OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_bottom,
 563                                   I915_GEM_DOMAIN_INSTRUCTION, 0,
 564                                   0);
 565                 else
 566                     OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top,
 567                                   I915_GEM_DOMAIN_INSTRUCTION, 0,
 568                                   0);
 569             }
 570         } else {
 571             OUT_BCS_BATCH(batch, 0);
 572             OUT_BCS_BATCH(batch, 0);
 573         }
 574     }
 575
 576     /* the current decoding frame/field */
 577     va_pic = &pic_param->CurrPic;
 578     assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
 579     obj_surface = SURFACE(va_pic->picture_id);
 580     assert(obj_surface && obj_surface->bo && obj_surface->private_data);
 581     gen6_avc_surface = obj_surface->private_data;
 582
 583     OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top,
 584                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 585                   0);
 586
 587     if (gen6_avc_surface->dmv_bottom_flag == 1)
 588         OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_bottom,
 589                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 590                       0);
 591     else
 592         OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top,
 593                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 594                       0);
 595
 596     /* POC List */
 597     for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) {
 598         if (gen6_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
 599             int found = 0;
 600             for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) {
 601                 va_pic = &pic_param->ReferenceFrames[j];
 602
 603                 if (va_pic->flags & VA_PICTURE_H264_INVALID)
 604                     continue;
 605
 606                 if (va_pic->picture_id == gen6_mfd_context->reference_surface[i].surface_id) {
 607                     found = 1;
 608                     break;
 609                 }
 610             }
 611
 612             assert(found == 1);
 613             assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
 614
 615             OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
 616             OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
 617         } else {
 618             OUT_BCS_BATCH(batch, 0);
 619             OUT_BCS_BATCH(batch, 0);
 620         }
 621     }
 622
 623     va_pic = &pic_param->CurrPic;
 624     OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
 625     OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
 626
 627     ADVANCE_BCS_BATCH(batch);
 628 }
 629
 630 static void
 631 gen6_mfd_avc_slice_state(VADriverContextP ctx,
 632                          VAPictureParameterBufferH264 *pic_param,
 633                          VASliceParameterBufferH264 *slice_param,
 634                          VASliceParameterBufferH264 *next_slice_param,
 635                          struct gen6_mfd_context *gen6_mfd_context)
 636 {
 637     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 638     int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 639     int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1;
 640     int slice_hor_pos, slice_ver_pos, next_slice_hor_pos, next_slice_ver_pos;
 641     int num_ref_idx_l0, num_ref_idx_l1;
 642     int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag &&
 643                          pic_param->seq_fields.bits.mb_adaptive_frame_field_flag);
 644     int weighted_pred_idc = 0;
 645     int first_mb_in_slice = 0, first_mb_in_next_slice = 0;
 646     unsigned int chroma_log2_weight_denom, luma_log2_weight_denom;
 647     int slice_type;
 648
 649     if (slice_param->slice_type == SLICE_TYPE_I ||
 650         slice_param->slice_type == SLICE_TYPE_SI) {
 651         slice_type = SLICE_TYPE_I;
 652     } else if (slice_param->slice_type == SLICE_TYPE_P ||
 653                slice_param->slice_type == SLICE_TYPE_SP) {
 654         slice_type = SLICE_TYPE_P;
 655     } else {
 656         assert(slice_param->slice_type == SLICE_TYPE_B);
 657         slice_type = SLICE_TYPE_B;
 658     }
 659
 660     luma_log2_weight_denom   = slice_param->luma_log2_weight_denom;
 661     chroma_log2_weight_denom = slice_param->chroma_log2_weight_denom;
 662
 663     if (slice_type == SLICE_TYPE_I) {
 664         assert(slice_param->num_ref_idx_l0_active_minus1 == 0);
 665         assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
 666         num_ref_idx_l0 = 0;
 667         num_ref_idx_l1 = 0;
 668     } else if (slice_type == SLICE_TYPE_P) {
 669         assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
 670         num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
 671         num_ref_idx_l1 = 0;
 672         weighted_pred_idc = (pic_param->pic_fields.bits.weighted_pred_flag == 1);
 673     } else {
 674         num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
 675         num_ref_idx_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
 676         weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc;
 677
 678         if (weighted_pred_idc == 2) {
 679             /* 8.4.3 - Derivation process for prediction weights (8-279) */
 680             luma_log2_weight_denom   = 5;
 681             chroma_log2_weight_denom = 5;
 682         }
 683     }
 684
 685     first_mb_in_slice = slice_param->first_mb_in_slice << mbaff_picture;
 686     slice_hor_pos = first_mb_in_slice % width_in_mbs;
 687     slice_ver_pos = first_mb_in_slice / width_in_mbs;
 688
 689     if (next_slice_param) {
 690         first_mb_in_next_slice = next_slice_param->first_mb_in_slice << mbaff_picture;
 691         next_slice_hor_pos = first_mb_in_next_slice % width_in_mbs;
 692         next_slice_ver_pos = first_mb_in_next_slice / width_in_mbs;
 693     } else {
 694         next_slice_hor_pos = 0;
 695         next_slice_ver_pos = height_in_mbs;
 696     }
 697
 698     BEGIN_BCS_BATCH(batch, 11); /* FIXME: is it 10??? */
 699     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
 700     OUT_BCS_BATCH(batch, slice_type);
 701     OUT_BCS_BATCH(batch,
 702                   (num_ref_idx_l1 << 24) |
 703                   (num_ref_idx_l0 << 16) |
 704                   (chroma_log2_weight_denom << 8) |
 705                   (luma_log2_weight_denom << 0));
 706     OUT_BCS_BATCH(batch,
 707                   (weighted_pred_idc << 30) |
 708                   (slice_param->direct_spatial_mv_pred_flag << 29) |
 709                   (slice_param->disable_deblocking_filter_idc << 27) |
 710                   (slice_param->cabac_init_idc << 24) |
 711                   ((pic_param->pic_init_qp_minus26 + 26 + slice_param->slice_qp_delta) << 16) |
 712                   ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
 713                   ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
 714     OUT_BCS_BATCH(batch,
 715                   (slice_ver_pos << 24) |
 716                   (slice_hor_pos << 16) |
 717                   (first_mb_in_slice << 0));
 718     OUT_BCS_BATCH(batch,
 719                   (next_slice_ver_pos << 16) |
 720                   (next_slice_hor_pos << 0));
 721     OUT_BCS_BATCH(batch,
 722                   (next_slice_param == NULL) << 19); /* last slice flag */
 723     OUT_BCS_BATCH(batch, 0);
 724     OUT_BCS_BATCH(batch, 0);
 725     OUT_BCS_BATCH(batch, 0);
 726     OUT_BCS_BATCH(batch, 0);
 727     ADVANCE_BCS_BATCH(batch);
 728 }
 729
 730 static void
 731 gen6_mfd_avc_phantom_slice_state(VADriverContextP ctx,
 732                                  VAPictureParameterBufferH264 *pic_param,
 733                                  struct gen6_mfd_context *gen6_mfd_context)
 734 {
 735     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 736     int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 737     int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */
 738
 739     BEGIN_BCS_BATCH(batch, 11); /* FIXME: is it 10??? */
 740     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
 741     OUT_BCS_BATCH(batch, 0);
 742     OUT_BCS_BATCH(batch, 0);
 743     OUT_BCS_BATCH(batch, 0);
 744     OUT_BCS_BATCH(batch,
 745                   height_in_mbs << 24 |
 746                   width_in_mbs * height_in_mbs / (1 + !!pic_param->pic_fields.bits.field_pic_flag));
 747     OUT_BCS_BATCH(batch, 0);
 748     OUT_BCS_BATCH(batch, 0);
 749     OUT_BCS_BATCH(batch, 0);
 750     OUT_BCS_BATCH(batch, 0);
 751     OUT_BCS_BATCH(batch, 0);
 752     OUT_BCS_BATCH(batch, 0);
 753     ADVANCE_BCS_BATCH(batch);
 754 }
 755
 756 static inline void
 757 gen6_mfd_avc_ref_idx_state(VADriverContextP ctx,
 758                            VAPictureParameterBufferH264 *pic_param,
 759                            VASliceParameterBufferH264 *slice_param,
 760                            struct gen6_mfd_context *gen6_mfd_context)
 761 {
 762     gen6_send_avc_ref_idx_state(
 763         gen6_mfd_context->base.batch,
 764         slice_param,
 765         gen6_mfd_context->reference_surface
 766     );
 767 }
 768
 769 static void
 770 gen6_mfd_avc_weightoffset_state(VADriverContextP ctx,
 771                                 VAPictureParameterBufferH264 *pic_param,
 772                                 VASliceParameterBufferH264 *slice_param,
 773                                 struct gen6_mfd_context *gen6_mfd_context)
 774 {
 775     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 776     int i, j, num_weight_offset_table = 0;
 777     short weightoffsets[32 * 6];
 778
 779     if ((slice_param->slice_type == SLICE_TYPE_P ||
 780          slice_param->slice_type == SLICE_TYPE_SP) &&
 781         (pic_param->pic_fields.bits.weighted_pred_flag == 1)) {
 782         num_weight_offset_table = 1;
 783     }
 784
 785     if ((slice_param->slice_type == SLICE_TYPE_B) &&
 786         (pic_param->pic_fields.bits.weighted_bipred_idc == 1)) {
 787         num_weight_offset_table = 2;
 788     }
 789
 790     for (i = 0; i < num_weight_offset_table; i++) {
 791         BEGIN_BCS_BATCH(batch, 98);
 792         OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2));
 793         OUT_BCS_BATCH(batch, i);
 794
 795         if (i == 0) {
 796             for (j = 0; j < 32; j++) {
 797                 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l0[j];
 798                 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l0[j];
 799                 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l0[j][0];
 800                 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l0[j][0];
 801                 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l0[j][1];
 802                 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l0[j][1];
 803             }
 804         } else {
 805             for (j = 0; j < 32; j++) {
 806                 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l1[j];
 807                 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l1[j];
 808                 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l1[j][0];
 809                 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l1[j][0];
 810                 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l1[j][1];
 811                 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l1[j][1];
 812             }
 813         }
 814
 815         intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
 816         ADVANCE_BCS_BATCH(batch);
 817     }
 818 }
 819
 820 static void
 821 gen6_mfd_avc_bsd_object(VADriverContextP ctx,
 822                         VAPictureParameterBufferH264 *pic_param,
 823                         VASliceParameterBufferH264 *slice_param,
 824                         dri_bo *slice_data_bo,
 825                         struct gen6_mfd_context *gen6_mfd_context)
 826 {
 827     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 828     unsigned int slice_data_bit_offset;
 829
 830     slice_data_bit_offset = avc_get_first_mb_bit_offset(
 831         slice_data_bo,
 832         slice_param,
 833         pic_param->pic_fields.bits.entropy_coding_mode_flag
 834     );
 835
 836     BEGIN_BCS_BATCH(batch, 6);
 837     OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
 838     OUT_BCS_BATCH(batch,
 839                   (slice_param->slice_data_size - slice_param->slice_data_offset));
 840     OUT_BCS_BATCH(batch, slice_param->slice_data_offset);
 841     OUT_BCS_BATCH(batch,
 842                   (0 << 31) |
 843                   (0 << 14) |
 844                   (0 << 12) |
 845                   (0 << 10) |
 846                   (0 << 8));
 847     OUT_BCS_BATCH(batch,
 848                   ((slice_data_bit_offset >> 3) << 16) |
 849                   (1 << 6)  |
 850                   ((0x7 - (slice_data_bit_offset & 0x7)) << 0));
 851     OUT_BCS_BATCH(batch, 0);
 852     ADVANCE_BCS_BATCH(batch);
 853 }
 854
 855 static void
 856 gen6_mfd_avc_phantom_slice_bsd_object(VADriverContextP ctx,
 857                                       VAPictureParameterBufferH264 *pic_param,
 858                                       struct gen6_mfd_context *gen6_mfd_context)
 859 {
 860     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 861
 862     BEGIN_BCS_BATCH(batch, 6);
 863     OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
 864     OUT_BCS_BATCH(batch, 0);
 865     OUT_BCS_BATCH(batch, 0);
 866     OUT_BCS_BATCH(batch, 0);
 867     OUT_BCS_BATCH(batch, 0);
 868     OUT_BCS_BATCH(batch, 0);
 869     ADVANCE_BCS_BATCH(batch);
 870 }
 871
 872 static void
 873 gen6_mfd_avc_phantom_slice(VADriverContextP ctx,
 874                            VAPictureParameterBufferH264 *pic_param,
 875                            struct gen6_mfd_context *gen6_mfd_context)
 876 {
 877     gen6_mfd_avc_phantom_slice_state(ctx, pic_param, gen6_mfd_context);
 878     gen6_mfd_avc_phantom_slice_bsd_object(ctx, pic_param, gen6_mfd_context);
 879 }
 880
 881 static void
 882 gen6_mfd_avc_decode_init(VADriverContextP ctx,
 883                          struct decode_state *decode_state,
 884                          struct gen6_mfd_context *gen6_mfd_context)
 885 {
 886     VAPictureParameterBufferH264 *pic_param;
 887     VASliceParameterBufferH264 *slice_param;
 888     VAPictureH264 *va_pic;
 889     struct i965_driver_data *i965 = i965_driver_data(ctx);
 890     struct object_surface *obj_surface;
 891     dri_bo *bo;
 892     int i, j, enable_avc_ildb = 0;
 893     int width_in_mbs;
 894
 895     for (j = 0; j < decode_state->num_slice_params && enable_avc_ildb == 0; j++) {
 896         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
 897         slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
 898
 899         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
 900             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
 901             assert((slice_param->slice_type == SLICE_TYPE_I) ||
 902                    (slice_param->slice_type == SLICE_TYPE_SI) ||
 903                    (slice_param->slice_type == SLICE_TYPE_P) ||
 904                    (slice_param->slice_type == SLICE_TYPE_SP) ||
 905                    (slice_param->slice_type == SLICE_TYPE_B));
 906
 907             if (slice_param->disable_deblocking_filter_idc != 1) {
 908                 enable_avc_ildb = 1;
 909                 break;
 910             }
 911
 912             slice_param++;
 913         }
 914     }
 915
 916     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 917     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 918     gen6_mfd_avc_frame_store_index(ctx, pic_param, gen6_mfd_context);
 919     width_in_mbs = ((pic_param->picture_width_in_mbs_minus1 + 1) & 0xff);
 920
 921     /* Current decoded picture */
 922     va_pic = &pic_param->CurrPic;
 923     assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
 924     obj_surface = SURFACE(va_pic->picture_id);
 925     assert(obj_surface);
 926     obj_surface->flags &= ~SURFACE_REF_DIS_MASK;
 927     obj_surface->flags |= (pic_param->pic_fields.bits.reference_pic_flag ? SURFACE_REFERENCED : 0);
 928     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
 929
 930     /* initial uv component for YUV400 case */
 931     if (pic_param->seq_fields.bits.chroma_format_idc == 0) {
 932          unsigned int uv_offset = obj_surface->width * obj_surface->height;
 933          unsigned int uv_size   = obj_surface->width * obj_surface->height / 2;
 934
 935          drm_intel_gem_bo_map_gtt(obj_surface->bo);
 936          memset(obj_surface->bo->virtual + uv_offset, 0x80, uv_size);
 937          drm_intel_gem_bo_unmap_gtt(obj_surface->bo);
 938     }
 939
 940     gen6_mfd_init_avc_surface(ctx, pic_param, obj_surface);
 941
 942     dri_bo_unreference(gen6_mfd_context->post_deblocking_output.bo);
 943     gen6_mfd_context->post_deblocking_output.bo = obj_surface->bo;
 944     dri_bo_reference(gen6_mfd_context->post_deblocking_output.bo);
 945     gen6_mfd_context->post_deblocking_output.valid = enable_avc_ildb;
 946
 947     dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo);
 948     gen6_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
 949     dri_bo_reference(gen6_mfd_context->pre_deblocking_output.bo);
 950     gen6_mfd_context->pre_deblocking_output.valid = !enable_avc_ildb;
 951
 952     dri_bo_unreference(gen6_mfd_context->intra_row_store_scratch_buffer.bo);
 953     bo = dri_bo_alloc(i965->intel.bufmgr,
 954                       "intra row store",
 955                       width_in_mbs * 64,
 956                       0x1000);
 957     assert(bo);
 958     gen6_mfd_context->intra_row_store_scratch_buffer.bo = bo;
 959     gen6_mfd_context->intra_row_store_scratch_buffer.valid = 1;
 960
 961     dri_bo_unreference(gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
 962     bo = dri_bo_alloc(i965->intel.bufmgr,
 963                       "deblocking filter row store",
 964                       width_in_mbs * 64 * 4,
 965                       0x1000);
 966     assert(bo);
 967     gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
 968     gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
 969
 970     dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
 971     bo = dri_bo_alloc(i965->intel.bufmgr,
 972                       "bsd mpc row store",
 973                       width_in_mbs * 96,
 974                       0x1000);
 975     assert(bo);
 976     gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
 977     gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
 978
 979     dri_bo_unreference(gen6_mfd_context->mpr_row_store_scratch_buffer.bo);
 980     bo = dri_bo_alloc(i965->intel.bufmgr,
 981                       "mpr row store",
 982                       width_in_mbs * 64,
 983                       0x1000);
 984     assert(bo);
 985     gen6_mfd_context->mpr_row_store_scratch_buffer.bo = bo;
 986     gen6_mfd_context->mpr_row_store_scratch_buffer.valid = 1;
 987
 988     gen6_mfd_context->bitplane_read_buffer.valid = 0;
 989 }
 990
 991 static void
 992 gen6_mfd_avc_decode_picture(VADriverContextP ctx,
 993                             struct decode_state *decode_state,
 994                             struct gen6_mfd_context *gen6_mfd_context)
 995 {
 996     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 997     VAPictureParameterBufferH264 *pic_param;
 998     VASliceParameterBufferH264 *slice_param, *next_slice_param, *next_slice_group_param;
 999     dri_bo *slice_data_bo;
1000     int i, j;
1001
1002     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1003     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
1004     gen6_mfd_avc_decode_init(ctx, decode_state, gen6_mfd_context);
1005
1006     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1007     intel_batchbuffer_emit_mi_flush(batch);
1008     gen6_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context);
1009     gen6_mfd_surface_state(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context);
1010     gen6_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context);
1011     gen6_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context);
1012     gen6_mfd_avc_img_state(ctx, decode_state, gen6_mfd_context);
1013     gen6_mfd_avc_qm_state(ctx, decode_state, gen6_mfd_context);
1014
1015     for (j = 0; j < decode_state->num_slice_params; j++) {
1016         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1017         slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
1018         slice_data_bo = decode_state->slice_datas[j]->bo;
1019         gen6_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_AVC, gen6_mfd_context);
1020
1021         if (j == decode_state->num_slice_params - 1)
1022             next_slice_group_param = NULL;
1023         else
1024             next_slice_group_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j + 1]->buffer;
1025
1026         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1027             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1028             assert((slice_param->slice_type == SLICE_TYPE_I) ||
1029                    (slice_param->slice_type == SLICE_TYPE_SI) ||
1030                    (slice_param->slice_type == SLICE_TYPE_P) ||
1031                    (slice_param->slice_type == SLICE_TYPE_SP) ||
1032                    (slice_param->slice_type == SLICE_TYPE_B));
1033
1034             if (i < decode_state->slice_params[j]->num_elements - 1)
1035                 next_slice_param = slice_param + 1;
1036             else
1037                 next_slice_param = next_slice_group_param;
1038
1039             gen6_mfd_avc_directmode_state(ctx, pic_param, slice_param, gen6_mfd_context);
1040             gen6_mfd_avc_slice_state(ctx, pic_param, slice_param, next_slice_param, gen6_mfd_context);
1041             gen6_mfd_avc_ref_idx_state(ctx, pic_param, slice_param, gen6_mfd_context);
1042             gen6_mfd_avc_weightoffset_state(ctx, pic_param, slice_param, gen6_mfd_context);
1043             gen6_mfd_avc_bsd_object(ctx, pic_param, slice_param, slice_data_bo, gen6_mfd_context);
1044             slice_param++;
1045         }
1046     }
1047
1048     gen6_mfd_avc_phantom_slice(ctx, pic_param, gen6_mfd_context);
1049     intel_batchbuffer_end_atomic(batch);
1050     intel_batchbuffer_flush(batch);
1051 }
1052
1053 static void
1054 gen6_mfd_mpeg2_decode_init(VADriverContextP ctx,
1055                            struct decode_state *decode_state,
1056                            struct gen6_mfd_context *gen6_mfd_context)
1057 {
1058     VAPictureParameterBufferMPEG2 *pic_param;
1059     struct i965_driver_data *i965 = i965_driver_data(ctx);
1060     struct object_surface *obj_surface;
1061     dri_bo *bo;
1062     unsigned int width_in_mbs;
1063
1064     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1065     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1066     width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
1067
1068     mpeg2_set_reference_surfaces(
1069         ctx,
1070         gen6_mfd_context->reference_surface,
1071         decode_state,
1072         pic_param
1073     );
1074
1075     /* Current decoded picture */
1076     obj_surface = SURFACE(decode_state->current_render_target);
1077     assert(obj_surface);
1078     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
1079
1080     dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo);
1081     gen6_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1082     dri_bo_reference(gen6_mfd_context->pre_deblocking_output.bo);
1083     gen6_mfd_context->pre_deblocking_output.valid = 1;
1084
1085     dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1086     bo = dri_bo_alloc(i965->intel.bufmgr,
1087                       "bsd mpc row store",
1088                       width_in_mbs * 96,
1089                       0x1000);
1090     assert(bo);
1091     gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1092     gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1093
1094     gen6_mfd_context->post_deblocking_output.valid = 0;
1095     gen6_mfd_context->intra_row_store_scratch_buffer.valid = 0;
1096     gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0;
1097     gen6_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1098     gen6_mfd_context->bitplane_read_buffer.valid = 0;
1099 }
1100
1101 static void
1102 gen6_mfd_mpeg2_pic_state(VADriverContextP ctx,
1103                          struct decode_state *decode_state,
1104                          struct gen6_mfd_context *gen6_mfd_context)
1105 {
1106     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1107     VAPictureParameterBufferMPEG2 *pic_param;
1108     unsigned int tff, pic_structure;
1109
1110     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1111     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1112
1113     pic_structure = pic_param->picture_coding_extension.bits.picture_structure;
1114     if (pic_structure == MPEG_FRAME)
1115         tff = pic_param->picture_coding_extension.bits.top_field_first;
1116     else
1117         tff = !(pic_param->picture_coding_extension.bits.is_first_field ^
1118                 (pic_structure & MPEG_TOP_FIELD));
1119
1120     BEGIN_BCS_BATCH(batch, 4);
1121     OUT_BCS_BATCH(batch, MFX_MPEG2_PIC_STATE | (4 - 2));
1122     OUT_BCS_BATCH(batch,
1123                   (pic_param->f_code & 0xf) << 28 | /* f_code[1][1] */
1124                   ((pic_param->f_code >> 4) & 0xf) << 24 | /* f_code[1][0] */
1125                   ((pic_param->f_code >> 8) & 0xf) << 20 | /* f_code[0][1] */
1126                   ((pic_param->f_code >> 12) & 0xf) << 16 | /* f_code[0][0] */
1127                   pic_param->picture_coding_extension.bits.intra_dc_precision << 14 |
1128                   pic_param->picture_coding_extension.bits.picture_structure << 12 |
1129                   tff << 11 |
1130                   pic_param->picture_coding_extension.bits.frame_pred_frame_dct << 10 |
1131                   pic_param->picture_coding_extension.bits.concealment_motion_vectors << 9 |
1132                   pic_param->picture_coding_extension.bits.q_scale_type << 8 |
1133                   pic_param->picture_coding_extension.bits.intra_vlc_format << 7 |
1134                   pic_param->picture_coding_extension.bits.alternate_scan << 6);
1135     OUT_BCS_BATCH(batch,
1136                   pic_param->picture_coding_type << 9);
1137     OUT_BCS_BATCH(batch,
1138                   (ALIGN(pic_param->vertical_size, 16) / 16) << 16 |
1139                   (ALIGN(pic_param->horizontal_size, 16) / 16));
1140     ADVANCE_BCS_BATCH(batch);
1141 }
1142
1143 static void
1144 gen6_mfd_mpeg2_qm_state(VADriverContextP ctx,
1145                         struct decode_state *decode_state,
1146                         struct gen6_mfd_context *gen6_mfd_context)
1147 {
1148     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1149     VAIQMatrixBufferMPEG2 * const gen_iq_matrix = &gen6_mfd_context->iq_matrix.mpeg2;
1150     int i, j;
1151
1152     /* Update internal QM state */
1153     if (decode_state->iq_matrix && decode_state->iq_matrix->buffer) {
1154         VAIQMatrixBufferMPEG2 * const iq_matrix =
1155             (VAIQMatrixBufferMPEG2 *)decode_state->iq_matrix->buffer;
1156
1157         gen_iq_matrix->load_intra_quantiser_matrix =
1158             iq_matrix->load_intra_quantiser_matrix;
1159         if (iq_matrix->load_intra_quantiser_matrix) {
1160             for (j = 0; j < 64; j++)
1161                 gen_iq_matrix->intra_quantiser_matrix[zigzag_direct[j]] =
1162                     iq_matrix->intra_quantiser_matrix[j];
1163         }
1164
1165         gen_iq_matrix->load_non_intra_quantiser_matrix =
1166             iq_matrix->load_non_intra_quantiser_matrix;
1167         if (iq_matrix->load_non_intra_quantiser_matrix) {
1168             for (j = 0; j < 64; j++)
1169                 gen_iq_matrix->non_intra_quantiser_matrix[zigzag_direct[j]] =
1170                     iq_matrix->non_intra_quantiser_matrix[j];
1171         }
1172     }
1173
1174     /* Commit QM state to HW */
1175     for (i = 0; i < 2; i++) {
1176         unsigned char *qm = NULL;
1177
1178         if (i == 0) {
1179             if (gen_iq_matrix->load_intra_quantiser_matrix)
1180                 qm = gen_iq_matrix->intra_quantiser_matrix;
1181         } else {
1182             if (gen_iq_matrix->load_non_intra_quantiser_matrix)
1183                 qm = gen_iq_matrix->non_intra_quantiser_matrix;
1184         }
1185
1186         if (!qm)
1187             continue;
1188
1189         BEGIN_BCS_BATCH(batch, 18);
1190         OUT_BCS_BATCH(batch, MFX_MPEG2_QM_STATE | (18 - 2));
1191         OUT_BCS_BATCH(batch, i);
1192         intel_batchbuffer_data(batch, qm, 64);
1193         ADVANCE_BCS_BATCH(batch);
1194     }
1195 }
1196
1197 static void
1198 gen6_mfd_mpeg2_bsd_object(VADriverContextP ctx,
1199                           VAPictureParameterBufferMPEG2 *pic_param,
1200                           VASliceParameterBufferMPEG2 *slice_param,
1201                           VASliceParameterBufferMPEG2 *next_slice_param,
1202                           struct gen6_mfd_context *gen6_mfd_context)
1203 {
1204     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1205     unsigned int width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
1206     int mb_count, vpos0, hpos0, vpos1, hpos1, is_field_pic_wa, is_field_pic = 0;
1207
1208     if (pic_param->picture_coding_extension.bits.picture_structure == MPEG_TOP_FIELD ||
1209         pic_param->picture_coding_extension.bits.picture_structure == MPEG_BOTTOM_FIELD)
1210         is_field_pic = 1;
1211     is_field_pic_wa = is_field_pic &&
1212         gen6_mfd_context->wa_mpeg2_slice_vertical_position > 0;
1213
1214     vpos0 = slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1215     hpos0 = slice_param->slice_horizontal_position;
1216
1217     if (next_slice_param == NULL) {
1218         vpos1 = ALIGN(pic_param->vertical_size, 16) / 16 / (1 + is_field_pic);
1219         hpos1 = 0;
1220     } else {
1221         vpos1 = next_slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1222         hpos1 = next_slice_param->slice_horizontal_position;
1223     }
1224
1225     mb_count = (vpos1 * width_in_mbs + hpos1) - (vpos0 * width_in_mbs + hpos0);
1226
1227     BEGIN_BCS_BATCH(batch, 5);
1228     OUT_BCS_BATCH(batch, MFD_MPEG2_BSD_OBJECT | (5 - 2));
1229     OUT_BCS_BATCH(batch,
1230                   slice_param->slice_data_size - (slice_param->macroblock_offset >> 3));
1231     OUT_BCS_BATCH(batch,
1232                   slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3));
1233     OUT_BCS_BATCH(batch,
1234                   hpos0 << 24 |
1235                   vpos0 << 16 |
1236                   mb_count << 8 |
1237                   (next_slice_param == NULL) << 5 |
1238                   (next_slice_param == NULL) << 3 |
1239                   (slice_param->macroblock_offset & 0x7));
1240     OUT_BCS_BATCH(batch,
1241                   slice_param->quantiser_scale_code << 24);
1242     ADVANCE_BCS_BATCH(batch);
1243 }
1244
1245 static void
1246 gen6_mfd_mpeg2_decode_picture(VADriverContextP ctx,
1247                               struct decode_state *decode_state,
1248                               struct gen6_mfd_context *gen6_mfd_context)
1249 {
1250     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1251     VAPictureParameterBufferMPEG2 *pic_param;
1252     VASliceParameterBufferMPEG2 *slice_param, *next_slice_param, *next_slice_group_param;
1253     dri_bo *slice_data_bo;
1254     int i, j;
1255
1256     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1257     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1258
1259     gen6_mfd_mpeg2_decode_init(ctx, decode_state, gen6_mfd_context);
1260     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1261     intel_batchbuffer_emit_mi_flush(batch);
1262     gen6_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context);
1263     gen6_mfd_surface_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context);
1264     gen6_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context);
1265     gen6_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context);
1266     gen6_mfd_mpeg2_pic_state(ctx, decode_state, gen6_mfd_context);
1267     gen6_mfd_mpeg2_qm_state(ctx, decode_state, gen6_mfd_context);
1268
1269     if (gen6_mfd_context->wa_mpeg2_slice_vertical_position < 0)
1270         gen6_mfd_context->wa_mpeg2_slice_vertical_position =
1271             mpeg2_wa_slice_vertical_position(decode_state, pic_param);
1272
1273     for (j = 0; j < decode_state->num_slice_params; j++) {
1274         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1275         slice_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j]->buffer;
1276         slice_data_bo = decode_state->slice_datas[j]->bo;
1277         gen6_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_MPEG2, gen6_mfd_context);
1278
1279         if (j == decode_state->num_slice_params - 1)
1280             next_slice_group_param = NULL;
1281         else
1282             next_slice_group_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[j + 1]->buffer;
1283
1284         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1285             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1286
1287             if (i < decode_state->slice_params[j]->num_elements - 1)
1288                 next_slice_param = slice_param + 1;
1289             else
1290                 next_slice_param = next_slice_group_param;
1291
1292             gen6_mfd_mpeg2_bsd_object(ctx, pic_param, slice_param, next_slice_param, gen6_mfd_context);
1293             slice_param++;
1294         }
1295     }
1296
1297     intel_batchbuffer_end_atomic(batch);
1298     intel_batchbuffer_flush(batch);
1299 }
1300
1301 static const int va_to_gen6_vc1_pic_type[5] = {
1302     GEN6_VC1_I_PICTURE,
1303     GEN6_VC1_P_PICTURE,
1304     GEN6_VC1_B_PICTURE,
1305     GEN6_VC1_BI_PICTURE,
1306     GEN6_VC1_P_PICTURE,
1307 };
1308
1309 static const int va_to_gen6_vc1_mv[4] = {
1310     1, /* 1-MV */
1311     2, /* 1-MV half-pel */
1312     3, /* 1-MV half-pef bilinear */
1313     0, /* Mixed MV */
1314 };
1315
1316 static const int b_picture_scale_factor[21] = {
1317     128, 85,  170, 64,  192,
1318     51,  102, 153, 204, 43,
1319     215, 37,  74,  111, 148,
1320     185, 222, 32,  96,  160,
1321     224,
1322 };
1323
1324 static const int va_to_gen6_vc1_condover[3] = {
1325     0,
1326     2,
1327     3
1328 };
1329
1330 static const int va_to_gen6_vc1_profile[4] = {
1331     GEN6_VC1_SIMPLE_PROFILE,
1332     GEN6_VC1_MAIN_PROFILE,
1333     GEN6_VC1_RESERVED_PROFILE,
1334     GEN6_VC1_ADVANCED_PROFILE
1335 };
1336
1337 static void
1338 gen6_mfd_free_vc1_surface(void **data)
1339 {
1340     struct gen6_vc1_surface *gen6_vc1_surface = *data;
1341
1342     if (!gen6_vc1_surface)
1343         return;
1344
1345     dri_bo_unreference(gen6_vc1_surface->dmv);
1346     free(gen6_vc1_surface);
1347     *data = NULL;
1348 }
1349
1350 static void
1351 gen6_mfd_init_vc1_surface(VADriverContextP ctx,
1352                           VAPictureParameterBufferVC1 *pic_param,
1353                           struct object_surface *obj_surface)
1354 {
1355     struct i965_driver_data *i965 = i965_driver_data(ctx);
1356     struct gen6_vc1_surface *gen6_vc1_surface = obj_surface->private_data;
1357     int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1358
1359     obj_surface->free_private_data = gen6_mfd_free_vc1_surface;
1360
1361     if (!gen6_vc1_surface) {
1362         gen6_vc1_surface = calloc(sizeof(struct gen6_vc1_surface), 1);
1363         assert((obj_surface->size & 0x3f) == 0);
1364         obj_surface->private_data = gen6_vc1_surface;
1365     }
1366
1367     gen6_vc1_surface->picture_type = pic_param->picture_fields.bits.picture_type;
1368
1369     if (gen6_vc1_surface->dmv == NULL) {
1370         gen6_vc1_surface->dmv = dri_bo_alloc(i965->intel.bufmgr,
1371                                              "direct mv w/r buffer",
1372                                              128 * height_in_mbs * 64,  /* scalable with frame height */
1373                                              0x1000);
1374     }
1375 }
1376
1377 static void
1378 gen6_mfd_vc1_decode_init(VADriverContextP ctx,
1379                          struct decode_state *decode_state,
1380                          struct gen6_mfd_context *gen6_mfd_context)
1381 {
1382     VAPictureParameterBufferVC1 *pic_param;
1383     struct i965_driver_data *i965 = i965_driver_data(ctx);
1384     struct object_surface *obj_surface;
1385     int i;
1386     dri_bo *bo;
1387     int width_in_mbs;
1388
1389     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1390     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1391     width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1392
1393     /* reference picture */
1394     obj_surface = SURFACE(pic_param->forward_reference_picture);
1395
1396     if (obj_surface && obj_surface->bo)
1397         gen6_mfd_context->reference_surface[0].surface_id = pic_param->forward_reference_picture;
1398     else
1399         gen6_mfd_context->reference_surface[0].surface_id = VA_INVALID_ID;
1400
1401     obj_surface = SURFACE(pic_param->backward_reference_picture);
1402
1403     if (obj_surface && obj_surface->bo)
1404         gen6_mfd_context->reference_surface[1].surface_id = pic_param->backward_reference_picture;
1405     else
1406         gen6_mfd_context->reference_surface[1].surface_id = pic_param->forward_reference_picture;
1407
1408     /* must do so !!! */
1409     for (i = 2; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++)
1410         gen6_mfd_context->reference_surface[i].surface_id = gen6_mfd_context->reference_surface[i % 2].surface_id;
1411
1412     /* Current decoded picture */
1413     obj_surface = SURFACE(decode_state->current_render_target);
1414     assert(obj_surface);
1415     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
1416     gen6_mfd_init_vc1_surface(ctx, pic_param, obj_surface);
1417
1418     dri_bo_unreference(gen6_mfd_context->post_deblocking_output.bo);
1419     gen6_mfd_context->post_deblocking_output.bo = obj_surface->bo;
1420     dri_bo_reference(gen6_mfd_context->post_deblocking_output.bo);
1421     gen6_mfd_context->post_deblocking_output.valid = pic_param->entrypoint_fields.bits.loopfilter;
1422
1423     dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo);
1424     gen6_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1425     dri_bo_reference(gen6_mfd_context->pre_deblocking_output.bo);
1426     gen6_mfd_context->pre_deblocking_output.valid = !pic_param->entrypoint_fields.bits.loopfilter;
1427
1428     dri_bo_unreference(gen6_mfd_context->intra_row_store_scratch_buffer.bo);
1429     bo = dri_bo_alloc(i965->intel.bufmgr,
1430                       "intra row store",
1431                       width_in_mbs * 64,
1432                       0x1000);
1433     assert(bo);
1434     gen6_mfd_context->intra_row_store_scratch_buffer.bo = bo;
1435     gen6_mfd_context->intra_row_store_scratch_buffer.valid = 1;
1436
1437     dri_bo_unreference(gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
1438     bo = dri_bo_alloc(i965->intel.bufmgr,
1439                       "deblocking filter row store",
1440                       width_in_mbs * 6 * 64,
1441                       0x1000);
1442     assert(bo);
1443     gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
1444     gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
1445
1446     dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1447     bo = dri_bo_alloc(i965->intel.bufmgr,
1448                       "bsd mpc row store",
1449                       width_in_mbs * 96,
1450                       0x1000);
1451     assert(bo);
1452     gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1453     gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1454
1455     gen6_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1456
1457     gen6_mfd_context->bitplane_read_buffer.valid = !!pic_param->bitplane_present.value;
1458     dri_bo_unreference(gen6_mfd_context->bitplane_read_buffer.bo);
1459
1460     if (gen6_mfd_context->bitplane_read_buffer.valid) {
1461         int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1462         int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1463         int bitplane_width = ALIGN(width_in_mbs, 2) / 2;
1464         int src_w, src_h;
1465         uint8_t *src = NULL, *dst = NULL;
1466
1467         assert(decode_state->bit_plane->buffer);
1468         src = decode_state->bit_plane->buffer;
1469
1470         bo = dri_bo_alloc(i965->intel.bufmgr,
1471                           "VC-1 Bitplane",
1472                           bitplane_width * height_in_mbs,
1473                           0x1000);
1474         assert(bo);
1475         gen6_mfd_context->bitplane_read_buffer.bo = bo;
1476
1477         dri_bo_map(bo, True);
1478         assert(bo->virtual);
1479         dst = bo->virtual;
1480
1481         for (src_h = 0; src_h < height_in_mbs; src_h++) {
1482             for(src_w = 0; src_w < width_in_mbs; src_w++) {
1483                 int src_index, dst_index;
1484                 int src_shift;
1485                 uint8_t src_value;
1486
1487                 src_index = (src_h * width_in_mbs + src_w) / 2;
1488                 src_shift = !((src_h * width_in_mbs + src_w) & 1) * 4;
1489                 src_value = ((src[src_index] >> src_shift) & 0xf);
1490
1491                 dst_index = src_w / 2;
1492                 dst[dst_index] = ((dst[dst_index] >> 4) | (src_value << 4));
1493             }
1494
1495             if (src_w & 1)
1496                 dst[src_w / 2] >>= 4;
1497
1498             dst += bitplane_width;
1499         }
1500
1501         dri_bo_unmap(bo);
1502     } else
1503         gen6_mfd_context->bitplane_read_buffer.bo = NULL;
1504 }
1505
1506 static void
1507 gen6_mfd_vc1_pic_state(VADriverContextP ctx,
1508                        struct decode_state *decode_state,
1509                        struct gen6_mfd_context *gen6_mfd_context)
1510 {
1511     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1512     VAPictureParameterBufferVC1 *pic_param;
1513     struct i965_driver_data *i965 = i965_driver_data(ctx);
1514     struct object_surface *obj_surface;
1515     int alt_pquant_config = 0, alt_pquant_edge_mask = 0, alt_pq;
1516     int dquant, dquantfrm, dqprofile, dqdbedge, dqsbedge, dqbilevel;
1517     int unified_mv_mode;
1518     int ref_field_pic_polarity = 0;
1519     int scale_factor = 0;
1520     int trans_ac_y = 0;
1521     int dmv_surface_valid = 0;
1522     int brfd = 0;
1523     int fcm = 0;
1524     int picture_type;
1525     int profile;
1526     int overlap;
1527
1528     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1529     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1530
1531     profile = va_to_gen6_vc1_profile[pic_param->sequence_fields.bits.profile];
1532     dquant = pic_param->pic_quantizer_fields.bits.dquant;
1533     dquantfrm = pic_param->pic_quantizer_fields.bits.dq_frame;
1534     dqprofile = pic_param->pic_quantizer_fields.bits.dq_profile;
1535     dqdbedge = pic_param->pic_quantizer_fields.bits.dq_db_edge;
1536     dqsbedge = pic_param->pic_quantizer_fields.bits.dq_sb_edge;
1537     dqbilevel = pic_param->pic_quantizer_fields.bits.dq_binary_level;
1538     alt_pq = pic_param->pic_quantizer_fields.bits.alt_pic_quantizer;
1539
1540     if (dquant == 0) {
1541         alt_pquant_config = 0;
1542         alt_pquant_edge_mask = 0;
1543     } else if (dquant == 2) {
1544         alt_pquant_config = 1;
1545         alt_pquant_edge_mask = 0xf;
1546     } else {
1547         assert(dquant == 1);
1548         if (dquantfrm == 0) {
1549             alt_pquant_config = 0;
1550             alt_pquant_edge_mask = 0;
1551             alt_pq = 0;
1552         } else {
1553             assert(dquantfrm == 1);
1554             alt_pquant_config = 1;
1555
1556             switch (dqprofile) {
1557             case 3:
1558                 if (dqbilevel == 0) {
1559                     alt_pquant_config = 2;
1560                     alt_pquant_edge_mask = 0;
1561                 } else {
1562                     assert(dqbilevel == 1);
1563                     alt_pquant_config = 3;
1564                     alt_pquant_edge_mask = 0;
1565                 }
1566                 break;
1567
1568             case 0:
1569                 alt_pquant_edge_mask = 0xf;
1570                 break;
1571
1572             case 1:
1573                 if (dqdbedge == 3)
1574                     alt_pquant_edge_mask = 0x9;
1575                 else
1576                     alt_pquant_edge_mask = (0x3 << dqdbedge);
1577
1578                 break;
1579
1580             case 2:
1581                 alt_pquant_edge_mask = (0x1 << dqsbedge);
1582                 break;
1583
1584             default:
1585                 assert(0);
1586             }
1587         }
1588     }
1589
1590     if (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation) {
1591         assert(pic_param->mv_fields.bits.mv_mode2 < 4);
1592         unified_mv_mode = va_to_gen6_vc1_mv[pic_param->mv_fields.bits.mv_mode2];
1593     } else {
1594         assert(pic_param->mv_fields.bits.mv_mode < 4);
1595         unified_mv_mode = va_to_gen6_vc1_mv[pic_param->mv_fields.bits.mv_mode];
1596     }
1597
1598     if (pic_param->sequence_fields.bits.interlace == 1 &&
1599         pic_param->picture_fields.bits.frame_coding_mode != 0) { /* frame-interlace or field-interlace */
1600         /* FIXME: calculate reference field picture polarity */
1601         assert(0);
1602         ref_field_pic_polarity = 0;
1603     }
1604
1605     if (pic_param->b_picture_fraction < 21)
1606         scale_factor = b_picture_scale_factor[pic_param->b_picture_fraction];
1607
1608     picture_type = va_to_gen6_vc1_pic_type[pic_param->picture_fields.bits.picture_type];
1609
1610     if (profile == GEN6_VC1_ADVANCED_PROFILE &&
1611         picture_type == GEN6_VC1_I_PICTURE)
1612         picture_type = GEN6_VC1_BI_PICTURE;
1613
1614     if (picture_type == GEN6_VC1_I_PICTURE || picture_type == GEN6_VC1_BI_PICTURE) /* I picture */
1615         trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx2;
1616     else {
1617         trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx1;
1618         /*
1619          * 8.3.6.2.1 Transform Type Selection
1620          * If variable-sized transform coding is not enabled,
1621          * then the 8x8 transform shall be used for all blocks.
1622          * it is also MFX_VC1_PIC_STATE requirement.
1623          */
1624         if (pic_param->transform_fields.bits.variable_sized_transform_flag == 0) {
1625             pic_param->transform_fields.bits.mb_level_transform_type_flag   = 1;
1626             pic_param->transform_fields.bits.frame_level_transform_type     = 0;
1627         }
1628     }
1629
1630     if (picture_type == GEN6_VC1_B_PICTURE) {
1631         struct gen6_vc1_surface *gen6_vc1_surface = NULL;
1632
1633         obj_surface = SURFACE(pic_param->backward_reference_picture);
1634         assert(obj_surface);
1635         gen6_vc1_surface = obj_surface->private_data;
1636
1637         if (!gen6_vc1_surface ||
1638             (va_to_gen6_vc1_pic_type[gen6_vc1_surface->picture_type] == GEN6_VC1_I_PICTURE ||
1639              va_to_gen6_vc1_pic_type[gen6_vc1_surface->picture_type] == GEN6_VC1_BI_PICTURE))
1640             dmv_surface_valid = 0;
1641         else
1642             dmv_surface_valid = 1;
1643     }
1644
1645     assert(pic_param->picture_fields.bits.frame_coding_mode < 3);
1646
1647     if (pic_param->picture_fields.bits.frame_coding_mode < 2)
1648         fcm = pic_param->picture_fields.bits.frame_coding_mode;
1649     else {
1650         if (pic_param->picture_fields.bits.top_field_first)
1651             fcm = 2;
1652         else
1653             fcm = 3;
1654     }
1655
1656     if (pic_param->picture_fields.bits.picture_type == GEN6_VC1_B_PICTURE) { /* B picture */
1657         brfd = pic_param->reference_fields.bits.reference_distance;
1658         brfd = (scale_factor * brfd) >> 8;
1659         brfd = pic_param->reference_fields.bits.reference_distance - brfd - 1;
1660
1661         if (brfd < 0)
1662             brfd = 0;
1663     }
1664
1665     overlap = pic_param->sequence_fields.bits.overlap;
1666     if (profile != GEN6_VC1_ADVANCED_PROFILE && pic_param->pic_quantizer_fields.bits.pic_quantizer_scale < 9)
1667         overlap = 0;
1668
1669     assert(pic_param->conditional_overlap_flag < 3);
1670     assert(pic_param->mv_fields.bits.mv_table < 4); /* FIXME: interlace mode */
1671
1672     BEGIN_BCS_BATCH(batch, 6);
1673     OUT_BCS_BATCH(batch, MFX_VC1_PIC_STATE | (6 - 2));
1674     OUT_BCS_BATCH(batch,
1675                   (ALIGN(pic_param->coded_height, 16) / 16) << 16 |
1676                   (ALIGN(pic_param->coded_width, 16) / 16));
1677     OUT_BCS_BATCH(batch,
1678                   pic_param->sequence_fields.bits.syncmarker << 31 |
1679                   1 << 29 | /* concealment */
1680                   alt_pq << 24 |
1681                   pic_param->entrypoint_fields.bits.loopfilter << 23 |
1682                   overlap << 22 |
1683                   (pic_param->pic_quantizer_fields.bits.quantizer == 0) << 21 | /* implicit quantizer */
1684                   pic_param->pic_quantizer_fields.bits.pic_quantizer_scale << 16 |
1685                   alt_pquant_edge_mask << 12 |
1686                   alt_pquant_config << 10 |
1687                   pic_param->pic_quantizer_fields.bits.half_qp << 9 |
1688                   pic_param->pic_quantizer_fields.bits.pic_quantizer_type << 8 |
1689                   va_to_gen6_vc1_condover[pic_param->conditional_overlap_flag] << 6 |
1690                   !pic_param->picture_fields.bits.is_first_field << 5 |
1691                   picture_type << 2 |
1692                   fcm << 0);
1693     OUT_BCS_BATCH(batch,
1694                   !!pic_param->bitplane_present.value << 23 |
1695                   !pic_param->bitplane_present.flags.bp_forward_mb << 22 |
1696                   !pic_param->bitplane_present.flags.bp_mv_type_mb << 21 |
1697                   !pic_param->bitplane_present.flags.bp_skip_mb << 20 |
1698                   !pic_param->bitplane_present.flags.bp_direct_mb << 19 |
1699                   !pic_param->bitplane_present.flags.bp_overflags << 18 |
1700                   !pic_param->bitplane_present.flags.bp_ac_pred << 17 |
1701                   !pic_param->bitplane_present.flags.bp_field_tx << 16 |
1702                   pic_param->mv_fields.bits.extended_dmv_range << 14 |
1703                   pic_param->mv_fields.bits.extended_mv_range << 12 |
1704                   pic_param->mv_fields.bits.four_mv_switch << 11 |
1705                   pic_param->fast_uvmc_flag << 10 |
1706                   unified_mv_mode << 8 |
1707                   ref_field_pic_polarity << 6 |
1708                   pic_param->reference_fields.bits.num_reference_pictures << 5 |
1709                   pic_param->reference_fields.bits.reference_distance << 0);
1710     OUT_BCS_BATCH(batch,
1711                   scale_factor << 24 |
1712                   pic_param->mv_fields.bits.mv_table << 20 |
1713                   pic_param->mv_fields.bits.four_mv_block_pattern_table << 18 |
1714                   pic_param->mv_fields.bits.two_mv_block_pattern_table << 16 |
1715                   pic_param->transform_fields.bits.frame_level_transform_type << 12 |
1716                   pic_param->transform_fields.bits.mb_level_transform_type_flag << 11 |
1717                   pic_param->mb_mode_table << 8 |
1718                   trans_ac_y << 6 |
1719                   pic_param->transform_fields.bits.transform_ac_codingset_idx1 << 4 |
1720                   pic_param->transform_fields.bits.intra_transform_dc_table << 3 |
1721                   pic_param->cbp_table << 0);
1722     OUT_BCS_BATCH(batch,
1723                   dmv_surface_valid << 13 |
1724                   brfd << 8 |
1725                   ((ALIGN(pic_param->coded_width, 16) / 16 + 1) / 2 - 1));
1726     ADVANCE_BCS_BATCH(batch);
1727 }
1728
1729 static void
1730 gen6_mfd_vc1_pred_pipe_state(VADriverContextP ctx,
1731                              struct decode_state *decode_state,
1732                              struct gen6_mfd_context *gen6_mfd_context)
1733 {
1734     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1735     VAPictureParameterBufferVC1 *pic_param;
1736     int interpolation_mode = 0;
1737     int intensitycomp_single;
1738
1739     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1740     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1741
1742     if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPelBilinear ||
1743         (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
1744          pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPelBilinear))
1745         interpolation_mode = 2; /* Half-pel bilinear */
1746     else if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPel ||
1747              (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
1748               pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPel))
1749         interpolation_mode = 0; /* Half-pel bicubic */
1750     else
1751         interpolation_mode = 1; /* Quarter-pel bicubic */
1752
1753     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1754     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1755     intensitycomp_single = (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation);
1756
1757     BEGIN_BCS_BATCH(batch, 7);
1758     OUT_BCS_BATCH(batch, MFX_VC1_PRED_PIPE_STATE | (7 - 2));
1759     OUT_BCS_BATCH(batch,
1760                   0 << 8 | /* FIXME: interlace mode */
1761                   pic_param->rounding_control << 4 |
1762                   va_to_gen6_vc1_profile[pic_param->sequence_fields.bits.profile] << 2);
1763     OUT_BCS_BATCH(batch,
1764                   pic_param->luma_shift << 16 |
1765                   pic_param->luma_scale << 0); /* FIXME: Luma Scaling */
1766     OUT_BCS_BATCH(batch, 0);
1767     OUT_BCS_BATCH(batch, 0);
1768     OUT_BCS_BATCH(batch, 0);
1769     OUT_BCS_BATCH(batch,
1770                   interpolation_mode << 19 |
1771                   pic_param->fast_uvmc_flag << 18 |
1772                   0 << 17 | /* FIXME: scale up or down ??? */
1773                   pic_param->range_reduction_frame << 16 |
1774                   0 << 6 | /* FIXME: double ??? */
1775                   0 << 4 |
1776                   intensitycomp_single << 2 |
1777                   intensitycomp_single << 0);
1778     ADVANCE_BCS_BATCH(batch);
1779 }
1780
1781
1782 static void
1783 gen6_mfd_vc1_directmode_state(VADriverContextP ctx,
1784                               struct decode_state *decode_state,
1785                               struct gen6_mfd_context *gen6_mfd_context)
1786 {
1787     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1788     VAPictureParameterBufferVC1 *pic_param;
1789     struct i965_driver_data *i965 = i965_driver_data(ctx);
1790     struct object_surface *obj_surface;
1791     dri_bo *dmv_read_buffer = NULL, *dmv_write_buffer = NULL;
1792
1793     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1794     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1795
1796     obj_surface = SURFACE(decode_state->current_render_target);
1797
1798     if (obj_surface && obj_surface->private_data) {
1799         dmv_write_buffer = ((struct gen6_vc1_surface *)(obj_surface->private_data))->dmv;
1800     }
1801
1802     obj_surface = SURFACE(pic_param->backward_reference_picture);
1803
1804     if (obj_surface && obj_surface->private_data) {
1805         dmv_read_buffer = ((struct gen6_vc1_surface *)(obj_surface->private_data))->dmv;
1806     }
1807
1808     BEGIN_BCS_BATCH(batch, 3);
1809     OUT_BCS_BATCH(batch, MFX_VC1_DIRECTMODE_STATE | (3 - 2));
1810
1811     if (dmv_write_buffer)
1812         OUT_BCS_RELOC(batch, dmv_write_buffer,
1813                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
1814                       0);
1815     else
1816         OUT_BCS_BATCH(batch, 0);
1817
1818     if (dmv_read_buffer)
1819         OUT_BCS_RELOC(batch, dmv_read_buffer,
1820                       I915_GEM_DOMAIN_INSTRUCTION, 0,
1821                       0);
1822     else
1823         OUT_BCS_BATCH(batch, 0);
1824
1825     ADVANCE_BCS_BATCH(batch);
1826 }
1827
1828 static int
1829 gen6_mfd_vc1_get_macroblock_bit_offset(uint8_t *buf, int in_slice_data_bit_offset, int profile)
1830 {
1831     int out_slice_data_bit_offset;
1832     int slice_header_size = in_slice_data_bit_offset / 8;
1833     int i, j;
1834
1835     if (profile != 3)
1836         out_slice_data_bit_offset = in_slice_data_bit_offset;
1837     else {
1838         for (i = 0, j = 0; i < slice_header_size; i++, j++) {
1839             if (!buf[j] && !buf[j + 1] && buf[j + 2] == 3 && buf[j + 3] < 4) {
1840                 i++, j += 2;
1841             }
1842         }
1843
1844         out_slice_data_bit_offset = 8 * j + in_slice_data_bit_offset % 8;
1845     }
1846
1847     return out_slice_data_bit_offset;
1848 }
1849
1850 static void
1851 gen6_mfd_vc1_bsd_object(VADriverContextP ctx,
1852                         VAPictureParameterBufferVC1 *pic_param,
1853                         VASliceParameterBufferVC1 *slice_param,
1854                         VASliceParameterBufferVC1 *next_slice_param,
1855                         dri_bo *slice_data_bo,
1856                         struct gen6_mfd_context *gen6_mfd_context)
1857 {
1858     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1859     int next_slice_start_vert_pos;
1860     int macroblock_offset;
1861     uint8_t *slice_data = NULL;
1862
1863     dri_bo_map(slice_data_bo, 0);
1864     slice_data = (uint8_t *)(slice_data_bo->virtual + slice_param->slice_data_offset);
1865     macroblock_offset = gen6_mfd_vc1_get_macroblock_bit_offset(slice_data,
1866                                                                slice_param->macroblock_offset,
1867                                                                pic_param->sequence_fields.bits.profile);
1868     dri_bo_unmap(slice_data_bo);
1869
1870     if (next_slice_param)
1871         next_slice_start_vert_pos = next_slice_param->slice_vertical_position;
1872     else
1873         next_slice_start_vert_pos = ALIGN(pic_param->coded_height, 16) / 16;
1874
1875     BEGIN_BCS_BATCH(batch, 4);
1876     OUT_BCS_BATCH(batch, MFD_VC1_BSD_OBJECT | (4 - 2));
1877     OUT_BCS_BATCH(batch,
1878                   slice_param->slice_data_size - (macroblock_offset >> 3));
1879     OUT_BCS_BATCH(batch,
1880                   slice_param->slice_data_offset + (macroblock_offset >> 3));
1881     OUT_BCS_BATCH(batch,
1882                   slice_param->slice_vertical_position << 24 |
1883                   next_slice_start_vert_pos << 16 |
1884                   (1 << 7) |
1885                   (macroblock_offset & 0x7));
1886     ADVANCE_BCS_BATCH(batch);
1887 }
1888
1889 static void
1890 gen6_mfd_vc1_decode_picture(VADriverContextP ctx,
1891                             struct decode_state *decode_state,
1892                             struct gen6_mfd_context *gen6_mfd_context)
1893 {
1894     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1895     VAPictureParameterBufferVC1 *pic_param;
1896     VASliceParameterBufferVC1 *slice_param, *next_slice_param, *next_slice_group_param;
1897     dri_bo *slice_data_bo;
1898     int i, j;
1899
1900     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1901     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1902
1903     gen6_mfd_vc1_decode_init(ctx, decode_state, gen6_mfd_context);
1904     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1905     intel_batchbuffer_emit_mi_flush(batch);
1906     gen6_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context);
1907     gen6_mfd_surface_state(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context);
1908     gen6_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context);
1909     gen6_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context);
1910     gen6_mfd_vc1_pic_state(ctx, decode_state, gen6_mfd_context);
1911     gen6_mfd_vc1_pred_pipe_state(ctx, decode_state, gen6_mfd_context);
1912     gen6_mfd_vc1_directmode_state(ctx, decode_state, gen6_mfd_context);
1913
1914     for (j = 0; j < decode_state->num_slice_params; j++) {
1915         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1916         slice_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j]->buffer;
1917         slice_data_bo = decode_state->slice_datas[j]->bo;
1918         gen6_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_VC1, gen6_mfd_context);
1919
1920         if (j == decode_state->num_slice_params - 1)
1921             next_slice_group_param = NULL;
1922         else
1923             next_slice_group_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j + 1]->buffer;
1924
1925         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1926             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1927
1928             if (i < decode_state->slice_params[j]->num_elements - 1)
1929                 next_slice_param = slice_param + 1;
1930             else
1931                 next_slice_param = next_slice_group_param;
1932
1933             gen6_mfd_vc1_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen6_mfd_context);
1934             slice_param++;
1935         }
1936     }
1937
1938     intel_batchbuffer_end_atomic(batch);
1939     intel_batchbuffer_flush(batch);
1940 }
1941
1942 static void
1943 gen6_mfd_decode_picture(VADriverContextP ctx,
1944                         VAProfile profile,
1945                         union codec_state *codec_state,
1946                         struct hw_context *hw_context)
1947
1948 {
1949     struct gen6_mfd_context *gen6_mfd_context = (struct gen6_mfd_context *)hw_context;
1950     struct decode_state *decode_state = &codec_state->decode;
1951
1952     assert(gen6_mfd_context);
1953
1954     switch (profile) {
1955     case VAProfileMPEG2Simple:
1956     case VAProfileMPEG2Main:
1957         gen6_mfd_mpeg2_decode_picture(ctx, decode_state, gen6_mfd_context);
1958         break;
1959
1960     case VAProfileH264Baseline:
1961     case VAProfileH264Main:
1962     case VAProfileH264High:
1963         gen6_mfd_avc_decode_picture(ctx, decode_state, gen6_mfd_context);
1964         break;
1965
1966     case VAProfileVC1Simple:
1967     case VAProfileVC1Main:
1968     case VAProfileVC1Advanced:
1969         gen6_mfd_vc1_decode_picture(ctx, decode_state, gen6_mfd_context);
1970         break;
1971
1972     default:
1973         assert(0);
1974         break;
1975     }
1976 }
1977
1978 static void
1979 gen6_mfd_context_destroy(void *hw_context)
1980 {
1981     struct gen6_mfd_context *gen6_mfd_context = (struct gen6_mfd_context *)hw_context;
1982
1983     dri_bo_unreference(gen6_mfd_context->post_deblocking_output.bo);
1984     gen6_mfd_context->post_deblocking_output.bo = NULL;
1985
1986     dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo);
1987     gen6_mfd_context->pre_deblocking_output.bo = NULL;
1988
1989     dri_bo_unreference(gen6_mfd_context->intra_row_store_scratch_buffer.bo);
1990     gen6_mfd_context->intra_row_store_scratch_buffer.bo = NULL;
1991
1992     dri_bo_unreference(gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
1993     gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
1994
1995     dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1996     gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
1997
1998     dri_bo_unreference(gen6_mfd_context->mpr_row_store_scratch_buffer.bo);
1999     gen6_mfd_context->mpr_row_store_scratch_buffer.bo = NULL;
2000
2001     dri_bo_unreference(gen6_mfd_context->bitplane_read_buffer.bo);
2002     gen6_mfd_context->bitplane_read_buffer.bo = NULL;
2003
2004     intel_batchbuffer_free(gen6_mfd_context->base.batch);
2005     free(gen6_mfd_context);
2006 }
2007
2008 struct hw_context *
2009 gen6_dec_hw_context_init(VADriverContextP ctx, VAProfile profile)
2010 {
2011     struct intel_driver_data *intel = intel_driver_data(ctx);
2012     struct gen6_mfd_context *gen6_mfd_context = calloc(1, sizeof(struct gen6_mfd_context));
2013     int i;
2014
2015     gen6_mfd_context->base.destroy = gen6_mfd_context_destroy;
2016     gen6_mfd_context->base.run = gen6_mfd_decode_picture;
2017     gen6_mfd_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0);
2018
2019     for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) {
2020         gen6_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID;
2021         gen6_mfd_context->reference_surface[i].frame_store_id = -1;
2022     }
2023
2024     gen6_mfd_context->wa_mpeg2_slice_vertical_position = -1;
2025
2026     return (struct hw_context *)gen6_mfd_context;
2027 }