src/gen6_mfd.c

   1 /*
   2  * Copyright © 2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Xiang Haihao <haihao.xiang@intel.com>
  26  *
  27  */
  28
  29 #include "sysdeps.h"
  30 #include "intel_batchbuffer.h"
  31 #include "intel_driver.h"
  32 #include "i965_defines.h"
  33 #include "i965_drv_video.h"
  34 #include "i965_decoder_utils.h"
  35
  36 #include "gen6_mfd.h"
  37 #include "intel_media.h"
  38
  39 static const uint32_t zigzag_direct[64] = {
  40     0,   1,  8, 16,  9,  2,  3, 10,
  41     17, 24, 32, 25, 18, 11,  4,  5,
  42     12, 19, 26, 33, 40, 48, 41, 34,
  43     27, 20, 13,  6,  7, 14, 21, 28,
  44     35, 42, 49, 56, 57, 50, 43, 36,
  45     29, 22, 15, 23, 30, 37, 44, 51,
  46     58, 59, 52, 45, 38, 31, 39, 46,
  47     53, 60, 61, 54, 47, 55, 62, 63
  48 };
  49
  50 static void
  51 gen6_mfd_init_avc_surface(VADriverContextP ctx,
  52                           VAPictureParameterBufferH264 *pic_param,
  53                           struct object_surface *obj_surface)
  54 {
  55     struct i965_driver_data *i965 = i965_driver_data(ctx);
  56     GenAvcSurface *gen6_avc_surface = obj_surface->private_data;
  57     int height_in_mbs;
  58
  59     obj_surface->free_private_data = gen_free_avc_surface;
  60     height_in_mbs = ((pic_param->picture_height_in_mbs_minus1 + 1) & 0xff); /* frame height */
  61
  62     if (!gen6_avc_surface) {
  63         gen6_avc_surface = calloc(sizeof(GenAvcSurface), 1);
  64         assert((obj_surface->size & 0x3f) == 0);
  65         obj_surface->private_data = gen6_avc_surface;
  66     }
  67
  68     gen6_avc_surface->dmv_bottom_flag = (pic_param->pic_fields.bits.field_pic_flag &&
  69                                          !pic_param->seq_fields.bits.direct_8x8_inference_flag);
  70
  71     if (gen6_avc_surface->dmv_top == NULL) {
  72         gen6_avc_surface->dmv_top = dri_bo_alloc(i965->intel.bufmgr,
  73                                                  "direct mv w/r buffer",
  74                                                  128 * height_in_mbs * 64,      /* scalable with frame height */
  75                                                  0x1000);
  76     }
  77
  78     if (gen6_avc_surface->dmv_bottom_flag &&
  79         gen6_avc_surface->dmv_bottom == NULL) {
  80         gen6_avc_surface->dmv_bottom = dri_bo_alloc(i965->intel.bufmgr,
  81                                                     "direct mv w/r buffer",
  82                                                     128 * height_in_mbs * 64,   /* scalable with frame height */
  83                                                     0x1000);
  84     }
  85 }
  86
  87 static void
  88 gen6_mfd_pipe_mode_select(VADriverContextP ctx,
  89                           struct decode_state *decode_state,
  90                           int standard_select,
  91                           struct gen6_mfd_context *gen6_mfd_context)
  92 {
  93     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
  94
  95     assert(standard_select == MFX_FORMAT_MPEG2 ||
  96            standard_select == MFX_FORMAT_AVC ||
  97            standard_select == MFX_FORMAT_VC1);
  98
  99     BEGIN_BCS_BATCH(batch, 4);
 100     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (4 - 2));
 101     OUT_BCS_BATCH(batch,
 102                   (MFD_MODE_VLD << 16) | /* VLD mode */
 103                   (0 << 10) | /* disable Stream-Out */
 104                   (gen6_mfd_context->post_deblocking_output.valid << 9)  | /* Post Deblocking Output */
 105                   (gen6_mfd_context->pre_deblocking_output.valid << 8)  | /* Pre Deblocking Output */
 106                   (0 << 7)  | /* disable TLB prefectch */
 107                   (0 << 5)  | /* not in stitch mode */
 108                   (MFX_CODEC_DECODE << 4)  | /* decoding mode */
 109                   (standard_select << 0));
 110     OUT_BCS_BATCH(batch,
 111                   (0 << 20) | /* round flag in PB slice */
 112                   (0 << 19) | /* round flag in Intra8x8 */
 113                   (0 << 7)  | /* expand NOA bus flag */
 114                   (1 << 6)  | /* must be 1 */
 115                   (0 << 5)  | /* disable clock gating for NOA */
 116                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
 117                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
 118                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
 119                   (0 << 1)  | /* AVC long field motion vector */
 120                   (1 << 0));  /* always calculate AVC ILDB boundary strength */
 121     OUT_BCS_BATCH(batch, 0);
 122     ADVANCE_BCS_BATCH(batch);
 123 }
 124
 125 static void
 126 gen6_mfd_surface_state(VADriverContextP ctx,
 127                        struct decode_state *decode_state,
 128                        int standard_select,
 129                        struct gen6_mfd_context *gen6_mfd_context)
 130 {
 131     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 132     struct object_surface *obj_surface = decode_state->render_object;
 133
 134     BEGIN_BCS_BATCH(batch, 6);
 135     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
 136     OUT_BCS_BATCH(batch, 0);
 137     OUT_BCS_BATCH(batch,
 138                   ((obj_surface->orig_height - 1) << 19) |
 139                   ((obj_surface->orig_width - 1) << 6));
 140     OUT_BCS_BATCH(batch,
 141                   (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
 142                   (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
 143                   (0 << 22) | /* surface object control state, FIXME??? */
 144                   ((obj_surface->width - 1) << 3) | /* pitch */
 145                   (0 << 2)  | /* must be 0 for interleave U/V */
 146                   (1 << 1)  | /* must be y-tiled */
 147                   (I965_TILEWALK_YMAJOR << 0));  /* tile walk, FIXME: must be 1 ??? */
 148     OUT_BCS_BATCH(batch,
 149                   (0 << 16) | /* must be 0 for interleave U/V */
 150                   (obj_surface->height)); /* y offset for U(cb) */
 151     OUT_BCS_BATCH(batch, 0);
 152     ADVANCE_BCS_BATCH(batch);
 153 }
 154
 155 static void
 156 gen6_mfd_pipe_buf_addr_state(VADriverContextP ctx,
 157                              struct decode_state *decode_state,
 158                              int standard_select,
 159                              struct gen6_mfd_context *gen6_mfd_context)
 160 {
 161     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 162     int i;
 163
 164     BEGIN_BCS_BATCH(batch, 24);
 165     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
 166     if (gen6_mfd_context->pre_deblocking_output.valid)
 167         OUT_BCS_RELOC(batch, gen6_mfd_context->pre_deblocking_output.bo,
 168                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 169                       0);
 170     else
 171         OUT_BCS_BATCH(batch, 0);
 172
 173     if (gen6_mfd_context->post_deblocking_output.valid)
 174         OUT_BCS_RELOC(batch, gen6_mfd_context->post_deblocking_output.bo,
 175                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 176                       0);
 177     else
 178         OUT_BCS_BATCH(batch, 0);
 179
 180     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 181     OUT_BCS_BATCH(batch, 0); /* ignore for decoding */
 182
 183     if (gen6_mfd_context->intra_row_store_scratch_buffer.valid)
 184         OUT_BCS_RELOC(batch, gen6_mfd_context->intra_row_store_scratch_buffer.bo,
 185                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 186                       0);
 187     else
 188         OUT_BCS_BATCH(batch, 0);
 189
 190     if (gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid)
 191         OUT_BCS_RELOC(batch, gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo,
 192                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 193                       0);
 194     else
 195         OUT_BCS_BATCH(batch, 0);
 196
 197     /* DW 7..22 */
 198     for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) {
 199         struct object_surface *obj_surface;
 200
 201         if (gen6_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
 202             gen6_mfd_context->reference_surface[i].obj_surface &&
 203             gen6_mfd_context->reference_surface[i].obj_surface->bo) {
 204             obj_surface = gen6_mfd_context->reference_surface[i].obj_surface;
 205
 206             OUT_BCS_RELOC(batch, obj_surface->bo,
 207                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 208                           0);
 209         } else {
 210             OUT_BCS_BATCH(batch, 0);
 211         }
 212     }
 213
 214     OUT_BCS_BATCH(batch, 0);   /* ignore DW23 for decoding */
 215     ADVANCE_BCS_BATCH(batch);
 216 }
 217
 218 static void
 219 gen6_mfd_ind_obj_base_addr_state(VADriverContextP ctx,
 220                                  dri_bo *slice_data_bo,
 221                                  int standard_select,
 222                                  struct gen6_mfd_context *gen6_mfd_context)
 223 {
 224     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 225
 226     BEGIN_BCS_BATCH(batch, 11);
 227     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
 228     OUT_BCS_RELOC(batch, slice_data_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); /* MFX Indirect Bitstream Object Base Address */
 229     OUT_BCS_BATCH(batch, 0);
 230     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 231     OUT_BCS_BATCH(batch, 0);
 232     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 233     OUT_BCS_BATCH(batch, 0);
 234     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 235     OUT_BCS_BATCH(batch, 0);
 236     OUT_BCS_BATCH(batch, 0); /* ignore for VLD mode */
 237     OUT_BCS_BATCH(batch, 0);
 238     ADVANCE_BCS_BATCH(batch);
 239 }
 240
 241 static void
 242 gen6_mfd_bsp_buf_base_addr_state(VADriverContextP ctx,
 243                                  struct decode_state *decode_state,
 244                                  int standard_select,
 245                                  struct gen6_mfd_context *gen6_mfd_context)
 246 {
 247     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 248
 249     BEGIN_BCS_BATCH(batch, 4);
 250     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
 251
 252     if (gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid)
 253         OUT_BCS_RELOC(batch, gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo,
 254                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 255                       0);
 256     else
 257         OUT_BCS_BATCH(batch, 0);
 258
 259     if (gen6_mfd_context->mpr_row_store_scratch_buffer.valid)
 260         OUT_BCS_RELOC(batch, gen6_mfd_context->mpr_row_store_scratch_buffer.bo,
 261                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 262                       0);
 263     else
 264         OUT_BCS_BATCH(batch, 0);
 265
 266     if (gen6_mfd_context->bitplane_read_buffer.valid)
 267         OUT_BCS_RELOC(batch, gen6_mfd_context->bitplane_read_buffer.bo,
 268                       I915_GEM_DOMAIN_INSTRUCTION, 0,
 269                       0);
 270     else
 271         OUT_BCS_BATCH(batch, 0);
 272
 273     ADVANCE_BCS_BATCH(batch);
 274 }
 275
 276 static void
 277 gen6_mfd_avc_img_state(VADriverContextP ctx,
 278                        struct decode_state *decode_state,
 279                        struct gen6_mfd_context *gen6_mfd_context)
 280 {
 281     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 282     int qm_present_flag;
 283     int img_struct;
 284     int mbaff_frame_flag;
 285     unsigned int width_in_mbs, height_in_mbs;
 286     VAPictureParameterBufferH264 *pic_param;
 287
 288     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 289     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 290
 291     if (decode_state->iq_matrix && decode_state->iq_matrix->buffer)
 292         qm_present_flag = 1;
 293     else
 294         qm_present_flag = 0; /* built-in QM matrices */
 295
 296     if (pic_param->CurrPic.flags & VA_PICTURE_H264_TOP_FIELD)
 297         img_struct = 1;
 298     else if (pic_param->CurrPic.flags & VA_PICTURE_H264_BOTTOM_FIELD)
 299         img_struct = 3;
 300     else
 301         img_struct = 0;
 302
 303     if ((img_struct & 0x1) == 0x1) {
 304         assert(pic_param->pic_fields.bits.field_pic_flag == 0x1);
 305     } else {
 306         assert(pic_param->pic_fields.bits.field_pic_flag == 0x0);
 307     }
 308
 309     if (pic_param->seq_fields.bits.frame_mbs_only_flag) { /* a frame containing only frame macroblocks */
 310         assert(pic_param->seq_fields.bits.mb_adaptive_frame_field_flag == 0);
 311         assert(pic_param->pic_fields.bits.field_pic_flag == 0);
 312     } else {
 313         assert(pic_param->seq_fields.bits.direct_8x8_inference_flag == 1); /* see H.264 spec */
 314     }
 315
 316     mbaff_frame_flag = (pic_param->seq_fields.bits.mb_adaptive_frame_field_flag &&
 317                         !pic_param->pic_fields.bits.field_pic_flag);
 318
 319     width_in_mbs = ((pic_param->picture_width_in_mbs_minus1 + 1) & 0xff);
 320     height_in_mbs = ((pic_param->picture_height_in_mbs_minus1 + 1) & 0xff); /* frame height */
 321     assert(!((width_in_mbs * height_in_mbs) & 0x8000)); /* hardware requirement */
 322
 323     /* MFX unit doesn't support 4:2:2 and 4:4:4 picture */
 324     assert(pic_param->seq_fields.bits.chroma_format_idc == 0 || /* monochrome picture */
 325            pic_param->seq_fields.bits.chroma_format_idc == 1);  /* 4:2:0 */
 326     assert(pic_param->seq_fields.bits.residual_colour_transform_flag == 0); /* only available for 4:4:4 */
 327
 328     BEGIN_BCS_BATCH(batch, 13);
 329     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (13 - 2));
 330     OUT_BCS_BATCH(batch,
 331                   ((width_in_mbs * height_in_mbs) & 0x7fff));
 332     OUT_BCS_BATCH(batch,
 333                   (height_in_mbs << 16) |
 334                   (width_in_mbs << 0));
 335     OUT_BCS_BATCH(batch,
 336                   ((pic_param->second_chroma_qp_index_offset & 0x1f) << 24) |
 337                   ((pic_param->chroma_qp_index_offset & 0x1f) << 16) |
 338                   (0 << 14) | /* Max-bit conformance Intra flag ??? FIXME */
 339                   (0 << 13) | /* Max Macroblock size conformance Inter flag ??? FIXME */
 340                   (1 << 12) | /* always 1, hardware requirement */
 341                   (qm_present_flag << 10) |
 342                   (img_struct << 8) |
 343                   (16 << 0));
 344     OUT_BCS_BATCH(batch,
 345                   (pic_param->seq_fields.bits.chroma_format_idc << 10) |
 346                   (pic_param->pic_fields.bits.entropy_coding_mode_flag << 7) |
 347                   ((!pic_param->pic_fields.bits.reference_pic_flag) << 6) |
 348                   (pic_param->pic_fields.bits.constrained_intra_pred_flag << 5) |
 349                   (pic_param->seq_fields.bits.direct_8x8_inference_flag << 4) |
 350                   (pic_param->pic_fields.bits.transform_8x8_mode_flag << 3) |
 351                   (pic_param->seq_fields.bits.frame_mbs_only_flag << 2) |
 352                   (mbaff_frame_flag << 1) |
 353                   (pic_param->pic_fields.bits.field_pic_flag << 0));
 354     OUT_BCS_BATCH(batch, 0);
 355     OUT_BCS_BATCH(batch, 0);
 356     OUT_BCS_BATCH(batch, 0);
 357     OUT_BCS_BATCH(batch, 0);
 358     OUT_BCS_BATCH(batch, 0);
 359     OUT_BCS_BATCH(batch, 0);
 360     OUT_BCS_BATCH(batch, 0);
 361     OUT_BCS_BATCH(batch, 0);
 362     ADVANCE_BCS_BATCH(batch);
 363 }
 364
 365 static void
 366 gen6_mfd_avc_qm_state(VADriverContextP ctx,
 367                       struct decode_state *decode_state,
 368                       struct gen6_mfd_context *gen6_mfd_context)
 369 {
 370     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 371     int cmd_len;
 372     VAIQMatrixBufferH264 *iq_matrix;
 373     VAPictureParameterBufferH264 *pic_param;
 374
 375     if (!decode_state->iq_matrix || !decode_state->iq_matrix->buffer)
 376         return;
 377
 378     iq_matrix = (VAIQMatrixBufferH264 *)decode_state->iq_matrix->buffer;
 379
 380     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 381     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 382
 383     cmd_len = 2 + 6 * 4; /* always load six 4x4 scaling matrices */
 384
 385     if (pic_param->pic_fields.bits.transform_8x8_mode_flag)
 386         cmd_len += 2 * 16; /* load two 8x8 scaling matrices */
 387
 388     BEGIN_BCS_BATCH(batch, cmd_len);
 389     OUT_BCS_BATCH(batch, MFX_AVC_QM_STATE | (cmd_len - 2));
 390
 391     if (pic_param->pic_fields.bits.transform_8x8_mode_flag)
 392         OUT_BCS_BATCH(batch,
 393                       (0x0  << 8) | /* don't use default built-in matrices */
 394                       (0xff << 0)); /* six 4x4 and two 8x8 scaling matrices */
 395     else
 396         OUT_BCS_BATCH(batch,
 397                       (0x0  << 8) | /* don't use default built-in matrices */
 398                       (0x3f << 0)); /* six 4x4 scaling matrices */
 399
 400     intel_batchbuffer_data(batch, &iq_matrix->ScalingList4x4[0][0], 6 * 4 * 4);
 401
 402     if (pic_param->pic_fields.bits.transform_8x8_mode_flag)
 403         intel_batchbuffer_data(batch, &iq_matrix->ScalingList8x8[0][0], 2 * 16 * 4);
 404
 405     ADVANCE_BCS_BATCH(batch);
 406 }
 407
 408 static void
 409 gen6_mfd_avc_directmode_state(VADriverContextP ctx,
 410                               struct decode_state *decode_state,
 411                               VAPictureParameterBufferH264 *pic_param,
 412                               VASliceParameterBufferH264 *slice_param,
 413                               struct gen6_mfd_context *gen6_mfd_context)
 414 {
 415     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 416     struct object_surface *obj_surface;
 417     GenAvcSurface *gen6_avc_surface;
 418     VAPictureH264 *va_pic;
 419     int i, j;
 420
 421     BEGIN_BCS_BATCH(batch, 69);
 422     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
 423
 424     /* reference surfaces 0..15 */
 425     for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) {
 426         if (gen6_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID &&
 427             gen6_mfd_context->reference_surface[i].obj_surface &&
 428             gen6_mfd_context->reference_surface[i].obj_surface->private_data) {
 429
 430             obj_surface = gen6_mfd_context->reference_surface[i].obj_surface;
 431             gen6_avc_surface = obj_surface->private_data;
 432             OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top,
 433                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 434                           0);
 435
 436             if (gen6_avc_surface->dmv_bottom_flag == 1)
 437                 OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_bottom,
 438                               I915_GEM_DOMAIN_INSTRUCTION, 0,
 439                               0);
 440             else
 441                 OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top,
 442                               I915_GEM_DOMAIN_INSTRUCTION, 0,
 443                               0);
 444         } else {
 445             OUT_BCS_BATCH(batch, 0);
 446             OUT_BCS_BATCH(batch, 0);
 447         }
 448     }
 449
 450     /* the current decoding frame/field */
 451     va_pic = &pic_param->CurrPic;
 452     obj_surface = decode_state->render_object;
 453     assert(obj_surface->bo && obj_surface->private_data);
 454     gen6_avc_surface = obj_surface->private_data;
 455
 456     OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top,
 457                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 458                   0);
 459
 460     if (gen6_avc_surface->dmv_bottom_flag == 1)
 461         OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_bottom,
 462                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 463                       0);
 464     else
 465         OUT_BCS_RELOC(batch, gen6_avc_surface->dmv_top,
 466                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 467                       0);
 468
 469     /* POC List */
 470     for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) {
 471         if (gen6_mfd_context->reference_surface[i].surface_id != VA_INVALID_ID) {
 472             int found = 0;
 473
 474             assert(gen6_mfd_context->reference_surface[i].obj_surface != NULL);
 475
 476             for (j = 0; j < ARRAY_ELEMS(pic_param->ReferenceFrames); j++) {
 477                 va_pic = &pic_param->ReferenceFrames[j];
 478
 479                 if (va_pic->flags & VA_PICTURE_H264_INVALID)
 480                     continue;
 481
 482                 if (va_pic->picture_id == gen6_mfd_context->reference_surface[i].surface_id) {
 483                     found = 1;
 484                     break;
 485                 }
 486             }
 487
 488             assert(found == 1);
 489             assert(!(va_pic->flags & VA_PICTURE_H264_INVALID));
 490
 491             OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
 492             OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
 493         } else {
 494             OUT_BCS_BATCH(batch, 0);
 495             OUT_BCS_BATCH(batch, 0);
 496         }
 497     }
 498
 499     va_pic = &pic_param->CurrPic;
 500     OUT_BCS_BATCH(batch, va_pic->TopFieldOrderCnt);
 501     OUT_BCS_BATCH(batch, va_pic->BottomFieldOrderCnt);
 502
 503     ADVANCE_BCS_BATCH(batch);
 504 }
 505
 506 static void
 507 gen6_mfd_avc_slice_state(VADriverContextP ctx,
 508                          VAPictureParameterBufferH264 *pic_param,
 509                          VASliceParameterBufferH264 *slice_param,
 510                          VASliceParameterBufferH264 *next_slice_param,
 511                          struct gen6_mfd_context *gen6_mfd_context)
 512 {
 513     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 514     int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 515     int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1;
 516     int slice_hor_pos, slice_ver_pos, next_slice_hor_pos, next_slice_ver_pos;
 517     int num_ref_idx_l0, num_ref_idx_l1;
 518     int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag &&
 519                          pic_param->seq_fields.bits.mb_adaptive_frame_field_flag);
 520     int weighted_pred_idc = 0;
 521     int first_mb_in_slice = 0, first_mb_in_next_slice = 0;
 522     unsigned int chroma_log2_weight_denom, luma_log2_weight_denom;
 523     int slice_type;
 524
 525     if (slice_param->slice_type == SLICE_TYPE_I ||
 526         slice_param->slice_type == SLICE_TYPE_SI) {
 527         slice_type = SLICE_TYPE_I;
 528     } else if (slice_param->slice_type == SLICE_TYPE_P ||
 529                slice_param->slice_type == SLICE_TYPE_SP) {
 530         slice_type = SLICE_TYPE_P;
 531     } else {
 532         assert(slice_param->slice_type == SLICE_TYPE_B);
 533         slice_type = SLICE_TYPE_B;
 534     }
 535
 536     luma_log2_weight_denom   = slice_param->luma_log2_weight_denom;
 537     chroma_log2_weight_denom = slice_param->chroma_log2_weight_denom;
 538
 539     if (slice_type == SLICE_TYPE_I) {
 540         assert(slice_param->num_ref_idx_l0_active_minus1 == 0);
 541         assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
 542         num_ref_idx_l0 = 0;
 543         num_ref_idx_l1 = 0;
 544     } else if (slice_type == SLICE_TYPE_P) {
 545         assert(slice_param->num_ref_idx_l1_active_minus1 == 0);
 546         num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
 547         num_ref_idx_l1 = 0;
 548         weighted_pred_idc = (pic_param->pic_fields.bits.weighted_pred_flag == 1);
 549     } else {
 550         num_ref_idx_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
 551         num_ref_idx_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
 552         weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc;
 553
 554         if (weighted_pred_idc == 2) {
 555             /* 8.4.3 - Derivation process for prediction weights (8-279) */
 556             luma_log2_weight_denom   = 5;
 557             chroma_log2_weight_denom = 5;
 558         }
 559     }
 560
 561     first_mb_in_slice = slice_param->first_mb_in_slice << mbaff_picture;
 562     slice_hor_pos = first_mb_in_slice % width_in_mbs;
 563     slice_ver_pos = first_mb_in_slice / width_in_mbs;
 564
 565     if (next_slice_param) {
 566         first_mb_in_next_slice = next_slice_param->first_mb_in_slice << mbaff_picture;
 567         next_slice_hor_pos = first_mb_in_next_slice % width_in_mbs;
 568         next_slice_ver_pos = first_mb_in_next_slice / width_in_mbs;
 569     } else {
 570         next_slice_hor_pos = 0;
 571         next_slice_ver_pos = height_in_mbs;
 572     }
 573
 574     BEGIN_BCS_BATCH(batch, 11); /* FIXME: is it 10??? */
 575     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
 576     OUT_BCS_BATCH(batch, slice_type);
 577     OUT_BCS_BATCH(batch,
 578                   (num_ref_idx_l1 << 24) |
 579                   (num_ref_idx_l0 << 16) |
 580                   (chroma_log2_weight_denom << 8) |
 581                   (luma_log2_weight_denom << 0));
 582     OUT_BCS_BATCH(batch,
 583                   (weighted_pred_idc << 30) |
 584                   (slice_param->direct_spatial_mv_pred_flag << 29) |
 585                   (slice_param->disable_deblocking_filter_idc << 27) |
 586                   (slice_param->cabac_init_idc << 24) |
 587                   ((pic_param->pic_init_qp_minus26 + 26 + slice_param->slice_qp_delta) << 16) |
 588                   ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
 589                   ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
 590     OUT_BCS_BATCH(batch,
 591                   (slice_ver_pos << 24) |
 592                   (slice_hor_pos << 16) |
 593                   (first_mb_in_slice << 0));
 594     OUT_BCS_BATCH(batch,
 595                   (next_slice_ver_pos << 16) |
 596                   (next_slice_hor_pos << 0));
 597     OUT_BCS_BATCH(batch,
 598                   (next_slice_param == NULL) << 19); /* last slice flag */
 599     OUT_BCS_BATCH(batch, 0);
 600     OUT_BCS_BATCH(batch, 0);
 601     OUT_BCS_BATCH(batch, 0);
 602     OUT_BCS_BATCH(batch, 0);
 603     ADVANCE_BCS_BATCH(batch);
 604 }
 605
 606 static void
 607 gen6_mfd_avc_phantom_slice_state(VADriverContextP ctx,
 608                                  VAPictureParameterBufferH264 *pic_param,
 609                                  VASliceParameterBufferH264 *next_slice_param,
 610                                  struct gen6_mfd_context *gen6_mfd_context)
 611 {
 612     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 613     int width_in_mbs = pic_param->picture_width_in_mbs_minus1 + 1;
 614     int height_in_mbs = pic_param->picture_height_in_mbs_minus1 + 1; /* frame height */
 615     int slice_hor_pos, slice_ver_pos, slice_start_mb_num, next_slice_hor_pos, next_slice_ver_pos;
 616     int mbaff_picture = (!pic_param->pic_fields.bits.field_pic_flag &&
 617                          pic_param->seq_fields.bits.mb_adaptive_frame_field_flag);
 618
 619     if (next_slice_param) {
 620         int first_mb_in_next_slice;
 621
 622         slice_hor_pos = 0;
 623         slice_ver_pos = 0;
 624         slice_start_mb_num = 0;
 625         first_mb_in_next_slice = next_slice_param->first_mb_in_slice << mbaff_picture;
 626         next_slice_hor_pos = first_mb_in_next_slice % width_in_mbs;
 627         next_slice_ver_pos = first_mb_in_next_slice / width_in_mbs;
 628     } else {
 629         slice_hor_pos = 0;
 630         slice_ver_pos = height_in_mbs;
 631         slice_start_mb_num = width_in_mbs * height_in_mbs / (1 + !!pic_param->pic_fields.bits.field_pic_flag);
 632         next_slice_hor_pos = 0;
 633         next_slice_ver_pos = 0;
 634     }
 635
 636     BEGIN_BCS_BATCH(batch, 11); /* FIXME: is it 10??? */
 637     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2));
 638     OUT_BCS_BATCH(batch, 0);
 639     OUT_BCS_BATCH(batch, 0);
 640     OUT_BCS_BATCH(batch, 0);
 641     OUT_BCS_BATCH(batch,
 642                   slice_ver_pos << 24 |
 643                   slice_hor_pos << 16 |
 644                   slice_start_mb_num << 0);
 645     OUT_BCS_BATCH(batch,
 646                   next_slice_ver_pos << 16 |
 647                   next_slice_hor_pos << 0);
 648     OUT_BCS_BATCH(batch, 0);
 649     OUT_BCS_BATCH(batch, 0);
 650     OUT_BCS_BATCH(batch, 0);
 651     OUT_BCS_BATCH(batch, 0);
 652     OUT_BCS_BATCH(batch, 0);
 653     ADVANCE_BCS_BATCH(batch);
 654 }
 655
 656 static inline void
 657 gen6_mfd_avc_ref_idx_state(VADriverContextP ctx,
 658                            VAPictureParameterBufferH264 *pic_param,
 659                            VASliceParameterBufferH264 *slice_param,
 660                            struct gen6_mfd_context *gen6_mfd_context)
 661 {
 662     gen6_send_avc_ref_idx_state(
 663         gen6_mfd_context->base.batch,
 664         slice_param,
 665         gen6_mfd_context->reference_surface
 666     );
 667 }
 668
 669 static void
 670 gen6_mfd_avc_weightoffset_state(VADriverContextP ctx,
 671                                 VAPictureParameterBufferH264 *pic_param,
 672                                 VASliceParameterBufferH264 *slice_param,
 673                                 struct gen6_mfd_context *gen6_mfd_context)
 674 {
 675     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 676     int i, j, num_weight_offset_table = 0;
 677     short weightoffsets[32 * 6];
 678
 679     if ((slice_param->slice_type == SLICE_TYPE_P ||
 680          slice_param->slice_type == SLICE_TYPE_SP) &&
 681         (pic_param->pic_fields.bits.weighted_pred_flag == 1)) {
 682         num_weight_offset_table = 1;
 683     }
 684
 685     if ((slice_param->slice_type == SLICE_TYPE_B) &&
 686         (pic_param->pic_fields.bits.weighted_bipred_idc == 1)) {
 687         num_weight_offset_table = 2;
 688     }
 689
 690     for (i = 0; i < num_weight_offset_table; i++) {
 691         BEGIN_BCS_BATCH(batch, 98);
 692         OUT_BCS_BATCH(batch, MFX_AVC_WEIGHTOFFSET_STATE | (98 - 2));
 693         OUT_BCS_BATCH(batch, i);
 694
 695         if (i == 0) {
 696             for (j = 0; j < 32; j++) {
 697                 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l0[j];
 698                 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l0[j];
 699                 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l0[j][0];
 700                 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l0[j][0];
 701                 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l0[j][1];
 702                 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l0[j][1];
 703             }
 704         } else {
 705             for (j = 0; j < 32; j++) {
 706                 weightoffsets[j * 6 + 0] = slice_param->luma_weight_l1[j];
 707                 weightoffsets[j * 6 + 1] = slice_param->luma_offset_l1[j];
 708                 weightoffsets[j * 6 + 2] = slice_param->chroma_weight_l1[j][0];
 709                 weightoffsets[j * 6 + 3] = slice_param->chroma_offset_l1[j][0];
 710                 weightoffsets[j * 6 + 4] = slice_param->chroma_weight_l1[j][1];
 711                 weightoffsets[j * 6 + 5] = slice_param->chroma_offset_l1[j][1];
 712             }
 713         }
 714
 715         intel_batchbuffer_data(batch, weightoffsets, sizeof(weightoffsets));
 716         ADVANCE_BCS_BATCH(batch);
 717     }
 718 }
 719
 720 static void
 721 gen6_mfd_avc_bsd_object(VADriverContextP ctx,
 722                         VAPictureParameterBufferH264 *pic_param,
 723                         VASliceParameterBufferH264 *slice_param,
 724                         dri_bo *slice_data_bo,
 725                         struct gen6_mfd_context *gen6_mfd_context)
 726 {
 727     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 728     unsigned int slice_data_bit_offset;
 729
 730     slice_data_bit_offset = avc_get_first_mb_bit_offset(
 731         slice_data_bo,
 732         slice_param,
 733         pic_param->pic_fields.bits.entropy_coding_mode_flag
 734     );
 735
 736     BEGIN_BCS_BATCH(batch, 6);
 737     OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
 738     OUT_BCS_BATCH(batch,
 739                   (slice_param->slice_data_size - slice_param->slice_data_offset));
 740     OUT_BCS_BATCH(batch, slice_param->slice_data_offset);
 741     OUT_BCS_BATCH(batch,
 742                   (0 << 31) |
 743                   (0 << 14) |
 744                   (0 << 12) |
 745                   (0 << 10) |
 746                   (0 << 8));
 747     OUT_BCS_BATCH(batch,
 748                   ((slice_data_bit_offset >> 3) << 16) |
 749                   (1 << 7)  |
 750                   (1 << 6)  |
 751                   ((0x7 - (slice_data_bit_offset & 0x7)) << 0));
 752     OUT_BCS_BATCH(batch, 0);
 753     ADVANCE_BCS_BATCH(batch);
 754 }
 755
 756 static void
 757 gen6_mfd_avc_phantom_slice_bsd_object(VADriverContextP ctx,
 758                                       VAPictureParameterBufferH264 *pic_param,
 759                                       struct gen6_mfd_context *gen6_mfd_context)
 760 {
 761     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 762
 763     BEGIN_BCS_BATCH(batch, 6);
 764     OUT_BCS_BATCH(batch, MFD_AVC_BSD_OBJECT | (6 - 2));
 765     OUT_BCS_BATCH(batch, 0);
 766     OUT_BCS_BATCH(batch, 0);
 767     OUT_BCS_BATCH(batch, 0);
 768     OUT_BCS_BATCH(batch, 0);
 769     OUT_BCS_BATCH(batch, 0);
 770     ADVANCE_BCS_BATCH(batch);
 771 }
 772
 773 static void
 774 gen6_mfd_avc_phantom_slice(VADriverContextP ctx,
 775                            VAPictureParameterBufferH264 *pic_param,
 776                            VASliceParameterBufferH264 *next_slice_param,
 777                            struct gen6_mfd_context *gen6_mfd_context)
 778 {
 779     gen6_mfd_avc_phantom_slice_state(ctx, pic_param, next_slice_param, gen6_mfd_context);
 780     gen6_mfd_avc_phantom_slice_bsd_object(ctx, pic_param, gen6_mfd_context);
 781 }
 782
 783 static void
 784 gen6_mfd_avc_phantom_slice_first(VADriverContextP ctx,
 785                                  VAPictureParameterBufferH264 *pic_param,
 786                                  VASliceParameterBufferH264 *next_slice_param,
 787                                  struct gen6_mfd_context *gen6_mfd_context)
 788 {
 789     gen6_mfd_avc_phantom_slice(ctx, pic_param, next_slice_param, gen6_mfd_context);
 790 }
 791
 792 static void
 793 gen6_mfd_avc_phantom_slice_last(VADriverContextP ctx,
 794                                 VAPictureParameterBufferH264 *pic_param,
 795                                 struct gen6_mfd_context *gen6_mfd_context)
 796 {
 797     gen6_mfd_avc_phantom_slice(ctx, pic_param, NULL, gen6_mfd_context);
 798 }
 799
 800 static void
 801 gen6_mfd_avc_decode_init(VADriverContextP ctx,
 802                          struct decode_state *decode_state,
 803                          struct gen6_mfd_context *gen6_mfd_context)
 804 {
 805     VAPictureParameterBufferH264 *pic_param;
 806     VASliceParameterBufferH264 *slice_param;
 807     struct i965_driver_data *i965 = i965_driver_data(ctx);
 808     struct object_surface *obj_surface;
 809     dri_bo *bo;
 810     int i, j, enable_avc_ildb = 0;
 811     int width_in_mbs;
 812
 813     for (j = 0; j < decode_state->num_slice_params && enable_avc_ildb == 0; j++) {
 814         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
 815         slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
 816
 817         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
 818             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
 819             assert((slice_param->slice_type == SLICE_TYPE_I) ||
 820                    (slice_param->slice_type == SLICE_TYPE_SI) ||
 821                    (slice_param->slice_type == SLICE_TYPE_P) ||
 822                    (slice_param->slice_type == SLICE_TYPE_SP) ||
 823                    (slice_param->slice_type == SLICE_TYPE_B));
 824
 825             if (slice_param->disable_deblocking_filter_idc != 1) {
 826                 enable_avc_ildb = 1;
 827                 break;
 828             }
 829
 830             slice_param++;
 831         }
 832     }
 833
 834     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 835     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 836     intel_update_avc_frame_store_index(ctx, decode_state, pic_param, gen6_mfd_context->reference_surface);
 837     width_in_mbs = ((pic_param->picture_width_in_mbs_minus1 + 1) & 0xff);
 838
 839     /* Current decoded picture */
 840     obj_surface = decode_state->render_object;
 841     obj_surface->flags &= ~SURFACE_REF_DIS_MASK;
 842     obj_surface->flags |= (pic_param->pic_fields.bits.reference_pic_flag ? SURFACE_REFERENCED : 0);
 843     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
 844
 845     /* initial uv component for YUV400 case */
 846     if (pic_param->seq_fields.bits.chroma_format_idc == 0) {
 847          unsigned int uv_offset = obj_surface->width * obj_surface->height;
 848          unsigned int uv_size   = obj_surface->width * obj_surface->height / 2;
 849
 850          drm_intel_gem_bo_map_gtt(obj_surface->bo);
 851          memset(obj_surface->bo->virtual + uv_offset, 0x80, uv_size);
 852          drm_intel_gem_bo_unmap_gtt(obj_surface->bo);
 853     }
 854
 855     gen6_mfd_init_avc_surface(ctx, pic_param, obj_surface);
 856
 857     dri_bo_unreference(gen6_mfd_context->post_deblocking_output.bo);
 858     gen6_mfd_context->post_deblocking_output.bo = obj_surface->bo;
 859     dri_bo_reference(gen6_mfd_context->post_deblocking_output.bo);
 860     gen6_mfd_context->post_deblocking_output.valid = enable_avc_ildb;
 861
 862     dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo);
 863     gen6_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
 864     dri_bo_reference(gen6_mfd_context->pre_deblocking_output.bo);
 865     gen6_mfd_context->pre_deblocking_output.valid = !enable_avc_ildb;
 866
 867     dri_bo_unreference(gen6_mfd_context->intra_row_store_scratch_buffer.bo);
 868     bo = dri_bo_alloc(i965->intel.bufmgr,
 869                       "intra row store",
 870                       width_in_mbs * 64,
 871                       0x1000);
 872     assert(bo);
 873     gen6_mfd_context->intra_row_store_scratch_buffer.bo = bo;
 874     gen6_mfd_context->intra_row_store_scratch_buffer.valid = 1;
 875
 876     dri_bo_unreference(gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
 877     bo = dri_bo_alloc(i965->intel.bufmgr,
 878                       "deblocking filter row store",
 879                       width_in_mbs * 64 * 4,
 880                       0x1000);
 881     assert(bo);
 882     gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
 883     gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
 884
 885     dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
 886     bo = dri_bo_alloc(i965->intel.bufmgr,
 887                       "bsd mpc row store",
 888                       width_in_mbs * 96,
 889                       0x1000);
 890     assert(bo);
 891     gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
 892     gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
 893
 894     dri_bo_unreference(gen6_mfd_context->mpr_row_store_scratch_buffer.bo);
 895     bo = dri_bo_alloc(i965->intel.bufmgr,
 896                       "mpr row store",
 897                       width_in_mbs * 64,
 898                       0x1000);
 899     assert(bo);
 900     gen6_mfd_context->mpr_row_store_scratch_buffer.bo = bo;
 901     gen6_mfd_context->mpr_row_store_scratch_buffer.valid = 1;
 902
 903     gen6_mfd_context->bitplane_read_buffer.valid = 0;
 904 }
 905
 906 static void
 907 gen6_mfd_avc_decode_picture(VADriverContextP ctx,
 908                             struct decode_state *decode_state,
 909                             struct gen6_mfd_context *gen6_mfd_context)
 910 {
 911     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
 912     VAPictureParameterBufferH264 *pic_param;
 913     VASliceParameterBufferH264 *slice_param, *next_slice_param, *next_slice_group_param;
 914     dri_bo *slice_data_bo;
 915     int i, j;
 916
 917     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 918     pic_param = (VAPictureParameterBufferH264 *)decode_state->pic_param->buffer;
 919     gen6_mfd_avc_decode_init(ctx, decode_state, gen6_mfd_context);
 920
 921     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
 922     intel_batchbuffer_emit_mi_flush(batch);
 923     gen6_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context);
 924     gen6_mfd_surface_state(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context);
 925     gen6_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context);
 926     gen6_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_AVC, gen6_mfd_context);
 927     gen6_mfd_avc_img_state(ctx, decode_state, gen6_mfd_context);
 928     gen6_mfd_avc_qm_state(ctx, decode_state, gen6_mfd_context);
 929
 930     for (j = 0; j < decode_state->num_slice_params; j++) {
 931         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
 932         slice_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j]->buffer;
 933         slice_data_bo = decode_state->slice_datas[j]->bo;
 934         gen6_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_AVC, gen6_mfd_context);
 935
 936         if (j == decode_state->num_slice_params - 1)
 937             next_slice_group_param = NULL;
 938         else
 939             next_slice_group_param = (VASliceParameterBufferH264 *)decode_state->slice_params[j + 1]->buffer;
 940
 941             if (j == 0 &&
 942                 slice_param->first_mb_in_slice)
 943                 gen6_mfd_avc_phantom_slice_first(ctx, pic_param, slice_param, gen6_mfd_context);
 944
 945         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
 946             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
 947             assert((slice_param->slice_type == SLICE_TYPE_I) ||
 948                    (slice_param->slice_type == SLICE_TYPE_SI) ||
 949                    (slice_param->slice_type == SLICE_TYPE_P) ||
 950                    (slice_param->slice_type == SLICE_TYPE_SP) ||
 951                    (slice_param->slice_type == SLICE_TYPE_B));
 952
 953             if (i < decode_state->slice_params[j]->num_elements - 1)
 954                 next_slice_param = slice_param + 1;
 955             else
 956                 next_slice_param = next_slice_group_param;
 957
 958             gen6_mfd_avc_directmode_state(ctx, decode_state, pic_param, slice_param, gen6_mfd_context);
 959             gen6_mfd_avc_slice_state(ctx, pic_param, slice_param, next_slice_param, gen6_mfd_context);
 960             gen6_mfd_avc_ref_idx_state(ctx, pic_param, slice_param, gen6_mfd_context);
 961             gen6_mfd_avc_weightoffset_state(ctx, pic_param, slice_param, gen6_mfd_context);
 962             gen6_mfd_avc_bsd_object(ctx, pic_param, slice_param, slice_data_bo, gen6_mfd_context);
 963             slice_param++;
 964         }
 965     }
 966
 967     gen6_mfd_avc_phantom_slice_last(ctx, pic_param, gen6_mfd_context);
 968     intel_batchbuffer_end_atomic(batch);
 969     intel_batchbuffer_flush(batch);
 970 }
 971
 972 static void
 973 gen6_mfd_mpeg2_decode_init(VADriverContextP ctx,
 974                            struct decode_state *decode_state,
 975                            struct gen6_mfd_context *gen6_mfd_context)
 976 {
 977     VAPictureParameterBufferMPEG2 *pic_param;
 978     struct i965_driver_data *i965 = i965_driver_data(ctx);
 979     struct object_surface *obj_surface;
 980     dri_bo *bo;
 981     unsigned int width_in_mbs;
 982
 983     assert(decode_state->pic_param && decode_state->pic_param->buffer);
 984     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
 985     width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
 986
 987     mpeg2_set_reference_surfaces(
 988         ctx,
 989         gen6_mfd_context->reference_surface,
 990         decode_state,
 991         pic_param
 992     );
 993
 994     /* Current decoded picture */
 995     obj_surface = decode_state->render_object;
 996     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
 997
 998     dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo);
 999     gen6_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1000     dri_bo_reference(gen6_mfd_context->pre_deblocking_output.bo);
1001     gen6_mfd_context->pre_deblocking_output.valid = 1;
1002
1003     dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1004     bo = dri_bo_alloc(i965->intel.bufmgr,
1005                       "bsd mpc row store",
1006                       width_in_mbs * 96,
1007                       0x1000);
1008     assert(bo);
1009     gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1010     gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1011
1012     gen6_mfd_context->post_deblocking_output.valid = 0;
1013     gen6_mfd_context->intra_row_store_scratch_buffer.valid = 0;
1014     gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 0;
1015     gen6_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1016     gen6_mfd_context->bitplane_read_buffer.valid = 0;
1017 }
1018
1019 static void
1020 gen6_mfd_mpeg2_pic_state(VADriverContextP ctx,
1021                          struct decode_state *decode_state,
1022                          struct gen6_mfd_context *gen6_mfd_context)
1023 {
1024     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1025     VAPictureParameterBufferMPEG2 *pic_param;
1026     unsigned int tff, pic_structure;
1027
1028     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1029     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1030
1031     pic_structure = pic_param->picture_coding_extension.bits.picture_structure;
1032     if (pic_structure == MPEG_FRAME)
1033         tff = pic_param->picture_coding_extension.bits.top_field_first;
1034     else
1035         tff = !(pic_param->picture_coding_extension.bits.is_first_field ^
1036                 (pic_structure & MPEG_TOP_FIELD));
1037
1038     BEGIN_BCS_BATCH(batch, 4);
1039     OUT_BCS_BATCH(batch, MFX_MPEG2_PIC_STATE | (4 - 2));
1040     OUT_BCS_BATCH(batch,
1041                   (pic_param->f_code & 0xf) << 28 | /* f_code[1][1] */
1042                   ((pic_param->f_code >> 4) & 0xf) << 24 | /* f_code[1][0] */
1043                   ((pic_param->f_code >> 8) & 0xf) << 20 | /* f_code[0][1] */
1044                   ((pic_param->f_code >> 12) & 0xf) << 16 | /* f_code[0][0] */
1045                   pic_param->picture_coding_extension.bits.intra_dc_precision << 14 |
1046                   pic_param->picture_coding_extension.bits.picture_structure << 12 |
1047                   tff << 11 |
1048                   pic_param->picture_coding_extension.bits.frame_pred_frame_dct << 10 |
1049                   pic_param->picture_coding_extension.bits.concealment_motion_vectors << 9 |
1050                   pic_param->picture_coding_extension.bits.q_scale_type << 8 |
1051                   pic_param->picture_coding_extension.bits.intra_vlc_format << 7 |
1052                   pic_param->picture_coding_extension.bits.alternate_scan << 6);
1053     OUT_BCS_BATCH(batch,
1054                   pic_param->picture_coding_type << 9);
1055     OUT_BCS_BATCH(batch,
1056                   (ALIGN(pic_param->vertical_size, 16) / 16) << 16 |
1057                   (ALIGN(pic_param->horizontal_size, 16) / 16));
1058     ADVANCE_BCS_BATCH(batch);
1059 }
1060
1061 static void
1062 gen6_mfd_mpeg2_qm_state(VADriverContextP ctx,
1063                         struct decode_state *decode_state,
1064                         struct gen6_mfd_context *gen6_mfd_context)
1065 {
1066     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1067     VAIQMatrixBufferMPEG2 * const gen_iq_matrix = &gen6_mfd_context->iq_matrix.mpeg2;
1068     int i, j;
1069
1070     /* Update internal QM state */
1071     if (decode_state->iq_matrix && decode_state->iq_matrix->buffer) {
1072         VAIQMatrixBufferMPEG2 * const iq_matrix =
1073             (VAIQMatrixBufferMPEG2 *)decode_state->iq_matrix->buffer;
1074
1075         gen_iq_matrix->load_intra_quantiser_matrix =
1076             iq_matrix->load_intra_quantiser_matrix;
1077         if (iq_matrix->load_intra_quantiser_matrix) {
1078             for (j = 0; j < 64; j++)
1079                 gen_iq_matrix->intra_quantiser_matrix[zigzag_direct[j]] =
1080                     iq_matrix->intra_quantiser_matrix[j];
1081         }
1082
1083         gen_iq_matrix->load_non_intra_quantiser_matrix =
1084             iq_matrix->load_non_intra_quantiser_matrix;
1085         if (iq_matrix->load_non_intra_quantiser_matrix) {
1086             for (j = 0; j < 64; j++)
1087                 gen_iq_matrix->non_intra_quantiser_matrix[zigzag_direct[j]] =
1088                     iq_matrix->non_intra_quantiser_matrix[j];
1089         }
1090     }
1091
1092     /* Commit QM state to HW */
1093     for (i = 0; i < 2; i++) {
1094         unsigned char *qm = NULL;
1095
1096         if (i == 0) {
1097             if (gen_iq_matrix->load_intra_quantiser_matrix)
1098                 qm = gen_iq_matrix->intra_quantiser_matrix;
1099         } else {
1100             if (gen_iq_matrix->load_non_intra_quantiser_matrix)
1101                 qm = gen_iq_matrix->non_intra_quantiser_matrix;
1102         }
1103
1104         if (!qm)
1105             continue;
1106
1107         BEGIN_BCS_BATCH(batch, 18);
1108         OUT_BCS_BATCH(batch, MFX_MPEG2_QM_STATE | (18 - 2));
1109         OUT_BCS_BATCH(batch, i);
1110         intel_batchbuffer_data(batch, qm, 64);
1111         ADVANCE_BCS_BATCH(batch);
1112     }
1113 }
1114
1115 static void
1116 gen6_mfd_mpeg2_bsd_object(VADriverContextP ctx,
1117                           VAPictureParameterBufferMPEG2 *pic_param,
1118                           VASliceParameterBufferMPEG2 *slice_param,
1119                           VASliceParameterBufferMPEG2 *next_slice_param,
1120                           struct gen6_mfd_context *gen6_mfd_context)
1121 {
1122     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1123     unsigned int width_in_mbs = ALIGN(pic_param->horizontal_size, 16) / 16;
1124     int mb_count, vpos0, hpos0, vpos1, hpos1, is_field_pic_wa, is_field_pic = 0;
1125
1126     if (pic_param->picture_coding_extension.bits.picture_structure == MPEG_TOP_FIELD ||
1127         pic_param->picture_coding_extension.bits.picture_structure == MPEG_BOTTOM_FIELD)
1128         is_field_pic = 1;
1129     is_field_pic_wa = is_field_pic &&
1130         gen6_mfd_context->wa_mpeg2_slice_vertical_position > 0;
1131
1132     vpos0 = slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1133     hpos0 = slice_param->slice_horizontal_position;
1134
1135     if (next_slice_param == NULL) {
1136         vpos1 = ALIGN(pic_param->vertical_size, 16) / 16 / (1 + is_field_pic);
1137         hpos1 = 0;
1138     } else {
1139         vpos1 = next_slice_param->slice_vertical_position / (1 + is_field_pic_wa);
1140         hpos1 = next_slice_param->slice_horizontal_position;
1141     }
1142
1143     mb_count = (vpos1 * width_in_mbs + hpos1) - (vpos0 * width_in_mbs + hpos0);
1144
1145     BEGIN_BCS_BATCH(batch, 5);
1146     OUT_BCS_BATCH(batch, MFD_MPEG2_BSD_OBJECT | (5 - 2));
1147     OUT_BCS_BATCH(batch,
1148                   slice_param->slice_data_size - (slice_param->macroblock_offset >> 3));
1149     OUT_BCS_BATCH(batch,
1150                   slice_param->slice_data_offset + (slice_param->macroblock_offset >> 3));
1151     OUT_BCS_BATCH(batch,
1152                   hpos0 << 24 |
1153                   vpos0 << 16 |
1154                   mb_count << 8 |
1155                   (next_slice_param == NULL) << 5 |
1156                   (next_slice_param == NULL) << 3 |
1157                   (slice_param->macroblock_offset & 0x7));
1158     OUT_BCS_BATCH(batch,
1159                   slice_param->quantiser_scale_code << 24);
1160     ADVANCE_BCS_BATCH(batch);
1161 }
1162
1163 static void
1164 gen6_mfd_mpeg2_decode_picture(VADriverContextP ctx,
1165                               struct decode_state *decode_state,
1166                               struct gen6_mfd_context *gen6_mfd_context)
1167 {
1168     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1169     VAPictureParameterBufferMPEG2 *pic_param;
1170     VASliceParameterBufferMPEG2 *slice_param, *next_slice_param;
1171     dri_bo *slice_data_bo;
1172     int group_idx = 0, pre_group_idx = -1, element_idx = 0;
1173
1174     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1175     pic_param = (VAPictureParameterBufferMPEG2 *)decode_state->pic_param->buffer;
1176
1177     gen6_mfd_mpeg2_decode_init(ctx, decode_state, gen6_mfd_context);
1178     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1179     intel_batchbuffer_emit_mi_flush(batch);
1180     gen6_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context);
1181     gen6_mfd_surface_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context);
1182     gen6_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context);
1183     gen6_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_MPEG2, gen6_mfd_context);
1184     gen6_mfd_mpeg2_pic_state(ctx, decode_state, gen6_mfd_context);
1185     gen6_mfd_mpeg2_qm_state(ctx, decode_state, gen6_mfd_context);
1186
1187     if (gen6_mfd_context->wa_mpeg2_slice_vertical_position < 0)
1188         gen6_mfd_context->wa_mpeg2_slice_vertical_position =
1189             mpeg2_wa_slice_vertical_position(decode_state, pic_param);
1190
1191     slice_param = (VASliceParameterBufferMPEG2 *)decode_state->slice_params[group_idx]->buffer;
1192
1193     for (; slice_param;) {
1194         if (pre_group_idx != group_idx) {
1195             slice_data_bo = decode_state->slice_datas[group_idx]->bo;
1196             gen6_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_MPEG2, gen6_mfd_context);
1197             pre_group_idx = group_idx;
1198         }
1199
1200         next_slice_param = intel_mpeg2_find_next_slice(decode_state, pic_param, slice_param, &group_idx, &element_idx);
1201         gen6_mfd_mpeg2_bsd_object(ctx, pic_param, slice_param, next_slice_param, gen6_mfd_context);
1202         slice_param = next_slice_param;
1203     }
1204
1205     intel_batchbuffer_end_atomic(batch);
1206     intel_batchbuffer_flush(batch);
1207 }
1208
1209 static const int va_to_gen6_vc1_pic_type[5] = {
1210     GEN6_VC1_I_PICTURE,
1211     GEN6_VC1_P_PICTURE,
1212     GEN6_VC1_B_PICTURE,
1213     GEN6_VC1_BI_PICTURE,
1214     GEN6_VC1_P_PICTURE,
1215 };
1216
1217 static const int va_to_gen6_vc1_mv[4] = {
1218     1, /* 1-MV */
1219     2, /* 1-MV half-pel */
1220     3, /* 1-MV half-pef bilinear */
1221     0, /* Mixed MV */
1222 };
1223
1224 static const int b_picture_scale_factor[21] = {
1225     128, 85,  170, 64,  192,
1226     51,  102, 153, 204, 43,
1227     215, 37,  74,  111, 148,
1228     185, 222, 32,  96,  160,
1229     224,
1230 };
1231
1232 static const int va_to_gen6_vc1_condover[3] = {
1233     0,
1234     2,
1235     3
1236 };
1237
1238 static const int va_to_gen6_vc1_profile[4] = {
1239     GEN6_VC1_SIMPLE_PROFILE,
1240     GEN6_VC1_MAIN_PROFILE,
1241     GEN6_VC1_RESERVED_PROFILE,
1242     GEN6_VC1_ADVANCED_PROFILE
1243 };
1244
1245 static void
1246 gen6_mfd_free_vc1_surface(void **data)
1247 {
1248     struct gen6_vc1_surface *gen6_vc1_surface = *data;
1249
1250     if (!gen6_vc1_surface)
1251         return;
1252
1253     dri_bo_unreference(gen6_vc1_surface->dmv);
1254     free(gen6_vc1_surface);
1255     *data = NULL;
1256 }
1257
1258 static void
1259 gen6_mfd_init_vc1_surface(VADriverContextP ctx,
1260                           VAPictureParameterBufferVC1 *pic_param,
1261                           struct object_surface *obj_surface)
1262 {
1263     struct i965_driver_data *i965 = i965_driver_data(ctx);
1264     struct gen6_vc1_surface *gen6_vc1_surface = obj_surface->private_data;
1265     int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1266
1267     obj_surface->free_private_data = gen6_mfd_free_vc1_surface;
1268
1269     if (!gen6_vc1_surface) {
1270         gen6_vc1_surface = calloc(sizeof(struct gen6_vc1_surface), 1);
1271         assert((obj_surface->size & 0x3f) == 0);
1272         obj_surface->private_data = gen6_vc1_surface;
1273     }
1274
1275     gen6_vc1_surface->picture_type = pic_param->picture_fields.bits.picture_type;
1276
1277     if (gen6_vc1_surface->dmv == NULL) {
1278         gen6_vc1_surface->dmv = dri_bo_alloc(i965->intel.bufmgr,
1279                                              "direct mv w/r buffer",
1280                                              128 * height_in_mbs * 64,  /* scalable with frame height */
1281                                              0x1000);
1282     }
1283 }
1284
1285 static void
1286 gen6_mfd_vc1_decode_init(VADriverContextP ctx,
1287                          struct decode_state *decode_state,
1288                          struct gen6_mfd_context *gen6_mfd_context)
1289 {
1290     VAPictureParameterBufferVC1 *pic_param;
1291     struct i965_driver_data *i965 = i965_driver_data(ctx);
1292     struct object_surface *obj_surface;
1293     dri_bo *bo;
1294     int width_in_mbs;
1295     int picture_type;
1296
1297     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1298     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1299     width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1300     picture_type = pic_param->picture_fields.bits.picture_type;
1301
1302     intel_update_vc1_frame_store_index(ctx,
1303                                        decode_state,
1304                                        pic_param,
1305                                        gen6_mfd_context->reference_surface);
1306
1307     /* Current decoded picture */
1308     obj_surface = decode_state->render_object;
1309     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
1310     gen6_mfd_init_vc1_surface(ctx, pic_param, obj_surface);
1311
1312     dri_bo_unreference(gen6_mfd_context->post_deblocking_output.bo);
1313     gen6_mfd_context->post_deblocking_output.bo = obj_surface->bo;
1314     dri_bo_reference(gen6_mfd_context->post_deblocking_output.bo);
1315     gen6_mfd_context->post_deblocking_output.valid = pic_param->entrypoint_fields.bits.loopfilter;
1316
1317     dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo);
1318     gen6_mfd_context->pre_deblocking_output.bo = obj_surface->bo;
1319     dri_bo_reference(gen6_mfd_context->pre_deblocking_output.bo);
1320     gen6_mfd_context->pre_deblocking_output.valid = !pic_param->entrypoint_fields.bits.loopfilter;
1321
1322     dri_bo_unreference(gen6_mfd_context->intra_row_store_scratch_buffer.bo);
1323     bo = dri_bo_alloc(i965->intel.bufmgr,
1324                       "intra row store",
1325                       width_in_mbs * 64,
1326                       0x1000);
1327     assert(bo);
1328     gen6_mfd_context->intra_row_store_scratch_buffer.bo = bo;
1329     gen6_mfd_context->intra_row_store_scratch_buffer.valid = 1;
1330
1331     dri_bo_unreference(gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
1332     bo = dri_bo_alloc(i965->intel.bufmgr,
1333                       "deblocking filter row store",
1334                       width_in_mbs * 7 * 64,
1335                       0x1000);
1336     assert(bo);
1337     gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
1338     gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.valid = 1;
1339
1340     dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1341     bo = dri_bo_alloc(i965->intel.bufmgr,
1342                       "bsd mpc row store",
1343                       width_in_mbs * 96,
1344                       0x1000);
1345     assert(bo);
1346     gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
1347     gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.valid = 1;
1348
1349     gen6_mfd_context->mpr_row_store_scratch_buffer.valid = 0;
1350
1351     gen6_mfd_context->bitplane_read_buffer.valid = !!pic_param->bitplane_present.value;
1352     dri_bo_unreference(gen6_mfd_context->bitplane_read_buffer.bo);
1353
1354     if (gen6_mfd_context->bitplane_read_buffer.valid) {
1355         int width_in_mbs = ALIGN(pic_param->coded_width, 16) / 16;
1356         int height_in_mbs = ALIGN(pic_param->coded_height, 16) / 16;
1357         int bitplane_width = ALIGN(width_in_mbs, 2) / 2;
1358         int src_w, src_h;
1359         uint8_t *src = NULL, *dst = NULL;
1360
1361         assert(decode_state->bit_plane->buffer);
1362         src = decode_state->bit_plane->buffer;
1363
1364         bo = dri_bo_alloc(i965->intel.bufmgr,
1365                           "VC-1 Bitplane",
1366                           bitplane_width * height_in_mbs,
1367                           0x1000);
1368         assert(bo);
1369         gen6_mfd_context->bitplane_read_buffer.bo = bo;
1370
1371         dri_bo_map(bo, True);
1372         assert(bo->virtual);
1373         dst = bo->virtual;
1374
1375         for (src_h = 0; src_h < height_in_mbs; src_h++) {
1376             for(src_w = 0; src_w < width_in_mbs; src_w++) {
1377                 int src_index, dst_index;
1378                 int src_shift;
1379                 uint8_t src_value;
1380
1381                 src_index = (src_h * width_in_mbs + src_w) / 2;
1382                 src_shift = !((src_h * width_in_mbs + src_w) & 1) * 4;
1383                 src_value = ((src[src_index] >> src_shift) & 0xf);
1384
1385                 if (picture_type == GEN6_VC1_SKIPPED_PICTURE){
1386                     src_value |= 0x2;
1387                 }
1388
1389                 dst_index = src_w / 2;
1390                 dst[dst_index] = ((dst[dst_index] >> 4) | (src_value << 4));
1391             }
1392
1393             if (src_w & 1)
1394                 dst[src_w / 2] >>= 4;
1395
1396             dst += bitplane_width;
1397         }
1398
1399         dri_bo_unmap(bo);
1400     } else
1401         gen6_mfd_context->bitplane_read_buffer.bo = NULL;
1402 }
1403
1404 static void
1405 gen6_mfd_vc1_pic_state(VADriverContextP ctx,
1406                        struct decode_state *decode_state,
1407                        struct gen6_mfd_context *gen6_mfd_context)
1408 {
1409     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1410     VAPictureParameterBufferVC1 *pic_param;
1411     struct object_surface *obj_surface;
1412     int alt_pquant_config = 0, alt_pquant_edge_mask = 0, alt_pq;
1413     int dquant, dquantfrm, dqprofile, dqdbedge, dqsbedge, dqbilevel;
1414     int unified_mv_mode;
1415     int ref_field_pic_polarity = 0;
1416     int scale_factor = 0;
1417     int trans_ac_y = 0;
1418     int dmv_surface_valid = 0;
1419     int brfd = 0;
1420     int fcm = 0;
1421     int picture_type;
1422     int profile;
1423     int overlap;
1424
1425     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1426     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1427
1428     profile = va_to_gen6_vc1_profile[pic_param->sequence_fields.bits.profile];
1429     dquant = pic_param->pic_quantizer_fields.bits.dquant;
1430     dquantfrm = pic_param->pic_quantizer_fields.bits.dq_frame;
1431     dqprofile = pic_param->pic_quantizer_fields.bits.dq_profile;
1432     dqdbedge = pic_param->pic_quantizer_fields.bits.dq_db_edge;
1433     dqsbedge = pic_param->pic_quantizer_fields.bits.dq_sb_edge;
1434     dqbilevel = pic_param->pic_quantizer_fields.bits.dq_binary_level;
1435     alt_pq = pic_param->pic_quantizer_fields.bits.alt_pic_quantizer;
1436
1437     if (dquant == 0) {
1438         alt_pquant_config = 0;
1439         alt_pquant_edge_mask = 0;
1440     } else if (dquant == 2) {
1441         alt_pquant_config = 1;
1442         alt_pquant_edge_mask = 0xf;
1443     } else {
1444         assert(dquant == 1);
1445         if (dquantfrm == 0) {
1446             alt_pquant_config = 0;
1447             alt_pquant_edge_mask = 0;
1448             alt_pq = 0;
1449         } else {
1450             assert(dquantfrm == 1);
1451             alt_pquant_config = 1;
1452
1453             switch (dqprofile) {
1454             case 3:
1455                 if (dqbilevel == 0) {
1456                     alt_pquant_config = 2;
1457                     alt_pquant_edge_mask = 0;
1458                 } else {
1459                     assert(dqbilevel == 1);
1460                     alt_pquant_config = 3;
1461                     alt_pquant_edge_mask = 0;
1462                 }
1463                 break;
1464
1465             case 0:
1466                 alt_pquant_edge_mask = 0xf;
1467                 break;
1468
1469             case 1:
1470                 if (dqdbedge == 3)
1471                     alt_pquant_edge_mask = 0x9;
1472                 else
1473                     alt_pquant_edge_mask = (0x3 << dqdbedge);
1474
1475                 break;
1476
1477             case 2:
1478                 alt_pquant_edge_mask = (0x1 << dqsbedge);
1479                 break;
1480
1481             default:
1482                 assert(0);
1483             }
1484         }
1485     }
1486
1487     if (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation) {
1488         assert(pic_param->mv_fields.bits.mv_mode2 < 4);
1489         unified_mv_mode = va_to_gen6_vc1_mv[pic_param->mv_fields.bits.mv_mode2];
1490     } else {
1491         assert(pic_param->mv_fields.bits.mv_mode < 4);
1492         unified_mv_mode = va_to_gen6_vc1_mv[pic_param->mv_fields.bits.mv_mode];
1493     }
1494
1495     if (pic_param->sequence_fields.bits.interlace == 1 &&
1496         pic_param->picture_fields.bits.frame_coding_mode != 0) { /* frame-interlace or field-interlace */
1497         /* FIXME: calculate reference field picture polarity */
1498         assert(0);
1499         ref_field_pic_polarity = 0;
1500     }
1501
1502     if (pic_param->b_picture_fraction < 21)
1503         scale_factor = b_picture_scale_factor[pic_param->b_picture_fraction];
1504
1505     picture_type = va_to_gen6_vc1_pic_type[pic_param->picture_fields.bits.picture_type];
1506
1507     if (profile == GEN6_VC1_ADVANCED_PROFILE &&
1508         picture_type == GEN6_VC1_I_PICTURE)
1509         picture_type = GEN6_VC1_BI_PICTURE;
1510
1511     if (picture_type == GEN6_VC1_I_PICTURE || picture_type == GEN6_VC1_BI_PICTURE) /* I picture */
1512         trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx2;
1513     else {
1514         trans_ac_y = pic_param->transform_fields.bits.transform_ac_codingset_idx1;
1515         /*
1516          * 8.3.6.2.1 Transform Type Selection
1517          * If variable-sized transform coding is not enabled,
1518          * then the 8x8 transform shall be used for all blocks.
1519          * it is also MFX_VC1_PIC_STATE requirement.
1520          */
1521         if (pic_param->transform_fields.bits.variable_sized_transform_flag == 0) {
1522             pic_param->transform_fields.bits.mb_level_transform_type_flag   = 1;
1523             pic_param->transform_fields.bits.frame_level_transform_type     = 0;
1524         }
1525     }
1526
1527     if (picture_type == GEN6_VC1_B_PICTURE) {
1528         struct gen6_vc1_surface *gen6_vc1_surface = NULL;
1529
1530         obj_surface = decode_state->reference_objects[1];
1531
1532         if (obj_surface)
1533             gen6_vc1_surface = obj_surface->private_data;
1534
1535         if (!gen6_vc1_surface ||
1536             (va_to_gen6_vc1_pic_type[gen6_vc1_surface->picture_type] == GEN6_VC1_I_PICTURE ||
1537              va_to_gen6_vc1_pic_type[gen6_vc1_surface->picture_type] == GEN6_VC1_BI_PICTURE))
1538             dmv_surface_valid = 0;
1539         else
1540             dmv_surface_valid = 1;
1541     }
1542
1543     assert(pic_param->picture_fields.bits.frame_coding_mode < 3);
1544
1545     if (pic_param->picture_fields.bits.frame_coding_mode < 2)
1546         fcm = pic_param->picture_fields.bits.frame_coding_mode;
1547     else {
1548         if (pic_param->picture_fields.bits.top_field_first)
1549             fcm = 2;
1550         else
1551             fcm = 3;
1552     }
1553
1554     if (pic_param->picture_fields.bits.picture_type == GEN6_VC1_B_PICTURE) { /* B picture */
1555         brfd = pic_param->reference_fields.bits.reference_distance;
1556         brfd = (scale_factor * brfd) >> 8;
1557         brfd = pic_param->reference_fields.bits.reference_distance - brfd - 1;
1558
1559         if (brfd < 0)
1560             brfd = 0;
1561     }
1562
1563     overlap = 0;
1564     if (profile != GEN6_VC1_ADVANCED_PROFILE){
1565         if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9 &&
1566             pic_param->picture_fields.bits.picture_type != GEN6_VC1_B_PICTURE) {
1567             overlap = 1;
1568         }
1569     }else {
1570         if (pic_param->picture_fields.bits.picture_type == GEN6_VC1_P_PICTURE &&
1571              pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9){
1572               overlap = 1;
1573         }
1574         if (pic_param->picture_fields.bits.picture_type == GEN6_VC1_I_PICTURE ||
1575             pic_param->picture_fields.bits.picture_type == GEN6_VC1_BI_PICTURE){
1576              if (pic_param->pic_quantizer_fields.bits.pic_quantizer_scale >= 9){
1577                 overlap = 1;
1578              } else if (va_to_gen6_vc1_condover[pic_param->conditional_overlap_flag] == 2 ||
1579                         va_to_gen6_vc1_condover[pic_param->conditional_overlap_flag] == 3) {
1580                  overlap = 1;
1581              }
1582         }
1583     }
1584
1585     assert(pic_param->conditional_overlap_flag < 3);
1586     assert(pic_param->mv_fields.bits.mv_table < 4); /* FIXME: interlace mode */
1587
1588     BEGIN_BCS_BATCH(batch, 6);
1589     OUT_BCS_BATCH(batch, MFX_VC1_PIC_STATE | (6 - 2));
1590     OUT_BCS_BATCH(batch,
1591                   (ALIGN(pic_param->coded_height, 16) / 16) << 16 |
1592                   (ALIGN(pic_param->coded_width, 16) / 16));
1593     OUT_BCS_BATCH(batch,
1594                   pic_param->sequence_fields.bits.syncmarker << 31 |
1595                   1 << 29 | /* concealment */
1596                   alt_pq << 24 |
1597                   pic_param->entrypoint_fields.bits.loopfilter << 23 |
1598                   overlap << 22 |
1599                   (pic_param->pic_quantizer_fields.bits.quantizer == 0) << 21 | /* implicit quantizer */
1600                   pic_param->pic_quantizer_fields.bits.pic_quantizer_scale << 16 |
1601                   alt_pquant_edge_mask << 12 |
1602                   alt_pquant_config << 10 |
1603                   pic_param->pic_quantizer_fields.bits.half_qp << 9 |
1604                   pic_param->pic_quantizer_fields.bits.pic_quantizer_type << 8 |
1605                   va_to_gen6_vc1_condover[pic_param->conditional_overlap_flag] << 6 |
1606                   !pic_param->picture_fields.bits.is_first_field << 5 |
1607                   picture_type << 2 |
1608                   fcm << 0);
1609     OUT_BCS_BATCH(batch,
1610                   !!pic_param->bitplane_present.value << 23 |
1611                   !pic_param->bitplane_present.flags.bp_forward_mb << 22 |
1612                   !pic_param->bitplane_present.flags.bp_mv_type_mb << 21 |
1613                   !pic_param->bitplane_present.flags.bp_skip_mb << 20 |
1614                   !pic_param->bitplane_present.flags.bp_direct_mb << 19 |
1615                   !pic_param->bitplane_present.flags.bp_overflags << 18 |
1616                   !pic_param->bitplane_present.flags.bp_ac_pred << 17 |
1617                   !pic_param->bitplane_present.flags.bp_field_tx << 16 |
1618                   pic_param->mv_fields.bits.extended_dmv_range << 14 |
1619                   pic_param->mv_fields.bits.extended_mv_range << 12 |
1620                   pic_param->mv_fields.bits.four_mv_switch << 11 |
1621                   pic_param->fast_uvmc_flag << 10 |
1622                   unified_mv_mode << 8 |
1623                   ref_field_pic_polarity << 6 |
1624                   pic_param->reference_fields.bits.num_reference_pictures << 5 |
1625                   pic_param->reference_fields.bits.reference_distance << 0);
1626     OUT_BCS_BATCH(batch,
1627                   scale_factor << 24 |
1628                   pic_param->mv_fields.bits.mv_table << 20 |
1629                   pic_param->mv_fields.bits.four_mv_block_pattern_table << 18 |
1630                   pic_param->mv_fields.bits.two_mv_block_pattern_table << 16 |
1631                   pic_param->transform_fields.bits.frame_level_transform_type << 12 |
1632                   pic_param->transform_fields.bits.mb_level_transform_type_flag << 11 |
1633                   pic_param->mb_mode_table << 8 |
1634                   trans_ac_y << 6 |
1635                   pic_param->transform_fields.bits.transform_ac_codingset_idx1 << 4 |
1636                   pic_param->transform_fields.bits.intra_transform_dc_table << 3 |
1637                   pic_param->cbp_table << 0);
1638     OUT_BCS_BATCH(batch,
1639                   dmv_surface_valid << 13 |
1640                   brfd << 8 |
1641                   ((ALIGN(pic_param->coded_width, 16) / 16 + 1) / 2 - 1));
1642     ADVANCE_BCS_BATCH(batch);
1643 }
1644
1645 static void
1646 gen6_mfd_vc1_pred_pipe_state(VADriverContextP ctx,
1647                              struct decode_state *decode_state,
1648                              struct gen6_mfd_context *gen6_mfd_context)
1649 {
1650     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1651     VAPictureParameterBufferVC1 *pic_param;
1652     int interpolation_mode = 0;
1653     int intensitycomp_single;
1654
1655     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1656     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1657
1658     if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPelBilinear ||
1659         (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
1660          pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPelBilinear))
1661         interpolation_mode = 2; /* Half-pel bilinear */
1662     else if (pic_param->mv_fields.bits.mv_mode == VAMvMode1MvHalfPel ||
1663              (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation &&
1664               pic_param->mv_fields.bits.mv_mode2 == VAMvMode1MvHalfPel))
1665         interpolation_mode = 0; /* Half-pel bicubic */
1666     else
1667         interpolation_mode = 1; /* Quarter-pel bicubic */
1668
1669     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1670     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1671     intensitycomp_single = (pic_param->mv_fields.bits.mv_mode == VAMvModeIntensityCompensation);
1672
1673     BEGIN_BCS_BATCH(batch, 7);
1674     OUT_BCS_BATCH(batch, MFX_VC1_PRED_PIPE_STATE | (7 - 2));
1675     OUT_BCS_BATCH(batch,
1676                   0 << 8 | /* FIXME: interlace mode */
1677                   pic_param->rounding_control << 4 |
1678                   va_to_gen6_vc1_profile[pic_param->sequence_fields.bits.profile] << 2);
1679     OUT_BCS_BATCH(batch,
1680                   pic_param->luma_shift << 16 |
1681                   pic_param->luma_scale << 0); /* FIXME: Luma Scaling */
1682     OUT_BCS_BATCH(batch, 0);
1683     OUT_BCS_BATCH(batch, 0);
1684     OUT_BCS_BATCH(batch, 0);
1685     OUT_BCS_BATCH(batch,
1686                   interpolation_mode << 19 |
1687                   pic_param->fast_uvmc_flag << 18 |
1688                   0 << 17 | /* FIXME: scale up or down ??? */
1689                   pic_param->range_reduction_frame << 16 |
1690                   0 << 6 | /* FIXME: double ??? */
1691                   0 << 4 |
1692                   intensitycomp_single << 2 |
1693                   intensitycomp_single << 0);
1694     ADVANCE_BCS_BATCH(batch);
1695 }
1696
1697
1698 static void
1699 gen6_mfd_vc1_directmode_state(VADriverContextP ctx,
1700                               struct decode_state *decode_state,
1701                               struct gen6_mfd_context *gen6_mfd_context)
1702 {
1703     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1704     struct object_surface *obj_surface;
1705     dri_bo *dmv_read_buffer = NULL, *dmv_write_buffer = NULL;
1706
1707     obj_surface = decode_state->render_object;
1708
1709     if (obj_surface && obj_surface->private_data) {
1710         dmv_write_buffer = ((struct gen6_vc1_surface *)(obj_surface->private_data))->dmv;
1711     }
1712
1713     obj_surface = decode_state->reference_objects[1];
1714
1715     if (obj_surface && obj_surface->private_data) {
1716         dmv_read_buffer = ((struct gen6_vc1_surface *)(obj_surface->private_data))->dmv;
1717     }
1718
1719     BEGIN_BCS_BATCH(batch, 3);
1720     OUT_BCS_BATCH(batch, MFX_VC1_DIRECTMODE_STATE | (3 - 2));
1721
1722     if (dmv_write_buffer)
1723         OUT_BCS_RELOC(batch, dmv_write_buffer,
1724                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
1725                       0);
1726     else
1727         OUT_BCS_BATCH(batch, 0);
1728
1729     if (dmv_read_buffer)
1730         OUT_BCS_RELOC(batch, dmv_read_buffer,
1731                       I915_GEM_DOMAIN_INSTRUCTION, 0,
1732                       0);
1733     else
1734         OUT_BCS_BATCH(batch, 0);
1735
1736     ADVANCE_BCS_BATCH(batch);
1737 }
1738
1739 static int
1740 gen6_mfd_vc1_get_macroblock_bit_offset(uint8_t *buf, int in_slice_data_bit_offset, int profile)
1741 {
1742     int out_slice_data_bit_offset;
1743     int slice_header_size = in_slice_data_bit_offset / 8;
1744     int i, j;
1745
1746     if (profile != 3)
1747         out_slice_data_bit_offset = in_slice_data_bit_offset;
1748     else {
1749         for (i = 0, j = 0; i < slice_header_size; i++, j++) {
1750             if (!buf[j] && !buf[j + 1] && buf[j + 2] == 3 && buf[j + 3] < 4) {
1751                 i++, j += 2;
1752             }
1753         }
1754
1755         out_slice_data_bit_offset = 8 * j + in_slice_data_bit_offset % 8;
1756     }
1757
1758     return out_slice_data_bit_offset;
1759 }
1760
1761 static void
1762 gen6_mfd_vc1_bsd_object(VADriverContextP ctx,
1763                         VAPictureParameterBufferVC1 *pic_param,
1764                         VASliceParameterBufferVC1 *slice_param,
1765                         VASliceParameterBufferVC1 *next_slice_param,
1766                         dri_bo *slice_data_bo,
1767                         struct gen6_mfd_context *gen6_mfd_context)
1768 {
1769     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1770     int next_slice_start_vert_pos;
1771     int macroblock_offset;
1772     uint8_t *slice_data = NULL;
1773
1774     dri_bo_map(slice_data_bo, 0);
1775     slice_data = (uint8_t *)(slice_data_bo->virtual + slice_param->slice_data_offset);
1776     macroblock_offset = gen6_mfd_vc1_get_macroblock_bit_offset(slice_data,
1777                                                                slice_param->macroblock_offset,
1778                                                                pic_param->sequence_fields.bits.profile);
1779     dri_bo_unmap(slice_data_bo);
1780
1781     if (next_slice_param)
1782         next_slice_start_vert_pos = next_slice_param->slice_vertical_position;
1783     else
1784         next_slice_start_vert_pos = ALIGN(pic_param->coded_height, 16) / 16;
1785
1786     BEGIN_BCS_BATCH(batch, 4);
1787     OUT_BCS_BATCH(batch, MFD_VC1_BSD_OBJECT | (4 - 2));
1788     OUT_BCS_BATCH(batch,
1789                   slice_param->slice_data_size - (macroblock_offset >> 3));
1790     OUT_BCS_BATCH(batch,
1791                   slice_param->slice_data_offset + (macroblock_offset >> 3));
1792     OUT_BCS_BATCH(batch,
1793                   slice_param->slice_vertical_position << 24 |
1794                   next_slice_start_vert_pos << 16 |
1795                   (macroblock_offset & 0x7));
1796     ADVANCE_BCS_BATCH(batch);
1797 }
1798
1799 static void
1800 gen6_mfd_vc1_decode_picture(VADriverContextP ctx,
1801                             struct decode_state *decode_state,
1802                             struct gen6_mfd_context *gen6_mfd_context)
1803 {
1804     struct intel_batchbuffer *batch = gen6_mfd_context->base.batch;
1805     VAPictureParameterBufferVC1 *pic_param;
1806     VASliceParameterBufferVC1 *slice_param, *next_slice_param, *next_slice_group_param;
1807     dri_bo *slice_data_bo;
1808     int i, j;
1809
1810     assert(decode_state->pic_param && decode_state->pic_param->buffer);
1811     pic_param = (VAPictureParameterBufferVC1 *)decode_state->pic_param->buffer;
1812
1813     gen6_mfd_vc1_decode_init(ctx, decode_state, gen6_mfd_context);
1814     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
1815     intel_batchbuffer_emit_mi_flush(batch);
1816     gen6_mfd_pipe_mode_select(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context);
1817     gen6_mfd_surface_state(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context);
1818     gen6_mfd_pipe_buf_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context);
1819     gen6_mfd_bsp_buf_base_addr_state(ctx, decode_state, MFX_FORMAT_VC1, gen6_mfd_context);
1820     gen6_mfd_vc1_pic_state(ctx, decode_state, gen6_mfd_context);
1821     gen6_mfd_vc1_pred_pipe_state(ctx, decode_state, gen6_mfd_context);
1822     gen6_mfd_vc1_directmode_state(ctx, decode_state, gen6_mfd_context);
1823
1824     for (j = 0; j < decode_state->num_slice_params; j++) {
1825         assert(decode_state->slice_params && decode_state->slice_params[j]->buffer);
1826         slice_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j]->buffer;
1827         slice_data_bo = decode_state->slice_datas[j]->bo;
1828         gen6_mfd_ind_obj_base_addr_state(ctx, slice_data_bo, MFX_FORMAT_VC1, gen6_mfd_context);
1829
1830         if (j == decode_state->num_slice_params - 1)
1831             next_slice_group_param = NULL;
1832         else
1833             next_slice_group_param = (VASliceParameterBufferVC1 *)decode_state->slice_params[j + 1]->buffer;
1834
1835         for (i = 0; i < decode_state->slice_params[j]->num_elements; i++) {
1836             assert(slice_param->slice_data_flag == VA_SLICE_DATA_FLAG_ALL);
1837
1838             if (i < decode_state->slice_params[j]->num_elements - 1)
1839                 next_slice_param = slice_param + 1;
1840             else
1841                 next_slice_param = next_slice_group_param;
1842
1843             gen6_mfd_vc1_bsd_object(ctx, pic_param, slice_param, next_slice_param, slice_data_bo, gen6_mfd_context);
1844             slice_param++;
1845         }
1846     }
1847
1848     intel_batchbuffer_end_atomic(batch);
1849     intel_batchbuffer_flush(batch);
1850 }
1851
1852 static VAStatus
1853 gen6_mfd_decode_picture(VADriverContextP ctx,
1854                         VAProfile profile,
1855                         union codec_state *codec_state,
1856                         struct hw_context *hw_context)
1857
1858 {
1859     struct gen6_mfd_context *gen6_mfd_context = (struct gen6_mfd_context *)hw_context;
1860     struct decode_state *decode_state = &codec_state->decode;
1861     VAStatus vaStatus;
1862
1863     assert(gen6_mfd_context);
1864
1865     vaStatus = intel_decoder_sanity_check_input(ctx, profile, decode_state);
1866
1867     if (vaStatus != VA_STATUS_SUCCESS)
1868         goto out;
1869
1870     switch (profile) {
1871     case VAProfileMPEG2Simple:
1872     case VAProfileMPEG2Main:
1873         gen6_mfd_mpeg2_decode_picture(ctx, decode_state, gen6_mfd_context);
1874         break;
1875
1876     case VAProfileH264ConstrainedBaseline:
1877     case VAProfileH264Main:
1878     case VAProfileH264High:
1879         gen6_mfd_avc_decode_picture(ctx, decode_state, gen6_mfd_context);
1880         break;
1881
1882     case VAProfileVC1Simple:
1883     case VAProfileVC1Main:
1884     case VAProfileVC1Advanced:
1885         gen6_mfd_vc1_decode_picture(ctx, decode_state, gen6_mfd_context);
1886         break;
1887
1888     default:
1889         assert(0);
1890         break;
1891     }
1892
1893     vaStatus = VA_STATUS_SUCCESS;
1894
1895 out:
1896     return vaStatus;
1897 }
1898
1899 static void
1900 gen6_mfd_context_destroy(void *hw_context)
1901 {
1902     struct gen6_mfd_context *gen6_mfd_context = (struct gen6_mfd_context *)hw_context;
1903
1904     dri_bo_unreference(gen6_mfd_context->post_deblocking_output.bo);
1905     gen6_mfd_context->post_deblocking_output.bo = NULL;
1906
1907     dri_bo_unreference(gen6_mfd_context->pre_deblocking_output.bo);
1908     gen6_mfd_context->pre_deblocking_output.bo = NULL;
1909
1910     dri_bo_unreference(gen6_mfd_context->intra_row_store_scratch_buffer.bo);
1911     gen6_mfd_context->intra_row_store_scratch_buffer.bo = NULL;
1912
1913     dri_bo_unreference(gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo);
1914     gen6_mfd_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
1915
1916     dri_bo_unreference(gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo);
1917     gen6_mfd_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
1918
1919     dri_bo_unreference(gen6_mfd_context->mpr_row_store_scratch_buffer.bo);
1920     gen6_mfd_context->mpr_row_store_scratch_buffer.bo = NULL;
1921
1922     dri_bo_unreference(gen6_mfd_context->bitplane_read_buffer.bo);
1923     gen6_mfd_context->bitplane_read_buffer.bo = NULL;
1924
1925     intel_batchbuffer_free(gen6_mfd_context->base.batch);
1926     free(gen6_mfd_context);
1927 }
1928
1929 struct hw_context *
1930 gen6_dec_hw_context_init(VADriverContextP ctx, struct object_config *obj_config)
1931 {
1932     struct intel_driver_data *intel = intel_driver_data(ctx);
1933     struct gen6_mfd_context *gen6_mfd_context = calloc(1, sizeof(struct gen6_mfd_context));
1934     int i;
1935
1936     gen6_mfd_context->base.destroy = gen6_mfd_context_destroy;
1937     gen6_mfd_context->base.run = gen6_mfd_decode_picture;
1938     gen6_mfd_context->base.batch = intel_batchbuffer_new(intel, I915_EXEC_RENDER, 0);
1939
1940     for (i = 0; i < ARRAY_ELEMS(gen6_mfd_context->reference_surface); i++) {
1941         gen6_mfd_context->reference_surface[i].surface_id = VA_INVALID_ID;
1942         gen6_mfd_context->reference_surface[i].frame_store_id = -1;
1943         gen6_mfd_context->reference_surface[i].obj_surface = NULL;
1944     }
1945
1946     gen6_mfd_context->wa_mpeg2_slice_vertical_position = -1;
1947
1948     return (struct hw_context *)gen6_mfd_context;
1949 }