2 * Copyright © 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Zhou Chang <chang.zhou@intel.com>
34 #include <intel_bufmgr.h>
36 #include "i965_gpe_utils.h"
40 #define MAX_MFC_REFERENCE_SURFACES 16
41 #define NUM_MFC_DMV_BUFFERS 34
43 #define INTRA_MB_FLAG_MASK 0x00002000
45 /* The space required for slice header SLICE_STATE + header.
47 #define SLICE_HEADER 80
49 /* the space required for slice tail. */
52 #define __SOFTWARE__ 0
54 #define MFC_BATCHBUFFER_AVC_INTRA 0
55 #define MFC_BATCHBUFFER_AVC_INTER 1
56 #define NUM_MFC_KERNEL 2
58 #define BIND_IDX_VME_OUTPUT 0
59 #define BIND_IDX_MFC_SLICE_HEADER 1
60 #define BIND_IDX_MFC_BATCHBUFFER 2
62 #define CMD_LEN_IN_OWORD 4
65 typedef enum _gen6_brc_status
67 BRC_NO_HRD_VIOLATION = 0,
70 BRC_UNDERFLOW_WITH_MAX_QP = 3,
71 BRC_OVERFLOW_WITH_MIN_QP = 4,
74 struct gen6_mfc_avc_surface_aux
80 struct gen6_mfc_context
89 //MFX_PIPE_BUF_ADDR_STATE
92 } post_deblocking_output; //OUTPUT: reconstructed picture
96 } pre_deblocking_output; //OUTPUT: reconstructed picture with deblocked
100 } uncompressed_picture_source; //INPUT: original compressed image
104 } intra_row_store_scratch_buffer; //INTERNAL:
108 } macroblock_status_buffer; //INTERNAL:
112 } deblocking_filter_row_store_scratch_buffer; //INTERNAL:
116 } reference_surfaces[MAX_MFC_REFERENCE_SURFACES]; //INTERNAL: refrence surfaces
118 //MFX_IND_OBJ_BASE_ADDR_STATE
121 } mfc_indirect_mv_object; //INPUT: the blocks' mv info
127 } mfc_indirect_pak_bse_object; //OUTPUT: the compressed bitstream
129 //MFX_BSP_BUF_BASE_ADDR_STATE
132 } bsd_mpc_row_store_scratch_buffer; //INTERNAL:
134 //MFX_AVC_DIRECTMODE_STATE
137 } direct_mv_buffers[NUM_MFC_DMV_BUFFERS]; //INTERNAL: 0-31 as input,32 and 33 as output
139 //Bit rate tracking context
141 unsigned int QpPrimeY;
142 unsigned int MaxQpNegModifier;
143 unsigned int MaxQpPosModifier;
144 unsigned char MaxSizeInWord;
145 unsigned char TargetSizeInWord;
146 unsigned char Correct[6];
147 unsigned char GrowInit;
148 unsigned char GrowResistance;
149 unsigned char ShrinkInit;
150 unsigned char ShrinkResistance;
152 unsigned int target_mb_size;
153 unsigned int target_frame_size;
154 } bit_rate_control_context[3]; //INTERNAL: for I, P, B frames
159 int target_frame_size[3]; // I,P,B
160 double bits_per_frame;
161 double qpf_rounding_accumulator;
165 double current_buffer_fullness;
166 double target_buffer_fullness;
167 double buffer_capacity;
168 unsigned int buffer_size;
169 unsigned int violation_noted;
172 //HRD control context
174 int i_bit_rate_value;
175 int i_cpb_size_value;
177 int i_initial_cpb_removal_delay;
178 int i_cpb_removal_delay;
182 int i_initial_cpb_removal_delay_length;
183 int i_cpb_removal_delay_length;
184 int i_dpb_output_delay_length;
187 struct i965_gpe_context gpe_context;
188 struct i965_buffer_surface mfc_batchbuffer_surface;
189 struct intel_batchbuffer *aux_batchbuffer;
190 struct i965_buffer_surface aux_batchbuffer_surface;
192 void (*pipe_mode_select)(VADriverContextP ctx,
194 struct intel_encoder_context *encoder_context);
195 void (*set_surface_state)(VADriverContextP ctx,
196 struct intel_encoder_context *encoder_context);
197 void (*ind_obj_base_addr_state)(VADriverContextP ctx,
198 struct intel_encoder_context *encoder_context);
199 void (*avc_img_state)(VADriverContextP ctx,
200 struct encode_state *encode_state,
201 struct intel_encoder_context *encoder_context);
202 void (*avc_qm_state)(VADriverContextP ctx,
203 struct intel_encoder_context *encoder_context);
204 void (*avc_fqm_state)(VADriverContextP ctx,
205 struct intel_encoder_context *encoder_context);
206 void (*insert_object)(VADriverContextP ctx,
207 struct intel_encoder_context *encoder_context,
208 unsigned int *insert_data,
209 int lenght_in_dws, int data_bits_in_last_dw,
210 int skip_emul_byte_count,
211 int is_last_header, int is_end_of_slice,
213 struct intel_batchbuffer *batch);
214 void (*buffer_suface_setup)(VADriverContextP ctx,
215 struct i965_gpe_context *gpe_context,
216 struct i965_buffer_surface *buffer_surface,
217 unsigned long binding_table_offset,
218 unsigned long surface_state_offset);
221 VAStatus gen6_mfc_pipeline(VADriverContextP ctx,
223 struct encode_state *encode_state,
224 struct intel_encoder_context *encoder_context);
225 void gen6_mfc_context_destroy(void *context);
228 Bool gen75_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
231 extern int intel_mfc_update_hrd(struct encode_state *encode_state,
232 struct gen6_mfc_context *mfc_context,
235 extern int intel_mfc_brc_postpack(struct encode_state *encode_state,
236 struct gen6_mfc_context *mfc_context,
239 extern void intel_mfc_hrd_context_update(struct encode_state *encode_state,
240 struct gen6_mfc_context *mfc_context);
242 extern int intel_mfc_interlace_check(VADriverContextP ctx,
243 struct encode_state *encode_state,
244 struct intel_encoder_context *encoder_context);
246 extern void intel_mfc_brc_prepare(struct encode_state *encode_state,
247 struct intel_encoder_context *encoder_context);
249 extern void intel_mfc_avc_pipeline_header_programing(VADriverContextP ctx,
250 struct encode_state *encode_state,
251 struct intel_encoder_context *encoder_context,
252 struct intel_batchbuffer *slice_batch);
254 extern VAStatus intel_mfc_avc_prepare(VADriverContextP ctx,
255 struct encode_state *encode_state,
256 struct intel_encoder_context *encoder_context);
258 extern int intel_avc_enc_slice_type_fixup(int type);
261 intel_mfc_avc_ref_idx_state(VADriverContextP ctx,
262 struct encode_state *encode_state,
263 struct intel_encoder_context *encoder_context);
266 Bool gen8_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context);
268 #endif /* _GEN6_MFC_BCS_H_ */