src/gen6_mfc.c

   1 /*
   2  * Copyright © 2010-2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Zhou Chang <chang.zhou@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <assert.h>
  33 #include <math.h>
  34
  35 #include "intel_batchbuffer.h"
  36 #include "i965_defines.h"
  37 #include "i965_structs.h"
  38 #include "i965_drv_video.h"
  39 #include "i965_encoder.h"
  40 #include "i965_encoder_utils.h"
  41 #include "gen6_mfc.h"
  42 #include "gen6_vme.h"
  43 #include "intel_media.h"
  44
  45 static const uint32_t gen6_mfc_batchbuffer_avc_intra[][4] = {
  46 #include "shaders/utils/mfc_batchbuffer_avc_intra.g6b"
  47 };
  48
  49 static const uint32_t gen6_mfc_batchbuffer_avc_inter[][4] = {
  50 #include "shaders/utils/mfc_batchbuffer_avc_inter.g6b"
  51 };
  52
  53 static struct i965_kernel gen6_mfc_kernels[] = {
  54     {
  55         "MFC AVC INTRA BATCHBUFFER ",
  56         MFC_BATCHBUFFER_AVC_INTRA,
  57         gen6_mfc_batchbuffer_avc_intra,
  58         sizeof(gen6_mfc_batchbuffer_avc_intra),
  59         NULL
  60     },
  61
  62     {
  63         "MFC AVC INTER BATCHBUFFER ",
  64         MFC_BATCHBUFFER_AVC_INTER,
  65         gen6_mfc_batchbuffer_avc_inter,
  66         sizeof(gen6_mfc_batchbuffer_avc_inter),
  67         NULL
  68     },
  69 };
  70
  71 static void
  72 gen6_mfc_pipe_mode_select(VADriverContextP ctx,
  73                           int standard_select,
  74                           struct intel_encoder_context *encoder_context)
  75 {
  76     struct intel_batchbuffer *batch = encoder_context->base.batch;
  77     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
  78
  79     assert(standard_select == MFX_FORMAT_AVC);
  80
  81     BEGIN_BCS_BATCH(batch, 4);
  82
  83     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (4 - 2));
  84     OUT_BCS_BATCH(batch,
  85                   (1 << 10) | /* disable Stream-Out , advanced QP/bitrate control need enable it*/
  86                   ((!!mfc_context->post_deblocking_output.bo) << 9)  | /* Post Deblocking Output */
  87                   ((!!mfc_context->pre_deblocking_output.bo) << 8)  | /* Pre Deblocking Output */
  88                   (0 << 7)  | /* disable TLB prefectch */
  89                   (0 << 5)  | /* not in stitch mode */
  90                   (1 << 4)  | /* encoding mode */
  91                   (2 << 0));  /* Standard Select: AVC */
  92     OUT_BCS_BATCH(batch,
  93                   (0 << 20) | /* round flag in PB slice */
  94                   (0 << 19) | /* round flag in Intra8x8 */
  95                   (0 << 7)  | /* expand NOA bus flag */
  96                   (1 << 6)  | /* must be 1 */
  97                   (0 << 5)  | /* disable clock gating for NOA */
  98                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
  99                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
 100                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
 101                   (0 << 1)  | /* AVC long field motion vector */
 102                   (0 << 0));  /* always calculate AVC ILDB boundary strength */
 103     OUT_BCS_BATCH(batch, 0);
 104
 105     ADVANCE_BCS_BATCH(batch);
 106 }
 107
 108 static void
 109 gen6_mfc_surface_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 110 {
 111     struct intel_batchbuffer *batch = encoder_context->base.batch;
 112     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 113
 114     BEGIN_BCS_BATCH(batch, 6);
 115
 116     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
 117     OUT_BCS_BATCH(batch, 0);
 118     OUT_BCS_BATCH(batch,
 119                   ((mfc_context->surface_state.height - 1) << 19) |
 120                   ((mfc_context->surface_state.width - 1) << 6));
 121     OUT_BCS_BATCH(batch,
 122                   (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
 123                   (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
 124                   (0 << 22) | /* surface object control state, FIXME??? */
 125                   ((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */
 126                   (0 << 2)  | /* must be 0 for interleave U/V */
 127                   (1 << 1)  | /* must be y-tiled */
 128                   (I965_TILEWALK_YMAJOR << 0));                         /* tile walk, TILEWALK_YMAJOR */
 129     OUT_BCS_BATCH(batch,
 130                   (0 << 16) |                                                           /* must be 0 for interleave U/V */
 131                   (mfc_context->surface_state.h_pitch));                /* y offset for U(cb) */
 132     OUT_BCS_BATCH(batch, 0);
 133     ADVANCE_BCS_BATCH(batch);
 134 }
 135
 136 void
 137 gen6_mfc_pipe_buf_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 138 {
 139     struct intel_batchbuffer *batch = encoder_context->base.batch;
 140     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 141     int i;
 142
 143     BEGIN_BCS_BATCH(batch, 24);
 144
 145     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
 146
 147     if (mfc_context->pre_deblocking_output.bo)
 148         OUT_BCS_RELOC(batch, mfc_context->pre_deblocking_output.bo,
 149                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 150                       0);
 151     else
 152         OUT_BCS_BATCH(batch, 0);                                                                                        /* pre output addr   */
 153
 154     if (mfc_context->post_deblocking_output.bo)
 155         OUT_BCS_RELOC(batch, mfc_context->post_deblocking_output.bo,
 156                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 157                       0);                                                                                       /* post output addr  */
 158     else
 159         OUT_BCS_BATCH(batch, 0);
 160
 161     OUT_BCS_RELOC(batch, mfc_context->uncompressed_picture_source.bo,
 162                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 163                   0);                                                                                   /* uncompressed data */
 164     OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
 165                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 166                   0);                                                                                   /* StreamOut data*/
 167     OUT_BCS_RELOC(batch, mfc_context->intra_row_store_scratch_buffer.bo,
 168                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 169                   0);
 170     OUT_BCS_RELOC(batch, mfc_context->deblocking_filter_row_store_scratch_buffer.bo,
 171                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 172                   0);
 173     /* 7..22 Reference pictures*/
 174     for (i = 0; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) {
 175         if ( mfc_context->reference_surfaces[i].bo != NULL) {
 176             OUT_BCS_RELOC(batch, mfc_context->reference_surfaces[i].bo,
 177                           I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 178                           0);
 179         } else {
 180             OUT_BCS_BATCH(batch, 0);
 181         }
 182     }
 183     OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
 184                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 185                   0);                                                                                   /* Macroblock status buffer*/
 186
 187     ADVANCE_BCS_BATCH(batch);
 188 }
 189
 190 static void
 191 gen6_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 192 {
 193     struct intel_batchbuffer *batch = encoder_context->base.batch;
 194     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 195     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 196
 197     BEGIN_BCS_BATCH(batch, 11);
 198
 199     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
 200     OUT_BCS_BATCH(batch, 0);
 201     OUT_BCS_BATCH(batch, 0);
 202     /* MFX Indirect MV Object Base Address */
 203     OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 204     OUT_BCS_BATCH(batch, 0);
 205     OUT_BCS_BATCH(batch, 0);
 206     OUT_BCS_BATCH(batch, 0);
 207     OUT_BCS_BATCH(batch, 0);
 208     OUT_BCS_BATCH(batch, 0);
 209     /*MFC Indirect PAK-BSE Object Base Address for Encoder*/
 210     OUT_BCS_RELOC(batch,
 211                   mfc_context->mfc_indirect_pak_bse_object.bo,
 212                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 213                   0);
 214     OUT_BCS_RELOC(batch,
 215                   mfc_context->mfc_indirect_pak_bse_object.bo,
 216                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 217                   mfc_context->mfc_indirect_pak_bse_object.end_offset);
 218
 219     ADVANCE_BCS_BATCH(batch);
 220 }
 221
 222 void
 223 gen6_mfc_bsp_buf_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 224 {
 225     struct intel_batchbuffer *batch = encoder_context->base.batch;
 226     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 227
 228     BEGIN_BCS_BATCH(batch, 4);
 229
 230     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
 231     OUT_BCS_RELOC(batch, mfc_context->bsd_mpc_row_store_scratch_buffer.bo,
 232                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 233                   0);
 234     OUT_BCS_BATCH(batch, 0);
 235     OUT_BCS_BATCH(batch, 0);
 236
 237     ADVANCE_BCS_BATCH(batch);
 238 }
 239
 240 static void
 241 gen6_mfc_avc_img_state(VADriverContextP ctx,struct encode_state *encode_state,
 242                        struct intel_encoder_context *encoder_context)
 243 {
 244     struct intel_batchbuffer *batch = encoder_context->base.batch;
 245     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 246     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 247     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 248     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 249     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 250
 251     BEGIN_BCS_BATCH(batch, 13);
 252     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (13 - 2));
 253     OUT_BCS_BATCH(batch,
 254                   ((width_in_mbs * height_in_mbs) & 0xFFFF));
 255     OUT_BCS_BATCH(batch,
 256                   (height_in_mbs << 16) |
 257                   (width_in_mbs << 0));
 258     OUT_BCS_BATCH(batch,
 259                   (0 << 24) |     /*Second Chroma QP Offset*/
 260                   (0 << 16) |     /*Chroma QP Offset*/
 261                   (0 << 14) |   /*Max-bit conformance Intra flag*/
 262                   (0 << 13) |   /*Max Macroblock size conformance Inter flag*/
 263                   (1 << 12) |   /*Should always be written as "1" */
 264                   (0 << 10) |   /*QM Preset FLag */
 265                   (0 << 8)  |   /*Image Structure*/
 266                   (0 << 0) );   /*Current Decoed Image Frame Store ID, reserved in Encode mode*/
 267     OUT_BCS_BATCH(batch,
 268                   (400 << 16) |   /*Mininum Frame size*/
 269                   (0 << 15) |   /*Disable reading of Macroblock Status Buffer*/
 270                   (0 << 14) |   /*Load BitStream Pointer only once, 1 slic 1 frame*/
 271                   (0 << 13) |   /*CABAC 0 word insertion test enable*/
 272                   (1 << 12) |   /*MVUnpackedEnable,compliant to DXVA*/
 273                   (1 << 10) |   /*Chroma Format IDC, 4:2:0*/
 274                   (pPicParameter->pic_fields.bits.entropy_coding_mode_flag << 7)  |   /*0:CAVLC encoding mode,1:CABAC*/
 275                   (0 << 6)  |   /*Only valid for VLD decoding mode*/
 276                   (0 << 5)  |   /*Constrained Intra Predition Flag, from PPS*/
 277                   (pSequenceParameter->seq_fields.bits.direct_8x8_inference_flag << 4)  |   /*Direct 8x8 inference flag*/
 278                   (pPicParameter->pic_fields.bits.transform_8x8_mode_flag << 3)  |   /*8x8 or 4x4 IDCT Transform Mode Flag*/
 279                   (1 << 2)  |   /*Frame MB only flag*/
 280                   (0 << 1)  |   /*MBAFF mode is in active*/
 281                   (0 << 0) );   /*Field picture flag*/
 282     OUT_BCS_BATCH(batch,
 283                   (1<<16)   |   /*Frame Size Rate Control Flag*/
 284                   (1<<12)   |
 285                   (1<<9)    |   /*MB level Rate Control Enabling Flag*/
 286                   (1 << 3)  |   /*FrameBitRateMinReportMask*/
 287                   (1 << 2)  |   /*FrameBitRateMaxReportMask*/
 288                   (1 << 1)  |   /*InterMBMaxSizeReportMask*/
 289                   (1 << 0) );   /*IntraMBMaxSizeReportMask*/
 290     OUT_BCS_BATCH(batch,                        /*Inter and Intra Conformance Max size limit*/
 291                   (0x0600 << 16) |              /*InterMbMaxSz 192 Byte*/
 292                   (0x0800) );                   /*IntraMbMaxSz 256 Byte*/
 293     OUT_BCS_BATCH(batch, 0x00000000);   /*Reserved : MBZReserved*/
 294     OUT_BCS_BATCH(batch, 0x01020304);   /*Slice QP Delta for bitrate control*/
 295     OUT_BCS_BATCH(batch, 0xFEFDFCFB);
 296     OUT_BCS_BATCH(batch, 0x80601004);   /*MAX = 128KB, MIN = 64KB*/
 297     OUT_BCS_BATCH(batch, 0x00800001);
 298     OUT_BCS_BATCH(batch, 0);
 299
 300     ADVANCE_BCS_BATCH(batch);
 301 }
 302
 303 static void
 304 gen6_mfc_avc_directmode_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 305 {
 306     struct intel_batchbuffer *batch = encoder_context->base.batch;
 307     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 308
 309     int i;
 310
 311     BEGIN_BCS_BATCH(batch, 69);
 312
 313     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
 314
 315     /* Reference frames and Current frames */
 316     for(i = 0; i < NUM_MFC_DMV_BUFFERS; i++) {
 317         if ( mfc_context->direct_mv_buffers[i].bo != NULL) {
 318             OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[i].bo,
 319                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 320                           0);
 321         } else {
 322             OUT_BCS_BATCH(batch, 0);
 323         }
 324     }
 325
 326     /* POL list */
 327     for(i = 0; i < 32; i++) {
 328         OUT_BCS_BATCH(batch, i/2);
 329     }
 330     OUT_BCS_BATCH(batch, 0);
 331     OUT_BCS_BATCH(batch, 0);
 332
 333     ADVANCE_BCS_BATCH(batch);
 334 }
 335
 336 static void
 337 gen6_mfc_avc_slice_state(VADriverContextP ctx,
 338                          VAEncPictureParameterBufferH264 *pic_param,
 339                          VAEncSliceParameterBufferH264 *slice_param,
 340                          struct encode_state *encode_state,
 341                          struct intel_encoder_context *encoder_context,
 342                          int rate_control_enable,
 343                          int qp,
 344                          struct intel_batchbuffer *batch)
 345 {
 346     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 347     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 348     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 349     int beginmb = slice_param->macroblock_address;
 350     int endmb = beginmb + slice_param->num_macroblocks;
 351     int beginx = beginmb % width_in_mbs;
 352     int beginy = beginmb / width_in_mbs;
 353     int nextx =  endmb % width_in_mbs;
 354     int nexty = endmb / width_in_mbs;
 355     int slice_type = slice_param->slice_type;
 356     int last_slice = (endmb == (width_in_mbs * height_in_mbs));
 357     int bit_rate_control_target, maxQpN, maxQpP;
 358     unsigned char correct[6], grow, shrink;
 359     int i;
 360     int weighted_pred_idc = 0;
 361     unsigned int luma_log2_weight_denom = slice_param->luma_log2_weight_denom;
 362     unsigned int chroma_log2_weight_denom = slice_param->chroma_log2_weight_denom;
 363     int bslice = 0;
 364
 365     if (batch == NULL)
 366         batch = encoder_context->base.batch;
 367
 368     bit_rate_control_target = slice_type;
 369     if (slice_type == SLICE_TYPE_SP)
 370         bit_rate_control_target = SLICE_TYPE_P;
 371     else if (slice_type == SLICE_TYPE_SI)
 372         bit_rate_control_target = SLICE_TYPE_I;
 373
 374     if (slice_type == SLICE_TYPE_P) {
 375         weighted_pred_idc = pic_param->pic_fields.bits.weighted_pred_flag;
 376     } else if (slice_type == SLICE_TYPE_B) {
 377         weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc;
 378         bslice = 1;
 379
 380         if (weighted_pred_idc == 2) {
 381             /* 8.4.3 - Derivation process for prediction weights (8-279) */
 382             luma_log2_weight_denom = 5;
 383             chroma_log2_weight_denom = 5;
 384         }
 385     }
 386
 387     maxQpN = mfc_context->bit_rate_control_context[bit_rate_control_target].MaxQpNegModifier;
 388     maxQpP = mfc_context->bit_rate_control_context[bit_rate_control_target].MaxQpPosModifier;
 389
 390     for (i = 0; i < 6; i++)
 391         correct[i] = mfc_context->bit_rate_control_context[bit_rate_control_target].Correct[i];
 392
 393     grow = mfc_context->bit_rate_control_context[bit_rate_control_target].GrowInit +
 394         (mfc_context->bit_rate_control_context[bit_rate_control_target].GrowResistance << 4);
 395     shrink = mfc_context->bit_rate_control_context[bit_rate_control_target].ShrinkInit +
 396         (mfc_context->bit_rate_control_context[bit_rate_control_target].ShrinkResistance << 4);
 397
 398     BEGIN_BCS_BATCH(batch, 11);;
 399
 400     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) );
 401     OUT_BCS_BATCH(batch, slice_type);                   /*Slice Type: I:P:B Slice*/
 402
 403     if (slice_type == SLICE_TYPE_I) {
 404         OUT_BCS_BATCH(batch, 0);                        /*no reference frames and pred_weight_table*/
 405     } else {
 406         OUT_BCS_BATCH(batch,
 407                       (1 << 16) | (bslice << 24) |     /*1 reference frame*/
 408                       (chroma_log2_weight_denom << 8) |
 409                       (luma_log2_weight_denom << 0));
 410     }
 411
 412     OUT_BCS_BATCH(batch,
 413                   (weighted_pred_idc << 30) |
 414                   (slice_param->direct_spatial_mv_pred_flag<<29) |             /*Direct Prediction Type*/
 415                   (slice_param->disable_deblocking_filter_idc << 27) |
 416                   (slice_param->cabac_init_idc << 24) |
 417                   (qp<<16) |                    /*Slice Quantization Parameter*/
 418                   ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
 419                   ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
 420     OUT_BCS_BATCH(batch,
 421                   (beginy << 24) |                      /*First MB X&Y , the begin postion of current slice*/
 422                   (beginx << 16) |
 423                   slice_param->macroblock_address );
 424     OUT_BCS_BATCH(batch, (nexty << 16) | nextx);                       /*Next slice first MB X&Y*/
 425     OUT_BCS_BATCH(batch,
 426                   (0/*rate_control_enable*/ << 31) |            /*in CBR mode RateControlCounterEnable = enable*/
 427                   (1 << 30) |           /*ResetRateControlCounter*/
 428                   (0 << 28) |           /*RC Triggle Mode = Always Rate Control*/
 429                   (4 << 24) |     /*RC Stable Tolerance, middle level*/
 430                   (0/*rate_control_enable*/ << 23) |     /*RC Panic Enable*/
 431                   (0 << 22) |     /*QP mode, don't modfiy CBP*/
 432                   (0 << 21) |     /*MB Type Direct Conversion Enabled*/
 433                   (0 << 20) |     /*MB Type Skip Conversion Enabled*/
 434                   (last_slice << 19) |     /*IsLastSlice*/
 435                   (0 << 18) |   /*BitstreamOutputFlag Compressed BitStream Output Disable Flag 0:enable 1:disable*/
 436                   (1 << 17) |       /*HeaderPresentFlag*/
 437                   (1 << 16) |       /*SliceData PresentFlag*/
 438                   (1 << 15) |       /*TailPresentFlag*/
 439                   (1 << 13) |       /*RBSP NAL TYPE*/
 440                   (0 << 12) );    /*CabacZeroWordInsertionEnable*/
 441     OUT_BCS_BATCH(batch, mfc_context->mfc_indirect_pak_bse_object.offset);
 442     OUT_BCS_BATCH(batch,
 443                   (maxQpN << 24) |     /*Target QP - 24 is lowest QP*/
 444                   (maxQpP << 16) |     /*Target QP + 20 is highest QP*/
 445                   (shrink << 8)  |
 446                   (grow << 0));
 447     OUT_BCS_BATCH(batch,
 448                   (correct[5] << 20) |
 449                   (correct[4] << 16) |
 450                   (correct[3] << 12) |
 451                   (correct[2] << 8) |
 452                   (correct[1] << 4) |
 453                   (correct[0] << 0));
 454     OUT_BCS_BATCH(batch, 0);
 455
 456     ADVANCE_BCS_BATCH(batch);
 457 }
 458 static void gen6_mfc_avc_qm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 459 {
 460     struct intel_batchbuffer *batch = encoder_context->base.batch;
 461     int i;
 462
 463     BEGIN_BCS_BATCH(batch, 58);
 464
 465     OUT_BCS_BATCH(batch, MFX_AVC_QM_STATE | 56);
 466     OUT_BCS_BATCH(batch, 0xFF ) ;
 467     for( i = 0; i < 56; i++) {
 468         OUT_BCS_BATCH(batch, 0x10101010);
 469     }
 470
 471     ADVANCE_BCS_BATCH(batch);
 472 }
 473
 474 static void gen6_mfc_avc_fqm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 475 {
 476     struct intel_batchbuffer *batch = encoder_context->base.batch;
 477     int i;
 478
 479     BEGIN_BCS_BATCH(batch, 113);
 480     OUT_BCS_BATCH(batch, MFC_AVC_FQM_STATE | (113 - 2));
 481
 482     for(i = 0; i < 112;i++) {
 483         OUT_BCS_BATCH(batch, 0x10001000);
 484     }
 485
 486     ADVANCE_BCS_BATCH(batch);
 487 }
 488
 489 static void
 490 gen6_mfc_avc_ref_idx_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 491 {
 492     struct intel_batchbuffer *batch = encoder_context->base.batch;
 493     int i;
 494
 495     BEGIN_BCS_BATCH(batch, 10);
 496     OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
 497     OUT_BCS_BATCH(batch, 0);                  //Select L0
 498     OUT_BCS_BATCH(batch, 0x80808020);         //Only 1 reference
 499     for(i = 0; i < 7; i++) {
 500         OUT_BCS_BATCH(batch, 0x80808080);
 501     }
 502     ADVANCE_BCS_BATCH(batch);
 503
 504     BEGIN_BCS_BATCH(batch, 10);
 505     OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
 506     OUT_BCS_BATCH(batch, 1);                  //Select L1
 507     OUT_BCS_BATCH(batch, 0x80808022);         //Only 1 reference
 508     for(i = 0; i < 7; i++) {
 509         OUT_BCS_BATCH(batch, 0x80808080);
 510     }
 511     ADVANCE_BCS_BATCH(batch);
 512 }
 513
 514 static void
 515 gen6_mfc_avc_insert_object(VADriverContextP ctx, struct intel_encoder_context *encoder_context,
 516                            unsigned int *insert_data, int lenght_in_dws, int data_bits_in_last_dw,
 517                            int skip_emul_byte_count, int is_last_header, int is_end_of_slice, int emulation_flag,
 518                            struct intel_batchbuffer *batch)
 519 {
 520     if (batch == NULL)
 521         batch = encoder_context->base.batch;
 522
 523     BEGIN_BCS_BATCH(batch, lenght_in_dws + 2);
 524
 525     OUT_BCS_BATCH(batch, MFC_AVC_INSERT_OBJECT | (lenght_in_dws + 2 - 2));
 526
 527     OUT_BCS_BATCH(batch,
 528                   (0 << 16) |   /* always start at offset 0 */
 529                   (data_bits_in_last_dw << 8) |
 530                   (skip_emul_byte_count << 4) |
 531                   (!!emulation_flag << 3) |
 532                   ((!!is_last_header) << 2) |
 533                   ((!!is_end_of_slice) << 1) |
 534                   (0 << 0));    /* FIXME: ??? */
 535
 536     intel_batchbuffer_data(batch, insert_data, lenght_in_dws * 4);
 537     ADVANCE_BCS_BATCH(batch);
 538 }
 539
 540 void
 541 gen6_mfc_init(VADriverContextP ctx,
 542               struct encode_state *encode_state,
 543               struct intel_encoder_context *encoder_context)
 544 {
 545     struct i965_driver_data *i965 = i965_driver_data(ctx);
 546     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 547     dri_bo *bo;
 548     int i;
 549     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 550     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 551     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 552
 553     /*Encode common setup for MFC*/
 554     dri_bo_unreference(mfc_context->post_deblocking_output.bo);
 555     mfc_context->post_deblocking_output.bo = NULL;
 556
 557     dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
 558     mfc_context->pre_deblocking_output.bo = NULL;
 559
 560     dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
 561     mfc_context->uncompressed_picture_source.bo = NULL;
 562
 563     dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
 564     mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
 565
 566     for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
 567         if ( mfc_context->direct_mv_buffers[i].bo != NULL);
 568         dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
 569         mfc_context->direct_mv_buffers[i].bo = NULL;
 570     }
 571
 572     for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
 573         if (mfc_context->reference_surfaces[i].bo != NULL)
 574             dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
 575         mfc_context->reference_surfaces[i].bo = NULL;
 576     }
 577
 578     dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
 579     bo = dri_bo_alloc(i965->intel.bufmgr,
 580                       "Buffer",
 581                       width_in_mbs * 64,
 582                       64);
 583     assert(bo);
 584     mfc_context->intra_row_store_scratch_buffer.bo = bo;
 585
 586     dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
 587     bo = dri_bo_alloc(i965->intel.bufmgr,
 588                       "Buffer",
 589                       width_in_mbs * height_in_mbs * 16,
 590                       64);
 591     assert(bo);
 592     mfc_context->macroblock_status_buffer.bo = bo;
 593
 594     dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
 595     bo = dri_bo_alloc(i965->intel.bufmgr,
 596                       "Buffer",
 597                       4 * width_in_mbs * 64,  /* 4 * width_in_mbs * 64 */
 598                       64);
 599     assert(bo);
 600     mfc_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
 601
 602     dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
 603     bo = dri_bo_alloc(i965->intel.bufmgr,
 604                       "Buffer",
 605                       128 * width_in_mbs, /* 2 * widht_in_mbs * 64 */
 606                       0x1000);
 607     assert(bo);
 608     mfc_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
 609
 610     dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo);
 611     mfc_context->mfc_batchbuffer_surface.bo = NULL;
 612
 613     dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo);
 614     mfc_context->aux_batchbuffer_surface.bo = NULL;
 615
 616     if (mfc_context->aux_batchbuffer)
 617         intel_batchbuffer_free(mfc_context->aux_batchbuffer);
 618
 619     mfc_context->aux_batchbuffer = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD, 0);
 620     mfc_context->aux_batchbuffer_surface.bo = mfc_context->aux_batchbuffer->buffer;
 621     dri_bo_reference(mfc_context->aux_batchbuffer_surface.bo);
 622     mfc_context->aux_batchbuffer_surface.pitch = 16;
 623     mfc_context->aux_batchbuffer_surface.num_blocks = mfc_context->aux_batchbuffer->size / 16;
 624     mfc_context->aux_batchbuffer_surface.size_block = 16;
 625
 626     i965_gpe_context_init(ctx, &mfc_context->gpe_context);
 627 }
 628
 629 static void gen6_mfc_avc_pipeline_picture_programing( VADriverContextP ctx,
 630                                       struct encode_state *encode_state,
 631                                       struct intel_encoder_context *encoder_context)
 632 {
 633     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 634
 635     mfc_context->pipe_mode_select(ctx, MFX_FORMAT_AVC, encoder_context);
 636     mfc_context->set_surface_state(ctx, encoder_context);
 637     mfc_context->ind_obj_base_addr_state(ctx, encoder_context);
 638     gen6_mfc_pipe_buf_addr_state(ctx, encoder_context);
 639     gen6_mfc_bsp_buf_base_addr_state(ctx, encoder_context);
 640     mfc_context->avc_img_state(ctx, encode_state, encoder_context);
 641     mfc_context->avc_qm_state(ctx, encoder_context);
 642     mfc_context->avc_fqm_state(ctx, encoder_context);
 643     gen6_mfc_avc_directmode_state(ctx, encoder_context);
 644     gen6_mfc_avc_ref_idx_state(ctx, encoder_context);
 645 }
 646
 647
 648 VAStatus
 649 gen6_mfc_run(VADriverContextP ctx,
 650              struct encode_state *encode_state,
 651              struct intel_encoder_context *encoder_context)
 652 {
 653     struct intel_batchbuffer *batch = encoder_context->base.batch;
 654
 655     intel_batchbuffer_flush(batch);             //run the pipeline
 656
 657     return VA_STATUS_SUCCESS;
 658 }
 659
 660 VAStatus
 661 gen6_mfc_stop(VADriverContextP ctx,
 662               struct encode_state *encode_state,
 663               struct intel_encoder_context *encoder_context,
 664               int *encoded_bits_size)
 665 {
 666     VAStatus vaStatus = VA_STATUS_ERROR_UNKNOWN;
 667     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 668     VACodedBufferSegment *coded_buffer_segment;
 669
 670     vaStatus = i965_MapBuffer(ctx, pPicParameter->coded_buf, (void **)&coded_buffer_segment);
 671     assert(vaStatus == VA_STATUS_SUCCESS);
 672     *encoded_bits_size = coded_buffer_segment->size * 8;
 673     i965_UnmapBuffer(ctx, pPicParameter->coded_buf);
 674
 675     return VA_STATUS_SUCCESS;
 676 }
 677
 678 #if __SOFTWARE__
 679
 680 static int
 681 gen6_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb, int qp,unsigned int *msg,
 682                               struct intel_encoder_context *encoder_context,
 683                               unsigned char target_mb_size, unsigned char max_mb_size,
 684                               struct intel_batchbuffer *batch)
 685 {
 686     int len_in_dwords = 11;
 687
 688     if (batch == NULL)
 689         batch = encoder_context->base.batch;
 690
 691     BEGIN_BCS_BATCH(batch, len_in_dwords);
 692
 693     OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
 694     OUT_BCS_BATCH(batch, 0);
 695     OUT_BCS_BATCH(batch, 0);
 696     OUT_BCS_BATCH(batch,
 697                   (0 << 24) |           /* PackedMvNum, Debug*/
 698                   (0 << 20) |           /* No motion vector */
 699                   (1 << 19) |           /* CbpDcY */
 700                   (1 << 18) |           /* CbpDcU */
 701                   (1 << 17) |           /* CbpDcV */
 702                   (msg[0] & 0xFFFF) );
 703
 704     OUT_BCS_BATCH(batch, (0xFFFF << 16) | (y << 8) | x);                /* Code Block Pattern for Y*/
 705     OUT_BCS_BATCH(batch, 0x000F000F);                                                   /* Code Block Pattern */
 706     OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp);      /* Last MB */
 707
 708     /*Stuff for Intra MB*/
 709     OUT_BCS_BATCH(batch, msg[1]);                       /* We using Intra16x16 no 4x4 predmode*/
 710     OUT_BCS_BATCH(batch, msg[2]);
 711     OUT_BCS_BATCH(batch, msg[3]&0xFC);
 712
 713     /*MaxSizeInWord and TargetSzieInWord*/
 714     OUT_BCS_BATCH(batch, (max_mb_size << 24) |
 715                   (target_mb_size << 16) );
 716
 717     ADVANCE_BCS_BATCH(batch);
 718
 719     return len_in_dwords;
 720 }
 721
 722 static int
 723 gen6_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, int qp,
 724                               unsigned int *msg, unsigned int offset,
 725                               struct intel_encoder_context *encoder_context,
 726                               unsigned char target_mb_size,unsigned char max_mb_size, int slice_type,
 727                               struct intel_batchbuffer *batch)
 728 {
 729     int len_in_dwords = 11;
 730
 731     if (batch == NULL)
 732         batch = encoder_context->base.batch;
 733
 734     BEGIN_BCS_BATCH(batch, len_in_dwords);
 735
 736     OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
 737
 738     OUT_BCS_BATCH(batch, msg[2]);         /* 32 MV*/
 739     OUT_BCS_BATCH(batch, offset);
 740
 741     OUT_BCS_BATCH(batch, msg[0]);
 742
 743     OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x);        /* Code Block Pattern for Y*/
 744     OUT_BCS_BATCH(batch, 0x000F000F);                         /* Code Block Pattern */
 745 #if 0
 746     if ( slice_type == SLICE_TYPE_B) {
 747         OUT_BCS_BATCH(batch, (0xF<<28) | (end_mb << 26) | qp);  /* Last MB */
 748     } else {
 749         OUT_BCS_BATCH(batch, (end_mb << 26) | qp);      /* Last MB */
 750     }
 751 #else
 752     OUT_BCS_BATCH(batch, (end_mb << 26) | qp);  /* Last MB */
 753 #endif
 754
 755
 756     /*Stuff for Inter MB*/
 757     OUT_BCS_BATCH(batch, msg[1]);
 758     OUT_BCS_BATCH(batch, 0x0);
 759     OUT_BCS_BATCH(batch, 0x0);
 760
 761     /*MaxSizeInWord and TargetSzieInWord*/
 762     OUT_BCS_BATCH(batch, (max_mb_size << 24) |
 763                   (target_mb_size << 16) );
 764
 765     ADVANCE_BCS_BATCH(batch);
 766
 767     return len_in_dwords;
 768 }
 769
 770 static void
 771 gen6_mfc_avc_pipeline_slice_programing(VADriverContextP ctx,
 772                                        struct encode_state *encode_state,
 773                                        struct intel_encoder_context *encoder_context,
 774                                        int slice_index,
 775                                        struct intel_batchbuffer *slice_batch)
 776 {
 777     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 778     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 779     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 780     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 781     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
 782     unsigned int *msg = NULL, offset = 0;
 783     int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
 784     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 785     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 786     int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs);
 787     int i,x,y;
 788     int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta;
 789     unsigned int rate_control_mode = encoder_context->rate_control_mode;
 790     unsigned char *slice_header = NULL;
 791     int slice_header_length_in_bits = 0;
 792     unsigned int tail_data[] = { 0x0, 0x0 };
 793     int slice_type = pSliceParameter->slice_type;
 794
 795
 796     if (rate_control_mode == VA_RC_CBR) {
 797         qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
 798         pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp;
 799     }
 800
 801     /* only support for 8-bit pixel bit-depth */
 802     assert(pSequenceParameter->bit_depth_luma_minus8 == 0);
 803     assert(pSequenceParameter->bit_depth_chroma_minus8 == 0);
 804     assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52);
 805     assert(qp >= 0 && qp < 52);
 806
 807     gen6_mfc_avc_slice_state(ctx,
 808                              pPicParameter,
 809                              pSliceParameter,
 810                              encode_state, encoder_context,
 811                              (rate_control_mode == VA_RC_CBR), qp, slice_batch);
 812
 813     if ( slice_index == 0)
 814         intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch);
 815
 816     slice_header_length_in_bits = build_avc_slice_header(pSequenceParameter, pPicParameter, pSliceParameter, &slice_header);
 817
 818     // slice hander
 819     mfc_context->insert_object(ctx, encoder_context,
 820                                (unsigned int *)slice_header, ALIGN(slice_header_length_in_bits, 32) >> 5, slice_header_length_in_bits & 0x1f,
 821                                5,  /* first 5 bytes are start code + nal unit type */
 822                                1, 0, 1, slice_batch);
 823
 824     dri_bo_map(vme_context->vme_output.bo , 1);
 825     msg = (unsigned int *)vme_context->vme_output.bo->virtual;
 826
 827     if (is_intra) {
 828         msg += pSliceParameter->macroblock_address * INTRA_VME_OUTPUT_IN_DWS;
 829     } else {
 830         msg += pSliceParameter->macroblock_address * INTER_VME_OUTPUT_IN_DWS;
 831         msg += 32; /* the first 32 DWs are MVs */
 832         offset = pSliceParameter->macroblock_address * INTER_VME_OUTPUT_IN_BYTES;
 833     }
 834
 835     for (i = pSliceParameter->macroblock_address;
 836          i < pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks; i++) {
 837         int last_mb = (i == (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks - 1) );
 838         x = i % width_in_mbs;
 839         y = i / width_in_mbs;
 840
 841         if (is_intra) {
 842             assert(msg);
 843             gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch);
 844             msg += INTRA_VME_OUTPUT_IN_DWS;
 845         } else {
 846             if (msg[0] & INTRA_MB_FLAG_MASK) {
 847                 gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch);
 848             } else {
 849                 gen6_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, msg, offset, encoder_context, 0, 0, pSliceParameter->slice_type, slice_batch);
 850             }
 851
 852             msg += INTER_VME_OUTPUT_IN_DWS;
 853             offset += INTER_VME_OUTPUT_IN_BYTES;
 854         }
 855     }
 856
 857     dri_bo_unmap(vme_context->vme_output.bo);
 858
 859     if ( last_slice ) {
 860         mfc_context->insert_object(ctx, encoder_context,
 861                                    tail_data, 2, 8,
 862                                    2, 1, 1, 0, slice_batch);
 863     } else {
 864         mfc_context->insert_object(ctx, encoder_context,
 865                                    tail_data, 1, 8,
 866                                    1, 1, 1, 0, slice_batch);
 867     }
 868
 869     free(slice_header);
 870
 871 }
 872
 873 static dri_bo *
 874 gen6_mfc_avc_software_batchbuffer(VADriverContextP ctx,
 875                                   struct encode_state *encode_state,
 876                                   struct intel_encoder_context *encoder_context)
 877 {
 878     struct i965_driver_data *i965 = i965_driver_data(ctx);
 879     struct intel_batchbuffer *batch = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD, 0);
 880     dri_bo *batch_bo = batch->buffer;
 881     int i;
 882
 883     for (i = 0; i < encode_state->num_slice_params_ext; i++) {
 884         gen6_mfc_avc_pipeline_slice_programing(ctx, encode_state, encoder_context, i, batch);
 885     }
 886
 887     intel_batchbuffer_align(batch, 8);
 888
 889     BEGIN_BCS_BATCH(batch, 2);
 890     OUT_BCS_BATCH(batch, 0);
 891     OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_END);
 892     ADVANCE_BCS_BATCH(batch);
 893
 894     dri_bo_reference(batch_bo);
 895     intel_batchbuffer_free(batch);
 896
 897     return batch_bo;
 898 }
 899
 900 #else
 901
 902 static void
 903 gen6_mfc_batchbuffer_surfaces_input(VADriverContextP ctx,
 904                                     struct encode_state *encode_state,
 905                                     struct intel_encoder_context *encoder_context)
 906
 907 {
 908     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 909     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 910
 911     assert(vme_context->vme_output.bo);
 912     mfc_context->buffer_suface_setup(ctx,
 913                                      &mfc_context->gpe_context,
 914                                      &vme_context->vme_output,
 915                                      BINDING_TABLE_OFFSET(BIND_IDX_VME_OUTPUT),
 916                                      SURFACE_STATE_OFFSET(BIND_IDX_VME_OUTPUT));
 917     assert(mfc_context->aux_batchbuffer_surface.bo);
 918     mfc_context->buffer_suface_setup(ctx,
 919                                      &mfc_context->gpe_context,
 920                                      &mfc_context->aux_batchbuffer_surface,
 921                                      BINDING_TABLE_OFFSET(BIND_IDX_MFC_SLICE_HEADER),
 922                                      SURFACE_STATE_OFFSET(BIND_IDX_MFC_SLICE_HEADER));
 923 }
 924
 925 static void
 926 gen6_mfc_batchbuffer_surfaces_output(VADriverContextP ctx,
 927                                      struct encode_state *encode_state,
 928                                      struct intel_encoder_context *encoder_context)
 929
 930 {
 931     struct i965_driver_data *i965 = i965_driver_data(ctx);
 932     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 933     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 934     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 935     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 936     mfc_context->mfc_batchbuffer_surface.num_blocks = width_in_mbs * height_in_mbs + encode_state->num_slice_params_ext * 8 + 1;
 937     mfc_context->mfc_batchbuffer_surface.size_block = 16 * CMD_LEN_IN_OWORD; /* 3 OWORDs */
 938     mfc_context->mfc_batchbuffer_surface.pitch = 16;
 939     mfc_context->mfc_batchbuffer_surface.bo = dri_bo_alloc(i965->intel.bufmgr,
 940                                                            "MFC batchbuffer",
 941                                                            mfc_context->mfc_batchbuffer_surface.num_blocks * mfc_context->mfc_batchbuffer_surface.size_block,
 942                                                            0x1000);
 943     mfc_context->buffer_suface_setup(ctx,
 944                                      &mfc_context->gpe_context,
 945                                      &mfc_context->mfc_batchbuffer_surface,
 946                                      BINDING_TABLE_OFFSET(BIND_IDX_MFC_BATCHBUFFER),
 947                                      SURFACE_STATE_OFFSET(BIND_IDX_MFC_BATCHBUFFER));
 948 }
 949
 950 static void
 951 gen6_mfc_batchbuffer_surfaces_setup(VADriverContextP ctx,
 952                                     struct encode_state *encode_state,
 953                                     struct intel_encoder_context *encoder_context)
 954 {
 955     gen6_mfc_batchbuffer_surfaces_input(ctx, encode_state, encoder_context);
 956     gen6_mfc_batchbuffer_surfaces_output(ctx, encode_state, encoder_context);
 957 }
 958
 959 static void
 960 gen6_mfc_batchbuffer_idrt_setup(VADriverContextP ctx,
 961                                 struct encode_state *encode_state,
 962                                 struct intel_encoder_context *encoder_context)
 963 {
 964     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 965     struct gen6_interface_descriptor_data *desc;
 966     int i;
 967     dri_bo *bo;
 968
 969     bo = mfc_context->gpe_context.idrt.bo;
 970     dri_bo_map(bo, 1);
 971     assert(bo->virtual);
 972     desc = bo->virtual;
 973
 974     for (i = 0; i < mfc_context->gpe_context.num_kernels; i++) {
 975         struct i965_kernel *kernel;
 976
 977         kernel = &mfc_context->gpe_context.kernels[i];
 978         assert(sizeof(*desc) == 32);
 979
 980         /*Setup the descritor table*/
 981         memset(desc, 0, sizeof(*desc));
 982         desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6);
 983         desc->desc2.sampler_count = 0;
 984         desc->desc2.sampler_state_pointer = 0;
 985         desc->desc3.binding_table_entry_count = 2;
 986         desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5);
 987         desc->desc4.constant_urb_entry_read_offset = 0;
 988         desc->desc4.constant_urb_entry_read_length = 4;
 989
 990         /*kernel start*/
 991         dri_bo_emit_reloc(bo,
 992                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 993                           0,
 994                           i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0),
 995                           kernel->bo);
 996         desc++;
 997     }
 998
 999     dri_bo_unmap(bo);
1000 }
1001
1002 static void
1003 gen6_mfc_batchbuffer_constant_setup(VADriverContextP ctx,
1004                                     struct encode_state *encode_state,
1005                                     struct intel_encoder_context *encoder_context)
1006 {
1007     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1008
1009     (void)mfc_context;
1010 }
1011
1012 static void
1013 gen6_mfc_batchbuffer_emit_object_command(struct intel_batchbuffer *batch,
1014                                          int index,
1015                                          int head_offset,
1016                                          int batchbuffer_offset,
1017                                          int head_size,
1018                                          int tail_size,
1019                                          int number_mb_cmds,
1020                                          int first_object,
1021                                          int last_object,
1022                                          int last_slice,
1023                                          int mb_x,
1024                                          int mb_y,
1025                                          int width_in_mbs,
1026                                          int qp)
1027 {
1028     BEGIN_BATCH(batch, 12);
1029
1030     OUT_BATCH(batch, CMD_MEDIA_OBJECT | (12 - 2));
1031     OUT_BATCH(batch, index);
1032     OUT_BATCH(batch, 0);
1033     OUT_BATCH(batch, 0);
1034     OUT_BATCH(batch, 0);
1035     OUT_BATCH(batch, 0);
1036
1037     /*inline data */
1038     OUT_BATCH(batch, head_offset);
1039     OUT_BATCH(batch, batchbuffer_offset);
1040     OUT_BATCH(batch,
1041               head_size << 16 |
1042               tail_size);
1043     OUT_BATCH(batch,
1044               number_mb_cmds << 16 |
1045               first_object << 2 |
1046               last_object << 1 |
1047               last_slice);
1048     OUT_BATCH(batch,
1049               mb_y << 8 |
1050               mb_x);
1051     OUT_BATCH(batch,
1052               qp << 16 |
1053               width_in_mbs);
1054
1055     ADVANCE_BATCH(batch);
1056 }
1057
1058 static void
1059 gen6_mfc_avc_batchbuffer_slice_command(VADriverContextP ctx,
1060                                        struct intel_encoder_context *encoder_context,
1061                                        VAEncSliceParameterBufferH264 *slice_param,
1062                                        int head_offset,
1063                                        unsigned short head_size,
1064                                        unsigned short tail_size,
1065                                        int batchbuffer_offset,
1066                                        int qp,
1067                                        int last_slice)
1068 {
1069     struct intel_batchbuffer *batch = encoder_context->base.batch;
1070     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1071     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
1072     int total_mbs = slice_param->num_macroblocks;
1073     int number_mb_cmds = 128;
1074     int starting_mb = 0;
1075     int last_object = 0;
1076     int first_object = 1;
1077     int i;
1078     int mb_x, mb_y;
1079     int index = (slice_param->slice_type == SLICE_TYPE_I) ? MFC_BATCHBUFFER_AVC_INTRA : MFC_BATCHBUFFER_AVC_INTER;
1080
1081     for (i = 0; i < total_mbs / number_mb_cmds; i++) {
1082         last_object = (total_mbs - starting_mb) == number_mb_cmds;
1083         mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs;
1084         mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs;
1085         assert(mb_x <= 255 && mb_y <= 255);
1086
1087         starting_mb += number_mb_cmds;
1088
1089         gen6_mfc_batchbuffer_emit_object_command(batch,
1090                                                  index,
1091                                                  head_offset,
1092                                                  batchbuffer_offset,
1093                                                  head_size,
1094                                                  tail_size,
1095                                                  number_mb_cmds,
1096                                                  first_object,
1097                                                  last_object,
1098                                                  last_slice,
1099                                                  mb_x,
1100                                                  mb_y,
1101                                                  width_in_mbs,
1102                                                  qp);
1103
1104         if (first_object) {
1105             head_offset += head_size;
1106             batchbuffer_offset += head_size;
1107         }
1108
1109         if (last_object) {
1110             head_offset += tail_size;
1111             batchbuffer_offset += tail_size;
1112         }
1113
1114         batchbuffer_offset += number_mb_cmds * CMD_LEN_IN_OWORD;
1115
1116         first_object = 0;
1117     }
1118
1119     if (!last_object) {
1120         last_object = 1;
1121         number_mb_cmds = total_mbs % number_mb_cmds;
1122         mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs;
1123         mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs;
1124         assert(mb_x <= 255 && mb_y <= 255);
1125         starting_mb += number_mb_cmds;
1126
1127         gen6_mfc_batchbuffer_emit_object_command(batch,
1128                                                  index,
1129                                                  head_offset,
1130                                                  batchbuffer_offset,
1131                                                  head_size,
1132                                                  tail_size,
1133                                                  number_mb_cmds,
1134                                                  first_object,
1135                                                  last_object,
1136                                                  last_slice,
1137                                                  mb_x,
1138                                                  mb_y,
1139                                                  width_in_mbs,
1140                                                  qp);
1141     }
1142 }
1143
1144 /*
1145  * return size in Owords (16bytes)
1146  */
1147 static int
1148 gen6_mfc_avc_batchbuffer_slice(VADriverContextP ctx,
1149                                struct encode_state *encode_state,
1150                                struct intel_encoder_context *encoder_context,
1151                                int slice_index,
1152                                int batchbuffer_offset)
1153 {
1154     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1155     struct intel_batchbuffer *slice_batch = mfc_context->aux_batchbuffer;
1156     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
1157     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
1158     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
1159     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
1160     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
1161     int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs);
1162     int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta;
1163     unsigned int rate_control_mode = encoder_context->rate_control_mode;
1164     unsigned char *slice_header = NULL;
1165     int slice_header_length_in_bits = 0;
1166     unsigned int tail_data[] = { 0x0, 0x0 };
1167     long head_offset;
1168     int old_used = intel_batchbuffer_used_size(slice_batch), used;
1169     unsigned short head_size, tail_size;
1170     int slice_type = pSliceParameter->slice_type;
1171
1172     if (rate_control_mode == VA_RC_CBR) {
1173         qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
1174         pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp;
1175     }
1176
1177     /* only support for 8-bit pixel bit-depth */
1178     assert(pSequenceParameter->bit_depth_luma_minus8 == 0);
1179     assert(pSequenceParameter->bit_depth_chroma_minus8 == 0);
1180     assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52);
1181     assert(qp >= 0 && qp < 52);
1182
1183     head_offset = old_used / 16;
1184     gen6_mfc_avc_slice_state(ctx,
1185                              pPicParameter,
1186                              pSliceParameter,
1187                              encode_state,
1188                              encoder_context,
1189                              (rate_control_mode == VA_RC_CBR),
1190                              qp,
1191                              slice_batch);
1192
1193     if (slice_index == 0)
1194         intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch);
1195
1196     slice_header_length_in_bits = build_avc_slice_header(pSequenceParameter, pPicParameter, pSliceParameter, &slice_header);
1197
1198     // slice hander
1199     mfc_context->insert_object(ctx,
1200                                encoder_context,
1201                                (unsigned int *)slice_header,
1202                                ALIGN(slice_header_length_in_bits, 32) >> 5,
1203                                slice_header_length_in_bits & 0x1f,
1204                                5,  /* first 5 bytes are start code + nal unit type */
1205                                1,
1206                                0,
1207                                1,
1208                                slice_batch);
1209     free(slice_header);
1210
1211     intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */
1212     used = intel_batchbuffer_used_size(slice_batch);
1213     head_size = (used - old_used) / 16;
1214     old_used = used;
1215
1216     /* tail */
1217     if (last_slice) {
1218         mfc_context->insert_object(ctx,
1219                                    encoder_context,
1220                                    tail_data,
1221                                    2,
1222                                    8,
1223                                    2,
1224                                    1,
1225                                    1,
1226                                    0,
1227                                    slice_batch);
1228     } else {
1229         mfc_context->insert_object(ctx,
1230                                    encoder_context,
1231                                    tail_data,
1232                                    1,
1233                                    8,
1234                                    1,
1235                                    1,
1236                                    1,
1237                                    0,
1238                                    slice_batch);
1239     }
1240
1241     intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */
1242     used = intel_batchbuffer_used_size(slice_batch);
1243     tail_size = (used - old_used) / 16;
1244
1245
1246     gen6_mfc_avc_batchbuffer_slice_command(ctx,
1247                                            encoder_context,
1248                                            pSliceParameter,
1249                                            head_offset,
1250                                            head_size,
1251                                            tail_size,
1252                                            batchbuffer_offset,
1253                                            qp,
1254                                            last_slice);
1255
1256     return head_size + tail_size + pSliceParameter->num_macroblocks * CMD_LEN_IN_OWORD;
1257 }
1258
1259 static void
1260 gen6_mfc_avc_batchbuffer_pipeline(VADriverContextP ctx,
1261                                   struct encode_state *encode_state,
1262                                   struct intel_encoder_context *encoder_context)
1263 {
1264     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1265     struct intel_batchbuffer *batch = encoder_context->base.batch;
1266     int i, size, offset = 0;
1267     intel_batchbuffer_start_atomic(batch, 0x4000);
1268     gen6_gpe_pipeline_setup(ctx, &mfc_context->gpe_context, batch);
1269
1270     for ( i = 0; i < encode_state->num_slice_params_ext; i++) {
1271         size = gen6_mfc_avc_batchbuffer_slice(ctx, encode_state, encoder_context, i, offset);
1272         offset += size;
1273     }
1274
1275     intel_batchbuffer_end_atomic(batch);
1276     intel_batchbuffer_flush(batch);
1277 }
1278
1279 static void
1280 gen6_mfc_build_avc_batchbuffer(VADriverContextP ctx,
1281                                struct encode_state *encode_state,
1282                                struct intel_encoder_context *encoder_context)
1283 {
1284     gen6_mfc_batchbuffer_surfaces_setup(ctx, encode_state, encoder_context);
1285     gen6_mfc_batchbuffer_idrt_setup(ctx, encode_state, encoder_context);
1286     gen6_mfc_batchbuffer_constant_setup(ctx, encode_state, encoder_context);
1287     gen6_mfc_avc_batchbuffer_pipeline(ctx, encode_state, encoder_context);
1288 }
1289
1290 static dri_bo *
1291 gen6_mfc_avc_hardware_batchbuffer(VADriverContextP ctx,
1292                                   struct encode_state *encode_state,
1293                                   struct intel_encoder_context *encoder_context)
1294 {
1295     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1296
1297     gen6_mfc_build_avc_batchbuffer(ctx, encode_state, encoder_context);
1298     dri_bo_reference(mfc_context->mfc_batchbuffer_surface.bo);
1299
1300     return mfc_context->mfc_batchbuffer_surface.bo;
1301 }
1302
1303 #endif
1304
1305
1306 static void
1307 gen6_mfc_avc_pipeline_programing(VADriverContextP ctx,
1308                                  struct encode_state *encode_state,
1309                                  struct intel_encoder_context *encoder_context)
1310 {
1311     struct intel_batchbuffer *batch = encoder_context->base.batch;
1312     dri_bo *slice_batch_bo;
1313
1314     if ( intel_mfc_interlace_check(ctx, encode_state, encoder_context) ) {
1315         fprintf(stderr, "Current VA driver don't support interlace mode!\n");
1316         assert(0);
1317         return;
1318     }
1319
1320 #if __SOFTWARE__
1321     slice_batch_bo = gen6_mfc_avc_software_batchbuffer(ctx, encode_state, encoder_context);
1322 #else
1323     slice_batch_bo = gen6_mfc_avc_hardware_batchbuffer(ctx, encode_state, encoder_context);
1324 #endif
1325
1326     // begin programing
1327     intel_batchbuffer_start_atomic_bcs(batch, 0x4000);
1328     intel_batchbuffer_emit_mi_flush(batch);
1329
1330     // picture level programing
1331     gen6_mfc_avc_pipeline_picture_programing(ctx, encode_state, encoder_context);
1332
1333     BEGIN_BCS_BATCH(batch, 2);
1334     OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8));
1335     OUT_BCS_RELOC(batch,
1336                   slice_batch_bo,
1337                   I915_GEM_DOMAIN_COMMAND, 0,
1338                   0);
1339     ADVANCE_BCS_BATCH(batch);
1340
1341     // end programing
1342     intel_batchbuffer_end_atomic(batch);
1343
1344     dri_bo_unreference(slice_batch_bo);
1345 }
1346
1347 VAStatus
1348 gen6_mfc_avc_encode_picture(VADriverContextP ctx,
1349                             struct encode_state *encode_state,
1350                             struct intel_encoder_context *encoder_context)
1351 {
1352     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1353     unsigned int rate_control_mode = encoder_context->rate_control_mode;
1354     int current_frame_bits_size;
1355     int sts;
1356
1357     for (;;) {
1358         gen6_mfc_init(ctx, encode_state, encoder_context);
1359         intel_mfc_avc_prepare(ctx, encode_state, encoder_context);
1360         /*Programing bcs pipeline*/
1361         gen6_mfc_avc_pipeline_programing(ctx, encode_state, encoder_context);   //filling the pipeline
1362         gen6_mfc_run(ctx, encode_state, encoder_context);
1363         if (rate_control_mode == VA_RC_CBR /*|| rate_control_mode == VA_RC_VBR*/) {
1364             gen6_mfc_stop(ctx, encode_state, encoder_context, &current_frame_bits_size);
1365             sts = intel_mfc_brc_postpack(encode_state, mfc_context, current_frame_bits_size);
1366             if (sts == BRC_NO_HRD_VIOLATION) {
1367                 intel_mfc_hrd_context_update(encode_state, mfc_context);
1368                 break;
1369             }
1370             else if (sts == BRC_OVERFLOW_WITH_MIN_QP || sts == BRC_UNDERFLOW_WITH_MAX_QP) {
1371                 if (!mfc_context->hrd.violation_noted) {
1372                     fprintf(stderr, "Unrepairable %s!\n", (sts == BRC_OVERFLOW_WITH_MIN_QP)? "overflow": "underflow");
1373                     mfc_context->hrd.violation_noted = 1;
1374                 }
1375                 return VA_STATUS_SUCCESS;
1376             }
1377         } else {
1378             break;
1379         }
1380     }
1381
1382     return VA_STATUS_SUCCESS;
1383 }
1384
1385 static void
1386 gen6_mfc_qm_state(VADriverContextP ctx,
1387                   int qm_type,
1388                   unsigned int *qm,
1389                   int qm_length,
1390                   struct intel_encoder_context *encoder_context)
1391 {
1392     struct intel_batchbuffer *batch = encoder_context->base.batch;
1393     unsigned int qm_buffer[16];
1394
1395     assert(qm_length <= 16);
1396     assert(sizeof(*qm) == 4);
1397     memcpy(qm_buffer, qm, qm_length * 4);
1398
1399     BEGIN_BCS_BATCH(batch, 18);
1400     OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2));
1401     OUT_BCS_BATCH(batch, qm_type << 0);
1402     intel_batchbuffer_data(batch, qm_buffer, 16 * 4);
1403     ADVANCE_BCS_BATCH(batch);
1404 }
1405
1406 static void
1407 gen6_mfc_fqm_state(VADriverContextP ctx,
1408                    int fqm_type,
1409                    unsigned int *fqm,
1410                    int fqm_length,
1411                    struct intel_encoder_context *encoder_context)
1412 {
1413     struct intel_batchbuffer *batch = encoder_context->base.batch;
1414     unsigned int fqm_buffer[32];
1415
1416     assert(fqm_length <= 32);
1417     assert(sizeof(*fqm) == 4);
1418     memcpy(fqm_buffer, fqm, fqm_length * 4);
1419
1420     BEGIN_BCS_BATCH(batch, 34);
1421     OUT_BCS_BATCH(batch, MFX_FQM_STATE | (34 - 2));
1422     OUT_BCS_BATCH(batch, fqm_type << 0);
1423     intel_batchbuffer_data(batch, fqm_buffer, 32 * 4);
1424     ADVANCE_BCS_BATCH(batch);
1425 }
1426
1427 VAStatus
1428 gen6_mfc_pipeline(VADriverContextP ctx,
1429                   VAProfile profile,
1430                   struct encode_state *encode_state,
1431                   struct intel_encoder_context *encoder_context)
1432 {
1433     VAStatus vaStatus;
1434
1435     switch (profile) {
1436     case VAProfileH264Baseline:
1437     case VAProfileH264Main:
1438     case VAProfileH264High:
1439         vaStatus = gen6_mfc_avc_encode_picture(ctx, encode_state, encoder_context);
1440         break;
1441
1442         /* FIXME: add for other profile */
1443     default:
1444         vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
1445         break;
1446     }
1447
1448     return vaStatus;
1449 }
1450
1451 void
1452 gen6_mfc_context_destroy(void *context)
1453 {
1454     struct gen6_mfc_context *mfc_context = context;
1455     int i;
1456
1457     dri_bo_unreference(mfc_context->post_deblocking_output.bo);
1458     mfc_context->post_deblocking_output.bo = NULL;
1459
1460     dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
1461     mfc_context->pre_deblocking_output.bo = NULL;
1462
1463     dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
1464     mfc_context->uncompressed_picture_source.bo = NULL;
1465
1466     dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
1467     mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
1468
1469     for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
1470         dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
1471         mfc_context->direct_mv_buffers[i].bo = NULL;
1472     }
1473
1474     dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
1475     mfc_context->intra_row_store_scratch_buffer.bo = NULL;
1476
1477     dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
1478     mfc_context->macroblock_status_buffer.bo = NULL;
1479
1480     dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
1481     mfc_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
1482
1483     dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
1484     mfc_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
1485
1486
1487     for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
1488         dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
1489         mfc_context->reference_surfaces[i].bo = NULL;
1490     }
1491
1492     i965_gpe_context_destroy(&mfc_context->gpe_context);
1493
1494     dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo);
1495     mfc_context->mfc_batchbuffer_surface.bo = NULL;
1496
1497     dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo);
1498     mfc_context->aux_batchbuffer_surface.bo = NULL;
1499
1500     if (mfc_context->aux_batchbuffer)
1501         intel_batchbuffer_free(mfc_context->aux_batchbuffer);
1502
1503     mfc_context->aux_batchbuffer = NULL;
1504
1505     free(mfc_context);
1506 }
1507
1508 Bool gen6_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
1509 {
1510     struct gen6_mfc_context *mfc_context = calloc(1, sizeof(struct gen6_mfc_context));
1511
1512     mfc_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6;
1513
1514     mfc_context->gpe_context.idrt.max_entries = MAX_GPE_KERNELS;
1515     mfc_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data);
1516
1517     mfc_context->gpe_context.curbe.length = 32 * 4;
1518
1519     mfc_context->gpe_context.vfe_state.max_num_threads = 60 - 1;
1520     mfc_context->gpe_context.vfe_state.num_urb_entries = 16;
1521     mfc_context->gpe_context.vfe_state.gpgpu_mode = 0;
1522     mfc_context->gpe_context.vfe_state.urb_entry_size = 59 - 1;
1523     mfc_context->gpe_context.vfe_state.curbe_allocation_size = 37 - 1;
1524
1525     i965_gpe_load_kernels(ctx,
1526                           &mfc_context->gpe_context,
1527                           gen6_mfc_kernels,
1528                           NUM_MFC_KERNEL);
1529
1530     mfc_context->pipe_mode_select = gen6_mfc_pipe_mode_select;
1531     mfc_context->set_surface_state = gen6_mfc_surface_state;
1532     mfc_context->ind_obj_base_addr_state = gen6_mfc_ind_obj_base_addr_state;
1533     mfc_context->avc_img_state = gen6_mfc_avc_img_state;
1534     mfc_context->avc_qm_state = gen6_mfc_avc_qm_state;
1535     mfc_context->avc_fqm_state = gen6_mfc_avc_fqm_state;
1536     mfc_context->insert_object = gen6_mfc_avc_insert_object;
1537     mfc_context->buffer_suface_setup = i965_gpe_buffer_suface_setup;
1538
1539     encoder_context->mfc_context = mfc_context;
1540     encoder_context->mfc_context_destroy = gen6_mfc_context_destroy;
1541     encoder_context->mfc_pipeline = gen6_mfc_pipeline;
1542     encoder_context->mfc_brc_prepare = intel_mfc_brc_prepare;
1543
1544     return True;
1545 }