src/gen6_mfc.c

   1 /*
   2  * Copyright © 2010-2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Zhou Chang <chang.zhou@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <assert.h>
  33
  34 #include "assert.h"
  35 #include "intel_batchbuffer.h"
  36 #include "i965_defines.h"
  37 #include "i965_structs.h"
  38 #include "i965_drv_video.h"
  39 #include "i965_encoder.h"
  40
  41 static void
  42 gen6_mfc_pipe_mode_select(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
  43 {
  44     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
  45
  46     BEGIN_BCS_BATCH(batch, 4);
  47
  48     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (4 - 2));
  49     OUT_BCS_BATCH(batch,
  50                   (0 << 10) | /* disable Stream-Out , advanced QP/bitrate control need enable it*/
  51                   (1 << 9)  | /* Post Deblocking Output */
  52                   (0 << 8)  | /* Pre Deblocking Output */
  53                   (0 << 7)  | /* disable TLB prefectch */
  54                   (0 << 5)  | /* not in stitch mode */
  55                   (1 << 4)  | /* encoding mode */
  56                   (2 << 0));  /* Standard Select: AVC */
  57     OUT_BCS_BATCH(batch,
  58                   (0 << 20) | /* round flag in PB slice */
  59                   (0 << 19) | /* round flag in Intra8x8 */
  60                   (0 << 7)  | /* expand NOA bus flag */
  61                   (1 << 6)  | /* must be 1 */
  62                   (0 << 5)  | /* disable clock gating for NOA */
  63                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
  64                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
  65                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
  66                   (0 << 1)  | /* AVC long field motion vector */
  67                   (0 << 0));  /* always calculate AVC ILDB boundary strength */
  68     OUT_BCS_BATCH(batch, 0);
  69
  70     ADVANCE_BCS_BATCH(batch);
  71 }
  72
  73 static void
  74 gen7_mfc_pipe_mode_select(VADriverContextP ctx,
  75                           int standard_select,
  76                           struct gen6_encoder_context *gen6_encoder_context)
  77 {
  78     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
  79
  80     assert(standard_select == MFX_FORMAT_MPEG2 ||
  81            standard_select == MFX_FORMAT_AVC);
  82
  83     BEGIN_BCS_BATCH(batch, 5);
  84     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
  85     OUT_BCS_BATCH(batch,
  86                   (MFX_LONG_MODE << 17) | /* Must be long format for encoder */
  87                   (MFD_MODE_VLD << 15) | /* VLD mode */
  88                   (0 << 10) | /* disable Stream-Out */
  89                   (1 << 9)  | /* Post Deblocking Output */
  90                   (0 << 8)  | /* Pre Deblocking Output */
  91                   (0 << 5)  | /* not in stitch mode */
  92                   (1 << 4)  | /* encoding mode */
  93                   (standard_select << 0));  /* standard select: avc or mpeg2 */
  94     OUT_BCS_BATCH(batch,
  95                   (0 << 7)  | /* expand NOA bus flag */
  96                   (0 << 6)  | /* disable slice-level clock gating */
  97                   (0 << 5)  | /* disable clock gating for NOA */
  98                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
  99                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
 100                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
 101                   (0 << 1)  |
 102                   (0 << 0));
 103     OUT_BCS_BATCH(batch, 0);
 104     OUT_BCS_BATCH(batch, 0);
 105
 106     ADVANCE_BCS_BATCH(batch);
 107 }
 108
 109 static void
 110 gen6_mfc_surface_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
 111 {
 112     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 113     struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
 114
 115     BEGIN_BCS_BATCH(batch, 6);
 116
 117     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
 118     OUT_BCS_BATCH(batch, 0);
 119     OUT_BCS_BATCH(batch,
 120                   ((mfc_context->surface_state.height - 1) << 19) |
 121                   ((mfc_context->surface_state.width - 1) << 6));
 122     OUT_BCS_BATCH(batch,
 123                   (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
 124                   (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
 125                   (0 << 22) | /* surface object control state, FIXME??? */
 126                   ((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */
 127                   (0 << 2)  | /* must be 0 for interleave U/V */
 128                   (1 << 1)  | /* must be y-tiled */
 129                   (I965_TILEWALK_YMAJOR << 0));                         /* tile walk, TILEWALK_YMAJOR */
 130     OUT_BCS_BATCH(batch,
 131                   (0 << 16) |                                                           /* must be 0 for interleave U/V */
 132                   (mfc_context->surface_state.h_pitch));                /* y offset for U(cb) */
 133     OUT_BCS_BATCH(batch, 0);
 134     ADVANCE_BCS_BATCH(batch);
 135 }
 136
 137 static void
 138 gen7_mfc_surface_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
 139 {
 140     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 141     struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
 142
 143     BEGIN_BCS_BATCH(batch, 6);
 144
 145     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
 146     OUT_BCS_BATCH(batch, 0);
 147     OUT_BCS_BATCH(batch,
 148                   ((mfc_context->surface_state.height - 1) << 18) |
 149                   ((mfc_context->surface_state.width - 1) << 4));
 150     OUT_BCS_BATCH(batch,
 151                   (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
 152                   (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
 153                   (0 << 22) | /* surface object control state, FIXME??? */
 154                   ((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */
 155                   (0 << 2)  | /* must be 0 for interleave U/V */
 156                   (1 << 1)  | /* must be tiled */
 157                   (I965_TILEWALK_YMAJOR << 0));  /* tile walk, TILEWALK_YMAJOR */
 158     OUT_BCS_BATCH(batch,
 159                   (0 << 16) |                                                           /* must be 0 for interleave U/V */
 160                   (mfc_context->surface_state.h_pitch));                /* y offset for U(cb) */
 161     OUT_BCS_BATCH(batch, 0);
 162     ADVANCE_BCS_BATCH(batch);
 163 }
 164
 165 static void
 166 gen6_mfc_pipe_buf_addr_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
 167 {
 168     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 169     struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
 170     int i;
 171
 172     BEGIN_BCS_BATCH(batch, 24);
 173
 174     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
 175
 176     OUT_BCS_BATCH(batch, 0);                                                                                    /* pre output addr   */
 177
 178     OUT_BCS_RELOC(batch, mfc_context->post_deblocking_output.bo,
 179                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 180                   0);                                                                                   /* post output addr  */
 181
 182     OUT_BCS_RELOC(batch, mfc_context->uncompressed_picture_source.bo,
 183                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 184                   0);                                                                                   /* uncompressed data */
 185     OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
 186                                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 187                                   0);                                                                                   /* StreamOut data*/
 188     OUT_BCS_RELOC(batch, mfc_context->intra_row_store_scratch_buffer.bo,
 189                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 190                   0);
 191     OUT_BCS_RELOC(batch, mfc_context->deblocking_filter_row_store_scratch_buffer.bo,
 192                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 193                   0);
 194     /* 7..22 Reference pictures*/
 195     for (i = 0; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) {
 196         if ( mfc_context->reference_surfaces[i].bo != NULL) {
 197             OUT_BCS_RELOC(batch, mfc_context->reference_surfaces[i].bo,
 198                           I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 199                           0);
 200         } else {
 201             OUT_BCS_BATCH(batch, 0);
 202         }
 203     }
 204     OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
 205                                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 206                                   0);                                                                                   /* Macroblock status buffer*/
 207
 208     ADVANCE_BCS_BATCH(batch);
 209 }
 210
 211 static void
 212 gen6_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
 213 {
 214     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 215     struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
 216
 217     BEGIN_BCS_BATCH(batch, 11);
 218
 219     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
 220     OUT_BCS_BATCH(batch, 0);
 221     OUT_BCS_BATCH(batch, 0);
 222     /* MFX Indirect MV Object Base Address */
 223     OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 224     OUT_BCS_BATCH(batch, 0);
 225     OUT_BCS_BATCH(batch, 0);
 226     OUT_BCS_BATCH(batch, 0);
 227     OUT_BCS_BATCH(batch, 0);
 228     OUT_BCS_BATCH(batch, 0);
 229     /*MFC Indirect PAK-BSE Object Base Address for Encoder*/
 230     OUT_BCS_BATCH(batch, 0);
 231     OUT_BCS_BATCH(batch, 0);
 232
 233     ADVANCE_BCS_BATCH(batch);
 234 }
 235
 236 static void
 237 gen7_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
 238 {
 239     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 240     struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
 241
 242     BEGIN_BCS_BATCH(batch, 11);
 243
 244     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
 245     OUT_BCS_BATCH(batch, 0);
 246     OUT_BCS_BATCH(batch, 0);
 247     /* MFX Indirect MV Object Base Address */
 248     OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 249     OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
 250     OUT_BCS_BATCH(batch, 0);
 251     OUT_BCS_BATCH(batch, 0);
 252     OUT_BCS_BATCH(batch, 0);
 253     OUT_BCS_BATCH(batch, 0);
 254     /*MFC Indirect PAK-BSE Object Base Address for Encoder*/
 255     OUT_BCS_BATCH(batch, 0);
 256     OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
 257
 258     ADVANCE_BCS_BATCH(batch);
 259 }
 260
 261 static void
 262 gen6_mfc_bsp_buf_base_addr_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
 263 {
 264     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 265     struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
 266
 267     BEGIN_BCS_BATCH(batch, 4);
 268
 269     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
 270     OUT_BCS_RELOC(batch, mfc_context->bsd_mpc_row_store_scratch_buffer.bo,
 271                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 272                   0);
 273     OUT_BCS_BATCH(batch, 0);
 274     OUT_BCS_BATCH(batch, 0);
 275
 276     ADVANCE_BCS_BATCH(batch);
 277 }
 278
 279 static void
 280 gen6_mfc_avc_img_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
 281 {
 282     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 283     struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
 284
 285     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 286     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 287
 288     BEGIN_BCS_BATCH(batch, 13);
 289     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (13 - 2));
 290     OUT_BCS_BATCH(batch,
 291                   ((width_in_mbs * height_in_mbs) & 0xFFFF));
 292     OUT_BCS_BATCH(batch,
 293                   (height_in_mbs << 16) |
 294                   (width_in_mbs << 0));
 295     OUT_BCS_BATCH(batch,
 296                   (0 << 24) |     /*Second Chroma QP Offset*/
 297                   (0 << 16) |     /*Chroma QP Offset*/
 298                   (0 << 14) |   /*Max-bit conformance Intra flag*/
 299                   (0 << 13) |   /*Max Macroblock size conformance Inter flag*/
 300                   (1 << 12) |   /*Should always be written as "1" */
 301                   (0 << 10) |   /*QM Preset FLag */
 302                   (0 << 8)  |   /*Image Structure*/
 303                   (0 << 0) );   /*Current Decoed Image Frame Store ID, reserved in Encode mode*/
 304     OUT_BCS_BATCH(batch,
 305                   (400 << 16) |   /*Mininum Frame size*/
 306                   (0 << 15) |   /*Disable reading of Macroblock Status Buffer*/
 307                   (0 << 14) |   /*Load BitStream Pointer only once, 1 slic 1 frame*/
 308                   (0 << 13) |   /*CABAC 0 word insertion test enable*/
 309                   (1 << 12) |   /*MVUnpackedEnable,compliant to DXVA*/
 310                   (1 << 10) |   /*Chroma Format IDC, 4:2:0*/
 311                   (1 << 7)  |   /*0:CAVLC encoding mode,1:CABAC*/
 312                   (0 << 6)  |   /*Only valid for VLD decoding mode*/
 313                   (0 << 5)  |   /*Constrained Intra Predition Flag, from PPS*/
 314                   (0 << 4)  |   /*Direct 8x8 inference flag*/
 315                   (0 << 3)  |   /*Only 8x8 IDCT Transform Mode Flag*/
 316                   (1 << 2)  |   /*Frame MB only flag*/
 317                   (0 << 1)  |   /*MBAFF mode is in active*/
 318                   (0 << 0) );   /*Field picture flag*/
 319     OUT_BCS_BATCH(batch,
 320                   (1<<16)   |   /*Frame Size Rate Control Flag*/
 321                   (1<<12)   |
 322                   (1<<9)    |   /*MB level Rate Control Enabling Flag*/
 323                   (1 << 3)  |   /*FrameBitRateMinReportMask*/
 324                   (1 << 2)  |   /*FrameBitRateMaxReportMask*/
 325                   (1 << 1)  |   /*InterMBMaxSizeReportMask*/
 326                   (1 << 0) );   /*IntraMBMaxSizeReportMask*/
 327     OUT_BCS_BATCH(batch,                        /*Inter and Intra Conformance Max size limit*/
 328                   (0x0600 << 16) |              /*InterMbMaxSz 192 Byte*/
 329                   (0x0800) );                   /*IntraMbMaxSz 256 Byte*/
 330     OUT_BCS_BATCH(batch, 0x00000000);   /*Reserved : MBZReserved*/
 331     OUT_BCS_BATCH(batch, 0x01020304);   /*Slice QP Delta for bitrate control*/
 332     OUT_BCS_BATCH(batch, 0xFEFDFCFB);
 333     OUT_BCS_BATCH(batch, 0x80601004);   /*MAX = 128KB, MIN = 64KB*/
 334     OUT_BCS_BATCH(batch, 0x00800001);
 335     OUT_BCS_BATCH(batch, 0);
 336
 337     ADVANCE_BCS_BATCH(batch);
 338 }
 339
 340 static void
 341 gen7_mfc_avc_img_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
 342 {
 343     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 344     struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
 345
 346     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 347     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 348
 349     BEGIN_BCS_BATCH(batch, 16);
 350     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
 351     OUT_BCS_BATCH(batch,
 352                   ((width_in_mbs * height_in_mbs) & 0xFFFF));
 353     OUT_BCS_BATCH(batch,
 354                   ((height_in_mbs - 1) << 16) |
 355                   ((width_in_mbs - 1) << 0));
 356     OUT_BCS_BATCH(batch,
 357                   (0 << 24) |   /* Second Chroma QP Offset */
 358                   (0 << 16) |   /* Chroma QP Offset */
 359                   (0 << 14) |   /* Max-bit conformance Intra flag */
 360                   (0 << 13) |   /* Max Macroblock size conformance Inter flag */
 361                   (0 << 12) |   /* FIXME: Weighted_Pred_Flag */
 362                   (0 << 10) |   /* FIXME: Weighted_BiPred_Idc */
 363                   (0 << 8)  |   /* FIXME: Image Structure */
 364                   (0 << 0) );   /* Current Decoed Image Frame Store ID, reserved in Encode mode */
 365     OUT_BCS_BATCH(batch,
 366                   (0 << 16) |   /* Mininum Frame size */
 367                   (0 << 15) |   /* Disable reading of Macroblock Status Buffer */
 368                   (0 << 14) |   /* Load BitStream Pointer only once, 1 slic 1 frame */
 369                   (0 << 13) |   /* CABAC 0 word insertion test enable */
 370                   (1 << 12) |   /* MVUnpackedEnable,compliant to DXVA */
 371                   (1 << 10) |   /* Chroma Format IDC, 4:2:0 */
 372                   (0 << 9)  |   /* FIXME: MbMvFormatFlag */
 373                   (1 << 7)  |   /* 0:CAVLC encoding mode,1:CABAC */
 374                   (0 << 6)  |   /* Only valid for VLD decoding mode */
 375                   (0 << 5)  |   /* Constrained Intra Predition Flag, from PPS */
 376                   (0 << 4)  |   /* Direct 8x8 inference flag */
 377                   (0 << 3)  |   /* Only 8x8 IDCT Transform Mode Flag */
 378                   (1 << 2)  |   /* Frame MB only flag */
 379                   (0 << 1)  |   /* MBAFF mode is in active */
 380                   (0 << 0));    /* Field picture flag */
 381     OUT_BCS_BATCH(batch, 0);    /* Mainly about MB rate control and debug, just ignoring */
 382     OUT_BCS_BATCH(batch,        /* Inter and Intra Conformance Max size limit */
 383                   (0xBB8 << 16) |       /* InterMbMaxSz */
 384                   (0xEE8) );            /* IntraMbMaxSz */
 385     OUT_BCS_BATCH(batch, 0);            /* Reserved */
 386     OUT_BCS_BATCH(batch, 0);            /* Slice QP Delta for bitrate control */
 387     OUT_BCS_BATCH(batch, 0);            /* Slice QP Delta for bitrate control */
 388     OUT_BCS_BATCH(batch, 0x8C000000);
 389     OUT_BCS_BATCH(batch, 0x00010000);
 390     OUT_BCS_BATCH(batch, 0);
 391     OUT_BCS_BATCH(batch, 0);
 392     OUT_BCS_BATCH(batch, 0);
 393     OUT_BCS_BATCH(batch, 0);
 394
 395     ADVANCE_BCS_BATCH(batch);
 396 }
 397
 398 static void gen6_mfc_avc_directmode_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
 399 {
 400     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 401     int i;
 402
 403     BEGIN_BCS_BATCH(batch, 69);
 404
 405     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
 406     //TODO: reference DMV
 407     for(i = 0; i < 16; i++){
 408         OUT_BCS_BATCH(batch, 0);
 409         OUT_BCS_BATCH(batch, 0);
 410     }
 411
 412     //TODO: current DMV just for test
 413 #if 0
 414     OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[0].bo,
 415                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 416                   0);
 417 #else
 418     //drm_intel_bo_pin(mfc_context->direct_mv_buffers[0].bo, 0x1000);
 419     //OUT_BCS_BATCH(batch, mfc_context->direct_mv_buffers[0].bo->offset);
 420     OUT_BCS_BATCH(batch, 0);
 421 #endif
 422
 423
 424     OUT_BCS_BATCH(batch, 0);
 425
 426     //TODO: POL list
 427     for(i = 0; i < 34; i++) {
 428         OUT_BCS_BATCH(batch, 0);
 429     }
 430
 431     ADVANCE_BCS_BATCH(batch);
 432 }
 433
 434 static void gen6_mfc_avc_slice_state(VADriverContextP ctx,
 435                                      int slice_type,
 436                                      struct gen6_encoder_context *gen6_encoder_context,
 437                                      int rate_control_enable,
 438                                      int qp)
 439 {
 440     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 441     struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
 442
 443     BEGIN_BCS_BATCH(batch, 11);;
 444
 445     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) );
 446
 447         OUT_BCS_BATCH(batch, slice_type);                       /*Slice Type: I:P:B Slice*/
 448
 449     if ( slice_type == SLICE_TYPE_I )
 450         OUT_BCS_BATCH(batch, 0);                        /*no reference frames and pred_weight_table*/
 451     else
 452         OUT_BCS_BATCH(batch, 0x00010000);       /*1 reference frame*/
 453
 454     OUT_BCS_BATCH(batch, (0<<24) |                /*Enable deblocking operation*/
 455                   (qp<<16) |                    /*Slice Quantization Parameter*/
 456                   0x0202 );
 457     OUT_BCS_BATCH(batch, 0);                    /*First MB X&Y , the postion of current slice*/
 458     OUT_BCS_BATCH(batch, ( ((mfc_context->surface_state.height+15)/16) << 16) );
 459
 460     OUT_BCS_BATCH(batch,
 461                   (rate_control_enable<<31) |           /*in CBR mode RateControlCounterEnable = enable*/
 462                   (1<<30) |             /*ResetRateControlCounter*/
 463                   (0<<28) |             /*RC Triggle Mode = Always Rate Control*/
 464                   (8<<24) |     /*RC Stable Tolerance, middle level*/
 465                   (rate_control_enable<<23) |     /*RC Panic Enable*/
 466                   (0<<22) |     /*QP mode, don't modfiy CBP*/
 467                   (1<<19) |     /*IsLastSlice*/
 468                   (0<<18) |     /*BitstreamOutputFlag Compressed BitStream Output Disable Flag 0:enable 1:disable*/
 469                   (0<<17) |         /*HeaderPresentFlag*/
 470                   (1<<16) |         /*SliceData PresentFlag*/
 471                   (0<<15) |         /*TailPresentFlag*/
 472                   (1<<13) |         /*RBSP NAL TYPE*/
 473                   (0<<12) );    /*CabacZeroWordInsertionEnable*/
 474
 475     OUT_BCS_RELOC(batch, mfc_context->mfc_indirect_pak_bse_object.bo,
 476                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 477                   mfc_context->mfc_indirect_pak_bse_object.offset);
 478
 479     OUT_BCS_BATCH(batch, (24<<24) |     /*Target QP - 24 is lowest QP*/
 480                          (20<<16) |     /*Target QP + 20 is highest QP*/
 481                          (8<<12)  |
 482                          (8<<8)   |
 483                          (8<<4)   |
 484                          (8<<0));
 485     OUT_BCS_BATCH(batch, 0x08888888);
 486     OUT_BCS_BATCH(batch, 0);
 487
 488     ADVANCE_BCS_BATCH(batch);
 489 }
 490 static void gen6_mfc_avc_qm_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
 491 {
 492     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 493     int i;
 494
 495     BEGIN_BCS_BATCH(batch, 58);
 496
 497     OUT_BCS_BATCH(batch, MFX_AVC_QM_STATE | 56);
 498     OUT_BCS_BATCH(batch, 0xFF ) ;
 499     for( i = 0; i < 56; i++) {
 500         OUT_BCS_BATCH(batch, 0x10101010);
 501     }
 502
 503     ADVANCE_BCS_BATCH(batch);
 504 }
 505
 506 static void gen6_mfc_avc_fqm_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
 507 {
 508     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 509     int i;
 510
 511     BEGIN_BCS_BATCH(batch, 113);
 512     OUT_BCS_BATCH(batch, MFC_AVC_FQM_STATE | (113 - 2));
 513
 514     for(i = 0; i < 112;i++) {
 515         OUT_BCS_BATCH(batch, 0x10001000);
 516     }
 517
 518     ADVANCE_BCS_BATCH(batch);
 519 }
 520
 521 static void
 522 gen7_mfc_qm_state(VADriverContextP ctx,
 523                   int qm_type,
 524                   unsigned int *qm,
 525                   int qm_length,
 526                   struct gen6_encoder_context *gen6_encoder_context)
 527 {
 528     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 529     unsigned int qm_buffer[16];
 530
 531     assert(qm_length <= 16);
 532     assert(sizeof(*qm) == 4);
 533     memcpy(qm_buffer, qm, qm_length * 4);
 534
 535     BEGIN_BCS_BATCH(batch, 18);
 536     OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2));
 537     OUT_BCS_BATCH(batch, qm_type << 0);
 538     intel_batchbuffer_data(batch, qm_buffer, 16 * 4);
 539     ADVANCE_BCS_BATCH(batch);
 540 }
 541
 542 static void gen7_mfc_avc_qm_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
 543 {
 544     unsigned int qm[16] = {
 545         0x10101010, 0x10101010, 0x10101010, 0x10101010,
 546         0x10101010, 0x10101010, 0x10101010, 0x10101010,
 547         0x10101010, 0x10101010, 0x10101010, 0x10101010,
 548         0x10101010, 0x10101010, 0x10101010, 0x10101010
 549     };
 550
 551     gen7_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 12, gen6_encoder_context);
 552     gen7_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 12, gen6_encoder_context);
 553     gen7_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 16, gen6_encoder_context);
 554     gen7_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 16, gen6_encoder_context);
 555 }
 556
 557 static void
 558 gen7_mfc_fqm_state(VADriverContextP ctx,
 559                    int fqm_type,
 560                    unsigned int *fqm,
 561                    int fqm_length,
 562                    struct gen6_encoder_context *gen6_encoder_context)
 563 {
 564     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 565     unsigned int fqm_buffer[32];
 566
 567     assert(fqm_length <= 32);
 568     assert(sizeof(*fqm) == 4);
 569     memcpy(fqm_buffer, fqm, fqm_length * 4);
 570
 571     BEGIN_BCS_BATCH(batch, 34);
 572     OUT_BCS_BATCH(batch, MFX_FQM_STATE | (34 - 2));
 573     OUT_BCS_BATCH(batch, fqm_type << 0);
 574     intel_batchbuffer_data(batch, fqm_buffer, 32 * 4);
 575     ADVANCE_BCS_BATCH(batch);
 576 }
 577
 578 static void gen7_mfc_avc_fqm_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
 579 {
 580     unsigned int qm[32] = {
 581         0x10001000, 0x10001000, 0x10001000, 0x10001000,
 582         0x10001000, 0x10001000, 0x10001000, 0x10001000,
 583         0x10001000, 0x10001000, 0x10001000, 0x10001000,
 584         0x10001000, 0x10001000, 0x10001000, 0x10001000,
 585         0x10001000, 0x10001000, 0x10001000, 0x10001000,
 586         0x10001000, 0x10001000, 0x10001000, 0x10001000,
 587         0x10001000, 0x10001000, 0x10001000, 0x10001000,
 588         0x10001000, 0x10001000, 0x10001000, 0x10001000
 589     };
 590
 591     gen7_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 24, gen6_encoder_context);
 592     gen7_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 24, gen6_encoder_context);
 593     gen7_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 32, gen6_encoder_context);
 594     gen7_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 32, gen6_encoder_context);
 595 }
 596
 597 static void gen6_mfc_avc_ref_idx_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
 598 {
 599     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 600     int i;
 601
 602         BEGIN_BCS_BATCH(batch, 10);
 603         OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
 604         OUT_BCS_BATCH(batch, 0);                  //Select L0
 605         OUT_BCS_BATCH(batch, 0x80808020);         //Only 1 reference
 606         for(i = 0; i < 7; i++) {
 607                 OUT_BCS_BATCH(batch, 0x80808080);
 608         }
 609         ADVANCE_BCS_BATCH(batch);
 610
 611         BEGIN_BCS_BATCH(batch, 10);
 612         OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
 613         OUT_BCS_BATCH(batch, 1);                  //Select L1
 614         OUT_BCS_BATCH(batch, 0x80808022);         //Only 1 reference
 615         for(i = 0; i < 7; i++) {
 616                 OUT_BCS_BATCH(batch, 0x80808080);
 617         }
 618         ADVANCE_BCS_BATCH(batch);
 619 }
 620
 621 static void
 622 gen6_mfc_avc_insert_object(VADriverContextP ctx, int flush_data, struct gen6_encoder_context *gen6_encoder_context)
 623 {
 624     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 625
 626     BEGIN_BCS_BATCH(batch, 4);
 627
 628     OUT_BCS_BATCH(batch, MFC_AVC_INSERT_OBJECT | (4 -2 ) );
 629     OUT_BCS_BATCH(batch, (32<<8) |
 630                   (1 << 3) |
 631                   (1 << 2) |
 632                   (flush_data << 1) |
 633                   (1<<0) );
 634     OUT_BCS_BATCH(batch, 0x00000003);
 635     OUT_BCS_BATCH(batch, 0xABCD1234);
 636
 637     ADVANCE_BCS_BATCH(batch);
 638 }
 639
 640 static int
 641 gen6_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb, int qp,unsigned int *msg,
 642                               struct gen6_encoder_context *gen6_encoder_context,
 643                               int intra_mb_size_in_bits)
 644 {
 645     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 646     int len_in_dwords = 11;
 647     unsigned char target_mb_size = intra_mb_size_in_bits / 16;     //In Words
 648     unsigned char max_mb_size = target_mb_size * 2 > 255? 255: target_mb_size * 2 ;
 649
 650     BEGIN_BCS_BATCH(batch, len_in_dwords);
 651
 652     OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
 653     OUT_BCS_BATCH(batch, 0);
 654     OUT_BCS_BATCH(batch, 0);
 655     OUT_BCS_BATCH(batch,
 656                   (0 << 24) |           /* PackedMvNum, Debug*/
 657                   (0 << 20) |           /* No motion vector */
 658                   (1 << 19) |           /* CbpDcY */
 659                   (1 << 18) |           /* CbpDcU */
 660                   (1 << 17) |           /* CbpDcV */
 661                   (msg[0] & 0xFFFF) );
 662
 663     OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x);          /* Code Block Pattern for Y*/
 664     OUT_BCS_BATCH(batch, 0x000F000F);                                                   /* Code Block Pattern */
 665     OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp);      /* Last MB */
 666
 667     /*Stuff for Intra MB*/
 668     OUT_BCS_BATCH(batch, msg[1]);                       /* We using Intra16x16 no 4x4 predmode*/
 669     OUT_BCS_BATCH(batch, msg[2]);
 670     OUT_BCS_BATCH(batch, msg[3]&0xFC);
 671
 672     /*MaxSizeInWord and TargetSzieInWord*/
 673     OUT_BCS_BATCH(batch, (max_mb_size << 24) |
 674                          (target_mb_size << 16) );
 675
 676     ADVANCE_BCS_BATCH(batch);
 677
 678     return len_in_dwords;
 679 }
 680
 681 static int gen6_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, int qp, unsigned int offset,
 682                                          struct gen6_encoder_context *gen6_encoder_context,
 683                                          int inter_mb_size_in_bits)
 684 {
 685     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 686     int len_in_dwords = 11;
 687     unsigned char target_mb_size = inter_mb_size_in_bits / 16;     //In Words
 688     unsigned char max_mb_size = target_mb_size * 16 > 255? 255: target_mb_size * 16 ;
 689
 690     BEGIN_BCS_BATCH(batch, len_in_dwords);
 691
 692     OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
 693
 694     OUT_BCS_BATCH(batch, 32);         /* 32 MV*/
 695     OUT_BCS_BATCH(batch, offset);
 696
 697     OUT_BCS_BATCH(batch,
 698                   (1 << 24) |     /* PackedMvNum, Debug*/
 699                   (4 << 20) |     /* 8 MV, SNB don't use it*/
 700                   (1 << 19) |     /* CbpDcY */
 701                   (1 << 18) |     /* CbpDcU */
 702                   (1 << 17) |     /* CbpDcV */
 703                   (0 << 15) |     /* Transform8x8Flag = 0*/
 704                   (0 << 14) |     /* Frame based*/
 705                   (0 << 13) |     /* Inter MB */
 706                   (1 << 8)  |     /* MbType = P_L0_16x16 */
 707                   (0 << 7)  |     /* MBZ for frame */
 708                   (0 << 6)  |     /* MBZ */
 709                   (2 << 4)  |     /* MBZ for inter*/
 710                   (0 << 3)  |     /* MBZ */
 711                   (0 << 2)  |     /* SkipMbFlag */
 712                   (0 << 0));      /* InterMbMode */
 713
 714     OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x);        /* Code Block Pattern for Y*/
 715     OUT_BCS_BATCH(batch, 0x000F000F);                         /* Code Block Pattern */
 716     OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp);      /* Last MB */
 717
 718     /*Stuff for Inter MB*/
 719     OUT_BCS_BATCH(batch, 0x0);
 720     OUT_BCS_BATCH(batch, 0x0);
 721     OUT_BCS_BATCH(batch, 0x0);
 722
 723     /*MaxSizeInWord and TargetSzieInWord*/
 724     OUT_BCS_BATCH(batch, (max_mb_size << 24) |
 725                          (target_mb_size << 16) );
 726
 727     ADVANCE_BCS_BATCH(batch);
 728
 729     return len_in_dwords;
 730 }
 731
 732 static void gen6_mfc_init(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
 733 {
 734     struct i965_driver_data *i965 = i965_driver_data(ctx);
 735     struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
 736     dri_bo *bo;
 737     int i;
 738
 739     /*Encode common setup for MFC*/
 740     dri_bo_unreference(mfc_context->post_deblocking_output.bo);
 741     mfc_context->post_deblocking_output.bo = NULL;
 742
 743     dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
 744     mfc_context->pre_deblocking_output.bo = NULL;
 745
 746     dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
 747     mfc_context->uncompressed_picture_source.bo = NULL;
 748
 749     dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
 750     mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
 751
 752     for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
 753         dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
 754         mfc_context->direct_mv_buffers[i].bo = NULL;
 755     }
 756
 757     for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
 758         if (mfc_context->reference_surfaces[i].bo != NULL)
 759             dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
 760         mfc_context->reference_surfaces[i].bo = NULL;
 761     }
 762
 763     dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
 764     bo = dri_bo_alloc(i965->intel.bufmgr,
 765                       "Buffer",
 766                       128 * 64,
 767                       64);
 768     assert(bo);
 769     mfc_context->intra_row_store_scratch_buffer.bo = bo;
 770
 771     dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
 772     bo = dri_bo_alloc(i965->intel.bufmgr,
 773                       "Buffer",
 774                       4*9600,
 775                       64);
 776     assert(bo);
 777     mfc_context->macroblock_status_buffer.bo = bo;
 778
 779     dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
 780     bo = dri_bo_alloc(i965->intel.bufmgr,
 781                       "Buffer",
 782                       49152,  /* 6 * 128 * 64 */
 783                       64);
 784     assert(bo);
 785     mfc_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
 786
 787     dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
 788     bo = dri_bo_alloc(i965->intel.bufmgr,
 789                       "Buffer",
 790                       12288, /* 1.5 * 128 * 64 */
 791                       0x1000);
 792     assert(bo);
 793     mfc_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
 794 }
 795
 796 void gen6_mfc_avc_pipeline_programing(VADriverContextP ctx,
 797                                       struct encode_state *encode_state,
 798                                       struct gen6_encoder_context *gen6_encoder_context)
 799 {
 800     struct i965_driver_data *i965 = i965_driver_data(ctx);
 801     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 802     struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
 803     struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
 804     VAEncSequenceParameterBufferH264Ext *pSequenceParameter = (VAEncSequenceParameterBufferH264Ext *)encode_state->seq_param_ext->buffer;
 805     VAEncPictureParameterBufferH264Ext *pPicParameter = (VAEncPictureParameterBufferH264Ext *)encode_state->pic_param_ext->buffer;
 806     VAEncSliceParameterBufferH264Ext *pSliceParameter = (VAEncSliceParameterBufferH264Ext *)encode_state->slice_params_ext[0]->buffer; /* FIXME: multi slices */
 807
 808     unsigned int *msg = NULL, offset = 0;
 809     int emit_new_state = 1, object_len_in_bytes;
 810     int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
 811     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 812     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 813     int x,y;
 814     int rate_control_mode = pSequenceParameter->rate_control_method;
 815     float fps =  pSequenceParameter->time_scale * 0.5 / pSequenceParameter->num_units_in_tick ;
 816
 817     int inter_mb_size = pSequenceParameter->bits_per_second * 1.0 / fps / width_in_mbs / height_in_mbs;
 818     int intra_mb_size = inter_mb_size * 5.0;
 819     int qp = pPicParameter->pic_init_qp;
 820
 821     if ( rate_control_mode != 2) {
 822         qp = 26;
 823         if ( intra_mb_size > 384*8)         //ONE MB raw data is 384 bytes
 824             intra_mb_size = 384*8;
 825         if ( inter_mb_size > 256*8)
 826             intra_mb_size = 256*8;
 827     }
 828
 829     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
 830
 831     if (is_intra) {
 832         dri_bo_map(vme_context->vme_output.bo , 1);
 833         msg = (unsigned int *)vme_context->vme_output.bo->virtual;
 834     }
 835
 836     for (y = 0; y < height_in_mbs; y++) {
 837         for (x = 0; x < width_in_mbs; x++) {
 838             int last_mb = (y == (height_in_mbs-1)) && ( x == (width_in_mbs-1) );
 839
 840             if (emit_new_state) {
 841                 intel_batchbuffer_emit_mi_flush(batch);
 842
 843                 if (IS_GEN7(i965->intel.device_id)) {
 844                     gen7_mfc_pipe_mode_select(ctx, MFX_FORMAT_AVC, gen6_encoder_context);
 845                     gen7_mfc_surface_state(ctx, gen6_encoder_context);
 846                     gen7_mfc_ind_obj_base_addr_state(ctx, gen6_encoder_context);
 847                 } else {
 848                     gen6_mfc_pipe_mode_select(ctx, gen6_encoder_context);
 849                     gen6_mfc_surface_state(ctx, gen6_encoder_context);
 850                     gen6_mfc_ind_obj_base_addr_state(ctx, gen6_encoder_context);
 851                 }
 852
 853                 gen6_mfc_pipe_buf_addr_state(ctx, gen6_encoder_context);
 854                 gen6_mfc_bsp_buf_base_addr_state(ctx, gen6_encoder_context);
 855
 856                 if (IS_GEN7(i965->intel.device_id)) {
 857                     gen7_mfc_avc_img_state(ctx, gen6_encoder_context);
 858                     gen7_mfc_avc_qm_state(ctx, gen6_encoder_context);
 859                     gen7_mfc_avc_fqm_state(ctx, gen6_encoder_context);
 860                 } else {
 861                     gen6_mfc_avc_img_state(ctx, gen6_encoder_context);
 862                     gen6_mfc_avc_qm_state(ctx, gen6_encoder_context);
 863                     gen6_mfc_avc_fqm_state(ctx, gen6_encoder_context);
 864                 }
 865
 866                 gen6_mfc_avc_ref_idx_state(ctx, gen6_encoder_context);
 867                 gen6_mfc_avc_slice_state(ctx, pSliceParameter->slice_type, gen6_encoder_context, rate_control_mode == 0, qp);
 868                 emit_new_state = 0;
 869             }
 870
 871             if (is_intra) {
 872                 assert(msg);
 873                 object_len_in_bytes = gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, gen6_encoder_context, intra_mb_size);
 874                 msg += 4;
 875             } else {
 876                 object_len_in_bytes = gen6_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, offset, gen6_encoder_context, inter_mb_size);
 877                 offset += 64;
 878             }
 879
 880             if (intel_batchbuffer_check_free_space(batch, object_len_in_bytes) == 0) {
 881                 intel_batchbuffer_end_atomic(batch);
 882                 intel_batchbuffer_flush(batch);
 883                 emit_new_state = 1;
 884                 intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
 885             }
 886         }
 887     }
 888
 889     if (is_intra)
 890         dri_bo_unmap(vme_context->vme_output.bo);
 891
 892     intel_batchbuffer_end_atomic(batch);
 893 }
 894
 895 static VAStatus gen6_mfc_avc_prepare(VADriverContextP ctx,
 896                                      struct encode_state *encode_state,
 897                                      struct gen6_encoder_context *gen6_encoder_context)
 898 {
 899     struct i965_driver_data *i965 = i965_driver_data(ctx);
 900     struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
 901     struct object_surface *obj_surface;
 902     struct object_buffer *obj_buffer;
 903     dri_bo *bo;
 904     VAEncPictureParameterBufferH264Ext *pPicParameter = (VAEncPictureParameterBufferH264Ext *)encode_state->pic_param_ext->buffer;
 905     VAStatus vaStatus = VA_STATUS_SUCCESS;
 906         int i;
 907
 908     /*Setup all the input&output object*/
 909     obj_surface = SURFACE(pPicParameter->CurrPic.picture_id);
 910     assert(obj_surface);
 911     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'));
 912
 913     mfc_context->post_deblocking_output.bo = obj_surface->bo;
 914     dri_bo_reference(mfc_context->post_deblocking_output.bo);
 915
 916     mfc_context->surface_state.width = obj_surface->orig_width;
 917     mfc_context->surface_state.height = obj_surface->orig_height;
 918     mfc_context->surface_state.w_pitch = obj_surface->width;
 919     mfc_context->surface_state.h_pitch = obj_surface->height;
 920
 921     for(i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++) {
 922                 if ( pPicParameter->ReferenceFrames[i].picture_id != VA_INVALID_ID ) {
 923                         obj_surface = SURFACE(pPicParameter->ReferenceFrames[i].picture_id);
 924                         assert(obj_surface);
 925                         if (obj_surface->bo != NULL) {
 926                                 mfc_context->reference_surfaces[i].bo = obj_surface->bo;
 927                                 dri_bo_reference(obj_surface->bo);
 928                         }
 929                 } else {
 930                         break;
 931                 }
 932         }
 933
 934     obj_surface = SURFACE(encode_state->current_render_target);
 935     assert(obj_surface && obj_surface->bo);
 936     mfc_context->uncompressed_picture_source.bo = obj_surface->bo;
 937     dri_bo_reference(mfc_context->uncompressed_picture_source.bo);
 938
 939     obj_buffer = BUFFER (pPicParameter->CodedBuf); /* FIXME: fix this later */
 940     bo = obj_buffer->buffer_store->bo;
 941     assert(bo);
 942     mfc_context->mfc_indirect_pak_bse_object.bo = bo;
 943     mfc_context->mfc_indirect_pak_bse_object.offset = ALIGN(sizeof(VACodedBufferSegment), 64);
 944     dri_bo_reference(mfc_context->mfc_indirect_pak_bse_object.bo);
 945
 946     /*Programing bcs pipeline*/
 947     gen6_mfc_avc_pipeline_programing(ctx, encode_state, gen6_encoder_context);  //filling the pipeline
 948
 949     return vaStatus;
 950 }
 951
 952 static VAStatus gen6_mfc_run(VADriverContextP ctx,
 953                              struct encode_state *encode_state,
 954                              struct gen6_encoder_context *gen6_encoder_context)
 955 {
 956     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 957
 958     intel_batchbuffer_flush(batch);             //run the pipeline
 959
 960     return VA_STATUS_SUCCESS;
 961 }
 962
 963 static VAStatus gen6_mfc_stop(VADriverContextP ctx,
 964                               struct encode_state *encode_state,
 965                               struct gen6_encoder_context *gen6_encoder_context)
 966 {
 967 #if 0
 968     struct i965_driver_data *i965 = i965_driver_data(ctx);
 969     struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
 970
 971     VAEncPictureParameterBufferH264Ext *pPicParameter = (VAEncPictureParameterBufferH264Ext *)encode_state->pic_param_ext->buffer;
 972
 973     struct object_surface *obj_surface = SURFACE(pPicParameter->reconstructed_picture);
 974     //struct object_surface *obj_surface = SURFACE(pPicParameter->reference_picture[0]);
 975     //struct object_surface *obj_surface = SURFACE(encode_state->current_render_target);
 976     my_debug(obj_surface);
 977
 978 #endif
 979
 980     return VA_STATUS_SUCCESS;
 981 }
 982
 983 static VAStatus
 984 gen6_mfc_avc_encode_picture(VADriverContextP ctx,
 985                             struct encode_state *encode_state,
 986                             struct gen6_encoder_context *gen6_encoder_context)
 987 {
 988     gen6_mfc_init(ctx, gen6_encoder_context);
 989     gen6_mfc_avc_prepare(ctx, encode_state, gen6_encoder_context);
 990     gen6_mfc_run(ctx, encode_state, gen6_encoder_context);
 991     gen6_mfc_stop(ctx, encode_state, gen6_encoder_context);
 992
 993     return VA_STATUS_SUCCESS;
 994 }
 995
 996 VAStatus
 997 gen6_mfc_pipeline(VADriverContextP ctx,
 998                   VAProfile profile,
 999                   struct encode_state *encode_state,
1000                   struct gen6_encoder_context *gen6_encoder_context)
1001 {
1002     VAStatus vaStatus;
1003
1004     switch (profile) {
1005     case VAProfileH264Baseline:
1006         vaStatus = gen6_mfc_avc_encode_picture(ctx, encode_state, gen6_encoder_context);
1007         break;
1008
1009         /* FIXME: add for other profile */
1010     default:
1011         vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
1012         break;
1013     }
1014
1015     return vaStatus;
1016 }
1017
1018 Bool gen6_mfc_context_init(VADriverContextP ctx, struct gen6_mfc_context *mfc_context)
1019 {
1020     return True;
1021 }
1022
1023 Bool gen6_mfc_context_destroy(struct gen6_mfc_context *mfc_context)
1024 {
1025     int i;
1026
1027     dri_bo_unreference(mfc_context->post_deblocking_output.bo);
1028     mfc_context->post_deblocking_output.bo = NULL;
1029
1030     dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
1031     mfc_context->pre_deblocking_output.bo = NULL;
1032
1033     dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
1034     mfc_context->uncompressed_picture_source.bo = NULL;
1035
1036     dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
1037     mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
1038
1039     for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
1040         dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
1041         mfc_context->direct_mv_buffers[i].bo = NULL;
1042     }
1043
1044     dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
1045     mfc_context->intra_row_store_scratch_buffer.bo = NULL;
1046
1047         dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
1048         mfc_context->macroblock_status_buffer.bo = NULL;
1049
1050     dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
1051     mfc_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
1052
1053     dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
1054     mfc_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
1055
1056     return True;
1057 }