src/gen6_mfc.c

   1 /*
   2  * Copyright © 2010-2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Zhou Chang <chang.zhou@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <assert.h>
  33
  34 #include "intel_batchbuffer.h"
  35 #include "i965_defines.h"
  36 #include "i965_structs.h"
  37 #include "i965_drv_video.h"
  38 #include "i965_encoder.h"
  39 #include "i965_encoder_utils.h"
  40 #include "gen6_mfc.h"
  41 #include "gen6_vme.h"
  42
  43 static void
  44 gen6_mfc_pipe_mode_select(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
  45 {
  46     struct intel_batchbuffer *batch = encoder_context->base.batch;
  47
  48     BEGIN_BCS_BATCH(batch, 4);
  49
  50     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (4 - 2));
  51     OUT_BCS_BATCH(batch,
  52                   (1 << 10) | /* disable Stream-Out , advanced QP/bitrate control need enable it*/
  53                   (1 << 9)  | /* Post Deblocking Output */
  54                   (0 << 8)  | /* Pre Deblocking Output */
  55                   (0 << 7)  | /* disable TLB prefectch */
  56                   (0 << 5)  | /* not in stitch mode */
  57                   (1 << 4)  | /* encoding mode */
  58                   (2 << 0));  /* Standard Select: AVC */
  59     OUT_BCS_BATCH(batch,
  60                   (0 << 20) | /* round flag in PB slice */
  61                   (0 << 19) | /* round flag in Intra8x8 */
  62                   (0 << 7)  | /* expand NOA bus flag */
  63                   (1 << 6)  | /* must be 1 */
  64                   (0 << 5)  | /* disable clock gating for NOA */
  65                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
  66                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
  67                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
  68                   (0 << 1)  | /* AVC long field motion vector */
  69                   (0 << 0));  /* always calculate AVC ILDB boundary strength */
  70     OUT_BCS_BATCH(batch, 0);
  71
  72     ADVANCE_BCS_BATCH(batch);
  73 }
  74
  75 static void
  76 gen6_mfc_surface_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
  77 {
  78     struct intel_batchbuffer *batch = encoder_context->base.batch;
  79     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
  80
  81     BEGIN_BCS_BATCH(batch, 6);
  82
  83     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
  84     OUT_BCS_BATCH(batch, 0);
  85     OUT_BCS_BATCH(batch,
  86                   ((mfc_context->surface_state.height - 1) << 19) |
  87                   ((mfc_context->surface_state.width - 1) << 6));
  88     OUT_BCS_BATCH(batch,
  89                   (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
  90                   (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
  91                   (0 << 22) | /* surface object control state, FIXME??? */
  92                   ((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */
  93                   (0 << 2)  | /* must be 0 for interleave U/V */
  94                   (1 << 1)  | /* must be y-tiled */
  95                   (I965_TILEWALK_YMAJOR << 0));                         /* tile walk, TILEWALK_YMAJOR */
  96     OUT_BCS_BATCH(batch,
  97                   (0 << 16) |                                                           /* must be 0 for interleave U/V */
  98                   (mfc_context->surface_state.h_pitch));                /* y offset for U(cb) */
  99     OUT_BCS_BATCH(batch, 0);
 100     ADVANCE_BCS_BATCH(batch);
 101 }
 102
 103 static void
 104 gen6_mfc_pipe_buf_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 105 {
 106     struct intel_batchbuffer *batch = encoder_context->base.batch;
 107     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 108     int i;
 109
 110     BEGIN_BCS_BATCH(batch, 24);
 111
 112     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
 113
 114     OUT_BCS_BATCH(batch, 0);                                                                                    /* pre output addr   */
 115
 116     OUT_BCS_RELOC(batch, mfc_context->post_deblocking_output.bo,
 117                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 118                   0);                                                                                   /* post output addr  */
 119
 120     OUT_BCS_RELOC(batch, mfc_context->uncompressed_picture_source.bo,
 121                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 122                   0);                                                                                   /* uncompressed data */
 123     OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
 124                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 125                   0);                                                                                   /* StreamOut data*/
 126     OUT_BCS_RELOC(batch, mfc_context->intra_row_store_scratch_buffer.bo,
 127                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 128                   0);
 129     OUT_BCS_RELOC(batch, mfc_context->deblocking_filter_row_store_scratch_buffer.bo,
 130                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 131                   0);
 132     /* 7..22 Reference pictures*/
 133     for (i = 0; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) {
 134         if ( mfc_context->reference_surfaces[i].bo != NULL) {
 135             OUT_BCS_RELOC(batch, mfc_context->reference_surfaces[i].bo,
 136                           I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 137                           0);
 138         } else {
 139             OUT_BCS_BATCH(batch, 0);
 140         }
 141     }
 142     OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
 143                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 144                   0);                                                                                   /* Macroblock status buffer*/
 145
 146     ADVANCE_BCS_BATCH(batch);
 147 }
 148
 149 static void
 150 gen6_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 151 {
 152     struct intel_batchbuffer *batch = encoder_context->base.batch;
 153     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 154     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 155
 156     BEGIN_BCS_BATCH(batch, 11);
 157
 158     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
 159     OUT_BCS_BATCH(batch, 0);
 160     OUT_BCS_BATCH(batch, 0);
 161     /* MFX Indirect MV Object Base Address */
 162     OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 163     OUT_BCS_BATCH(batch, 0);
 164     OUT_BCS_BATCH(batch, 0);
 165     OUT_BCS_BATCH(batch, 0);
 166     OUT_BCS_BATCH(batch, 0);
 167     OUT_BCS_BATCH(batch, 0);
 168     /*MFC Indirect PAK-BSE Object Base Address for Encoder*/
 169     OUT_BCS_RELOC(batch,
 170                   mfc_context->mfc_indirect_pak_bse_object.bo,
 171                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 172                   0);
 173     OUT_BCS_RELOC(batch,
 174                   mfc_context->mfc_indirect_pak_bse_object.bo,
 175                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 176                   mfc_context->mfc_indirect_pak_bse_object.end_offset);
 177
 178     ADVANCE_BCS_BATCH(batch);
 179 }
 180
 181 static void
 182 gen6_mfc_bsp_buf_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 183 {
 184     struct intel_batchbuffer *batch = encoder_context->base.batch;
 185     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 186
 187     BEGIN_BCS_BATCH(batch, 4);
 188
 189     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
 190     OUT_BCS_RELOC(batch, mfc_context->bsd_mpc_row_store_scratch_buffer.bo,
 191                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 192                   0);
 193     OUT_BCS_BATCH(batch, 0);
 194     OUT_BCS_BATCH(batch, 0);
 195
 196     ADVANCE_BCS_BATCH(batch);
 197 }
 198
 199 static void
 200 gen6_mfc_avc_img_state(VADriverContextP ctx,struct encode_state *encode_state,
 201                        struct intel_encoder_context *encoder_context)
 202 {
 203     struct intel_batchbuffer *batch = encoder_context->base.batch;
 204     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 205     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 206     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 207     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 208     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 209
 210     BEGIN_BCS_BATCH(batch, 13);
 211     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (13 - 2));
 212     OUT_BCS_BATCH(batch,
 213                   ((width_in_mbs * height_in_mbs) & 0xFFFF));
 214     OUT_BCS_BATCH(batch,
 215                   (height_in_mbs << 16) |
 216                   (width_in_mbs << 0));
 217     OUT_BCS_BATCH(batch,
 218                   (0 << 24) |     /*Second Chroma QP Offset*/
 219                   (0 << 16) |     /*Chroma QP Offset*/
 220                   (0 << 14) |   /*Max-bit conformance Intra flag*/
 221                   (0 << 13) |   /*Max Macroblock size conformance Inter flag*/
 222                   (1 << 12) |   /*Should always be written as "1" */
 223                   (0 << 10) |   /*QM Preset FLag */
 224                   (0 << 8)  |   /*Image Structure*/
 225                   (0 << 0) );   /*Current Decoed Image Frame Store ID, reserved in Encode mode*/
 226     OUT_BCS_BATCH(batch,
 227                   (400 << 16) |   /*Mininum Frame size*/
 228                   (0 << 15) |   /*Disable reading of Macroblock Status Buffer*/
 229                   (0 << 14) |   /*Load BitStream Pointer only once, 1 slic 1 frame*/
 230                   (0 << 13) |   /*CABAC 0 word insertion test enable*/
 231                   (1 << 12) |   /*MVUnpackedEnable,compliant to DXVA*/
 232                   (1 << 10) |   /*Chroma Format IDC, 4:2:0*/
 233                   (pPicParameter->pic_fields.bits.entropy_coding_mode_flag << 7)  |   /*0:CAVLC encoding mode,1:CABAC*/
 234                   (0 << 6)  |   /*Only valid for VLD decoding mode*/
 235                   (0 << 5)  |   /*Constrained Intra Predition Flag, from PPS*/
 236                   (pSequenceParameter->direct_8x8_inference_flag << 4)  |   /*Direct 8x8 inference flag*/
 237                   (pPicParameter->pic_fields.bits.transform_8x8_mode_flag << 3)  |   /*8x8 or 4x4 IDCT Transform Mode Flag*/
 238                   (1 << 2)  |   /*Frame MB only flag*/
 239                   (0 << 1)  |   /*MBAFF mode is in active*/
 240                   (0 << 0) );   /*Field picture flag*/
 241     OUT_BCS_BATCH(batch,
 242                   (1<<16)   |   /*Frame Size Rate Control Flag*/
 243                   (1<<12)   |
 244                   (1<<9)    |   /*MB level Rate Control Enabling Flag*/
 245                   (1 << 3)  |   /*FrameBitRateMinReportMask*/
 246                   (1 << 2)  |   /*FrameBitRateMaxReportMask*/
 247                   (1 << 1)  |   /*InterMBMaxSizeReportMask*/
 248                   (1 << 0) );   /*IntraMBMaxSizeReportMask*/
 249     OUT_BCS_BATCH(batch,                        /*Inter and Intra Conformance Max size limit*/
 250                   (0x0600 << 16) |              /*InterMbMaxSz 192 Byte*/
 251                   (0x0800) );                   /*IntraMbMaxSz 256 Byte*/
 252     OUT_BCS_BATCH(batch, 0x00000000);   /*Reserved : MBZReserved*/
 253     OUT_BCS_BATCH(batch, 0x01020304);   /*Slice QP Delta for bitrate control*/
 254     OUT_BCS_BATCH(batch, 0xFEFDFCFB);
 255     OUT_BCS_BATCH(batch, 0x80601004);   /*MAX = 128KB, MIN = 64KB*/
 256     OUT_BCS_BATCH(batch, 0x00800001);
 257     OUT_BCS_BATCH(batch, 0);
 258
 259     ADVANCE_BCS_BATCH(batch);
 260 }
 261
 262 static void gen6_mfc_avc_directmode_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 263 {
 264     struct intel_batchbuffer *batch = encoder_context->base.batch;
 265     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 266
 267     int i;
 268
 269     BEGIN_BCS_BATCH(batch, 69);
 270
 271     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
 272
 273     /* Reference frames and Current frames */
 274     for(i = 0; i < NUM_MFC_DMV_BUFFERS; i++) {
 275         if ( mfc_context->direct_mv_buffers[i].bo != NULL) {
 276             OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[i].bo,
 277                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 278                           0);
 279         } else {
 280             OUT_BCS_BATCH(batch, 0);
 281         }
 282     }
 283
 284     /* POL list */
 285     for(i = 0; i < 32; i++) {
 286         OUT_BCS_BATCH(batch, i/2);
 287     }
 288     OUT_BCS_BATCH(batch, 0);
 289     OUT_BCS_BATCH(batch, 0);
 290
 291     ADVANCE_BCS_BATCH(batch);
 292 }
 293
 294 static void gen6_mfc_avc_slice_state(VADriverContextP ctx,
 295                                      int slice_type,
 296                                      struct encode_state *encode_state,
 297                                      struct intel_encoder_context *encoder_context,
 298                                      int rate_control_enable,
 299                                      int qp)
 300 {
 301     struct intel_batchbuffer *batch = encoder_context->base.batch;
 302     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 303     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer; /* TODO: multi slices support */
 304     int bit_rate_control_target;
 305     if ( slice_type == SLICE_TYPE_I )
 306         bit_rate_control_target = 0;
 307     else
 308         bit_rate_control_target = 1;
 309     int maxQpN = mfc_context->bit_rate_control_context[bit_rate_control_target].MaxQpNegModifier;
 310     int maxQpP = mfc_context->bit_rate_control_context[bit_rate_control_target].MaxQpPosModifier;
 311     unsigned char correct[6];
 312     int i;
 313
 314     for (i = 0; i < 6; i++)
 315         correct[i] = mfc_context->bit_rate_control_context[bit_rate_control_target].Correct[i];
 316     unsigned char grow = mfc_context->bit_rate_control_context[bit_rate_control_target].GrowInit +
 317         (mfc_context->bit_rate_control_context[bit_rate_control_target].GrowResistance << 4);
 318     unsigned char shrink = mfc_context->bit_rate_control_context[bit_rate_control_target].ShrinkInit +
 319         (mfc_context->bit_rate_control_context[bit_rate_control_target].ShrinkResistance << 4);
 320
 321     BEGIN_BCS_BATCH(batch, 11);;
 322
 323     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) );
 324
 325     OUT_BCS_BATCH(batch, slice_type);                   /*Slice Type: I:P:B Slice*/
 326
 327     if ( slice_type == SLICE_TYPE_I ) {
 328         OUT_BCS_BATCH(batch, 0);                        /*no reference frames and pred_weight_table*/
 329     } else {
 330         OUT_BCS_BATCH(batch, 0x00010000);       /*1 reference frame*/
 331     }
 332
 333     OUT_BCS_BATCH(batch,
 334                   (pSliceParameter->direct_spatial_mv_pred_flag<<29) |             /*Direct Prediction Type*/
 335                   (0<<24) |                /*Enable deblocking operation*/
 336                   (qp<<16) |                    /*Slice Quantization Parameter*/
 337                   0x0202 );
 338     OUT_BCS_BATCH(batch, 0);                    /*First MB X&Y , the postion of current slice*/
 339     OUT_BCS_BATCH(batch, ( ((mfc_context->surface_state.height+15)/16) << 16) );
 340
 341     OUT_BCS_BATCH(batch,
 342                   (rate_control_enable<<31) |           /*in CBR mode RateControlCounterEnable = enable*/
 343                   (1<<30) |             /*ResetRateControlCounter*/
 344                   (0<<28) |             /*RC Triggle Mode = Always Rate Control*/
 345                   (4<<24) |     /*RC Stable Tolerance, middle level*/
 346                   (rate_control_enable<<23) |     /*RC Panic Enable*/
 347                   (0<<22) |     /*QP mode, don't modfiy CBP*/
 348                   (0<<21) |     /*MB Type Direct Conversion Enabled*/
 349                   (0<<20) |     /*MB Type Skip Conversion Enabled*/
 350                   (1<<19) |     /*IsLastSlice*/
 351                   (0<<18) |     /*BitstreamOutputFlag Compressed BitStream Output Disable Flag 0:enable 1:disable*/
 352                   (1<<17) |         /*HeaderPresentFlag*/
 353                   (1<<16) |         /*SliceData PresentFlag*/
 354                   (1<<15) |         /*TailPresentFlag*/
 355                   (1<<13) |         /*RBSP NAL TYPE*/
 356                   (0<<12) );    /*CabacZeroWordInsertionEnable*/
 357
 358     OUT_BCS_BATCH(batch, mfc_context->mfc_indirect_pak_bse_object.offset);
 359
 360     OUT_BCS_BATCH(batch, (maxQpN<<24) |     /*Target QP - 24 is lowest QP*/
 361                   (maxQpP<<16) |     /*Target QP + 20 is highest QP*/
 362                   (shrink<<8)  |
 363                   (grow<<0));
 364     OUT_BCS_BATCH(batch, (correct[5] << 20) |
 365                   (correct[4] << 16) |
 366                   (correct[3] << 12) |
 367                   (correct[2] << 8) |
 368                   (correct[1] << 4) |
 369                   (correct[0] << 0));
 370     OUT_BCS_BATCH(batch, 0);
 371
 372     ADVANCE_BCS_BATCH(batch);
 373 }
 374 static void gen6_mfc_avc_qm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 375 {
 376     struct intel_batchbuffer *batch = encoder_context->base.batch;
 377     int i;
 378
 379     BEGIN_BCS_BATCH(batch, 58);
 380
 381     OUT_BCS_BATCH(batch, MFX_AVC_QM_STATE | 56);
 382     OUT_BCS_BATCH(batch, 0xFF ) ;
 383     for( i = 0; i < 56; i++) {
 384         OUT_BCS_BATCH(batch, 0x10101010);
 385     }
 386
 387     ADVANCE_BCS_BATCH(batch);
 388 }
 389
 390 static void gen6_mfc_avc_fqm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 391 {
 392     struct intel_batchbuffer *batch = encoder_context->base.batch;
 393     int i;
 394
 395     BEGIN_BCS_BATCH(batch, 113);
 396     OUT_BCS_BATCH(batch, MFC_AVC_FQM_STATE | (113 - 2));
 397
 398     for(i = 0; i < 112;i++) {
 399         OUT_BCS_BATCH(batch, 0x10001000);
 400     }
 401
 402     ADVANCE_BCS_BATCH(batch);
 403 }
 404
 405 static void gen6_mfc_avc_ref_idx_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 406 {
 407     struct intel_batchbuffer *batch = encoder_context->base.batch;
 408     int i;
 409
 410     BEGIN_BCS_BATCH(batch, 10);
 411     OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
 412     OUT_BCS_BATCH(batch, 0);                  //Select L0
 413     OUT_BCS_BATCH(batch, 0x80808020);         //Only 1 reference
 414     for(i = 0; i < 7; i++) {
 415         OUT_BCS_BATCH(batch, 0x80808080);
 416     }
 417     ADVANCE_BCS_BATCH(batch);
 418
 419     BEGIN_BCS_BATCH(batch, 10);
 420     OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
 421     OUT_BCS_BATCH(batch, 1);                  //Select L1
 422     OUT_BCS_BATCH(batch, 0x80808022);         //Only 1 reference
 423     for(i = 0; i < 7; i++) {
 424         OUT_BCS_BATCH(batch, 0x80808080);
 425     }
 426     ADVANCE_BCS_BATCH(batch);
 427 }
 428
 429 static void
 430 gen6_mfc_avc_insert_object(VADriverContextP ctx, struct intel_encoder_context *encoder_context,
 431                            unsigned int *insert_data, int lenght_in_dws, int data_bits_in_last_dw,
 432                            int skip_emul_byte_count, int is_last_header, int is_end_of_slice, int emulation_flag)
 433 {
 434     struct i965_driver_data *i965 = i965_driver_data(ctx);
 435     struct intel_batchbuffer *batch = encoder_context->base.batch;
 436
 437     BEGIN_BCS_BATCH(batch, lenght_in_dws + 2);
 438
 439     if (IS_GEN7(i965->intel.device_id))
 440         OUT_BCS_BATCH(batch, MFX_INSERT_OBJECT | (lenght_in_dws + 2 - 2));
 441     else
 442         OUT_BCS_BATCH(batch, MFC_AVC_INSERT_OBJECT | (lenght_in_dws + 2 - 2));
 443
 444     OUT_BCS_BATCH(batch,
 445                   (0 << 16) |   /* always start at offset 0 */
 446                   (data_bits_in_last_dw << 8) |
 447                   (skip_emul_byte_count << 4) |
 448                   (!!emulation_flag << 3) |
 449                   ((!!is_last_header) << 2) |
 450                   ((!!is_end_of_slice) << 1) |
 451                   (0 << 0));    /* FIXME: ??? */
 452
 453     intel_batchbuffer_data(batch, insert_data, lenght_in_dws * 4);
 454     ADVANCE_BCS_BATCH(batch);
 455 }
 456
 457 static int
 458 gen6_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb, int qp,unsigned int *msg,
 459                               struct intel_encoder_context *encoder_context,
 460                               unsigned char target_mb_size, unsigned char max_mb_size)
 461 {
 462     struct intel_batchbuffer *batch = encoder_context->base.batch;
 463     int len_in_dwords = 11;
 464
 465     BEGIN_BCS_BATCH(batch, len_in_dwords);
 466
 467     OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
 468     OUT_BCS_BATCH(batch, 0);
 469     OUT_BCS_BATCH(batch, 0);
 470     OUT_BCS_BATCH(batch,
 471                   (0 << 24) |           /* PackedMvNum, Debug*/
 472                   (0 << 20) |           /* No motion vector */
 473                   (1 << 19) |           /* CbpDcY */
 474                   (1 << 18) |           /* CbpDcU */
 475                   (1 << 17) |           /* CbpDcV */
 476                   (msg[0] & 0xFFFF) );
 477
 478     OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x);          /* Code Block Pattern for Y*/
 479     OUT_BCS_BATCH(batch, 0x000F000F);                                                   /* Code Block Pattern */
 480     OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp);      /* Last MB */
 481
 482     /*Stuff for Intra MB*/
 483     OUT_BCS_BATCH(batch, msg[1]);                       /* We using Intra16x16 no 4x4 predmode*/
 484     OUT_BCS_BATCH(batch, msg[2]);
 485     OUT_BCS_BATCH(batch, msg[3]&0xFC);
 486
 487     /*MaxSizeInWord and TargetSzieInWord*/
 488     OUT_BCS_BATCH(batch, (max_mb_size << 24) |
 489                   (target_mb_size << 16) );
 490
 491     ADVANCE_BCS_BATCH(batch);
 492
 493     return len_in_dwords;
 494 }
 495
 496 static int gen6_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, int qp, unsigned int offset,
 497                                          struct intel_encoder_context *encoder_context,
 498                                          unsigned char target_mb_size,unsigned char max_mb_size, int slice_type)
 499 {
 500     struct intel_batchbuffer *batch = encoder_context->base.batch;
 501     int len_in_dwords = 11;
 502
 503     BEGIN_BCS_BATCH(batch, len_in_dwords);
 504
 505     OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
 506
 507     OUT_BCS_BATCH(batch, 32);         /* 32 MV*/
 508     OUT_BCS_BATCH(batch, offset);
 509
 510     OUT_BCS_BATCH(batch,
 511                   (1 << 24) |     /* PackedMvNum, Debug*/
 512                   (4 << 20) |     /* 8 MV, SNB don't use it*/
 513                   (1 << 19) |     /* CbpDcY */
 514                   (1 << 18) |     /* CbpDcU */
 515                   (1 << 17) |     /* CbpDcV */
 516                   (0 << 15) |     /* Transform8x8Flag = 0*/
 517                   (0 << 14) |     /* Frame based*/
 518                   (0 << 13) |     /* Inter MB */
 519                   (1 << 8)  |     /* MbType = P_L0_16x16 */
 520                   (0 << 7)  |     /* MBZ for frame */
 521                   (0 << 6)  |     /* MBZ */
 522                   (2 << 4)  |     /* MBZ for inter*/
 523                   (0 << 3)  |     /* MBZ */
 524                   (0 << 2)  |     /* SkipMbFlag */
 525                   (0 << 0));      /* InterMbMode */
 526
 527     OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x);        /* Code Block Pattern for Y*/
 528     OUT_BCS_BATCH(batch, 0x000F000F);                         /* Code Block Pattern */
 529 #if 0
 530     if ( slice_type == SLICE_TYPE_B) {
 531         OUT_BCS_BATCH(batch, (0xF<<28) | (end_mb << 26) | qp);  /* Last MB */
 532     } else {
 533         OUT_BCS_BATCH(batch, (end_mb << 26) | qp);      /* Last MB */
 534     }
 535 #else
 536     OUT_BCS_BATCH(batch, (end_mb << 26) | qp);  /* Last MB */
 537 #endif
 538
 539
 540     /*Stuff for Inter MB*/
 541     OUT_BCS_BATCH(batch, 0x0);
 542     OUT_BCS_BATCH(batch, 0x0);
 543     OUT_BCS_BATCH(batch, 0x0);
 544
 545     /*MaxSizeInWord and TargetSzieInWord*/
 546     OUT_BCS_BATCH(batch, (max_mb_size << 24) |
 547                   (target_mb_size << 16) );
 548
 549     ADVANCE_BCS_BATCH(batch);
 550
 551     return len_in_dwords;
 552 }
 553
 554 static void gen6_mfc_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 555 {
 556     struct i965_driver_data *i965 = i965_driver_data(ctx);
 557     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 558     dri_bo *bo;
 559     int i;
 560
 561     /*Encode common setup for MFC*/
 562     dri_bo_unreference(mfc_context->post_deblocking_output.bo);
 563     mfc_context->post_deblocking_output.bo = NULL;
 564
 565     dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
 566     mfc_context->pre_deblocking_output.bo = NULL;
 567
 568     dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
 569     mfc_context->uncompressed_picture_source.bo = NULL;
 570
 571     dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
 572     mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
 573
 574     for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
 575         if ( mfc_context->direct_mv_buffers[i].bo != NULL);
 576         dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
 577         mfc_context->direct_mv_buffers[i].bo = NULL;
 578     }
 579
 580     for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
 581         if (mfc_context->reference_surfaces[i].bo != NULL)
 582             dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
 583         mfc_context->reference_surfaces[i].bo = NULL;
 584     }
 585
 586     dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
 587     bo = dri_bo_alloc(i965->intel.bufmgr,
 588                       "Buffer",
 589                       128 * 64,
 590                       64);
 591     assert(bo);
 592     mfc_context->intra_row_store_scratch_buffer.bo = bo;
 593
 594     dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
 595     bo = dri_bo_alloc(i965->intel.bufmgr,
 596                       "Buffer",
 597                       128*128*16,
 598                       64);
 599     assert(bo);
 600     mfc_context->macroblock_status_buffer.bo = bo;
 601
 602     dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
 603     bo = dri_bo_alloc(i965->intel.bufmgr,
 604                       "Buffer",
 605                       49152,  /* 6 * 128 * 64 */
 606                       64);
 607     assert(bo);
 608     mfc_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
 609
 610     dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
 611     bo = dri_bo_alloc(i965->intel.bufmgr,
 612                       "Buffer",
 613                       12288, /* 1.5 * 128 * 64 */
 614                       0x1000);
 615     assert(bo);
 616     mfc_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
 617 }
 618
 619 void gen6_mfc_avc_pipeline_programing(VADriverContextP ctx,
 620                                       struct encode_state *encode_state,
 621                                       struct intel_encoder_context *encoder_context)
 622 {
 623     struct intel_batchbuffer *batch = encoder_context->base.batch;
 624     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 625     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 626     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 627     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 628     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer; /* FIXME: multi slices */
 629     VAEncH264DecRefPicMarkingBuffer *pDecRefPicMarking = NULL;
 630     unsigned int *msg = NULL, offset = 0;
 631     int emit_new_state = 1, object_len_in_bytes;
 632     int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
 633     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 634     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 635     int x,y;
 636     int rate_control_mode = pSequenceParameter->rate_control_method;
 637     unsigned char target_mb_size = mfc_context->bit_rate_control_context[1-is_intra].TargetSizeInWord;
 638     unsigned char max_mb_size = mfc_context->bit_rate_control_context[1-is_intra].MaxSizeInWord;
 639     int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta;
 640     unsigned char *slice_header = NULL;
 641     int slice_header_length_in_bits = 0;
 642     unsigned int tail_data[] = { 0x0 };
 643
 644     if (encode_state->dec_ref_pic_marking)
 645         pDecRefPicMarking = (VAEncH264DecRefPicMarkingBuffer *)encode_state->dec_ref_pic_marking->buffer;
 646
 647     slice_header_length_in_bits = build_avc_slice_header(pSequenceParameter, pPicParameter, pSliceParameter, pDecRefPicMarking, &slice_header);
 648
 649     if ( rate_control_mode == 0) {
 650         qp = mfc_context->bit_rate_control_context[1-is_intra].QpPrimeY;
 651     }
 652
 653     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
 654
 655     if (is_intra) {
 656         dri_bo_map(vme_context->vme_output.bo , 1);
 657         msg = (unsigned int *)vme_context->vme_output.bo->virtual;
 658     }
 659
 660     for (y = 0; y < height_in_mbs; y++) {
 661         for (x = 0; x < width_in_mbs; x++) {
 662             int last_mb = (y == (height_in_mbs-1)) && ( x == (width_in_mbs-1) );
 663
 664             if (emit_new_state) {
 665                 intel_batchbuffer_emit_mi_flush(batch);
 666                 gen6_mfc_pipe_mode_select(ctx, encoder_context);
 667                 gen6_mfc_surface_state(ctx, encoder_context);
 668                 gen6_mfc_ind_obj_base_addr_state(ctx, encoder_context);
 669                 gen6_mfc_pipe_buf_addr_state(ctx, encoder_context);
 670                 gen6_mfc_bsp_buf_base_addr_state(ctx, encoder_context);
 671                 gen6_mfc_avc_img_state(ctx, encode_state,encoder_context);
 672                 gen6_mfc_avc_qm_state(ctx, encoder_context);
 673                 gen6_mfc_avc_fqm_state(ctx, encoder_context);
 674                 gen6_mfc_avc_directmode_state(ctx, encoder_context);
 675                 gen6_mfc_avc_ref_idx_state(ctx, encoder_context);
 676                 gen6_mfc_avc_slice_state(ctx, pSliceParameter->slice_type,
 677                                          encode_state, encoder_context,
 678                                          rate_control_mode == 0, pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta);
 679
 680                 if (encode_state->packed_header_data[VAEncPackedHeaderSPS]) {
 681                     VAEncPackedHeaderParameterBuffer *param = NULL;
 682                     unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[VAEncPackedHeaderSPS]->buffer;
 683                     unsigned int length_in_bits;
 684
 685                     assert(encode_state->packed_header_param[VAEncPackedHeaderSPS]);
 686                     param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[VAEncPackedHeaderSPS]->buffer;
 687                     length_in_bits = param->length_in_bits[0];
 688
 689                     gen6_mfc_avc_insert_object(ctx,
 690                                                encoder_context,
 691                                                header_data,
 692                                                ALIGN(length_in_bits, 32) >> 5,
 693                                                length_in_bits & 0x1f,
 694                                                param->skip_emulation_check_count,
 695                                                0,
 696                                                0,
 697                                                param->insert_emulation_bytes);
 698                 }
 699
 700                 if (encode_state->packed_header_data[VAEncPackedHeaderPPS]) {
 701                     VAEncPackedHeaderParameterBuffer *param = NULL;
 702                     unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[VAEncPackedHeaderPPS]->buffer;
 703                     unsigned int length_in_bits;
 704
 705                     assert(encode_state->packed_header_param[VAEncPackedHeaderPPS]);
 706                     param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[VAEncPackedHeaderPPS]->buffer;
 707                     length_in_bits = param->length_in_bits[0];
 708
 709                     gen6_mfc_avc_insert_object(ctx,
 710                                                encoder_context,
 711                                                header_data,
 712                                                ALIGN(length_in_bits, 32) >> 5,
 713                                                length_in_bits & 0x1f,
 714                                                param->skip_emulation_check_count,
 715                                                0,
 716                                                0,
 717                                                param->insert_emulation_bytes);
 718                 }
 719
 720                 gen6_mfc_avc_insert_object(ctx, encoder_context,
 721                                            (unsigned int *)slice_header, ALIGN(slice_header_length_in_bits, 32) >> 5, slice_header_length_in_bits & 0x1f,
 722                                            5,  /* first 5 bytes are start code + nal unit type */
 723                                            1, 0, 1);
 724                 emit_new_state = 0;
 725             }
 726
 727             if (is_intra) {
 728                 assert(msg);
 729                 object_len_in_bytes = gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context,target_mb_size, max_mb_size);
 730                 msg += 4;
 731             } else {
 732                 object_len_in_bytes = gen6_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, offset, encoder_context, target_mb_size, max_mb_size, pSliceParameter->slice_type);
 733                 offset += 64;
 734             }
 735
 736             if (intel_batchbuffer_check_free_space(batch, object_len_in_bytes) == 0) {
 737                 assert(0);
 738                 intel_batchbuffer_end_atomic(batch);
 739                 intel_batchbuffer_flush(batch);
 740                 emit_new_state = 1;
 741                 intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
 742             }
 743         }
 744     }
 745
 746     gen6_mfc_avc_insert_object(ctx, encoder_context,
 747                                tail_data, sizeof(tail_data) >> 2, 32,
 748                                sizeof(tail_data), 1, 1, 1);
 749
 750     if (is_intra)
 751         dri_bo_unmap(vme_context->vme_output.bo);
 752
 753     free(slice_header);
 754
 755     intel_batchbuffer_end_atomic(batch);
 756 }
 757
 758 static void
 759 gen6_mfc_free_avc_surface(void **data)
 760 {
 761     struct gen6_mfc_avc_surface_aux *avc_surface = *data;
 762
 763     if (!avc_surface)
 764         return;
 765
 766     dri_bo_unreference(avc_surface->dmv_top);
 767     avc_surface->dmv_top = NULL;
 768     dri_bo_unreference(avc_surface->dmv_bottom);
 769     avc_surface->dmv_bottom = NULL;
 770
 771     free(avc_surface);
 772     *data = NULL;
 773 }
 774
 775 static void gen6_mfc_bit_rate_control_context_init(struct encode_state *encode_state,
 776                                                    struct gen6_mfc_context *mfc_context)
 777 {
 778     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 779
 780     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 781     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 782     float fps =  pSequenceParameter->time_scale * 0.5 / pSequenceParameter->num_units_in_tick ;
 783     int inter_mb_size = pSequenceParameter->bits_per_second * 1.0 / (fps+4.0) / width_in_mbs / height_in_mbs;
 784     int intra_mb_size = inter_mb_size * 5.0;
 785     int i;
 786
 787     mfc_context->bit_rate_control_context[0].target_mb_size = intra_mb_size;
 788     mfc_context->bit_rate_control_context[0].target_frame_size = intra_mb_size * width_in_mbs * height_in_mbs;
 789     mfc_context->bit_rate_control_context[1].target_mb_size = inter_mb_size;
 790     mfc_context->bit_rate_control_context[1].target_frame_size = inter_mb_size * width_in_mbs * height_in_mbs;
 791
 792     for(i = 0 ; i < 2; i++) {
 793         mfc_context->bit_rate_control_context[i].QpPrimeY = 26;
 794         mfc_context->bit_rate_control_context[i].MaxQpNegModifier = 6;
 795         mfc_context->bit_rate_control_context[i].MaxQpPosModifier = 6;
 796         mfc_context->bit_rate_control_context[i].GrowInit = 6;
 797         mfc_context->bit_rate_control_context[i].GrowResistance = 4;
 798         mfc_context->bit_rate_control_context[i].ShrinkInit = 6;
 799         mfc_context->bit_rate_control_context[i].ShrinkResistance = 4;
 800
 801         mfc_context->bit_rate_control_context[i].Correct[0] = 8;
 802         mfc_context->bit_rate_control_context[i].Correct[1] = 4;
 803         mfc_context->bit_rate_control_context[i].Correct[2] = 2;
 804         mfc_context->bit_rate_control_context[i].Correct[3] = 2;
 805         mfc_context->bit_rate_control_context[i].Correct[4] = 4;
 806         mfc_context->bit_rate_control_context[i].Correct[5] = 8;
 807     }
 808
 809     mfc_context->bit_rate_control_context[0].TargetSizeInWord = (intra_mb_size + 16)/ 16;
 810     mfc_context->bit_rate_control_context[1].TargetSizeInWord = (inter_mb_size + 16)/ 16;
 811
 812     mfc_context->bit_rate_control_context[0].MaxSizeInWord = mfc_context->bit_rate_control_context[0].TargetSizeInWord * 1.5;
 813     mfc_context->bit_rate_control_context[1].MaxSizeInWord = mfc_context->bit_rate_control_context[1].TargetSizeInWord * 1.5;
 814 }
 815
 816 static int gen6_mfc_bit_rate_control_context_update(struct encode_state *encode_state,
 817                                                     struct gen6_mfc_context *mfc_context,
 818                                                     int current_frame_size)
 819 {
 820     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
 821     int control_index = 1 - (pSliceParameter->slice_type == SLICE_TYPE_I);
 822     int oldQp = mfc_context->bit_rate_control_context[control_index].QpPrimeY;
 823
 824     /*
 825       printf("conrol_index = %d, start_qp = %d, result = %d, target = %d\n", control_index,
 826       mfc_context->bit_rate_control_context[control_index].QpPrimeY, current_frame_size,
 827       mfc_context->bit_rate_control_context[control_index].target_frame_size );
 828     */
 829
 830     if ( current_frame_size > mfc_context->bit_rate_control_context[control_index].target_frame_size * 4.0 ) {
 831         mfc_context->bit_rate_control_context[control_index].QpPrimeY += 4;
 832     } else if ( current_frame_size > mfc_context->bit_rate_control_context[control_index].target_frame_size * 2.0 ) {
 833         mfc_context->bit_rate_control_context[control_index].QpPrimeY += 3;
 834     } else if ( current_frame_size > mfc_context->bit_rate_control_context[control_index].target_frame_size * 1.50 ) {
 835         mfc_context->bit_rate_control_context[control_index].QpPrimeY += 2;
 836     } else if ( current_frame_size > mfc_context->bit_rate_control_context[control_index].target_frame_size * 1.20 ) {
 837         mfc_context->bit_rate_control_context[control_index].QpPrimeY ++;
 838     } else if (current_frame_size < mfc_context->bit_rate_control_context[control_index].target_frame_size * 0.30 )  {
 839         mfc_context->bit_rate_control_context[control_index].QpPrimeY -= 3;
 840     } else if (current_frame_size < mfc_context->bit_rate_control_context[control_index].target_frame_size * 0.50 )  {
 841         mfc_context->bit_rate_control_context[control_index].QpPrimeY -= 2;
 842     } else if (current_frame_size < mfc_context->bit_rate_control_context[control_index].target_frame_size * 0.80 )  {
 843         mfc_context->bit_rate_control_context[control_index].QpPrimeY --;
 844     }
 845
 846     if ( mfc_context->bit_rate_control_context[control_index].QpPrimeY > 51)
 847         mfc_context->bit_rate_control_context[control_index].QpPrimeY = 51;
 848     if ( mfc_context->bit_rate_control_context[control_index].QpPrimeY < 1)
 849         mfc_context->bit_rate_control_context[control_index].QpPrimeY = 1;
 850
 851     if ( mfc_context->bit_rate_control_context[control_index].QpPrimeY != oldQp)
 852         return 0;
 853
 854     return 1;
 855 }
 856
 857 static VAStatus gen6_mfc_avc_prepare(VADriverContextP ctx,
 858                                      struct encode_state *encode_state,
 859                                      struct intel_encoder_context *encoder_context)
 860 {
 861     struct i965_driver_data *i965 = i965_driver_data(ctx);
 862     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 863     struct object_surface *obj_surface;
 864     struct object_buffer *obj_buffer;
 865     struct gen6_mfc_avc_surface_aux* gen6_avc_surface;
 866     dri_bo *bo;
 867     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 868     VAStatus vaStatus = VA_STATUS_SUCCESS;
 869     int i;
 870
 871     /*Setup all the input&output object*/
 872
 873     /* Setup current frame and current direct mv buffer*/
 874     obj_surface = SURFACE(pPicParameter->CurrPic.picture_id);
 875     assert(obj_surface);
 876     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'));
 877     if ( obj_surface->private_data == NULL) {
 878         gen6_avc_surface = calloc(sizeof(struct gen6_mfc_avc_surface_aux), 1);
 879         gen6_avc_surface->dmv_top =
 880             dri_bo_alloc(i965->intel.bufmgr,
 881                          "Buffer",
 882                          68*8192,
 883                          64);
 884         gen6_avc_surface->dmv_bottom =
 885             dri_bo_alloc(i965->intel.bufmgr,
 886                          "Buffer",
 887                          68*8192,
 888                          64);
 889         assert(gen6_avc_surface->dmv_top);
 890         assert(gen6_avc_surface->dmv_bottom);
 891         obj_surface->private_data = (void *)gen6_avc_surface;
 892         obj_surface->free_private_data = (void *)gen6_mfc_free_avc_surface;
 893     }
 894     gen6_avc_surface = (struct gen6_mfc_avc_surface_aux*) obj_surface->private_data;
 895     mfc_context->direct_mv_buffers[NUM_MFC_DMV_BUFFERS - 2].bo = gen6_avc_surface->dmv_top;
 896     mfc_context->direct_mv_buffers[NUM_MFC_DMV_BUFFERS - 1].bo = gen6_avc_surface->dmv_bottom;
 897     dri_bo_reference(gen6_avc_surface->dmv_top);
 898     dri_bo_reference(gen6_avc_surface->dmv_bottom);
 899
 900     mfc_context->post_deblocking_output.bo = obj_surface->bo;
 901     dri_bo_reference(mfc_context->post_deblocking_output.bo);
 902
 903     mfc_context->surface_state.width = obj_surface->orig_width;
 904     mfc_context->surface_state.height = obj_surface->orig_height;
 905     mfc_context->surface_state.w_pitch = obj_surface->width;
 906     mfc_context->surface_state.h_pitch = obj_surface->height;
 907
 908     /* Setup reference frames and direct mv buffers*/
 909     for(i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++) {
 910         if ( pPicParameter->ReferenceFrames[i].picture_id != VA_INVALID_ID ) {
 911             obj_surface = SURFACE(pPicParameter->ReferenceFrames[i].picture_id);
 912             assert(obj_surface);
 913             if (obj_surface->bo != NULL) {
 914                 mfc_context->reference_surfaces[i].bo = obj_surface->bo;
 915                 dri_bo_reference(obj_surface->bo);
 916             }
 917             /* Check DMV buffer */
 918             if ( obj_surface->private_data == NULL) {
 919
 920                 gen6_avc_surface = calloc(sizeof(struct gen6_mfc_avc_surface_aux), 1);
 921                 gen6_avc_surface->dmv_top =
 922                     dri_bo_alloc(i965->intel.bufmgr,
 923                                  "Buffer",
 924                                  68*8192,
 925                                  64);
 926                 gen6_avc_surface->dmv_bottom =
 927                     dri_bo_alloc(i965->intel.bufmgr,
 928                                  "Buffer",
 929                                  68*8192,
 930                                  64);
 931                 assert(gen6_avc_surface->dmv_top);
 932                 assert(gen6_avc_surface->dmv_bottom);
 933                 obj_surface->private_data = gen6_avc_surface;
 934                 obj_surface->free_private_data = gen6_mfc_free_avc_surface;
 935             }
 936
 937             gen6_avc_surface = (struct gen6_mfc_avc_surface_aux*) obj_surface->private_data;
 938             /* Setup DMV buffer */
 939             mfc_context->direct_mv_buffers[i*2].bo = gen6_avc_surface->dmv_top;
 940             mfc_context->direct_mv_buffers[i*2+1].bo = gen6_avc_surface->dmv_bottom;
 941             dri_bo_reference(gen6_avc_surface->dmv_top);
 942             dri_bo_reference(gen6_avc_surface->dmv_bottom);
 943         } else {
 944             break;
 945         }
 946     }
 947
 948     obj_surface = SURFACE(encode_state->current_render_target);
 949     assert(obj_surface && obj_surface->bo);
 950     mfc_context->uncompressed_picture_source.bo = obj_surface->bo;
 951     dri_bo_reference(mfc_context->uncompressed_picture_source.bo);
 952
 953     obj_buffer = BUFFER (pPicParameter->CodedBuf); /* FIXME: fix this later */
 954     bo = obj_buffer->buffer_store->bo;
 955     assert(bo);
 956     mfc_context->mfc_indirect_pak_bse_object.bo = bo;
 957     mfc_context->mfc_indirect_pak_bse_object.offset = ALIGN(sizeof(VACodedBufferSegment), 64);
 958     mfc_context->mfc_indirect_pak_bse_object.end_offset = ALIGN (obj_buffer->size_element - 0x1000, 0x1000);
 959     dri_bo_reference(mfc_context->mfc_indirect_pak_bse_object.bo);
 960
 961     /*Programing bit rate control */
 962     if ( mfc_context->bit_rate_control_context[0].MaxSizeInWord == 0 )
 963         gen6_mfc_bit_rate_control_context_init(encode_state, mfc_context);
 964
 965     /*Programing bcs pipeline*/
 966     gen6_mfc_avc_pipeline_programing(ctx, encode_state, encoder_context);       //filling the pipeline
 967
 968     return vaStatus;
 969 }
 970
 971 static VAStatus gen6_mfc_run(VADriverContextP ctx,
 972                              struct encode_state *encode_state,
 973                              struct intel_encoder_context *encoder_context)
 974 {
 975     struct intel_batchbuffer *batch = encoder_context->base.batch;
 976
 977     intel_batchbuffer_flush(batch);             //run the pipeline
 978
 979     return VA_STATUS_SUCCESS;
 980 }
 981
 982 static VAStatus gen6_mfc_stop(VADriverContextP ctx,
 983                               struct encode_state *encode_state,
 984                               struct intel_encoder_context *encoder_context,
 985                               int *encoded_bits_size)
 986 {
 987     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 988     unsigned int *status_mem;
 989     unsigned int buffer_size_bits = 0;
 990     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 991     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 992     int i;
 993
 994     dri_bo_map(mfc_context->macroblock_status_buffer.bo, 1);
 995     status_mem = (unsigned int *)mfc_context->macroblock_status_buffer.bo->virtual;
 996     //Detecting encoder buffer size and bit rate control result
 997     for(i = 0; i < width_in_mbs * height_in_mbs; i++) {
 998         unsigned short current_mb = status_mem[1] >> 16;
 999         buffer_size_bits += current_mb;
1000         status_mem += 4;
1001     }
1002     dri_bo_unmap(mfc_context->macroblock_status_buffer.bo);
1003
1004     *encoded_bits_size = buffer_size_bits;
1005
1006     return VA_STATUS_SUCCESS;
1007 }
1008
1009 static VAStatus
1010 gen6_mfc_avc_encode_picture(VADriverContextP ctx,
1011                             struct encode_state *encode_state,
1012                             struct intel_encoder_context *encoder_context)
1013 {
1014     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
1015     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1016     int rate_control_mode = pSequenceParameter->rate_control_method;
1017     int MAX_CBR_INTERATE = 4;
1018     int current_frame_bits_size;
1019     int i;
1020
1021     for(i = 0; i < MAX_CBR_INTERATE; i++) {
1022         gen6_mfc_init(ctx, encoder_context);
1023         gen6_mfc_avc_prepare(ctx, encode_state, encoder_context);
1024         gen6_mfc_run(ctx, encode_state, encoder_context);
1025         gen6_mfc_stop(ctx, encode_state, encoder_context, &current_frame_bits_size);
1026         if ( rate_control_mode == 0) {
1027             if ( gen6_mfc_bit_rate_control_context_update( encode_state, mfc_context, current_frame_bits_size) )
1028                 break;
1029         } else {
1030             break;
1031         }
1032     }
1033
1034     return VA_STATUS_SUCCESS;
1035 }
1036
1037 static VAStatus
1038 gen6_mfc_pipeline(VADriverContextP ctx,
1039                   VAProfile profile,
1040                   struct encode_state *encode_state,
1041                   struct intel_encoder_context *encoder_context)
1042 {
1043     VAStatus vaStatus;
1044
1045     switch (profile) {
1046     case VAProfileH264Baseline:
1047         vaStatus = gen6_mfc_avc_encode_picture(ctx, encode_state, encoder_context);
1048         break;
1049
1050         /* FIXME: add for other profile */
1051     default:
1052         vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
1053         break;
1054     }
1055
1056     return vaStatus;
1057 }
1058
1059 static void
1060 gen6_mfc_context_destroy(void *context)
1061 {
1062     struct gen6_mfc_context *mfc_context = context;
1063     int i;
1064
1065     dri_bo_unreference(mfc_context->post_deblocking_output.bo);
1066     mfc_context->post_deblocking_output.bo = NULL;
1067
1068     dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
1069     mfc_context->pre_deblocking_output.bo = NULL;
1070
1071     dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
1072     mfc_context->uncompressed_picture_source.bo = NULL;
1073
1074     dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
1075     mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
1076
1077     for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
1078         dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
1079         mfc_context->direct_mv_buffers[i].bo = NULL;
1080     }
1081
1082     dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
1083     mfc_context->intra_row_store_scratch_buffer.bo = NULL;
1084
1085     dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
1086     mfc_context->macroblock_status_buffer.bo = NULL;
1087
1088     dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
1089     mfc_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
1090
1091     dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
1092     mfc_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
1093
1094
1095     for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
1096         dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
1097         mfc_context->reference_surfaces[i].bo = NULL;
1098     }
1099
1100     free(mfc_context);
1101 }
1102
1103 Bool gen6_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
1104 {
1105     encoder_context->mfc_context = calloc(1, sizeof(struct gen6_mfc_context));
1106     encoder_context->mfc_context_destroy = gen6_mfc_context_destroy;
1107     encoder_context->mfc_pipeline = gen6_mfc_pipeline;
1108
1109     return True;
1110 }