src/gen6_mfc.c

   1 /*
   2  * Copyright © 2010-2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Zhou Chang <chang.zhou@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <assert.h>
  33
  34 #include "assert.h"
  35 #include "intel_batchbuffer.h"
  36 #include "i965_defines.h"
  37 #include "i965_structs.h"
  38 #include "i965_drv_video.h"
  39 #include "i965_encoder.h"
  40
  41 static void
  42 gen6_mfc_pipe_mode_select(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
  43 {
  44     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
  45
  46     BEGIN_BCS_BATCH(batch, 4);
  47
  48     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (4 - 2));
  49     OUT_BCS_BATCH(batch,
  50                   (0 << 10) | /* disable Stream-Out */
  51                   (1 << 9)  | /* Post Deblocking Output */
  52                   (0 << 8)  | /* Pre Deblocking Output */
  53                   (0 << 7)  | /* disable TLB prefectch */
  54                   (0 << 5)  | /* not in stitch mode */
  55                   (1 << 4)  | /* encoding mode */
  56                   (2 << 0));  /* Standard Select: AVC */
  57     OUT_BCS_BATCH(batch,
  58                   (0 << 20) | /* round flag in PB slice */
  59                   (0 << 19) | /* round flag in Intra8x8 */
  60                   (0 << 7)  | /* expand NOA bus flag */
  61                   (1 << 6)  | /* must be 1 */
  62                   (0 << 5)  | /* disable clock gating for NOA */
  63                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
  64                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
  65                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
  66                   (0 << 1)  | /* AVC long field motion vector */
  67                   (0 << 0));  /* always calculate AVC ILDB boundary strength */
  68     OUT_BCS_BATCH(batch, 0);
  69
  70     ADVANCE_BCS_BATCH(batch);
  71 }
  72
  73 static void
  74 gen7_mfc_pipe_mode_select(VADriverContextP ctx,
  75                           int standard_select,
  76                           struct gen6_encoder_context *gen6_encoder_context)
  77 {
  78     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
  79
  80     assert(standard_select == MFX_FORMAT_MPEG2 ||
  81            standard_select == MFX_FORMAT_AVC);
  82
  83     BEGIN_BCS_BATCH(batch, 5);
  84     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
  85     OUT_BCS_BATCH(batch,
  86                   (MFX_LONG_MODE << 17) | /* Must be long format for encoder */
  87                   (MFD_MODE_VLD << 15) | /* VLD mode */
  88                   (0 << 10) | /* disable Stream-Out */
  89                   (1 << 9)  | /* Post Deblocking Output */
  90                   (0 << 8)  | /* Pre Deblocking Output */
  91                   (0 << 5)  | /* not in stitch mode */
  92                   (1 << 4)  | /* encoding mode */
  93                   (standard_select << 0));  /* standard select: avc or mpeg2 */
  94     OUT_BCS_BATCH(batch,
  95                   (0 << 7)  | /* expand NOA bus flag */
  96                   (0 << 6)  | /* disable slice-level clock gating */
  97                   (0 << 5)  | /* disable clock gating for NOA */
  98                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
  99                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
 100                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
 101                   (0 << 1)  |
 102                   (0 << 0));
 103     OUT_BCS_BATCH(batch, 0);
 104     OUT_BCS_BATCH(batch, 0);
 105
 106     ADVANCE_BCS_BATCH(batch);
 107 }
 108
 109 static void
 110 gen6_mfc_surface_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
 111 {
 112     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 113     struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
 114
 115     BEGIN_BCS_BATCH(batch, 6);
 116
 117     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
 118     OUT_BCS_BATCH(batch, 0);
 119     OUT_BCS_BATCH(batch,
 120                   ((mfc_context->surface_state.height - 1) << 19) |
 121                   ((mfc_context->surface_state.width - 1) << 6));
 122     OUT_BCS_BATCH(batch,
 123                   (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
 124                   (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
 125                   (0 << 22) | /* surface object control state, FIXME??? */
 126                   ((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */
 127                   (0 << 2)  | /* must be 0 for interleave U/V */
 128                   (1 << 1)  | /* must be y-tiled */
 129                   (I965_TILEWALK_YMAJOR << 0));                         /* tile walk, TILEWALK_YMAJOR */
 130     OUT_BCS_BATCH(batch,
 131                   (0 << 16) |                                                           /* must be 0 for interleave U/V */
 132                   (mfc_context->surface_state.h_pitch));                /* y offset for U(cb) */
 133     OUT_BCS_BATCH(batch, 0);
 134     ADVANCE_BCS_BATCH(batch);
 135 }
 136
 137 static void
 138 gen7_mfc_surface_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
 139 {
 140     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 141     struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
 142
 143     BEGIN_BCS_BATCH(batch, 6);
 144
 145     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
 146     OUT_BCS_BATCH(batch, 0);
 147     OUT_BCS_BATCH(batch,
 148                   ((mfc_context->surface_state.height - 1) << 18) |
 149                   ((mfc_context->surface_state.width - 1) << 4));
 150     OUT_BCS_BATCH(batch,
 151                   (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
 152                   (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
 153                   (0 << 22) | /* surface object control state, FIXME??? */
 154                   ((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */
 155                   (0 << 2)  | /* must be 0 for interleave U/V */
 156                   (1 << 1)  | /* must be tiled */
 157                   (I965_TILEWALK_YMAJOR << 0));  /* tile walk, TILEWALK_YMAJOR */
 158     OUT_BCS_BATCH(batch,
 159                   (0 << 16) |                                                           /* must be 0 for interleave U/V */
 160                   (mfc_context->surface_state.h_pitch));                /* y offset for U(cb) */
 161     OUT_BCS_BATCH(batch, 0);
 162     ADVANCE_BCS_BATCH(batch);
 163 }
 164
 165 static void
 166 gen6_mfc_pipe_buf_addr_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
 167 {
 168     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 169     struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
 170     int i;
 171
 172     BEGIN_BCS_BATCH(batch, 24);
 173
 174     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
 175
 176     OUT_BCS_BATCH(batch, 0);                                                                                    /* pre output addr   */
 177
 178     OUT_BCS_RELOC(batch, mfc_context->post_deblocking_output.bo,
 179                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 180                   0);                                                                                   /* post output addr  */
 181
 182     OUT_BCS_RELOC(batch, mfc_context->uncompressed_picture_source.bo,
 183                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 184                   0);                                                                                   /* uncompressed data */
 185
 186     OUT_BCS_BATCH(batch, 0);                                                                                    /* StreamOut data*/
 187     OUT_BCS_RELOC(batch, mfc_context->intra_row_store_scratch_buffer.bo,
 188                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 189                   0);
 190     OUT_BCS_RELOC(batch, mfc_context->deblocking_filter_row_store_scratch_buffer.bo,
 191                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 192                   0);
 193     /* 7..22 Reference pictures*/
 194     for (i = 0; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) {
 195         if ( mfc_context->reference_surfaces[i].bo != NULL) {
 196             OUT_BCS_RELOC(batch, mfc_context->reference_surfaces[i].bo,
 197                           I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 198                           0);
 199         } else {
 200             OUT_BCS_BATCH(batch, 0);
 201         }
 202     }
 203     OUT_BCS_BATCH(batch, 0);                                                                                    /* no block status  */
 204
 205     ADVANCE_BCS_BATCH(batch);
 206 }
 207
 208 static void
 209 gen6_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
 210 {
 211     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 212     struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
 213
 214     BEGIN_BCS_BATCH(batch, 11);
 215
 216     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
 217     OUT_BCS_BATCH(batch, 0);
 218     OUT_BCS_BATCH(batch, 0);
 219     /* MFX Indirect MV Object Base Address */
 220     OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 221     OUT_BCS_BATCH(batch, 0);
 222     OUT_BCS_BATCH(batch, 0);
 223     OUT_BCS_BATCH(batch, 0);
 224     OUT_BCS_BATCH(batch, 0);
 225     OUT_BCS_BATCH(batch, 0);
 226     /*MFC Indirect PAK-BSE Object Base Address for Encoder*/
 227     OUT_BCS_BATCH(batch, 0);
 228     OUT_BCS_BATCH(batch, 0);
 229
 230     ADVANCE_BCS_BATCH(batch);
 231 }
 232
 233 static void
 234 gen7_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
 235 {
 236     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 237     struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
 238
 239     BEGIN_BCS_BATCH(batch, 11);
 240
 241     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
 242     OUT_BCS_BATCH(batch, 0);
 243     OUT_BCS_BATCH(batch, 0);
 244     /* MFX Indirect MV Object Base Address */
 245     OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 246     OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
 247     OUT_BCS_BATCH(batch, 0);
 248     OUT_BCS_BATCH(batch, 0);
 249     OUT_BCS_BATCH(batch, 0);
 250     OUT_BCS_BATCH(batch, 0);
 251     /*MFC Indirect PAK-BSE Object Base Address for Encoder*/
 252     OUT_BCS_BATCH(batch, 0);
 253     OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
 254
 255     ADVANCE_BCS_BATCH(batch);
 256 }
 257
 258 static void
 259 gen6_mfc_bsp_buf_base_addr_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
 260 {
 261     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 262     struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
 263
 264     BEGIN_BCS_BATCH(batch, 4);
 265
 266     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
 267     OUT_BCS_RELOC(batch, mfc_context->bsd_mpc_row_store_scratch_buffer.bo,
 268                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 269                   0);
 270     OUT_BCS_BATCH(batch, 0);
 271     OUT_BCS_BATCH(batch, 0);
 272
 273     ADVANCE_BCS_BATCH(batch);
 274 }
 275
 276 static void
 277 gen6_mfc_avc_img_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
 278 {
 279     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 280     struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
 281
 282     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 283     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 284
 285     BEGIN_BCS_BATCH(batch, 13);
 286     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (13 - 2));
 287     OUT_BCS_BATCH(batch,
 288                   ((width_in_mbs * height_in_mbs) & 0xFFFF));
 289     OUT_BCS_BATCH(batch,
 290                   (height_in_mbs << 16) |
 291                   (width_in_mbs << 0));
 292     OUT_BCS_BATCH(batch,
 293                   (0 << 24) |     /*Second Chroma QP Offset*/
 294                   (0 << 16) |     /*Chroma QP Offset*/
 295                   (0 << 14) |   /*Max-bit conformance Intra flag*/
 296                   (0 << 13) |   /*Max Macroblock size conformance Inter flag*/
 297                   (1 << 12) |   /*Should always be written as "1" */
 298                   (0 << 10) |   /*QM Preset FLag */
 299                   (0 << 8)  |   /*Image Structure*/
 300                   (0 << 0) );   /*Current Decoed Image Frame Store ID, reserved in Encode mode*/
 301     OUT_BCS_BATCH(batch,
 302                   (0 << 16) |   /*Mininum Frame size*/
 303                   (0 << 15) |     /*Disable reading of Macroblock Status Buffer*/
 304                   (0 << 14) |   /*Load BitStream Pointer only once, 1 slic 1 frame*/
 305                   (0 << 13) |   /*CABAC 0 word insertion test enable*/
 306                   (1 << 12) |   /*MVUnpackedEnable,compliant to DXVA*/
 307                   (1 << 10) |   /*Chroma Format IDC, 4:2:0*/
 308                   (1 << 7)  |   /*0:CAVLC encoding mode,1:CABAC*/
 309                   (0 << 6)  |   /*Only valid for VLD decoding mode*/
 310                   (0 << 5)  |   /*Constrained Intra Predition Flag, from PPS*/
 311                   (0 << 4)  |   /*Direct 8x8 inference flag*/
 312                   (0 << 3)  |   /*Only 8x8 IDCT Transform Mode Flag*/
 313                   (1 << 2)  |   /*Frame MB only flag*/
 314                   (0 << 1)  |   /*MBAFF mode is in active*/
 315                   (0 << 0) );   /*Field picture flag*/
 316     OUT_BCS_BATCH(batch, 0);            /*Mainly about MB rate control and debug, just ignoring*/
 317     OUT_BCS_BATCH(batch,                        /*Inter and Intra Conformance Max size limit*/
 318                   (0xBB8 << 16) |               /*InterMbMaxSz*/
 319                   (0xEE8) );                    /*IntraMbMaxSz*/
 320     OUT_BCS_BATCH(batch, 0);            /*Reserved*/
 321     OUT_BCS_BATCH(batch, 0);            /*Slice QP Delta for bitrate control*/
 322     OUT_BCS_BATCH(batch, 0);            /*Slice QP Delta for bitrate control*/
 323     OUT_BCS_BATCH(batch, 0x8C000000);
 324     OUT_BCS_BATCH(batch, 0x00010000);
 325     OUT_BCS_BATCH(batch, 0);
 326
 327     ADVANCE_BCS_BATCH(batch);
 328 }
 329
 330 static void
 331 gen7_mfc_avc_img_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
 332 {
 333     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 334     struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
 335
 336     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 337     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 338
 339     BEGIN_BCS_BATCH(batch, 16);
 340     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
 341     OUT_BCS_BATCH(batch,
 342                   ((width_in_mbs * height_in_mbs) & 0xFFFF));
 343     OUT_BCS_BATCH(batch,
 344                   ((height_in_mbs - 1) << 16) |
 345                   ((width_in_mbs - 1) << 0));
 346     OUT_BCS_BATCH(batch,
 347                   (0 << 24) |   /* Second Chroma QP Offset */
 348                   (0 << 16) |   /* Chroma QP Offset */
 349                   (0 << 14) |   /* Max-bit conformance Intra flag */
 350                   (0 << 13) |   /* Max Macroblock size conformance Inter flag */
 351                   (0 << 12) |   /* FIXME: Weighted_Pred_Flag */
 352                   (0 << 10) |   /* FIXME: Weighted_BiPred_Idc */
 353                   (0 << 8)  |   /* FIXME: Image Structure */
 354                   (0 << 0) );   /* Current Decoed Image Frame Store ID, reserved in Encode mode */
 355     OUT_BCS_BATCH(batch,
 356                   (0 << 16) |   /* Mininum Frame size */
 357                   (0 << 15) |   /* Disable reading of Macroblock Status Buffer */
 358                   (0 << 14) |   /* Load BitStream Pointer only once, 1 slic 1 frame */
 359                   (0 << 13) |   /* CABAC 0 word insertion test enable */
 360                   (1 << 12) |   /* MVUnpackedEnable,compliant to DXVA */
 361                   (1 << 10) |   /* Chroma Format IDC, 4:2:0 */
 362                   (0 << 9)  |   /* FIXME: MbMvFormatFlag */
 363                   (1 << 7)  |   /* 0:CAVLC encoding mode,1:CABAC */
 364                   (0 << 6)  |   /* Only valid for VLD decoding mode */
 365                   (0 << 5)  |   /* Constrained Intra Predition Flag, from PPS */
 366                   (0 << 4)  |   /* Direct 8x8 inference flag */
 367                   (0 << 3)  |   /* Only 8x8 IDCT Transform Mode Flag */
 368                   (1 << 2)  |   /* Frame MB only flag */
 369                   (0 << 1)  |   /* MBAFF mode is in active */
 370                   (0 << 0));    /* Field picture flag */
 371     OUT_BCS_BATCH(batch, 0);    /* Mainly about MB rate control and debug, just ignoring */
 372     OUT_BCS_BATCH(batch,        /* Inter and Intra Conformance Max size limit */
 373                   (0xBB8 << 16) |       /* InterMbMaxSz */
 374                   (0xEE8) );            /* IntraMbMaxSz */
 375     OUT_BCS_BATCH(batch, 0);            /* Reserved */
 376     OUT_BCS_BATCH(batch, 0);            /* Slice QP Delta for bitrate control */
 377     OUT_BCS_BATCH(batch, 0);            /* Slice QP Delta for bitrate control */
 378     OUT_BCS_BATCH(batch, 0x8C000000);
 379     OUT_BCS_BATCH(batch, 0x00010000);
 380     OUT_BCS_BATCH(batch, 0);
 381     OUT_BCS_BATCH(batch, 0);
 382     OUT_BCS_BATCH(batch, 0);
 383     OUT_BCS_BATCH(batch, 0);
 384
 385     ADVANCE_BCS_BATCH(batch);
 386 }
 387
 388 static void gen6_mfc_avc_directmode_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
 389 {
 390     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 391     int i;
 392
 393     BEGIN_BCS_BATCH(batch, 69);
 394
 395     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
 396     //TODO: reference DMV
 397     for(i = 0; i < 16; i++){
 398         OUT_BCS_BATCH(batch, 0);
 399         OUT_BCS_BATCH(batch, 0);
 400     }
 401
 402     //TODO: current DMV just for test
 403 #if 0
 404     OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[0].bo,
 405                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 406                   0);
 407 #else
 408     //drm_intel_bo_pin(mfc_context->direct_mv_buffers[0].bo, 0x1000);
 409     //OUT_BCS_BATCH(batch, mfc_context->direct_mv_buffers[0].bo->offset);
 410     OUT_BCS_BATCH(batch, 0);
 411 #endif
 412
 413
 414     OUT_BCS_BATCH(batch, 0);
 415
 416     //TODO: POL list
 417     for(i = 0; i < 34; i++) {
 418         OUT_BCS_BATCH(batch, 0);
 419     }
 420
 421     ADVANCE_BCS_BATCH(batch);
 422 }
 423
 424 static void gen6_mfc_avc_slice_state(VADriverContextP ctx,
 425                                      int slice_type,
 426                                      struct gen6_encoder_context *gen6_encoder_context)
 427 {
 428     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 429     struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
 430
 431     BEGIN_BCS_BATCH(batch, 11);;
 432
 433     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) );
 434
 435         OUT_BCS_BATCH(batch, slice_type);                       /*Slice Type: I:P:B Slice*/
 436
 437     if ( slice_type == SLICE_TYPE_I )
 438         OUT_BCS_BATCH(batch, 0);                        /*no reference frames and pred_weight_table*/
 439     else
 440         OUT_BCS_BATCH(batch, 0x00010000);       /*1 reference frame*/
 441
 442     OUT_BCS_BATCH(batch, (0<<24) |                /*Enable deblocking operation*/
 443                   (26<<16) |                    /*Slice Quantization Parameter*/
 444                   0x0000 );
 445     OUT_BCS_BATCH(batch, 0);                    /*First MB X&Y , the postion of current slice*/
 446     OUT_BCS_BATCH(batch, ( ((mfc_context->surface_state.height+15)/16) << 16) );
 447
 448     OUT_BCS_BATCH(batch,
 449                   (0<<31) |             /*RateControlCounterEnable = disable*/
 450                   (1<<30) |             /*ResetRateControlCounter*/
 451                   (2<<28) |             /*RC Triggle Mode = Loose Rate Control*/
 452                   (1<<19) |             /*IsLastSlice*/
 453                   (0<<18) |             /*BitstreamOutputFlag Compressed BitStream Output Disable Flag 0:enable 1:disable*/
 454                   (0<<17) |             /*HeaderPresentFlag*/
 455                   (1<<16) |             /*SliceData PresentFlag*/
 456                   (0<<15) |             /*TailPresentFlag*/
 457                   (1<<13) |             /*RBSP NAL TYPE*/
 458                   (0<<12) );            /*CabacZeroWordInsertionEnable*/
 459
 460     OUT_BCS_RELOC(batch, mfc_context->mfc_indirect_pak_bse_object.bo,
 461                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 462                   mfc_context->mfc_indirect_pak_bse_object.offset);
 463
 464     OUT_BCS_BATCH(batch, 0);
 465     OUT_BCS_BATCH(batch, 0);
 466     OUT_BCS_BATCH(batch, 0);
 467
 468     ADVANCE_BCS_BATCH(batch);
 469 }
 470 static void gen6_mfc_avc_qm_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
 471 {
 472     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 473     int i;
 474
 475     BEGIN_BCS_BATCH(batch, 58);
 476
 477     OUT_BCS_BATCH(batch, MFX_AVC_QM_STATE | 56);
 478     OUT_BCS_BATCH(batch, 0xFF ) ;
 479     for( i = 0; i < 56; i++) {
 480         OUT_BCS_BATCH(batch, 0x10101010);
 481     }
 482
 483     ADVANCE_BCS_BATCH(batch);
 484 }
 485
 486 static void gen6_mfc_avc_fqm_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
 487 {
 488     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 489     int i;
 490
 491     BEGIN_BCS_BATCH(batch, 113);
 492     OUT_BCS_BATCH(batch, MFC_AVC_FQM_STATE | (113 - 2));
 493
 494     for(i = 0; i < 112;i++) {
 495         OUT_BCS_BATCH(batch, 0x10001000);
 496     }
 497
 498     ADVANCE_BCS_BATCH(batch);
 499 }
 500
 501 static void
 502 gen7_mfc_qm_state(VADriverContextP ctx,
 503                   int qm_type,
 504                   unsigned int *qm,
 505                   int qm_length,
 506                   struct gen6_encoder_context *gen6_encoder_context)
 507 {
 508     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 509     unsigned int qm_buffer[16];
 510
 511     assert(qm_length <= 16);
 512     assert(sizeof(*qm) == 4);
 513     memcpy(qm_buffer, qm, qm_length * 4);
 514
 515     BEGIN_BCS_BATCH(batch, 18);
 516     OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2));
 517     OUT_BCS_BATCH(batch, qm_type << 0);
 518     intel_batchbuffer_data(batch, qm_buffer, 16 * 4);
 519     ADVANCE_BCS_BATCH(batch);
 520 }
 521
 522 static void gen7_mfc_avc_qm_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
 523 {
 524     unsigned int qm[16] = {
 525         0x10101010, 0x10101010, 0x10101010, 0x10101010,
 526         0x10101010, 0x10101010, 0x10101010, 0x10101010,
 527         0x10101010, 0x10101010, 0x10101010, 0x10101010,
 528         0x10101010, 0x10101010, 0x10101010, 0x10101010
 529     };
 530
 531     gen7_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 12, gen6_encoder_context);
 532     gen7_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 12, gen6_encoder_context);
 533     gen7_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 16, gen6_encoder_context);
 534     gen7_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 16, gen6_encoder_context);
 535 }
 536
 537 static void
 538 gen7_mfc_fqm_state(VADriverContextP ctx,
 539                    int fqm_type,
 540                    unsigned int *fqm,
 541                    int fqm_length,
 542                    struct gen6_encoder_context *gen6_encoder_context)
 543 {
 544     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 545     unsigned int fqm_buffer[32];
 546
 547     assert(fqm_length <= 32);
 548     assert(sizeof(*fqm) == 4);
 549     memcpy(fqm_buffer, fqm, fqm_length * 4);
 550
 551     BEGIN_BCS_BATCH(batch, 34);
 552     OUT_BCS_BATCH(batch, MFX_FQM_STATE | (34 - 2));
 553     OUT_BCS_BATCH(batch, fqm_type << 0);
 554     intel_batchbuffer_data(batch, fqm_buffer, 32 * 4);
 555     ADVANCE_BCS_BATCH(batch);
 556 }
 557
 558 static void gen7_mfc_avc_fqm_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
 559 {
 560     unsigned int qm[32] = {
 561         0x10001000, 0x10001000, 0x10001000, 0x10001000,
 562         0x10001000, 0x10001000, 0x10001000, 0x10001000,
 563         0x10001000, 0x10001000, 0x10001000, 0x10001000,
 564         0x10001000, 0x10001000, 0x10001000, 0x10001000,
 565         0x10001000, 0x10001000, 0x10001000, 0x10001000,
 566         0x10001000, 0x10001000, 0x10001000, 0x10001000,
 567         0x10001000, 0x10001000, 0x10001000, 0x10001000,
 568         0x10001000, 0x10001000, 0x10001000, 0x10001000
 569     };
 570
 571     gen7_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 24, gen6_encoder_context);
 572     gen7_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 24, gen6_encoder_context);
 573     gen7_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 32, gen6_encoder_context);
 574     gen7_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 32, gen6_encoder_context);
 575 }
 576
 577 static void gen6_mfc_avc_ref_idx_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
 578 {
 579     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 580     int i;
 581
 582         BEGIN_BCS_BATCH(batch, 10);
 583         OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
 584         OUT_BCS_BATCH(batch, 0);                  //Select L0
 585         OUT_BCS_BATCH(batch, 0x80808020);         //Only 1 reference
 586         for(i = 0; i < 7; i++) {
 587                 OUT_BCS_BATCH(batch, 0x80808080);
 588         }
 589         ADVANCE_BCS_BATCH(batch);
 590
 591         BEGIN_BCS_BATCH(batch, 10);
 592         OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
 593         OUT_BCS_BATCH(batch, 1);                  //Select L1
 594         OUT_BCS_BATCH(batch, 0x80808022);         //Only 1 reference
 595         for(i = 0; i < 7; i++) {
 596                 OUT_BCS_BATCH(batch, 0x80808080);
 597         }
 598         ADVANCE_BCS_BATCH(batch);
 599 }
 600
 601 static void
 602 gen6_mfc_avc_insert_object(VADriverContextP ctx, int flush_data, struct gen6_encoder_context *gen6_encoder_context)
 603 {
 604     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 605
 606     BEGIN_BCS_BATCH(batch, 4);
 607
 608     OUT_BCS_BATCH(batch, MFC_AVC_INSERT_OBJECT | (4 -2 ) );
 609     OUT_BCS_BATCH(batch, (32<<8) |
 610                   (1 << 3) |
 611                   (1 << 2) |
 612                   (flush_data << 1) |
 613                   (1<<0) );
 614     OUT_BCS_BATCH(batch, 0x00000003);
 615     OUT_BCS_BATCH(batch, 0xABCD1234);
 616
 617     ADVANCE_BCS_BATCH(batch);
 618 }
 619
 620 static int
 621 gen6_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb, int qp,unsigned int *msg,
 622                               struct gen6_encoder_context *gen6_encoder_context)
 623 {
 624     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 625     int len_in_dwords = 11;
 626
 627     BEGIN_BCS_BATCH(batch, len_in_dwords);
 628
 629     OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
 630     OUT_BCS_BATCH(batch, 0);
 631     OUT_BCS_BATCH(batch, 0);
 632     OUT_BCS_BATCH(batch,
 633                   (0 << 24) |           /* PackedMvNum, Debug*/
 634                   (0 << 20) |           /* No motion vector */
 635                   (1 << 19) |           /* CbpDcY */
 636                   (1 << 18) |           /* CbpDcU */
 637                   (1 << 17) |           /* CbpDcV */
 638                   (msg[0] & 0xFFFF) );
 639
 640     OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x);          /* Code Block Pattern for Y*/
 641     OUT_BCS_BATCH(batch, 0x000F000F);                                                   /* Code Block Pattern */
 642     OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp);      /* Last MB */
 643
 644     /*Stuff for Intra MB*/
 645     OUT_BCS_BATCH(batch, msg[1]);                       /* We using Intra16x16 no 4x4 predmode*/
 646     OUT_BCS_BATCH(batch, msg[2]);
 647     OUT_BCS_BATCH(batch, msg[3]&0xFC);
 648
 649     OUT_BCS_BATCH(batch, 0x8040000);    /*MaxSizeInWord and TargetSzieInWord*/
 650
 651     ADVANCE_BCS_BATCH(batch);
 652
 653     return len_in_dwords;
 654 }
 655
 656 static int gen6_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, int qp, unsigned int offset,
 657                                          struct gen6_encoder_context *gen6_encoder_context)
 658 {
 659     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 660     int len_in_dwords = 11;
 661
 662     BEGIN_BCS_BATCH(batch, len_in_dwords);
 663
 664     OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
 665
 666     OUT_BCS_BATCH(batch, 32);         /* 32 MV*/
 667     OUT_BCS_BATCH(batch, offset);
 668
 669     OUT_BCS_BATCH(batch,
 670                   (1 << 24) |     /* PackedMvNum, Debug*/
 671                   (4 << 20) |     /* 8 MV, SNB don't use it*/
 672                   (1 << 19) |     /* CbpDcY */
 673                   (1 << 18) |     /* CbpDcU */
 674                   (1 << 17) |     /* CbpDcV */
 675                   (0 << 15) |     /* Transform8x8Flag = 0*/
 676                   (0 << 14) |     /* Frame based*/
 677                   (0 << 13) |     /* Inter MB */
 678                   (1 << 8)  |     /* MbType = P_L0_16x16 */
 679                   (0 << 7)  |     /* MBZ for frame */
 680                   (0 << 6)  |     /* MBZ */
 681                   (2 << 4)  |     /* MBZ for inter*/
 682                   (0 << 3)  |     /* MBZ */
 683                   (0 << 2)  |     /* SkipMbFlag */
 684                   (0 << 0));      /* InterMbMode */
 685
 686     OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x);        /* Code Block Pattern for Y*/
 687     OUT_BCS_BATCH(batch, 0x000F000F);                         /* Code Block Pattern */
 688     OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp);    /* Last MB */
 689
 690     /*Stuff for Inter MB*/
 691     OUT_BCS_BATCH(batch, 0x0);
 692     OUT_BCS_BATCH(batch, 0x0);
 693     OUT_BCS_BATCH(batch, 0x0);
 694
 695     OUT_BCS_BATCH(batch, 0xF0020000); /*MaxSizeInWord and TargetSzieInWord*/
 696
 697     ADVANCE_BCS_BATCH(batch);
 698
 699     return len_in_dwords;
 700 }
 701
 702 static void gen6_mfc_init(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
 703 {
 704     struct i965_driver_data *i965 = i965_driver_data(ctx);
 705     struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
 706     dri_bo *bo;
 707     int i;
 708
 709     /*Encode common setup for MFC*/
 710     dri_bo_unreference(mfc_context->post_deblocking_output.bo);
 711     mfc_context->post_deblocking_output.bo = NULL;
 712
 713     dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
 714     mfc_context->pre_deblocking_output.bo = NULL;
 715
 716     dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
 717     mfc_context->uncompressed_picture_source.bo = NULL;
 718
 719     dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
 720     mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
 721
 722     for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
 723         dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
 724         mfc_context->direct_mv_buffers[i].bo = NULL;
 725     }
 726
 727     for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
 728         if (mfc_context->reference_surfaces[i].bo != NULL)
 729             dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
 730         mfc_context->reference_surfaces[i].bo = NULL;
 731     }
 732
 733     dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
 734     bo = dri_bo_alloc(i965->intel.bufmgr,
 735                       "Buffer",
 736                       128 * 64,
 737                       64);
 738     assert(bo);
 739     mfc_context->intra_row_store_scratch_buffer.bo = bo;
 740
 741     dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
 742     bo = dri_bo_alloc(i965->intel.bufmgr,
 743                       "Buffer",
 744                       49152,  /* 6 * 128 * 64 */
 745                       64);
 746     assert(bo);
 747     mfc_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
 748
 749     dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
 750     bo = dri_bo_alloc(i965->intel.bufmgr,
 751                       "Buffer",
 752                       12288, /* 1.5 * 128 * 64 */
 753                       0x1000);
 754     assert(bo);
 755     mfc_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
 756 }
 757
 758 void gen6_mfc_avc_pipeline_programing(VADriverContextP ctx,
 759                                       struct encode_state *encode_state,
 760                                       struct gen6_encoder_context *gen6_encoder_context)
 761 {
 762     struct i965_driver_data *i965 = i965_driver_data(ctx);
 763     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 764     struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
 765     struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
 766     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param->buffer;
 767     VAEncSliceParameterBufferH264Ext *pSliceParameter = (VAEncSliceParameterBufferH264Ext *)encode_state->slice_params[0]->buffer; /* FIXME: multi slices */
 768     unsigned int *msg = NULL, offset = 0;
 769     int emit_new_state = 1, object_len_in_bytes;
 770     int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
 771     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 772     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 773     int x,y;
 774
 775     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
 776
 777     if (is_intra) {
 778         dri_bo_map(vme_context->vme_output.bo , 1);
 779         msg = (unsigned int *)vme_context->vme_output.bo->virtual;
 780     }
 781
 782     for (y = 0; y < height_in_mbs; y++) {
 783         for (x = 0; x < width_in_mbs; x++) {
 784             int last_mb = (y == (height_in_mbs-1)) && ( x == (width_in_mbs-1) );
 785             int qp = pSequenceParameter->initial_qp;
 786
 787             if (emit_new_state) {
 788                 intel_batchbuffer_emit_mi_flush(batch);
 789
 790                 if (IS_GEN7(i965->intel.device_id)) {
 791                     gen7_mfc_pipe_mode_select(ctx, MFX_FORMAT_AVC, gen6_encoder_context);
 792                     gen7_mfc_surface_state(ctx, gen6_encoder_context);
 793                     gen7_mfc_ind_obj_base_addr_state(ctx, gen6_encoder_context);
 794                 } else {
 795                     gen6_mfc_pipe_mode_select(ctx, gen6_encoder_context);
 796                     gen6_mfc_surface_state(ctx, gen6_encoder_context);
 797                     gen6_mfc_ind_obj_base_addr_state(ctx, gen6_encoder_context);
 798                 }
 799
 800                 gen6_mfc_pipe_buf_addr_state(ctx, gen6_encoder_context);
 801                 gen6_mfc_bsp_buf_base_addr_state(ctx, gen6_encoder_context);
 802
 803                 if (IS_GEN7(i965->intel.device_id)) {
 804                     gen7_mfc_avc_img_state(ctx, gen6_encoder_context);
 805                     gen7_mfc_avc_qm_state(ctx, gen6_encoder_context);
 806                     gen7_mfc_avc_fqm_state(ctx, gen6_encoder_context);
 807                 } else {
 808                     gen6_mfc_avc_img_state(ctx, gen6_encoder_context);
 809                     gen6_mfc_avc_qm_state(ctx, gen6_encoder_context);
 810                     gen6_mfc_avc_fqm_state(ctx, gen6_encoder_context);
 811                 }
 812
 813                 gen6_mfc_avc_ref_idx_state(ctx, gen6_encoder_context);
 814                 gen6_mfc_avc_slice_state(ctx, pSliceParameter->slice_type, gen6_encoder_context);
 815                 emit_new_state = 0;
 816             }
 817
 818             if (is_intra) {
 819                 assert(msg);
 820                 object_len_in_bytes = gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, gen6_encoder_context);
 821                 msg += 4;
 822             } else {
 823                 object_len_in_bytes = gen6_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, offset, gen6_encoder_context);
 824                 offset += 64;
 825             }
 826
 827             if (intel_batchbuffer_check_free_space(batch, object_len_in_bytes) == 0) {
 828                 intel_batchbuffer_end_atomic(batch);
 829                 intel_batchbuffer_flush(batch);
 830                 emit_new_state = 1;
 831                 intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
 832             }
 833         }
 834     }
 835
 836     if (is_intra)
 837         dri_bo_unmap(vme_context->vme_output.bo);
 838
 839     intel_batchbuffer_end_atomic(batch);
 840 }
 841
 842 static VAStatus gen6_mfc_avc_prepare(VADriverContextP ctx,
 843                                      struct encode_state *encode_state,
 844                                      struct gen6_encoder_context *gen6_encoder_context)
 845 {
 846     struct i965_driver_data *i965 = i965_driver_data(ctx);
 847     struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
 848     struct object_surface *obj_surface;
 849     struct object_buffer *obj_buffer;
 850     dri_bo *bo;
 851     VAEncPictureParameterBufferH264Ext *pPicParameter = (VAEncPictureParameterBufferH264Ext *)encode_state->pic_param->buffer;
 852     VAStatus vaStatus = VA_STATUS_SUCCESS;
 853         int i;
 854
 855     /*Setup all the input&output object*/
 856     obj_surface = SURFACE(pPicParameter->CurrPic.picture_id);
 857     assert(obj_surface);
 858     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'));
 859
 860     mfc_context->post_deblocking_output.bo = obj_surface->bo;
 861     dri_bo_reference(mfc_context->post_deblocking_output.bo);
 862
 863     mfc_context->surface_state.width = obj_surface->orig_width;
 864     mfc_context->surface_state.height = obj_surface->orig_height;
 865     mfc_context->surface_state.w_pitch = obj_surface->width;
 866     mfc_context->surface_state.h_pitch = obj_surface->height;
 867
 868     for(i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++) {
 869                 if ( pPicParameter->ReferenceFrames[i].picture_id != VA_INVALID_ID ) {
 870                         obj_surface = SURFACE(pPicParameter->ReferenceFrames[i].picture_id);
 871                         assert(obj_surface);
 872                         if (obj_surface->bo != NULL) {
 873                                 mfc_context->reference_surfaces[i].bo = obj_surface->bo;
 874                                 dri_bo_reference(obj_surface->bo);
 875                         }
 876                 } else {
 877                         break;
 878                 }
 879         }
 880
 881     obj_surface = SURFACE(encode_state->current_render_target);
 882     assert(obj_surface && obj_surface->bo);
 883     mfc_context->uncompressed_picture_source.bo = obj_surface->bo;
 884     dri_bo_reference(mfc_context->uncompressed_picture_source.bo);
 885
 886     obj_buffer = BUFFER (pPicParameter->CodedBuf); /* FIXME: fix this later */
 887     bo = obj_buffer->buffer_store->bo;
 888     assert(bo);
 889     mfc_context->mfc_indirect_pak_bse_object.bo = bo;
 890     mfc_context->mfc_indirect_pak_bse_object.offset = ALIGN(sizeof(VACodedBufferSegment), 64);
 891     dri_bo_reference(mfc_context->mfc_indirect_pak_bse_object.bo);
 892
 893     /*Programing bcs pipeline*/
 894     gen6_mfc_avc_pipeline_programing(ctx, encode_state, gen6_encoder_context);  //filling the pipeline
 895
 896     return vaStatus;
 897 }
 898
 899 static VAStatus gen6_mfc_run(VADriverContextP ctx,
 900                              struct encode_state *encode_state,
 901                              struct gen6_encoder_context *gen6_encoder_context)
 902 {
 903     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 904
 905     intel_batchbuffer_flush(batch);             //run the pipeline
 906
 907     return VA_STATUS_SUCCESS;
 908 }
 909
 910 static VAStatus gen6_mfc_stop(VADriverContextP ctx,
 911                               struct encode_state *encode_state,
 912                               struct gen6_encoder_context *gen6_encoder_context)
 913 {
 914 #if 0
 915     struct i965_driver_data *i965 = i965_driver_data(ctx);
 916     struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
 917
 918     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param->buffer;
 919
 920     struct object_surface *obj_surface = SURFACE(pPicParameter->reconstructed_picture);
 921     //struct object_surface *obj_surface = SURFACE(pPicParameter->reference_picture[0]);
 922     //struct object_surface *obj_surface = SURFACE(encode_state->current_render_target);
 923     my_debug(obj_surface);
 924
 925 #endif
 926
 927     return VA_STATUS_SUCCESS;
 928 }
 929
 930 static VAStatus
 931 gen6_mfc_avc_encode_picture(VADriverContextP ctx,
 932                             struct encode_state *encode_state,
 933                             struct gen6_encoder_context *gen6_encoder_context)
 934 {
 935     gen6_mfc_init(ctx, gen6_encoder_context);
 936     gen6_mfc_avc_prepare(ctx, encode_state, gen6_encoder_context);
 937     gen6_mfc_run(ctx, encode_state, gen6_encoder_context);
 938     gen6_mfc_stop(ctx, encode_state, gen6_encoder_context);
 939
 940     return VA_STATUS_SUCCESS;
 941 }
 942
 943 VAStatus
 944 gen6_mfc_pipeline(VADriverContextP ctx,
 945                   VAProfile profile,
 946                   struct encode_state *encode_state,
 947                   struct gen6_encoder_context *gen6_encoder_context)
 948 {
 949     VAStatus vaStatus;
 950
 951     switch (profile) {
 952     case VAProfileH264Baseline:
 953         vaStatus = gen6_mfc_avc_encode_picture(ctx, encode_state, gen6_encoder_context);
 954         break;
 955
 956         /* FIXME: add for other profile */
 957     default:
 958         vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
 959         break;
 960     }
 961
 962     return vaStatus;
 963 }
 964
 965 Bool gen6_mfc_context_init(VADriverContextP ctx, struct gen6_mfc_context *mfc_context)
 966 {
 967     return True;
 968 }
 969
 970 Bool gen6_mfc_context_destroy(struct gen6_mfc_context *mfc_context)
 971 {
 972     int i;
 973
 974     dri_bo_unreference(mfc_context->post_deblocking_output.bo);
 975     mfc_context->post_deblocking_output.bo = NULL;
 976
 977     dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
 978     mfc_context->pre_deblocking_output.bo = NULL;
 979
 980     dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
 981     mfc_context->uncompressed_picture_source.bo = NULL;
 982
 983     dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
 984     mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
 985
 986     for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
 987         dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
 988         mfc_context->direct_mv_buffers[i].bo = NULL;
 989     }
 990
 991     dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
 992     mfc_context->intra_row_store_scratch_buffer.bo = NULL;
 993
 994     dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
 995     mfc_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
 996
 997     dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
 998     mfc_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
 999
1000     return True;
1001 }