2 * Copyright © 2010-2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Zhou Chang <chang.zhou@intel.com>
35 #include "intel_batchbuffer.h"
36 #include "i965_defines.h"
37 #include "i965_structs.h"
38 #include "i965_drv_video.h"
39 #include "i965_encoder.h"
42 gen6_mfc_pipe_mode_select(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
44 struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
46 BEGIN_BCS_BATCH(batch, 4);
48 OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (4 - 2));
50 (0 << 10) | /* disable Stream-Out */
51 (1 << 9) | /* Post Deblocking Output */
52 (0 << 8) | /* Pre Deblocking Output */
53 (0 << 7) | /* disable TLB prefectch */
54 (0 << 5) | /* not in stitch mode */
55 (1 << 4) | /* encoding mode */
56 (2 << 0)); /* Standard Select: AVC */
58 (0 << 20) | /* round flag in PB slice */
59 (0 << 19) | /* round flag in Intra8x8 */
60 (0 << 7) | /* expand NOA bus flag */
61 (1 << 6) | /* must be 1 */
62 (0 << 5) | /* disable clock gating for NOA */
63 (0 << 4) | /* terminate if AVC motion and POC table error occurs */
64 (0 << 3) | /* terminate if AVC mbdata error occurs */
65 (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */
66 (0 << 1) | /* AVC long field motion vector */
67 (0 << 0)); /* always calculate AVC ILDB boundary strength */
68 OUT_BCS_BATCH(batch, 0);
70 ADVANCE_BCS_BATCH(batch);
74 gen7_mfc_pipe_mode_select(VADriverContextP ctx,
76 struct gen6_encoder_context *gen6_encoder_context)
78 struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
80 assert(standard_select == MFX_FORMAT_MPEG2 ||
81 standard_select == MFX_FORMAT_AVC);
83 BEGIN_BCS_BATCH(batch, 5);
84 OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
86 (MFX_LONG_MODE << 17) | /* Must be long format for encoder */
87 (MFD_MODE_VLD << 15) | /* VLD mode */
88 (0 << 10) | /* disable Stream-Out */
89 (1 << 9) | /* Post Deblocking Output */
90 (0 << 8) | /* Pre Deblocking Output */
91 (0 << 5) | /* not in stitch mode */
92 (1 << 4) | /* encoding mode */
93 (standard_select << 0)); /* standard select: avc or mpeg2 */
95 (0 << 7) | /* expand NOA bus flag */
96 (0 << 6) | /* disable slice-level clock gating */
97 (0 << 5) | /* disable clock gating for NOA */
98 (0 << 4) | /* terminate if AVC motion and POC table error occurs */
99 (0 << 3) | /* terminate if AVC mbdata error occurs */
100 (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */
103 OUT_BCS_BATCH(batch, 0);
104 OUT_BCS_BATCH(batch, 0);
106 ADVANCE_BCS_BATCH(batch);
110 gen6_mfc_surface_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
112 struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
113 struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
115 BEGIN_BCS_BATCH(batch, 6);
117 OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
118 OUT_BCS_BATCH(batch, 0);
120 ((mfc_context->surface_state.height - 1) << 19) |
121 ((mfc_context->surface_state.width - 1) << 6));
123 (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
124 (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
125 (0 << 22) | /* surface object control state, FIXME??? */
126 ((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */
127 (0 << 2) | /* must be 0 for interleave U/V */
128 (1 << 1) | /* must be y-tiled */
129 (I965_TILEWALK_YMAJOR << 0)); /* tile walk, TILEWALK_YMAJOR */
131 (0 << 16) | /* must be 0 for interleave U/V */
132 (mfc_context->surface_state.h_pitch)); /* y offset for U(cb) */
133 OUT_BCS_BATCH(batch, 0);
134 ADVANCE_BCS_BATCH(batch);
138 gen7_mfc_surface_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
140 struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
141 struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
143 BEGIN_BCS_BATCH(batch, 6);
145 OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
146 OUT_BCS_BATCH(batch, 0);
148 ((mfc_context->surface_state.height - 1) << 18) |
149 ((mfc_context->surface_state.width - 1) << 4));
151 (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
152 (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
153 (0 << 22) | /* surface object control state, FIXME??? */
154 ((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */
155 (0 << 2) | /* must be 0 for interleave U/V */
156 (1 << 1) | /* must be tiled */
157 (I965_TILEWALK_YMAJOR << 0)); /* tile walk, TILEWALK_YMAJOR */
159 (0 << 16) | /* must be 0 for interleave U/V */
160 (mfc_context->surface_state.h_pitch)); /* y offset for U(cb) */
161 OUT_BCS_BATCH(batch, 0);
162 ADVANCE_BCS_BATCH(batch);
166 gen6_mfc_pipe_buf_addr_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
168 struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
169 struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
172 BEGIN_BCS_BATCH(batch, 24);
174 OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
176 OUT_BCS_BATCH(batch, 0); /* pre output addr */
178 OUT_BCS_RELOC(batch, mfc_context->post_deblocking_output.bo,
179 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
180 0); /* post output addr */
182 OUT_BCS_RELOC(batch, mfc_context->uncompressed_picture_source.bo,
183 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
184 0); /* uncompressed data */
186 OUT_BCS_BATCH(batch, 0); /* StreamOut data*/
187 OUT_BCS_RELOC(batch, mfc_context->intra_row_store_scratch_buffer.bo,
188 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
190 OUT_BCS_RELOC(batch, mfc_context->deblocking_filter_row_store_scratch_buffer.bo,
191 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
193 /* 7..22 Reference pictures*/
194 for (i = 0; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) {
195 if ( mfc_context->reference_surfaces[i].bo != NULL) {
196 OUT_BCS_RELOC(batch, mfc_context->reference_surfaces[i].bo,
197 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
200 OUT_BCS_BATCH(batch, 0);
203 OUT_BCS_BATCH(batch, 0); /* no block status */
205 ADVANCE_BCS_BATCH(batch);
209 gen6_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
211 struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
212 struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
214 BEGIN_BCS_BATCH(batch, 11);
216 OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
217 OUT_BCS_BATCH(batch, 0);
218 OUT_BCS_BATCH(batch, 0);
219 /* MFX Indirect MV Object Base Address */
220 OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
221 OUT_BCS_BATCH(batch, 0);
222 OUT_BCS_BATCH(batch, 0);
223 OUT_BCS_BATCH(batch, 0);
224 OUT_BCS_BATCH(batch, 0);
225 OUT_BCS_BATCH(batch, 0);
226 /*MFC Indirect PAK-BSE Object Base Address for Encoder*/
227 OUT_BCS_BATCH(batch, 0);
228 OUT_BCS_BATCH(batch, 0);
230 ADVANCE_BCS_BATCH(batch);
234 gen7_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
236 struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
237 struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
239 BEGIN_BCS_BATCH(batch, 11);
241 OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
242 OUT_BCS_BATCH(batch, 0);
243 OUT_BCS_BATCH(batch, 0);
244 /* MFX Indirect MV Object Base Address */
245 OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
246 OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
247 OUT_BCS_BATCH(batch, 0);
248 OUT_BCS_BATCH(batch, 0);
249 OUT_BCS_BATCH(batch, 0);
250 OUT_BCS_BATCH(batch, 0);
251 /*MFC Indirect PAK-BSE Object Base Address for Encoder*/
252 OUT_BCS_BATCH(batch, 0);
253 OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
255 ADVANCE_BCS_BATCH(batch);
259 gen6_mfc_bsp_buf_base_addr_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
261 struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
262 struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
264 BEGIN_BCS_BATCH(batch, 4);
266 OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
267 OUT_BCS_RELOC(batch, mfc_context->bsd_mpc_row_store_scratch_buffer.bo,
268 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
270 OUT_BCS_BATCH(batch, 0);
271 OUT_BCS_BATCH(batch, 0);
273 ADVANCE_BCS_BATCH(batch);
277 gen6_mfc_avc_img_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
279 struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
280 struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
282 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
283 int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
285 BEGIN_BCS_BATCH(batch, 13);
286 OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (13 - 2));
288 ((width_in_mbs * height_in_mbs) & 0xFFFF));
290 (height_in_mbs << 16) |
291 (width_in_mbs << 0));
293 (0 << 24) | /*Second Chroma QP Offset*/
294 (0 << 16) | /*Chroma QP Offset*/
295 (0 << 14) | /*Max-bit conformance Intra flag*/
296 (0 << 13) | /*Max Macroblock size conformance Inter flag*/
297 (1 << 12) | /*Should always be written as "1" */
298 (0 << 10) | /*QM Preset FLag */
299 (0 << 8) | /*Image Structure*/
300 (0 << 0) ); /*Current Decoed Image Frame Store ID, reserved in Encode mode*/
302 (0 << 16) | /*Mininum Frame size*/
303 (0 << 15) | /*Disable reading of Macroblock Status Buffer*/
304 (0 << 14) | /*Load BitStream Pointer only once, 1 slic 1 frame*/
305 (0 << 13) | /*CABAC 0 word insertion test enable*/
306 (1 << 12) | /*MVUnpackedEnable,compliant to DXVA*/
307 (1 << 10) | /*Chroma Format IDC, 4:2:0*/
308 (1 << 7) | /*0:CAVLC encoding mode,1:CABAC*/
309 (0 << 6) | /*Only valid for VLD decoding mode*/
310 (0 << 5) | /*Constrained Intra Predition Flag, from PPS*/
311 (0 << 4) | /*Direct 8x8 inference flag*/
312 (0 << 3) | /*Only 8x8 IDCT Transform Mode Flag*/
313 (1 << 2) | /*Frame MB only flag*/
314 (0 << 1) | /*MBAFF mode is in active*/
315 (0 << 0) ); /*Field picture flag*/
316 OUT_BCS_BATCH(batch, 0); /*Mainly about MB rate control and debug, just ignoring*/
317 OUT_BCS_BATCH(batch, /*Inter and Intra Conformance Max size limit*/
318 (0xBB8 << 16) | /*InterMbMaxSz*/
319 (0xEE8) ); /*IntraMbMaxSz*/
320 OUT_BCS_BATCH(batch, 0); /*Reserved*/
321 OUT_BCS_BATCH(batch, 0); /*Slice QP Delta for bitrate control*/
322 OUT_BCS_BATCH(batch, 0); /*Slice QP Delta for bitrate control*/
323 OUT_BCS_BATCH(batch, 0x8C000000);
324 OUT_BCS_BATCH(batch, 0x00010000);
325 OUT_BCS_BATCH(batch, 0);
327 ADVANCE_BCS_BATCH(batch);
331 gen7_mfc_avc_img_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
333 struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
334 struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
336 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
337 int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
339 BEGIN_BCS_BATCH(batch, 16);
340 OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
342 ((width_in_mbs * height_in_mbs) & 0xFFFF));
344 ((height_in_mbs - 1) << 16) |
345 ((width_in_mbs - 1) << 0));
347 (0 << 24) | /* Second Chroma QP Offset */
348 (0 << 16) | /* Chroma QP Offset */
349 (0 << 14) | /* Max-bit conformance Intra flag */
350 (0 << 13) | /* Max Macroblock size conformance Inter flag */
351 (0 << 12) | /* FIXME: Weighted_Pred_Flag */
352 (0 << 10) | /* FIXME: Weighted_BiPred_Idc */
353 (0 << 8) | /* FIXME: Image Structure */
354 (0 << 0) ); /* Current Decoed Image Frame Store ID, reserved in Encode mode */
356 (0 << 16) | /* Mininum Frame size */
357 (0 << 15) | /* Disable reading of Macroblock Status Buffer */
358 (0 << 14) | /* Load BitStream Pointer only once, 1 slic 1 frame */
359 (0 << 13) | /* CABAC 0 word insertion test enable */
360 (1 << 12) | /* MVUnpackedEnable,compliant to DXVA */
361 (1 << 10) | /* Chroma Format IDC, 4:2:0 */
362 (0 << 9) | /* FIXME: MbMvFormatFlag */
363 (1 << 7) | /* 0:CAVLC encoding mode,1:CABAC */
364 (0 << 6) | /* Only valid for VLD decoding mode */
365 (0 << 5) | /* Constrained Intra Predition Flag, from PPS */
366 (0 << 4) | /* Direct 8x8 inference flag */
367 (0 << 3) | /* Only 8x8 IDCT Transform Mode Flag */
368 (1 << 2) | /* Frame MB only flag */
369 (0 << 1) | /* MBAFF mode is in active */
370 (0 << 0)); /* Field picture flag */
371 OUT_BCS_BATCH(batch, 0); /* Mainly about MB rate control and debug, just ignoring */
372 OUT_BCS_BATCH(batch, /* Inter and Intra Conformance Max size limit */
373 (0xBB8 << 16) | /* InterMbMaxSz */
374 (0xEE8) ); /* IntraMbMaxSz */
375 OUT_BCS_BATCH(batch, 0); /* Reserved */
376 OUT_BCS_BATCH(batch, 0); /* Slice QP Delta for bitrate control */
377 OUT_BCS_BATCH(batch, 0); /* Slice QP Delta for bitrate control */
378 OUT_BCS_BATCH(batch, 0x8C000000);
379 OUT_BCS_BATCH(batch, 0x00010000);
380 OUT_BCS_BATCH(batch, 0);
381 OUT_BCS_BATCH(batch, 0);
382 OUT_BCS_BATCH(batch, 0);
383 OUT_BCS_BATCH(batch, 0);
385 ADVANCE_BCS_BATCH(batch);
388 static void gen6_mfc_avc_directmode_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
390 struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
393 BEGIN_BCS_BATCH(batch, 69);
395 OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
396 //TODO: reference DMV
397 for(i = 0; i < 16; i++){
398 OUT_BCS_BATCH(batch, 0);
399 OUT_BCS_BATCH(batch, 0);
402 //TODO: current DMV just for test
404 OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[0].bo,
405 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
408 //drm_intel_bo_pin(mfc_context->direct_mv_buffers[0].bo, 0x1000);
409 //OUT_BCS_BATCH(batch, mfc_context->direct_mv_buffers[0].bo->offset);
410 OUT_BCS_BATCH(batch, 0);
414 OUT_BCS_BATCH(batch, 0);
417 for(i = 0; i < 34; i++) {
418 OUT_BCS_BATCH(batch, 0);
421 ADVANCE_BCS_BATCH(batch);
424 static void gen6_mfc_avc_slice_state(VADriverContextP ctx,
426 struct gen6_encoder_context *gen6_encoder_context)
428 struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
429 struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
431 BEGIN_BCS_BATCH(batch, 11);;
433 OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) );
436 OUT_BCS_BATCH(batch, 2); /*Slice Type: I Slice*/
438 OUT_BCS_BATCH(batch, 0); /*Slice Type: P Slice*/
441 OUT_BCS_BATCH(batch, 0); /*no reference frames and pred_weight_table*/
443 OUT_BCS_BATCH(batch, 0x00010000); /*1 reference frame*/
445 OUT_BCS_BATCH(batch, (0<<24) | /*Enable deblocking operation*/
446 (26<<16) | /*Slice Quantization Parameter*/
448 OUT_BCS_BATCH(batch, 0); /*First MB X&Y , the postion of current slice*/
449 OUT_BCS_BATCH(batch, ( ((mfc_context->surface_state.height+15)/16) << 16) );
452 (0<<31) | /*RateControlCounterEnable = disable*/
453 (1<<30) | /*ResetRateControlCounter*/
454 (2<<28) | /*RC Triggle Mode = Loose Rate Control*/
455 (1<<19) | /*IsLastSlice*/
456 (0<<18) | /*BitstreamOutputFlag Compressed BitStream Output Disable Flag 0:enable 1:disable*/
457 (0<<17) | /*HeaderPresentFlag*/
458 (1<<16) | /*SliceData PresentFlag*/
459 (0<<15) | /*TailPresentFlag*/
460 (1<<13) | /*RBSP NAL TYPE*/
461 (0<<12) ); /*CabacZeroWordInsertionEnable*/
463 OUT_BCS_RELOC(batch, mfc_context->mfc_indirect_pak_bse_object.bo,
464 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
465 mfc_context->mfc_indirect_pak_bse_object.offset);
467 OUT_BCS_BATCH(batch, 0);
468 OUT_BCS_BATCH(batch, 0);
469 OUT_BCS_BATCH(batch, 0);
471 ADVANCE_BCS_BATCH(batch);
473 static void gen6_mfc_avc_qm_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
475 struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
478 BEGIN_BCS_BATCH(batch, 58);
480 OUT_BCS_BATCH(batch, MFX_AVC_QM_STATE | 56);
481 OUT_BCS_BATCH(batch, 0xFF ) ;
482 for( i = 0; i < 56; i++) {
483 OUT_BCS_BATCH(batch, 0x10101010);
486 ADVANCE_BCS_BATCH(batch);
489 static void gen6_mfc_avc_fqm_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
491 struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
494 BEGIN_BCS_BATCH(batch, 113);
495 OUT_BCS_BATCH(batch, MFC_AVC_FQM_STATE | (113 - 2));
497 for(i = 0; i < 112;i++) {
498 OUT_BCS_BATCH(batch, 0x10001000);
501 ADVANCE_BCS_BATCH(batch);
505 gen7_mfc_qm_state(VADriverContextP ctx,
509 struct gen6_encoder_context *gen6_encoder_context)
511 struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
512 unsigned int qm_buffer[16];
514 assert(qm_length <= 16);
515 assert(sizeof(*qm) == 4);
516 memcpy(qm_buffer, qm, qm_length * 4);
518 BEGIN_BCS_BATCH(batch, 18);
519 OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2));
520 OUT_BCS_BATCH(batch, qm_type << 0);
521 intel_batchbuffer_data(batch, qm_buffer, 16 * 4);
522 ADVANCE_BCS_BATCH(batch);
525 static void gen7_mfc_avc_qm_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
527 unsigned int qm[16] = {
528 0x10101010, 0x10101010, 0x10101010, 0x10101010,
529 0x10101010, 0x10101010, 0x10101010, 0x10101010,
530 0x10101010, 0x10101010, 0x10101010, 0x10101010,
531 0x10101010, 0x10101010, 0x10101010, 0x10101010
534 gen7_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 12, gen6_encoder_context);
535 gen7_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 12, gen6_encoder_context);
536 gen7_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 16, gen6_encoder_context);
537 gen7_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 16, gen6_encoder_context);
541 gen7_mfc_fqm_state(VADriverContextP ctx,
545 struct gen6_encoder_context *gen6_encoder_context)
547 struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
548 unsigned int fqm_buffer[32];
550 assert(fqm_length <= 32);
551 assert(sizeof(*fqm) == 4);
552 memcpy(fqm_buffer, fqm, fqm_length * 4);
554 BEGIN_BCS_BATCH(batch, 34);
555 OUT_BCS_BATCH(batch, MFX_FQM_STATE | (34 - 2));
556 OUT_BCS_BATCH(batch, fqm_type << 0);
557 intel_batchbuffer_data(batch, fqm_buffer, 32 * 4);
558 ADVANCE_BCS_BATCH(batch);
561 static void gen7_mfc_avc_fqm_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
563 unsigned int qm[32] = {
564 0x10001000, 0x10001000, 0x10001000, 0x10001000,
565 0x10001000, 0x10001000, 0x10001000, 0x10001000,
566 0x10001000, 0x10001000, 0x10001000, 0x10001000,
567 0x10001000, 0x10001000, 0x10001000, 0x10001000,
568 0x10001000, 0x10001000, 0x10001000, 0x10001000,
569 0x10001000, 0x10001000, 0x10001000, 0x10001000,
570 0x10001000, 0x10001000, 0x10001000, 0x10001000,
571 0x10001000, 0x10001000, 0x10001000, 0x10001000
574 gen7_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 24, gen6_encoder_context);
575 gen7_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 24, gen6_encoder_context);
576 gen7_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 32, gen6_encoder_context);
577 gen7_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 32, gen6_encoder_context);
580 static void gen6_mfc_avc_ref_idx_state(VADriverContextP ctx, struct gen6_encoder_context *gen6_encoder_context)
582 struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
585 BEGIN_BCS_BATCH(batch, 10);
587 OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
588 OUT_BCS_BATCH(batch, 0); //Select L0
590 OUT_BCS_BATCH(batch, 0x80808000); //Only 1 reference
591 for(i = 0; i < 7; i++) {
592 OUT_BCS_BATCH(batch, 0x80808080);
595 ADVANCE_BCS_BATCH(batch);
599 gen6_mfc_avc_insert_object(VADriverContextP ctx, int flush_data, struct gen6_encoder_context *gen6_encoder_context)
601 struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
603 BEGIN_BCS_BATCH(batch, 4);
605 OUT_BCS_BATCH(batch, MFC_AVC_INSERT_OBJECT | (4 -2 ) );
606 OUT_BCS_BATCH(batch, (32<<8) |
611 OUT_BCS_BATCH(batch, 0x00000003);
612 OUT_BCS_BATCH(batch, 0xABCD1234);
614 ADVANCE_BCS_BATCH(batch);
618 gen6_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb, int qp,unsigned int *msg,
619 struct gen6_encoder_context *gen6_encoder_context)
621 struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
622 int len_in_dwords = 11;
624 BEGIN_BCS_BATCH(batch, len_in_dwords);
626 OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
627 OUT_BCS_BATCH(batch, 0);
628 OUT_BCS_BATCH(batch, 0);
630 (0 << 24) | /* PackedMvNum, Debug*/
631 (0 << 20) | /* No motion vector */
632 (1 << 19) | /* CbpDcY */
633 (1 << 18) | /* CbpDcU */
634 (1 << 17) | /* CbpDcV */
637 OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x); /* Code Block Pattern for Y*/
638 OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */
639 OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp); /* Last MB */
641 /*Stuff for Intra MB*/
642 OUT_BCS_BATCH(batch, msg[1]); /* We using Intra16x16 no 4x4 predmode*/
643 OUT_BCS_BATCH(batch, msg[2]);
644 OUT_BCS_BATCH(batch, msg[3]&0xFC);
646 OUT_BCS_BATCH(batch, 0x8040000); /*MaxSizeInWord and TargetSzieInWord*/
648 ADVANCE_BCS_BATCH(batch);
650 return len_in_dwords;
653 static int gen6_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, int qp, unsigned int offset,
654 struct gen6_encoder_context *gen6_encoder_context)
656 struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
657 int len_in_dwords = 11;
659 BEGIN_BCS_BATCH(batch, len_in_dwords);
661 OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
663 OUT_BCS_BATCH(batch, 32); /* 32 MV*/
664 OUT_BCS_BATCH(batch, offset);
667 (1 << 24) | /* PackedMvNum, Debug*/
668 (4 << 20) | /* 8 MV, SNB don't use it*/
669 (1 << 19) | /* CbpDcY */
670 (1 << 18) | /* CbpDcU */
671 (1 << 17) | /* CbpDcV */
672 (0 << 15) | /* Transform8x8Flag = 0*/
673 (0 << 14) | /* Frame based*/
674 (0 << 13) | /* Inter MB */
675 (1 << 8) | /* MbType = P_L0_16x16 */
676 (0 << 7) | /* MBZ for frame */
678 (2 << 4) | /* MBZ for inter*/
680 (0 << 2) | /* SkipMbFlag */
681 (0 << 0)); /* InterMbMode */
683 OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x); /* Code Block Pattern for Y*/
684 OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */
685 OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp); /* Last MB */
687 /*Stuff for Inter MB*/
688 OUT_BCS_BATCH(batch, 0x0);
689 OUT_BCS_BATCH(batch, 0x0);
690 OUT_BCS_BATCH(batch, 0x0);
692 OUT_BCS_BATCH(batch, 0xF0020000); /*MaxSizeInWord and TargetSzieInWord*/
694 ADVANCE_BCS_BATCH(batch);
696 return len_in_dwords;
699 static void gen6_mfc_init(VADriverContextP ctx,
700 struct encode_state *encode_state,
701 struct gen6_encoder_context *gen6_encoder_context)
703 struct i965_driver_data *i965 = i965_driver_data(ctx);
704 struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
707 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param->buffer;
708 int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
709 int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
711 /*Encode common setup for MFC*/
712 dri_bo_unreference(mfc_context->post_deblocking_output.bo);
713 mfc_context->post_deblocking_output.bo = NULL;
715 dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
716 mfc_context->pre_deblocking_output.bo = NULL;
718 dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
719 mfc_context->uncompressed_picture_source.bo = NULL;
721 dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
722 mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
724 for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
725 dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
726 mfc_context->direct_mv_buffers[i].bo = NULL;
729 for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
730 if (mfc_context->reference_surfaces[i].bo != NULL)
731 dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
732 mfc_context->reference_surfaces[i].bo = NULL;
735 dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
736 bo = dri_bo_alloc(i965->intel.bufmgr,
741 mfc_context->intra_row_store_scratch_buffer.bo = bo;
743 dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
744 bo = dri_bo_alloc(i965->intel.bufmgr,
746 4 * width_in_mbs * 64, /* 4 * width_in_mbs * 64 */
749 mfc_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
751 dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
752 bo = dri_bo_alloc(i965->intel.bufmgr,
754 128 * width_in_mbs, /* 2 * widht_in_mbs * 64 */
757 mfc_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
760 void gen6_mfc_avc_pipeline_programing(VADriverContextP ctx,
761 struct encode_state *encode_state,
762 struct gen6_encoder_context *gen6_encoder_context)
764 struct i965_driver_data *i965 = i965_driver_data(ctx);
765 struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
766 struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
767 struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
768 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param->buffer;
769 VAEncSliceParameterBuffer *pSliceParameter = (VAEncSliceParameterBuffer *)encode_state->slice_params[0]->buffer; /* FIXME: multi slices */
770 unsigned int *msg = NULL, offset = 0;
771 int emit_new_state = 1, object_len_in_bytes;
772 int is_intra = pSliceParameter->slice_flags.bits.is_intra;
773 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
774 int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
777 intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
780 dri_bo_map(vme_context->vme_output.bo , 1);
781 msg = (unsigned int *)vme_context->vme_output.bo->virtual;
784 for (y = 0; y < height_in_mbs; y++) {
785 for (x = 0; x < width_in_mbs; x++) {
786 int last_mb = (y == (height_in_mbs-1)) && ( x == (width_in_mbs-1) );
787 int qp = pSequenceParameter->initial_qp;
789 if (emit_new_state) {
790 intel_batchbuffer_emit_mi_flush(batch);
792 if (IS_GEN7(i965->intel.device_id)) {
793 gen7_mfc_pipe_mode_select(ctx, MFX_FORMAT_AVC, gen6_encoder_context);
794 gen7_mfc_surface_state(ctx, gen6_encoder_context);
795 gen7_mfc_ind_obj_base_addr_state(ctx, gen6_encoder_context);
797 gen6_mfc_pipe_mode_select(ctx, gen6_encoder_context);
798 gen6_mfc_surface_state(ctx, gen6_encoder_context);
799 gen6_mfc_ind_obj_base_addr_state(ctx, gen6_encoder_context);
802 gen6_mfc_pipe_buf_addr_state(ctx, gen6_encoder_context);
803 gen6_mfc_bsp_buf_base_addr_state(ctx, gen6_encoder_context);
805 if (IS_GEN7(i965->intel.device_id)) {
806 gen7_mfc_avc_img_state(ctx, gen6_encoder_context);
807 gen7_mfc_avc_qm_state(ctx, gen6_encoder_context);
808 gen7_mfc_avc_fqm_state(ctx, gen6_encoder_context);
810 gen6_mfc_avc_img_state(ctx, gen6_encoder_context);
811 gen6_mfc_avc_qm_state(ctx, gen6_encoder_context);
812 gen6_mfc_avc_fqm_state(ctx, gen6_encoder_context);
815 gen6_mfc_avc_ref_idx_state(ctx, gen6_encoder_context);
816 gen6_mfc_avc_slice_state(ctx, is_intra, gen6_encoder_context);
822 object_len_in_bytes = gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, gen6_encoder_context);
825 object_len_in_bytes = gen6_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, offset, gen6_encoder_context);
829 if (intel_batchbuffer_check_free_space(batch, object_len_in_bytes) == 0) {
830 intel_batchbuffer_end_atomic(batch);
831 intel_batchbuffer_flush(batch);
833 intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
839 dri_bo_unmap(vme_context->vme_output.bo);
841 intel_batchbuffer_end_atomic(batch);
844 static VAStatus gen6_mfc_avc_prepare(VADriverContextP ctx,
845 struct encode_state *encode_state,
846 struct gen6_encoder_context *gen6_encoder_context)
848 struct i965_driver_data *i965 = i965_driver_data(ctx);
849 struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
850 struct object_surface *obj_surface;
851 struct object_buffer *obj_buffer;
853 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param->buffer;
854 VAStatus vaStatus = VA_STATUS_SUCCESS;
856 /*Setup all the input&output object*/
857 obj_surface = SURFACE(pPicParameter->reconstructed_picture);
859 i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
860 mfc_context->post_deblocking_output.bo = obj_surface->bo;
861 dri_bo_reference(mfc_context->post_deblocking_output.bo);
863 mfc_context->surface_state.width = obj_surface->orig_width;
864 mfc_context->surface_state.height = obj_surface->orig_height;
865 mfc_context->surface_state.w_pitch = obj_surface->width;
866 mfc_context->surface_state.h_pitch = obj_surface->height;
868 obj_surface = SURFACE(pPicParameter->reference_picture);
870 if (obj_surface->bo != NULL) {
871 mfc_context->reference_surfaces[0].bo = obj_surface->bo;
872 dri_bo_reference(obj_surface->bo);
875 obj_surface = SURFACE(encode_state->current_render_target);
876 assert(obj_surface && obj_surface->bo);
877 mfc_context->uncompressed_picture_source.bo = obj_surface->bo;
878 dri_bo_reference(mfc_context->uncompressed_picture_source.bo);
880 obj_buffer = BUFFER (pPicParameter->coded_buf); /* FIXME: fix this later */
881 bo = obj_buffer->buffer_store->bo;
883 mfc_context->mfc_indirect_pak_bse_object.bo = bo;
884 mfc_context->mfc_indirect_pak_bse_object.offset = ALIGN(sizeof(VACodedBufferSegment), 64);
885 dri_bo_reference(mfc_context->mfc_indirect_pak_bse_object.bo);
887 /*Programing bcs pipeline*/
888 gen6_mfc_avc_pipeline_programing(ctx, encode_state, gen6_encoder_context); //filling the pipeline
893 static VAStatus gen6_mfc_run(VADriverContextP ctx,
894 struct encode_state *encode_state,
895 struct gen6_encoder_context *gen6_encoder_context)
897 struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
899 intel_batchbuffer_flush(batch); //run the pipeline
901 return VA_STATUS_SUCCESS;
904 static VAStatus gen6_mfc_stop(VADriverContextP ctx,
905 struct encode_state *encode_state,
906 struct gen6_encoder_context *gen6_encoder_context)
909 struct i965_driver_data *i965 = i965_driver_data(ctx);
910 struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
912 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param->buffer;
914 struct object_surface *obj_surface = SURFACE(pPicParameter->reconstructed_picture);
915 //struct object_surface *obj_surface = SURFACE(pPicParameter->reference_picture[0]);
916 //struct object_surface *obj_surface = SURFACE(encode_state->current_render_target);
917 my_debug(obj_surface);
921 return VA_STATUS_SUCCESS;
925 gen6_mfc_avc_encode_picture(VADriverContextP ctx,
926 struct encode_state *encode_state,
927 struct gen6_encoder_context *gen6_encoder_context)
929 gen6_mfc_init(ctx, encode_state, gen6_encoder_context);
930 gen6_mfc_avc_prepare(ctx, encode_state, gen6_encoder_context);
931 gen6_mfc_run(ctx, encode_state, gen6_encoder_context);
932 gen6_mfc_stop(ctx, encode_state, gen6_encoder_context);
934 return VA_STATUS_SUCCESS;
938 gen6_mfc_pipeline(VADriverContextP ctx,
940 struct encode_state *encode_state,
941 struct gen6_encoder_context *gen6_encoder_context)
946 case VAProfileH264Baseline:
947 vaStatus = gen6_mfc_avc_encode_picture(ctx, encode_state, gen6_encoder_context);
950 /* FIXME: add for other profile */
952 vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
959 Bool gen6_mfc_context_init(VADriverContextP ctx, struct gen6_mfc_context *mfc_context)
964 Bool gen6_mfc_context_destroy(struct gen6_mfc_context *mfc_context)
968 dri_bo_unreference(mfc_context->post_deblocking_output.bo);
969 mfc_context->post_deblocking_output.bo = NULL;
971 dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
972 mfc_context->pre_deblocking_output.bo = NULL;
974 dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
975 mfc_context->uncompressed_picture_source.bo = NULL;
977 dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
978 mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
980 for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
981 dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
982 mfc_context->direct_mv_buffers[i].bo = NULL;
985 dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
986 mfc_context->intra_row_store_scratch_buffer.bo = NULL;
988 dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
989 mfc_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
991 dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
992 mfc_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;