2 * Copyright © 2010-2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Zhou Chang <chang.zhou@intel.com>
35 #include "intel_batchbuffer.h"
36 #include "i965_defines.h"
37 #include "i965_structs.h"
38 #include "i965_drv_video.h"
39 #include "i965_encoder.h"
40 #include "i965_encoder_utils.h"
43 #include "intel_media.h"
45 static const uint32_t gen6_mfc_batchbuffer_avc_intra[][4] = {
46 #include "shaders/utils/mfc_batchbuffer_avc_intra.g6b"
49 static const uint32_t gen6_mfc_batchbuffer_avc_inter[][4] = {
50 #include "shaders/utils/mfc_batchbuffer_avc_inter.g6b"
53 static struct i965_kernel gen6_mfc_kernels[] = {
55 "MFC AVC INTRA BATCHBUFFER ",
56 MFC_BATCHBUFFER_AVC_INTRA,
57 gen6_mfc_batchbuffer_avc_intra,
58 sizeof(gen6_mfc_batchbuffer_avc_intra),
63 "MFC AVC INTER BATCHBUFFER ",
64 MFC_BATCHBUFFER_AVC_INTER,
65 gen6_mfc_batchbuffer_avc_inter,
66 sizeof(gen6_mfc_batchbuffer_avc_inter),
72 gen6_mfc_pipe_mode_select(VADriverContextP ctx,
74 struct intel_encoder_context *encoder_context)
76 struct intel_batchbuffer *batch = encoder_context->base.batch;
77 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
79 assert(standard_select == MFX_FORMAT_AVC);
81 BEGIN_BCS_BATCH(batch, 4);
83 OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (4 - 2));
85 (1 << 10) | /* disable Stream-Out , advanced QP/bitrate control need enable it*/
86 ((!!mfc_context->post_deblocking_output.bo) << 9) | /* Post Deblocking Output */
87 ((!!mfc_context->pre_deblocking_output.bo) << 8) | /* Pre Deblocking Output */
88 (0 << 7) | /* disable TLB prefectch */
89 (0 << 5) | /* not in stitch mode */
90 (1 << 4) | /* encoding mode */
91 (2 << 0)); /* Standard Select: AVC */
93 (0 << 20) | /* round flag in PB slice */
94 (0 << 19) | /* round flag in Intra8x8 */
95 (0 << 7) | /* expand NOA bus flag */
96 (1 << 6) | /* must be 1 */
97 (0 << 5) | /* disable clock gating for NOA */
98 (0 << 4) | /* terminate if AVC motion and POC table error occurs */
99 (0 << 3) | /* terminate if AVC mbdata error occurs */
100 (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */
101 (0 << 1) | /* AVC long field motion vector */
102 (0 << 0)); /* always calculate AVC ILDB boundary strength */
103 OUT_BCS_BATCH(batch, 0);
105 ADVANCE_BCS_BATCH(batch);
109 gen6_mfc_surface_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
111 struct intel_batchbuffer *batch = encoder_context->base.batch;
112 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
114 BEGIN_BCS_BATCH(batch, 6);
116 OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
117 OUT_BCS_BATCH(batch, 0);
119 ((mfc_context->surface_state.height - 1) << 19) |
120 ((mfc_context->surface_state.width - 1) << 6));
122 (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
123 (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
124 (0 << 22) | /* surface object control state, FIXME??? */
125 ((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */
126 (0 << 2) | /* must be 0 for interleave U/V */
127 (1 << 1) | /* must be y-tiled */
128 (I965_TILEWALK_YMAJOR << 0)); /* tile walk, TILEWALK_YMAJOR */
130 (0 << 16) | /* must be 0 for interleave U/V */
131 (mfc_context->surface_state.h_pitch)); /* y offset for U(cb) */
132 OUT_BCS_BATCH(batch, 0);
133 ADVANCE_BCS_BATCH(batch);
137 gen6_mfc_pipe_buf_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
139 struct intel_batchbuffer *batch = encoder_context->base.batch;
140 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
143 BEGIN_BCS_BATCH(batch, 24);
145 OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
147 if (mfc_context->pre_deblocking_output.bo)
148 OUT_BCS_RELOC(batch, mfc_context->pre_deblocking_output.bo,
149 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
152 OUT_BCS_BATCH(batch, 0); /* pre output addr */
154 if (mfc_context->post_deblocking_output.bo)
155 OUT_BCS_RELOC(batch, mfc_context->post_deblocking_output.bo,
156 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
157 0); /* post output addr */
159 OUT_BCS_BATCH(batch, 0);
161 OUT_BCS_RELOC(batch, mfc_context->uncompressed_picture_source.bo,
162 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
163 0); /* uncompressed data */
164 OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
165 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
166 0); /* StreamOut data*/
167 OUT_BCS_RELOC(batch, mfc_context->intra_row_store_scratch_buffer.bo,
168 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
170 OUT_BCS_RELOC(batch, mfc_context->deblocking_filter_row_store_scratch_buffer.bo,
171 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
173 /* 7..22 Reference pictures*/
174 for (i = 0; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) {
175 if ( mfc_context->reference_surfaces[i].bo != NULL) {
176 OUT_BCS_RELOC(batch, mfc_context->reference_surfaces[i].bo,
177 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
180 OUT_BCS_BATCH(batch, 0);
183 OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
184 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
185 0); /* Macroblock status buffer*/
187 ADVANCE_BCS_BATCH(batch);
191 gen6_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
193 struct intel_batchbuffer *batch = encoder_context->base.batch;
194 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
195 struct gen6_vme_context *vme_context = encoder_context->vme_context;
197 BEGIN_BCS_BATCH(batch, 11);
199 OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
200 OUT_BCS_BATCH(batch, 0);
201 OUT_BCS_BATCH(batch, 0);
202 /* MFX Indirect MV Object Base Address */
203 OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
204 OUT_BCS_BATCH(batch, 0);
205 OUT_BCS_BATCH(batch, 0);
206 OUT_BCS_BATCH(batch, 0);
207 OUT_BCS_BATCH(batch, 0);
208 OUT_BCS_BATCH(batch, 0);
209 /*MFC Indirect PAK-BSE Object Base Address for Encoder*/
211 mfc_context->mfc_indirect_pak_bse_object.bo,
212 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
215 mfc_context->mfc_indirect_pak_bse_object.bo,
216 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
217 mfc_context->mfc_indirect_pak_bse_object.end_offset);
219 ADVANCE_BCS_BATCH(batch);
223 gen6_mfc_bsp_buf_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
225 struct intel_batchbuffer *batch = encoder_context->base.batch;
226 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
228 BEGIN_BCS_BATCH(batch, 4);
230 OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
231 OUT_BCS_RELOC(batch, mfc_context->bsd_mpc_row_store_scratch_buffer.bo,
232 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
234 OUT_BCS_BATCH(batch, 0);
235 OUT_BCS_BATCH(batch, 0);
237 ADVANCE_BCS_BATCH(batch);
241 gen6_mfc_avc_img_state(VADriverContextP ctx,struct encode_state *encode_state,
242 struct intel_encoder_context *encoder_context)
244 struct intel_batchbuffer *batch = encoder_context->base.batch;
245 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
246 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
247 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
248 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
249 int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
251 BEGIN_BCS_BATCH(batch, 13);
252 OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (13 - 2));
254 ((width_in_mbs * height_in_mbs) & 0xFFFF));
256 (height_in_mbs << 16) |
257 (width_in_mbs << 0));
259 (0 << 24) | /*Second Chroma QP Offset*/
260 (0 << 16) | /*Chroma QP Offset*/
261 (0 << 14) | /*Max-bit conformance Intra flag*/
262 (0 << 13) | /*Max Macroblock size conformance Inter flag*/
263 (1 << 12) | /*Should always be written as "1" */
264 (0 << 10) | /*QM Preset FLag */
265 (0 << 8) | /*Image Structure*/
266 (0 << 0) ); /*Current Decoed Image Frame Store ID, reserved in Encode mode*/
268 (400 << 16) | /*Mininum Frame size*/
269 (0 << 15) | /*Disable reading of Macroblock Status Buffer*/
270 (0 << 14) | /*Load BitStream Pointer only once, 1 slic 1 frame*/
271 (0 << 13) | /*CABAC 0 word insertion test enable*/
272 (1 << 12) | /*MVUnpackedEnable,compliant to DXVA*/
273 (1 << 10) | /*Chroma Format IDC, 4:2:0*/
274 (pPicParameter->pic_fields.bits.entropy_coding_mode_flag << 7) | /*0:CAVLC encoding mode,1:CABAC*/
275 (0 << 6) | /*Only valid for VLD decoding mode*/
276 (0 << 5) | /*Constrained Intra Predition Flag, from PPS*/
277 (pSequenceParameter->seq_fields.bits.direct_8x8_inference_flag << 4) | /*Direct 8x8 inference flag*/
278 (pPicParameter->pic_fields.bits.transform_8x8_mode_flag << 3) | /*8x8 or 4x4 IDCT Transform Mode Flag*/
279 (1 << 2) | /*Frame MB only flag*/
280 (0 << 1) | /*MBAFF mode is in active*/
281 (0 << 0) ); /*Field picture flag*/
283 (1<<16) | /*Frame Size Rate Control Flag*/
285 (1<<9) | /*MB level Rate Control Enabling Flag*/
286 (1 << 3) | /*FrameBitRateMinReportMask*/
287 (1 << 2) | /*FrameBitRateMaxReportMask*/
288 (1 << 1) | /*InterMBMaxSizeReportMask*/
289 (1 << 0) ); /*IntraMBMaxSizeReportMask*/
290 OUT_BCS_BATCH(batch, /*Inter and Intra Conformance Max size limit*/
291 (0x0600 << 16) | /*InterMbMaxSz 192 Byte*/
292 (0x0800) ); /*IntraMbMaxSz 256 Byte*/
293 OUT_BCS_BATCH(batch, 0x00000000); /*Reserved : MBZReserved*/
294 OUT_BCS_BATCH(batch, 0x01020304); /*Slice QP Delta for bitrate control*/
295 OUT_BCS_BATCH(batch, 0xFEFDFCFB);
296 OUT_BCS_BATCH(batch, 0x80601004); /*MAX = 128KB, MIN = 64KB*/
297 OUT_BCS_BATCH(batch, 0x00800001);
298 OUT_BCS_BATCH(batch, 0);
300 ADVANCE_BCS_BATCH(batch);
304 gen6_mfc_avc_directmode_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
306 struct intel_batchbuffer *batch = encoder_context->base.batch;
307 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
311 BEGIN_BCS_BATCH(batch, 69);
313 OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
315 /* Reference frames and Current frames */
316 for(i = 0; i < NUM_MFC_DMV_BUFFERS; i++) {
317 if ( mfc_context->direct_mv_buffers[i].bo != NULL) {
318 OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[i].bo,
319 I915_GEM_DOMAIN_INSTRUCTION, 0,
322 OUT_BCS_BATCH(batch, 0);
327 for(i = 0; i < 32; i++) {
328 OUT_BCS_BATCH(batch, i/2);
330 OUT_BCS_BATCH(batch, 0);
331 OUT_BCS_BATCH(batch, 0);
333 ADVANCE_BCS_BATCH(batch);
337 gen6_mfc_avc_slice_state(VADriverContextP ctx,
338 VAEncPictureParameterBufferH264 *pic_param,
339 VAEncSliceParameterBufferH264 *slice_param,
340 struct encode_state *encode_state,
341 struct intel_encoder_context *encoder_context,
342 int rate_control_enable,
344 struct intel_batchbuffer *batch)
346 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
347 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
348 int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
349 int beginmb = slice_param->macroblock_address;
350 int endmb = beginmb + slice_param->num_macroblocks;
351 int beginx = beginmb % width_in_mbs;
352 int beginy = beginmb / width_in_mbs;
353 int nextx = endmb % width_in_mbs;
354 int nexty = endmb / width_in_mbs;
355 int slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
356 int last_slice = (endmb == (width_in_mbs * height_in_mbs));
358 unsigned char correct[6], grow, shrink;
360 int weighted_pred_idc = 0;
361 unsigned int luma_log2_weight_denom = slice_param->luma_log2_weight_denom;
362 unsigned int chroma_log2_weight_denom = slice_param->chroma_log2_weight_denom;
366 batch = encoder_context->base.batch;
368 if (slice_type == SLICE_TYPE_P) {
369 weighted_pred_idc = pic_param->pic_fields.bits.weighted_pred_flag;
370 } else if (slice_type == SLICE_TYPE_B) {
371 weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc;
374 if (weighted_pred_idc == 2) {
375 /* 8.4.3 - Derivation process for prediction weights (8-279) */
376 luma_log2_weight_denom = 5;
377 chroma_log2_weight_denom = 5;
381 maxQpN = mfc_context->bit_rate_control_context[slice_type].MaxQpNegModifier;
382 maxQpP = mfc_context->bit_rate_control_context[slice_type].MaxQpPosModifier;
384 for (i = 0; i < 6; i++)
385 correct[i] = mfc_context->bit_rate_control_context[slice_type].Correct[i];
387 grow = mfc_context->bit_rate_control_context[slice_type].GrowInit +
388 (mfc_context->bit_rate_control_context[slice_type].GrowResistance << 4);
389 shrink = mfc_context->bit_rate_control_context[slice_type].ShrinkInit +
390 (mfc_context->bit_rate_control_context[slice_type].ShrinkResistance << 4);
392 BEGIN_BCS_BATCH(batch, 11);;
394 OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) );
395 OUT_BCS_BATCH(batch, slice_type); /*Slice Type: I:P:B Slice*/
397 if (slice_type == SLICE_TYPE_I) {
398 OUT_BCS_BATCH(batch, 0); /*no reference frames and pred_weight_table*/
401 (1 << 16) | (bslice << 24) | /*1 reference frame*/
402 (chroma_log2_weight_denom << 8) |
403 (luma_log2_weight_denom << 0));
407 (weighted_pred_idc << 30) |
408 (slice_param->direct_spatial_mv_pred_flag<<29) | /*Direct Prediction Type*/
409 (slice_param->disable_deblocking_filter_idc << 27) |
410 (slice_param->cabac_init_idc << 24) |
411 (qp<<16) | /*Slice Quantization Parameter*/
412 ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
413 ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
415 (beginy << 24) | /*First MB X&Y , the begin postion of current slice*/
417 slice_param->macroblock_address );
418 OUT_BCS_BATCH(batch, (nexty << 16) | nextx); /*Next slice first MB X&Y*/
420 (0/*rate_control_enable*/ << 31) | /*in CBR mode RateControlCounterEnable = enable*/
421 (1 << 30) | /*ResetRateControlCounter*/
422 (0 << 28) | /*RC Triggle Mode = Always Rate Control*/
423 (4 << 24) | /*RC Stable Tolerance, middle level*/
424 (0/*rate_control_enable*/ << 23) | /*RC Panic Enable*/
425 (0 << 22) | /*QP mode, don't modfiy CBP*/
426 (0 << 21) | /*MB Type Direct Conversion Enabled*/
427 (0 << 20) | /*MB Type Skip Conversion Enabled*/
428 (last_slice << 19) | /*IsLastSlice*/
429 (0 << 18) | /*BitstreamOutputFlag Compressed BitStream Output Disable Flag 0:enable 1:disable*/
430 (1 << 17) | /*HeaderPresentFlag*/
431 (1 << 16) | /*SliceData PresentFlag*/
432 (1 << 15) | /*TailPresentFlag*/
433 (1 << 13) | /*RBSP NAL TYPE*/
434 (0 << 12) ); /*CabacZeroWordInsertionEnable*/
435 OUT_BCS_BATCH(batch, mfc_context->mfc_indirect_pak_bse_object.offset);
437 (maxQpN << 24) | /*Target QP - 24 is lowest QP*/
438 (maxQpP << 16) | /*Target QP + 20 is highest QP*/
448 OUT_BCS_BATCH(batch, 0);
450 ADVANCE_BCS_BATCH(batch);
453 static void gen6_mfc_avc_qm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
455 struct intel_batchbuffer *batch = encoder_context->base.batch;
458 BEGIN_BCS_BATCH(batch, 58);
460 OUT_BCS_BATCH(batch, MFX_AVC_QM_STATE | 56);
461 OUT_BCS_BATCH(batch, 0xFF ) ;
462 for( i = 0; i < 56; i++) {
463 OUT_BCS_BATCH(batch, 0x10101010);
466 ADVANCE_BCS_BATCH(batch);
469 static void gen6_mfc_avc_fqm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
471 struct intel_batchbuffer *batch = encoder_context->base.batch;
474 BEGIN_BCS_BATCH(batch, 113);
475 OUT_BCS_BATCH(batch, MFC_AVC_FQM_STATE | (113 - 2));
477 for(i = 0; i < 112;i++) {
478 OUT_BCS_BATCH(batch, 0x10001000);
481 ADVANCE_BCS_BATCH(batch);
485 gen6_mfc_avc_insert_object(VADriverContextP ctx, struct intel_encoder_context *encoder_context,
486 unsigned int *insert_data, int lenght_in_dws, int data_bits_in_last_dw,
487 int skip_emul_byte_count, int is_last_header, int is_end_of_slice, int emulation_flag,
488 struct intel_batchbuffer *batch)
491 batch = encoder_context->base.batch;
493 BEGIN_BCS_BATCH(batch, lenght_in_dws + 2);
495 OUT_BCS_BATCH(batch, MFC_AVC_INSERT_OBJECT | (lenght_in_dws + 2 - 2));
498 (0 << 16) | /* always start at offset 0 */
499 (data_bits_in_last_dw << 8) |
500 (skip_emul_byte_count << 4) |
501 (!!emulation_flag << 3) |
502 ((!!is_last_header) << 2) |
503 ((!!is_end_of_slice) << 1) |
504 (0 << 0)); /* FIXME: ??? */
506 intel_batchbuffer_data(batch, insert_data, lenght_in_dws * 4);
507 ADVANCE_BCS_BATCH(batch);
511 gen6_mfc_init(VADriverContextP ctx,
512 struct encode_state *encode_state,
513 struct intel_encoder_context *encoder_context)
515 struct i965_driver_data *i965 = i965_driver_data(ctx);
516 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
519 int width_in_mbs = 0;
520 int height_in_mbs = 0;
522 if (encoder_context->codec == CODEC_H264) {
523 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
524 width_in_mbs = pSequenceParameter->picture_width_in_mbs;
525 height_in_mbs = pSequenceParameter->picture_height_in_mbs;
527 VAEncSequenceParameterBufferMPEG2 *pSequenceParameter = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
529 assert(encoder_context->codec == CODEC_MPEG2);
531 width_in_mbs = ALIGN(pSequenceParameter->picture_width, 16) / 16;
532 height_in_mbs = ALIGN(pSequenceParameter->picture_height, 16) / 16;
535 /*Encode common setup for MFC*/
536 dri_bo_unreference(mfc_context->post_deblocking_output.bo);
537 mfc_context->post_deblocking_output.bo = NULL;
539 dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
540 mfc_context->pre_deblocking_output.bo = NULL;
542 dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
543 mfc_context->uncompressed_picture_source.bo = NULL;
545 dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
546 mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
548 for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
549 if ( mfc_context->direct_mv_buffers[i].bo != NULL);
550 dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
551 mfc_context->direct_mv_buffers[i].bo = NULL;
554 for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
555 if (mfc_context->reference_surfaces[i].bo != NULL)
556 dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
557 mfc_context->reference_surfaces[i].bo = NULL;
560 dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
561 bo = dri_bo_alloc(i965->intel.bufmgr,
566 mfc_context->intra_row_store_scratch_buffer.bo = bo;
568 dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
569 bo = dri_bo_alloc(i965->intel.bufmgr,
571 width_in_mbs * height_in_mbs * 16,
574 mfc_context->macroblock_status_buffer.bo = bo;
576 dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
577 bo = dri_bo_alloc(i965->intel.bufmgr,
579 4 * width_in_mbs * 64, /* 4 * width_in_mbs * 64 */
582 mfc_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
584 dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
585 bo = dri_bo_alloc(i965->intel.bufmgr,
587 128 * width_in_mbs, /* 2 * widht_in_mbs * 64 */
590 mfc_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
592 dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo);
593 mfc_context->mfc_batchbuffer_surface.bo = NULL;
595 dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo);
596 mfc_context->aux_batchbuffer_surface.bo = NULL;
598 if (mfc_context->aux_batchbuffer)
599 intel_batchbuffer_free(mfc_context->aux_batchbuffer);
601 mfc_context->aux_batchbuffer = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD, 0);
602 mfc_context->aux_batchbuffer_surface.bo = mfc_context->aux_batchbuffer->buffer;
603 dri_bo_reference(mfc_context->aux_batchbuffer_surface.bo);
604 mfc_context->aux_batchbuffer_surface.pitch = 16;
605 mfc_context->aux_batchbuffer_surface.num_blocks = mfc_context->aux_batchbuffer->size / 16;
606 mfc_context->aux_batchbuffer_surface.size_block = 16;
608 i965_gpe_context_init(ctx, &mfc_context->gpe_context);
611 static void gen6_mfc_avc_pipeline_picture_programing( VADriverContextP ctx,
612 struct encode_state *encode_state,
613 struct intel_encoder_context *encoder_context)
615 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
617 mfc_context->pipe_mode_select(ctx, MFX_FORMAT_AVC, encoder_context);
618 mfc_context->set_surface_state(ctx, encoder_context);
619 mfc_context->ind_obj_base_addr_state(ctx, encoder_context);
620 gen6_mfc_pipe_buf_addr_state(ctx, encoder_context);
621 gen6_mfc_bsp_buf_base_addr_state(ctx, encoder_context);
622 mfc_context->avc_img_state(ctx, encode_state, encoder_context);
623 mfc_context->avc_qm_state(ctx, encoder_context);
624 mfc_context->avc_fqm_state(ctx, encoder_context);
625 gen6_mfc_avc_directmode_state(ctx, encoder_context);
626 intel_mfc_avc_ref_idx_state(ctx, encode_state, encoder_context);
631 gen6_mfc_run(VADriverContextP ctx,
632 struct encode_state *encode_state,
633 struct intel_encoder_context *encoder_context)
635 struct intel_batchbuffer *batch = encoder_context->base.batch;
637 intel_batchbuffer_flush(batch); //run the pipeline
639 return VA_STATUS_SUCCESS;
643 gen6_mfc_stop(VADriverContextP ctx,
644 struct encode_state *encode_state,
645 struct intel_encoder_context *encoder_context,
646 int *encoded_bits_size)
648 VAStatus vaStatus = VA_STATUS_ERROR_UNKNOWN;
649 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
650 VACodedBufferSegment *coded_buffer_segment;
652 vaStatus = i965_MapBuffer(ctx, pPicParameter->coded_buf, (void **)&coded_buffer_segment);
653 assert(vaStatus == VA_STATUS_SUCCESS);
654 *encoded_bits_size = coded_buffer_segment->size * 8;
655 i965_UnmapBuffer(ctx, pPicParameter->coded_buf);
657 return VA_STATUS_SUCCESS;
663 gen6_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb, int qp,unsigned int *msg,
664 struct intel_encoder_context *encoder_context,
665 unsigned char target_mb_size, unsigned char max_mb_size,
666 struct intel_batchbuffer *batch)
668 int len_in_dwords = 11;
671 batch = encoder_context->base.batch;
673 BEGIN_BCS_BATCH(batch, len_in_dwords);
675 OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
676 OUT_BCS_BATCH(batch, 0);
677 OUT_BCS_BATCH(batch, 0);
679 (0 << 24) | /* PackedMvNum, Debug*/
680 (0 << 20) | /* No motion vector */
681 (1 << 19) | /* CbpDcY */
682 (1 << 18) | /* CbpDcU */
683 (1 << 17) | /* CbpDcV */
686 OUT_BCS_BATCH(batch, (0xFFFF << 16) | (y << 8) | x); /* Code Block Pattern for Y*/
687 OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */
688 OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp); /* Last MB */
690 /*Stuff for Intra MB*/
691 OUT_BCS_BATCH(batch, msg[1]); /* We using Intra16x16 no 4x4 predmode*/
692 OUT_BCS_BATCH(batch, msg[2]);
693 OUT_BCS_BATCH(batch, msg[3]&0xFC);
695 /*MaxSizeInWord and TargetSzieInWord*/
696 OUT_BCS_BATCH(batch, (max_mb_size << 24) |
697 (target_mb_size << 16) );
699 ADVANCE_BCS_BATCH(batch);
701 return len_in_dwords;
705 gen6_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, int qp,
706 unsigned int *msg, unsigned int offset,
707 struct intel_encoder_context *encoder_context,
708 unsigned char target_mb_size,unsigned char max_mb_size, int slice_type,
709 struct intel_batchbuffer *batch)
711 int len_in_dwords = 11;
714 batch = encoder_context->base.batch;
716 BEGIN_BCS_BATCH(batch, len_in_dwords);
718 OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
720 OUT_BCS_BATCH(batch, msg[2]); /* 32 MV*/
721 OUT_BCS_BATCH(batch, offset);
723 OUT_BCS_BATCH(batch, msg[0]);
725 OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x); /* Code Block Pattern for Y*/
726 OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */
728 if ( slice_type == SLICE_TYPE_B) {
729 OUT_BCS_BATCH(batch, (0xF<<28) | (end_mb << 26) | qp); /* Last MB */
731 OUT_BCS_BATCH(batch, (end_mb << 26) | qp); /* Last MB */
734 OUT_BCS_BATCH(batch, (end_mb << 26) | qp); /* Last MB */
738 /*Stuff for Inter MB*/
739 OUT_BCS_BATCH(batch, msg[1]);
740 OUT_BCS_BATCH(batch, 0x0);
741 OUT_BCS_BATCH(batch, 0x0);
743 /*MaxSizeInWord and TargetSzieInWord*/
744 OUT_BCS_BATCH(batch, (max_mb_size << 24) |
745 (target_mb_size << 16) );
747 ADVANCE_BCS_BATCH(batch);
749 return len_in_dwords;
753 gen6_mfc_avc_pipeline_slice_programing(VADriverContextP ctx,
754 struct encode_state *encode_state,
755 struct intel_encoder_context *encoder_context,
757 struct intel_batchbuffer *slice_batch)
759 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
760 struct gen6_vme_context *vme_context = encoder_context->vme_context;
761 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
762 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
763 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
764 unsigned int *msg = NULL, offset = 0;
765 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
766 int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
767 int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs);
769 int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta;
770 unsigned int rate_control_mode = encoder_context->rate_control_mode;
771 unsigned char *slice_header = NULL;
772 int slice_header_length_in_bits = 0;
773 unsigned int tail_data[] = { 0x0, 0x0 };
774 int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type);
775 int is_intra = slice_type == SLICE_TYPE_I;
777 if (rate_control_mode == VA_RC_CBR) {
778 qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
779 pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp;
782 /* only support for 8-bit pixel bit-depth */
783 assert(pSequenceParameter->bit_depth_luma_minus8 == 0);
784 assert(pSequenceParameter->bit_depth_chroma_minus8 == 0);
785 assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52);
786 assert(qp >= 0 && qp < 52);
788 gen6_mfc_avc_slice_state(ctx,
791 encode_state, encoder_context,
792 (rate_control_mode == VA_RC_CBR), qp, slice_batch);
794 if ( slice_index == 0)
795 intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch);
797 slice_header_length_in_bits = build_avc_slice_header(pSequenceParameter, pPicParameter, pSliceParameter, &slice_header);
800 mfc_context->insert_object(ctx, encoder_context,
801 (unsigned int *)slice_header, ALIGN(slice_header_length_in_bits, 32) >> 5, slice_header_length_in_bits & 0x1f,
802 5, /* first 5 bytes are start code + nal unit type */
803 1, 0, 1, slice_batch);
805 dri_bo_map(vme_context->vme_output.bo , 1);
806 msg = (unsigned int *)vme_context->vme_output.bo->virtual;
809 msg += pSliceParameter->macroblock_address * INTRA_VME_OUTPUT_IN_DWS;
811 msg += pSliceParameter->macroblock_address * INTER_VME_OUTPUT_IN_DWS;
812 msg += 32; /* the first 32 DWs are MVs */
813 offset = pSliceParameter->macroblock_address * INTER_VME_OUTPUT_IN_BYTES;
816 for (i = pSliceParameter->macroblock_address;
817 i < pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks; i++) {
818 int last_mb = (i == (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks - 1) );
819 x = i % width_in_mbs;
820 y = i / width_in_mbs;
824 gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch);
825 msg += INTRA_VME_OUTPUT_IN_DWS;
827 if (msg[0] & INTRA_MB_FLAG_MASK) {
828 gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch);
830 gen6_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, msg, offset, encoder_context, 0, 0, slice_type, slice_batch);
833 msg += INTER_VME_OUTPUT_IN_DWS;
834 offset += INTER_VME_OUTPUT_IN_BYTES;
838 dri_bo_unmap(vme_context->vme_output.bo);
841 mfc_context->insert_object(ctx, encoder_context,
843 2, 1, 1, 0, slice_batch);
845 mfc_context->insert_object(ctx, encoder_context,
847 1, 1, 1, 0, slice_batch);
855 gen6_mfc_avc_software_batchbuffer(VADriverContextP ctx,
856 struct encode_state *encode_state,
857 struct intel_encoder_context *encoder_context)
859 struct i965_driver_data *i965 = i965_driver_data(ctx);
860 struct intel_batchbuffer *batch = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD, 0);
861 dri_bo *batch_bo = batch->buffer;
864 for (i = 0; i < encode_state->num_slice_params_ext; i++) {
865 gen6_mfc_avc_pipeline_slice_programing(ctx, encode_state, encoder_context, i, batch);
868 intel_batchbuffer_align(batch, 8);
870 BEGIN_BCS_BATCH(batch, 2);
871 OUT_BCS_BATCH(batch, 0);
872 OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_END);
873 ADVANCE_BCS_BATCH(batch);
875 dri_bo_reference(batch_bo);
876 intel_batchbuffer_free(batch);
884 gen6_mfc_batchbuffer_surfaces_input(VADriverContextP ctx,
885 struct encode_state *encode_state,
886 struct intel_encoder_context *encoder_context)
889 struct gen6_vme_context *vme_context = encoder_context->vme_context;
890 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
892 assert(vme_context->vme_output.bo);
893 mfc_context->buffer_suface_setup(ctx,
894 &mfc_context->gpe_context,
895 &vme_context->vme_output,
896 BINDING_TABLE_OFFSET(BIND_IDX_VME_OUTPUT),
897 SURFACE_STATE_OFFSET(BIND_IDX_VME_OUTPUT));
898 assert(mfc_context->aux_batchbuffer_surface.bo);
899 mfc_context->buffer_suface_setup(ctx,
900 &mfc_context->gpe_context,
901 &mfc_context->aux_batchbuffer_surface,
902 BINDING_TABLE_OFFSET(BIND_IDX_MFC_SLICE_HEADER),
903 SURFACE_STATE_OFFSET(BIND_IDX_MFC_SLICE_HEADER));
907 gen6_mfc_batchbuffer_surfaces_output(VADriverContextP ctx,
908 struct encode_state *encode_state,
909 struct intel_encoder_context *encoder_context)
912 struct i965_driver_data *i965 = i965_driver_data(ctx);
913 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
914 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
915 int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
916 int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
917 mfc_context->mfc_batchbuffer_surface.num_blocks = width_in_mbs * height_in_mbs + encode_state->num_slice_params_ext * 8 + 1;
918 mfc_context->mfc_batchbuffer_surface.size_block = 16 * CMD_LEN_IN_OWORD; /* 3 OWORDs */
919 mfc_context->mfc_batchbuffer_surface.pitch = 16;
920 mfc_context->mfc_batchbuffer_surface.bo = dri_bo_alloc(i965->intel.bufmgr,
922 mfc_context->mfc_batchbuffer_surface.num_blocks * mfc_context->mfc_batchbuffer_surface.size_block,
924 mfc_context->buffer_suface_setup(ctx,
925 &mfc_context->gpe_context,
926 &mfc_context->mfc_batchbuffer_surface,
927 BINDING_TABLE_OFFSET(BIND_IDX_MFC_BATCHBUFFER),
928 SURFACE_STATE_OFFSET(BIND_IDX_MFC_BATCHBUFFER));
932 gen6_mfc_batchbuffer_surfaces_setup(VADriverContextP ctx,
933 struct encode_state *encode_state,
934 struct intel_encoder_context *encoder_context)
936 gen6_mfc_batchbuffer_surfaces_input(ctx, encode_state, encoder_context);
937 gen6_mfc_batchbuffer_surfaces_output(ctx, encode_state, encoder_context);
941 gen6_mfc_batchbuffer_idrt_setup(VADriverContextP ctx,
942 struct encode_state *encode_state,
943 struct intel_encoder_context *encoder_context)
945 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
946 struct gen6_interface_descriptor_data *desc;
950 bo = mfc_context->gpe_context.idrt.bo;
955 for (i = 0; i < mfc_context->gpe_context.num_kernels; i++) {
956 struct i965_kernel *kernel;
958 kernel = &mfc_context->gpe_context.kernels[i];
959 assert(sizeof(*desc) == 32);
961 /*Setup the descritor table*/
962 memset(desc, 0, sizeof(*desc));
963 desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6);
964 desc->desc2.sampler_count = 0;
965 desc->desc2.sampler_state_pointer = 0;
966 desc->desc3.binding_table_entry_count = 2;
967 desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5);
968 desc->desc4.constant_urb_entry_read_offset = 0;
969 desc->desc4.constant_urb_entry_read_length = 4;
972 dri_bo_emit_reloc(bo,
973 I915_GEM_DOMAIN_INSTRUCTION, 0,
975 i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0),
984 gen6_mfc_batchbuffer_constant_setup(VADriverContextP ctx,
985 struct encode_state *encode_state,
986 struct intel_encoder_context *encoder_context)
988 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
994 gen6_mfc_batchbuffer_emit_object_command(struct intel_batchbuffer *batch,
997 int batchbuffer_offset,
1009 BEGIN_BATCH(batch, 12);
1011 OUT_BATCH(batch, CMD_MEDIA_OBJECT | (12 - 2));
1012 OUT_BATCH(batch, index);
1013 OUT_BATCH(batch, 0);
1014 OUT_BATCH(batch, 0);
1015 OUT_BATCH(batch, 0);
1016 OUT_BATCH(batch, 0);
1019 OUT_BATCH(batch, head_offset);
1020 OUT_BATCH(batch, batchbuffer_offset);
1025 number_mb_cmds << 16 |
1036 ADVANCE_BATCH(batch);
1040 gen6_mfc_avc_batchbuffer_slice_command(VADriverContextP ctx,
1041 struct intel_encoder_context *encoder_context,
1042 VAEncSliceParameterBufferH264 *slice_param,
1044 unsigned short head_size,
1045 unsigned short tail_size,
1046 int batchbuffer_offset,
1050 struct intel_batchbuffer *batch = encoder_context->base.batch;
1051 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1052 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
1053 int total_mbs = slice_param->num_macroblocks;
1054 int number_mb_cmds = 128;
1055 int starting_mb = 0;
1056 int last_object = 0;
1057 int first_object = 1;
1060 int index = (slice_param->slice_type == SLICE_TYPE_I) ? MFC_BATCHBUFFER_AVC_INTRA : MFC_BATCHBUFFER_AVC_INTER;
1062 for (i = 0; i < total_mbs / number_mb_cmds; i++) {
1063 last_object = (total_mbs - starting_mb) == number_mb_cmds;
1064 mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs;
1065 mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs;
1066 assert(mb_x <= 255 && mb_y <= 255);
1068 starting_mb += number_mb_cmds;
1070 gen6_mfc_batchbuffer_emit_object_command(batch,
1086 head_offset += head_size;
1087 batchbuffer_offset += head_size;
1091 head_offset += tail_size;
1092 batchbuffer_offset += tail_size;
1095 batchbuffer_offset += number_mb_cmds * CMD_LEN_IN_OWORD;
1102 number_mb_cmds = total_mbs % number_mb_cmds;
1103 mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs;
1104 mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs;
1105 assert(mb_x <= 255 && mb_y <= 255);
1106 starting_mb += number_mb_cmds;
1108 gen6_mfc_batchbuffer_emit_object_command(batch,
1126 * return size in Owords (16bytes)
1129 gen6_mfc_avc_batchbuffer_slice(VADriverContextP ctx,
1130 struct encode_state *encode_state,
1131 struct intel_encoder_context *encoder_context,
1133 int batchbuffer_offset)
1135 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1136 struct intel_batchbuffer *slice_batch = mfc_context->aux_batchbuffer;
1137 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
1138 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
1139 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
1140 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
1141 int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
1142 int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs);
1143 int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta;
1144 unsigned int rate_control_mode = encoder_context->rate_control_mode;
1145 unsigned char *slice_header = NULL;
1146 int slice_header_length_in_bits = 0;
1147 unsigned int tail_data[] = { 0x0, 0x0 };
1149 int old_used = intel_batchbuffer_used_size(slice_batch), used;
1150 unsigned short head_size, tail_size;
1151 int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type);
1153 if (rate_control_mode == VA_RC_CBR) {
1154 qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
1155 pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp;
1158 /* only support for 8-bit pixel bit-depth */
1159 assert(pSequenceParameter->bit_depth_luma_minus8 == 0);
1160 assert(pSequenceParameter->bit_depth_chroma_minus8 == 0);
1161 assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52);
1162 assert(qp >= 0 && qp < 52);
1164 head_offset = old_used / 16;
1165 gen6_mfc_avc_slice_state(ctx,
1170 (rate_control_mode == VA_RC_CBR),
1174 if (slice_index == 0)
1175 intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch);
1177 slice_header_length_in_bits = build_avc_slice_header(pSequenceParameter, pPicParameter, pSliceParameter, &slice_header);
1180 mfc_context->insert_object(ctx,
1182 (unsigned int *)slice_header,
1183 ALIGN(slice_header_length_in_bits, 32) >> 5,
1184 slice_header_length_in_bits & 0x1f,
1185 5, /* first 5 bytes are start code + nal unit type */
1192 intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */
1193 used = intel_batchbuffer_used_size(slice_batch);
1194 head_size = (used - old_used) / 16;
1199 mfc_context->insert_object(ctx,
1210 mfc_context->insert_object(ctx,
1222 intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */
1223 used = intel_batchbuffer_used_size(slice_batch);
1224 tail_size = (used - old_used) / 16;
1227 gen6_mfc_avc_batchbuffer_slice_command(ctx,
1237 return head_size + tail_size + pSliceParameter->num_macroblocks * CMD_LEN_IN_OWORD;
1241 gen6_mfc_avc_batchbuffer_pipeline(VADriverContextP ctx,
1242 struct encode_state *encode_state,
1243 struct intel_encoder_context *encoder_context)
1245 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1246 struct intel_batchbuffer *batch = encoder_context->base.batch;
1247 int i, size, offset = 0;
1248 intel_batchbuffer_start_atomic(batch, 0x4000);
1249 gen6_gpe_pipeline_setup(ctx, &mfc_context->gpe_context, batch);
1251 for ( i = 0; i < encode_state->num_slice_params_ext; i++) {
1252 size = gen6_mfc_avc_batchbuffer_slice(ctx, encode_state, encoder_context, i, offset);
1256 intel_batchbuffer_end_atomic(batch);
1257 intel_batchbuffer_flush(batch);
1261 gen6_mfc_build_avc_batchbuffer(VADriverContextP ctx,
1262 struct encode_state *encode_state,
1263 struct intel_encoder_context *encoder_context)
1265 gen6_mfc_batchbuffer_surfaces_setup(ctx, encode_state, encoder_context);
1266 gen6_mfc_batchbuffer_idrt_setup(ctx, encode_state, encoder_context);
1267 gen6_mfc_batchbuffer_constant_setup(ctx, encode_state, encoder_context);
1268 gen6_mfc_avc_batchbuffer_pipeline(ctx, encode_state, encoder_context);
1272 gen6_mfc_avc_hardware_batchbuffer(VADriverContextP ctx,
1273 struct encode_state *encode_state,
1274 struct intel_encoder_context *encoder_context)
1276 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1278 gen6_mfc_build_avc_batchbuffer(ctx, encode_state, encoder_context);
1279 dri_bo_reference(mfc_context->mfc_batchbuffer_surface.bo);
1281 return mfc_context->mfc_batchbuffer_surface.bo;
1288 gen6_mfc_avc_pipeline_programing(VADriverContextP ctx,
1289 struct encode_state *encode_state,
1290 struct intel_encoder_context *encoder_context)
1292 struct intel_batchbuffer *batch = encoder_context->base.batch;
1293 dri_bo *slice_batch_bo;
1295 if ( intel_mfc_interlace_check(ctx, encode_state, encoder_context) ) {
1296 fprintf(stderr, "Current VA driver don't support interlace mode!\n");
1302 slice_batch_bo = gen6_mfc_avc_software_batchbuffer(ctx, encode_state, encoder_context);
1304 slice_batch_bo = gen6_mfc_avc_hardware_batchbuffer(ctx, encode_state, encoder_context);
1308 intel_batchbuffer_start_atomic_bcs(batch, 0x4000);
1309 intel_batchbuffer_emit_mi_flush(batch);
1311 // picture level programing
1312 gen6_mfc_avc_pipeline_picture_programing(ctx, encode_state, encoder_context);
1314 BEGIN_BCS_BATCH(batch, 2);
1315 OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8));
1316 OUT_BCS_RELOC(batch,
1318 I915_GEM_DOMAIN_COMMAND, 0,
1320 ADVANCE_BCS_BATCH(batch);
1323 intel_batchbuffer_end_atomic(batch);
1325 dri_bo_unreference(slice_batch_bo);
1329 gen6_mfc_avc_encode_picture(VADriverContextP ctx,
1330 struct encode_state *encode_state,
1331 struct intel_encoder_context *encoder_context)
1333 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1334 unsigned int rate_control_mode = encoder_context->rate_control_mode;
1335 int current_frame_bits_size;
1339 gen6_mfc_init(ctx, encode_state, encoder_context);
1340 intel_mfc_avc_prepare(ctx, encode_state, encoder_context);
1341 /*Programing bcs pipeline*/
1342 gen6_mfc_avc_pipeline_programing(ctx, encode_state, encoder_context); //filling the pipeline
1343 gen6_mfc_run(ctx, encode_state, encoder_context);
1344 if (rate_control_mode == VA_RC_CBR /*|| rate_control_mode == VA_RC_VBR*/) {
1345 gen6_mfc_stop(ctx, encode_state, encoder_context, ¤t_frame_bits_size);
1346 sts = intel_mfc_brc_postpack(encode_state, mfc_context, current_frame_bits_size);
1347 if (sts == BRC_NO_HRD_VIOLATION) {
1348 intel_mfc_hrd_context_update(encode_state, mfc_context);
1351 else if (sts == BRC_OVERFLOW_WITH_MIN_QP || sts == BRC_UNDERFLOW_WITH_MAX_QP) {
1352 if (!mfc_context->hrd.violation_noted) {
1353 fprintf(stderr, "Unrepairable %s!\n", (sts == BRC_OVERFLOW_WITH_MIN_QP)? "overflow": "underflow");
1354 mfc_context->hrd.violation_noted = 1;
1356 return VA_STATUS_SUCCESS;
1363 return VA_STATUS_SUCCESS;
1367 gen6_mfc_pipeline(VADriverContextP ctx,
1369 struct encode_state *encode_state,
1370 struct intel_encoder_context *encoder_context)
1375 case VAProfileH264Baseline:
1376 case VAProfileH264Main:
1377 case VAProfileH264High:
1378 vaStatus = gen6_mfc_avc_encode_picture(ctx, encode_state, encoder_context);
1381 /* FIXME: add for other profile */
1383 vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
1391 gen6_mfc_context_destroy(void *context)
1393 struct gen6_mfc_context *mfc_context = context;
1396 dri_bo_unreference(mfc_context->post_deblocking_output.bo);
1397 mfc_context->post_deblocking_output.bo = NULL;
1399 dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
1400 mfc_context->pre_deblocking_output.bo = NULL;
1402 dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
1403 mfc_context->uncompressed_picture_source.bo = NULL;
1405 dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
1406 mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
1408 for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
1409 dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
1410 mfc_context->direct_mv_buffers[i].bo = NULL;
1413 dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
1414 mfc_context->intra_row_store_scratch_buffer.bo = NULL;
1416 dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
1417 mfc_context->macroblock_status_buffer.bo = NULL;
1419 dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
1420 mfc_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
1422 dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
1423 mfc_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
1426 for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
1427 dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
1428 mfc_context->reference_surfaces[i].bo = NULL;
1431 i965_gpe_context_destroy(&mfc_context->gpe_context);
1433 dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo);
1434 mfc_context->mfc_batchbuffer_surface.bo = NULL;
1436 dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo);
1437 mfc_context->aux_batchbuffer_surface.bo = NULL;
1439 if (mfc_context->aux_batchbuffer)
1440 intel_batchbuffer_free(mfc_context->aux_batchbuffer);
1442 mfc_context->aux_batchbuffer = NULL;
1447 Bool gen6_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
1449 struct gen6_mfc_context *mfc_context = calloc(1, sizeof(struct gen6_mfc_context));
1451 mfc_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6;
1453 mfc_context->gpe_context.idrt.max_entries = MAX_GPE_KERNELS;
1454 mfc_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data);
1456 mfc_context->gpe_context.curbe.length = 32 * 4;
1458 mfc_context->gpe_context.vfe_state.max_num_threads = 60 - 1;
1459 mfc_context->gpe_context.vfe_state.num_urb_entries = 16;
1460 mfc_context->gpe_context.vfe_state.gpgpu_mode = 0;
1461 mfc_context->gpe_context.vfe_state.urb_entry_size = 59 - 1;
1462 mfc_context->gpe_context.vfe_state.curbe_allocation_size = 37 - 1;
1464 i965_gpe_load_kernels(ctx,
1465 &mfc_context->gpe_context,
1469 mfc_context->pipe_mode_select = gen6_mfc_pipe_mode_select;
1470 mfc_context->set_surface_state = gen6_mfc_surface_state;
1471 mfc_context->ind_obj_base_addr_state = gen6_mfc_ind_obj_base_addr_state;
1472 mfc_context->avc_img_state = gen6_mfc_avc_img_state;
1473 mfc_context->avc_qm_state = gen6_mfc_avc_qm_state;
1474 mfc_context->avc_fqm_state = gen6_mfc_avc_fqm_state;
1475 mfc_context->insert_object = gen6_mfc_avc_insert_object;
1476 mfc_context->buffer_suface_setup = i965_gpe_buffer_suface_setup;
1478 encoder_context->mfc_context = mfc_context;
1479 encoder_context->mfc_context_destroy = gen6_mfc_context_destroy;
1480 encoder_context->mfc_pipeline = gen6_mfc_pipeline;
1481 encoder_context->mfc_brc_prepare = intel_mfc_brc_prepare;