src/gen6_mfc.c

   1 /*
   2  * Copyright © 2010-2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Zhou Chang <chang.zhou@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <assert.h>
  33
  34 #include "intel_batchbuffer.h"
  35 #include "i965_defines.h"
  36 #include "i965_structs.h"
  37 #include "i965_drv_video.h"
  38 #include "i965_encoder.h"
  39 #include "i965_encoder_utils.h"
  40 #include "gen6_mfc.h"
  41 #include "gen6_vme.h"
  42
  43 static void
  44 gen6_mfc_pipe_mode_select(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
  45 {
  46     struct intel_batchbuffer *batch = encoder_context->base.batch;
  47
  48     BEGIN_BCS_BATCH(batch, 4);
  49
  50     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (4 - 2));
  51     OUT_BCS_BATCH(batch,
  52                   (1 << 10) | /* disable Stream-Out , advanced QP/bitrate control need enable it*/
  53                   (1 << 9)  | /* Post Deblocking Output */
  54                   (0 << 8)  | /* Pre Deblocking Output */
  55                   (0 << 7)  | /* disable TLB prefectch */
  56                   (0 << 5)  | /* not in stitch mode */
  57                   (1 << 4)  | /* encoding mode */
  58                   (2 << 0));  /* Standard Select: AVC */
  59     OUT_BCS_BATCH(batch,
  60                   (0 << 20) | /* round flag in PB slice */
  61                   (0 << 19) | /* round flag in Intra8x8 */
  62                   (0 << 7)  | /* expand NOA bus flag */
  63                   (1 << 6)  | /* must be 1 */
  64                   (0 << 5)  | /* disable clock gating for NOA */
  65                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
  66                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
  67                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
  68                   (0 << 1)  | /* AVC long field motion vector */
  69                   (0 << 0));  /* always calculate AVC ILDB boundary strength */
  70     OUT_BCS_BATCH(batch, 0);
  71
  72     ADVANCE_BCS_BATCH(batch);
  73 }
  74
  75 static void
  76 gen6_mfc_surface_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
  77 {
  78     struct intel_batchbuffer *batch = encoder_context->base.batch;
  79     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
  80
  81     BEGIN_BCS_BATCH(batch, 6);
  82
  83     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
  84     OUT_BCS_BATCH(batch, 0);
  85     OUT_BCS_BATCH(batch,
  86                   ((mfc_context->surface_state.height - 1) << 19) |
  87                   ((mfc_context->surface_state.width - 1) << 6));
  88     OUT_BCS_BATCH(batch,
  89                   (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
  90                   (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
  91                   (0 << 22) | /* surface object control state, FIXME??? */
  92                   ((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */
  93                   (0 << 2)  | /* must be 0 for interleave U/V */
  94                   (1 << 1)  | /* must be y-tiled */
  95                   (I965_TILEWALK_YMAJOR << 0));                         /* tile walk, TILEWALK_YMAJOR */
  96     OUT_BCS_BATCH(batch,
  97                   (0 << 16) |                                                           /* must be 0 for interleave U/V */
  98                   (mfc_context->surface_state.h_pitch));                /* y offset for U(cb) */
  99     OUT_BCS_BATCH(batch, 0);
 100     ADVANCE_BCS_BATCH(batch);
 101 }
 102
 103 static void
 104 gen6_mfc_pipe_buf_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 105 {
 106     struct intel_batchbuffer *batch = encoder_context->base.batch;
 107     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 108     int i;
 109
 110     BEGIN_BCS_BATCH(batch, 24);
 111
 112     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
 113
 114     OUT_BCS_BATCH(batch, 0);                                                                                    /* pre output addr   */
 115
 116     OUT_BCS_RELOC(batch, mfc_context->post_deblocking_output.bo,
 117                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 118                   0);                                                                                   /* post output addr  */
 119
 120     OUT_BCS_RELOC(batch, mfc_context->uncompressed_picture_source.bo,
 121                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 122                   0);                                                                                   /* uncompressed data */
 123     OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
 124                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 125                   0);                                                                                   /* StreamOut data*/
 126     OUT_BCS_RELOC(batch, mfc_context->intra_row_store_scratch_buffer.bo,
 127                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 128                   0);
 129     OUT_BCS_RELOC(batch, mfc_context->deblocking_filter_row_store_scratch_buffer.bo,
 130                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 131                   0);
 132     /* 7..22 Reference pictures*/
 133     for (i = 0; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) {
 134         if ( mfc_context->reference_surfaces[i].bo != NULL) {
 135             OUT_BCS_RELOC(batch, mfc_context->reference_surfaces[i].bo,
 136                           I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 137                           0);
 138         } else {
 139             OUT_BCS_BATCH(batch, 0);
 140         }
 141     }
 142     OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
 143                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 144                   0);                                                                                   /* Macroblock status buffer*/
 145
 146     ADVANCE_BCS_BATCH(batch);
 147 }
 148
 149 static void
 150 gen6_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 151 {
 152     struct intel_batchbuffer *batch = encoder_context->base.batch;
 153     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 154     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 155
 156     BEGIN_BCS_BATCH(batch, 11);
 157
 158     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
 159     OUT_BCS_BATCH(batch, 0);
 160     OUT_BCS_BATCH(batch, 0);
 161     /* MFX Indirect MV Object Base Address */
 162     OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 163     OUT_BCS_BATCH(batch, 0);
 164     OUT_BCS_BATCH(batch, 0);
 165     OUT_BCS_BATCH(batch, 0);
 166     OUT_BCS_BATCH(batch, 0);
 167     OUT_BCS_BATCH(batch, 0);
 168     /*MFC Indirect PAK-BSE Object Base Address for Encoder*/
 169     OUT_BCS_RELOC(batch,
 170                   mfc_context->mfc_indirect_pak_bse_object.bo,
 171                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 172                   0);
 173     OUT_BCS_RELOC(batch,
 174                   mfc_context->mfc_indirect_pak_bse_object.bo,
 175                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 176                   mfc_context->mfc_indirect_pak_bse_object.end_offset);
 177
 178     ADVANCE_BCS_BATCH(batch);
 179 }
 180
 181 static void
 182 gen6_mfc_bsp_buf_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 183 {
 184     struct intel_batchbuffer *batch = encoder_context->base.batch;
 185     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 186
 187     BEGIN_BCS_BATCH(batch, 4);
 188
 189     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
 190     OUT_BCS_RELOC(batch, mfc_context->bsd_mpc_row_store_scratch_buffer.bo,
 191                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 192                   0);
 193     OUT_BCS_BATCH(batch, 0);
 194     OUT_BCS_BATCH(batch, 0);
 195
 196     ADVANCE_BCS_BATCH(batch);
 197 }
 198
 199 static void
 200 gen6_mfc_avc_img_state(VADriverContextP ctx,struct encode_state *encode_state,
 201                        struct intel_encoder_context *encoder_context)
 202 {
 203     struct intel_batchbuffer *batch = encoder_context->base.batch;
 204     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 205     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 206     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 207     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 208     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 209
 210     BEGIN_BCS_BATCH(batch, 13);
 211     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (13 - 2));
 212     OUT_BCS_BATCH(batch,
 213                   ((width_in_mbs * height_in_mbs) & 0xFFFF));
 214     OUT_BCS_BATCH(batch,
 215                   (height_in_mbs << 16) |
 216                   (width_in_mbs << 0));
 217     OUT_BCS_BATCH(batch,
 218                   (0 << 24) |     /*Second Chroma QP Offset*/
 219                   (0 << 16) |     /*Chroma QP Offset*/
 220                   (0 << 14) |   /*Max-bit conformance Intra flag*/
 221                   (0 << 13) |   /*Max Macroblock size conformance Inter flag*/
 222                   (1 << 12) |   /*Should always be written as "1" */
 223                   (0 << 10) |   /*QM Preset FLag */
 224                   (0 << 8)  |   /*Image Structure*/
 225                   (0 << 0) );   /*Current Decoed Image Frame Store ID, reserved in Encode mode*/
 226     OUT_BCS_BATCH(batch,
 227                   (400 << 16) |   /*Mininum Frame size*/
 228                   (0 << 15) |   /*Disable reading of Macroblock Status Buffer*/
 229                   (0 << 14) |   /*Load BitStream Pointer only once, 1 slic 1 frame*/
 230                   (0 << 13) |   /*CABAC 0 word insertion test enable*/
 231                   (1 << 12) |   /*MVUnpackedEnable,compliant to DXVA*/
 232                   (1 << 10) |   /*Chroma Format IDC, 4:2:0*/
 233                   (pPicParameter->pic_fields.bits.entropy_coding_mode_flag << 7)  |   /*0:CAVLC encoding mode,1:CABAC*/
 234                   (0 << 6)  |   /*Only valid for VLD decoding mode*/
 235                   (0 << 5)  |   /*Constrained Intra Predition Flag, from PPS*/
 236                   (pSequenceParameter->direct_8x8_inference_flag << 4)  |   /*Direct 8x8 inference flag*/
 237                   (pPicParameter->pic_fields.bits.transform_8x8_mode_flag << 3)  |   /*8x8 or 4x4 IDCT Transform Mode Flag*/
 238                   (1 << 2)  |   /*Frame MB only flag*/
 239                   (0 << 1)  |   /*MBAFF mode is in active*/
 240                   (0 << 0) );   /*Field picture flag*/
 241     OUT_BCS_BATCH(batch,
 242                   (1<<16)   |   /*Frame Size Rate Control Flag*/
 243                   (1<<12)   |
 244                   (1<<9)    |   /*MB level Rate Control Enabling Flag*/
 245                   (1 << 3)  |   /*FrameBitRateMinReportMask*/
 246                   (1 << 2)  |   /*FrameBitRateMaxReportMask*/
 247                   (1 << 1)  |   /*InterMBMaxSizeReportMask*/
 248                   (1 << 0) );   /*IntraMBMaxSizeReportMask*/
 249     OUT_BCS_BATCH(batch,                        /*Inter and Intra Conformance Max size limit*/
 250                   (0x0600 << 16) |              /*InterMbMaxSz 192 Byte*/
 251                   (0x0800) );                   /*IntraMbMaxSz 256 Byte*/
 252     OUT_BCS_BATCH(batch, 0x00000000);   /*Reserved : MBZReserved*/
 253     OUT_BCS_BATCH(batch, 0x01020304);   /*Slice QP Delta for bitrate control*/
 254     OUT_BCS_BATCH(batch, 0xFEFDFCFB);
 255     OUT_BCS_BATCH(batch, 0x80601004);   /*MAX = 128KB, MIN = 64KB*/
 256     OUT_BCS_BATCH(batch, 0x00800001);
 257     OUT_BCS_BATCH(batch, 0);
 258
 259     ADVANCE_BCS_BATCH(batch);
 260 }
 261
 262 static void gen6_mfc_avc_directmode_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 263 {
 264     struct intel_batchbuffer *batch = encoder_context->base.batch;
 265     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 266
 267     int i;
 268
 269     BEGIN_BCS_BATCH(batch, 69);
 270
 271     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
 272
 273     /* Reference frames and Current frames */
 274     for(i = 0; i < NUM_MFC_DMV_BUFFERS; i++) {
 275         if ( mfc_context->direct_mv_buffers[i].bo != NULL) {
 276             OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[i].bo,
 277                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 278                           0);
 279         } else {
 280             OUT_BCS_BATCH(batch, 0);
 281         }
 282     }
 283
 284     /* POL list */
 285     for(i = 0; i < 32; i++) {
 286         OUT_BCS_BATCH(batch, i/2);
 287     }
 288     OUT_BCS_BATCH(batch, 0);
 289     OUT_BCS_BATCH(batch, 0);
 290
 291     ADVANCE_BCS_BATCH(batch);
 292 }
 293
 294 static void gen6_mfc_avc_slice_state(VADriverContextP ctx,
 295                                      int slice_type,
 296                                      struct encode_state *encode_state,
 297                                      struct intel_encoder_context *encoder_context,
 298                                      int rate_control_enable,
 299                                      int qp,
 300                                      int slice_index)
 301 {
 302     struct intel_batchbuffer *batch = encoder_context->base.batch;
 303     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 304     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer; /* TODO: multi slices support */
 305     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 306     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 307     int beginmb = pSliceParameter->starting_macroblock_address;
 308     int endmb = beginmb + pSliceParameter->number_of_mbs;
 309     int beginx = beginmb % width_in_mbs;
 310     int beginy = beginmb / width_in_mbs;
 311     int nextx =  endmb % width_in_mbs;
 312     int nexty = endmb / width_in_mbs;
 313     int last_slice = (pSliceParameter->starting_macroblock_address + pSliceParameter->number_of_mbs) == (width_in_mbs * height_in_mbs);
 314     int bit_rate_control_target;
 315     if ( slice_type == SLICE_TYPE_I )
 316         bit_rate_control_target = 0;
 317     else
 318         bit_rate_control_target = 1;
 319     int maxQpN = mfc_context->bit_rate_control_context[bit_rate_control_target].MaxQpNegModifier;
 320     int maxQpP = mfc_context->bit_rate_control_context[bit_rate_control_target].MaxQpPosModifier;
 321     unsigned char correct[6];
 322     int i;
 323
 324     for (i = 0; i < 6; i++)
 325         correct[i] = mfc_context->bit_rate_control_context[bit_rate_control_target].Correct[i];
 326     unsigned char grow = mfc_context->bit_rate_control_context[bit_rate_control_target].GrowInit +
 327         (mfc_context->bit_rate_control_context[bit_rate_control_target].GrowResistance << 4);
 328     unsigned char shrink = mfc_context->bit_rate_control_context[bit_rate_control_target].ShrinkInit +
 329         (mfc_context->bit_rate_control_context[bit_rate_control_target].ShrinkResistance << 4);
 330
 331     BEGIN_BCS_BATCH(batch, 11);;
 332
 333     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) );
 334
 335     OUT_BCS_BATCH(batch, slice_type);                   /*Slice Type: I:P:B Slice*/
 336
 337     if ( slice_type == SLICE_TYPE_I ) {
 338         OUT_BCS_BATCH(batch, 0);                        /*no reference frames and pred_weight_table*/
 339     } else {
 340         OUT_BCS_BATCH(batch, 0x00010000);       /*1 reference frame*/
 341     }
 342
 343     OUT_BCS_BATCH(batch,
 344                   (pSliceParameter->direct_spatial_mv_pred_flag<<29) |             /*Direct Prediction Type*/
 345                   (0<<24) |                /*Enable deblocking operation*/
 346                   (qp<<16) |                    /*Slice Quantization Parameter*/
 347                   0x0202 );
 348     OUT_BCS_BATCH(batch, (beginy << 24) |                       /*First MB X&Y , the begin postion of current slice*/
 349                          (beginx << 16) |
 350                          pSliceParameter->starting_macroblock_address );
 351     OUT_BCS_BATCH(batch, (nexty << 16) | nextx);                       /*Next slice first MB X&Y*/
 352     OUT_BCS_BATCH(batch,
 353                   (rate_control_enable<<31) |           /*in CBR mode RateControlCounterEnable = enable*/
 354                   (1<<30) |             /*ResetRateControlCounter*/
 355                   (0<<28) |             /*RC Triggle Mode = Always Rate Control*/
 356                   (4<<24) |     /*RC Stable Tolerance, middle level*/
 357                   (rate_control_enable<<23) |     /*RC Panic Enable*/
 358                   (0<<22) |     /*QP mode, don't modfiy CBP*/
 359                   (0<<21) |     /*MB Type Direct Conversion Enabled*/
 360                   (0<<20) |     /*MB Type Skip Conversion Enabled*/
 361                   (last_slice << 19) |     /*IsLastSlice*/
 362                   (0<<18) |     /*BitstreamOutputFlag Compressed BitStream Output Disable Flag 0:enable 1:disable*/
 363                   (1<<17) |         /*HeaderPresentFlag*/
 364                   (1<<16) |         /*SliceData PresentFlag*/
 365                   (1<<15) |         /*TailPresentFlag*/
 366                   (1<<13) |         /*RBSP NAL TYPE*/
 367                   (0<<12) );    /*CabacZeroWordInsertionEnable*/
 368
 369     OUT_BCS_BATCH(batch, mfc_context->mfc_indirect_pak_bse_object.offset);
 370
 371     OUT_BCS_BATCH(batch, (maxQpN<<24) |     /*Target QP - 24 is lowest QP*/
 372                   (maxQpP<<16) |     /*Target QP + 20 is highest QP*/
 373                   (shrink<<8)  |
 374                   (grow<<0));
 375     OUT_BCS_BATCH(batch, (correct[5] << 20) |
 376                   (correct[4] << 16) |
 377                   (correct[3] << 12) |
 378                   (correct[2] << 8) |
 379                   (correct[1] << 4) |
 380                   (correct[0] << 0));
 381     OUT_BCS_BATCH(batch, 0);
 382
 383     ADVANCE_BCS_BATCH(batch);
 384 }
 385 static void gen6_mfc_avc_qm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 386 {
 387     struct intel_batchbuffer *batch = encoder_context->base.batch;
 388     int i;
 389
 390     BEGIN_BCS_BATCH(batch, 58);
 391
 392     OUT_BCS_BATCH(batch, MFX_AVC_QM_STATE | 56);
 393     OUT_BCS_BATCH(batch, 0xFF ) ;
 394     for( i = 0; i < 56; i++) {
 395         OUT_BCS_BATCH(batch, 0x10101010);
 396     }
 397
 398     ADVANCE_BCS_BATCH(batch);
 399 }
 400
 401 static void gen6_mfc_avc_fqm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 402 {
 403     struct intel_batchbuffer *batch = encoder_context->base.batch;
 404     int i;
 405
 406     BEGIN_BCS_BATCH(batch, 113);
 407     OUT_BCS_BATCH(batch, MFC_AVC_FQM_STATE | (113 - 2));
 408
 409     for(i = 0; i < 112;i++) {
 410         OUT_BCS_BATCH(batch, 0x10001000);
 411     }
 412
 413     ADVANCE_BCS_BATCH(batch);
 414 }
 415
 416 static void gen6_mfc_avc_ref_idx_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 417 {
 418     struct intel_batchbuffer *batch = encoder_context->base.batch;
 419     int i;
 420
 421     BEGIN_BCS_BATCH(batch, 10);
 422     OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
 423     OUT_BCS_BATCH(batch, 0);                  //Select L0
 424     OUT_BCS_BATCH(batch, 0x80808020);         //Only 1 reference
 425     for(i = 0; i < 7; i++) {
 426         OUT_BCS_BATCH(batch, 0x80808080);
 427     }
 428     ADVANCE_BCS_BATCH(batch);
 429
 430     BEGIN_BCS_BATCH(batch, 10);
 431     OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
 432     OUT_BCS_BATCH(batch, 1);                  //Select L1
 433     OUT_BCS_BATCH(batch, 0x80808022);         //Only 1 reference
 434     for(i = 0; i < 7; i++) {
 435         OUT_BCS_BATCH(batch, 0x80808080);
 436     }
 437     ADVANCE_BCS_BATCH(batch);
 438 }
 439
 440 static void
 441 gen6_mfc_avc_insert_object(VADriverContextP ctx, struct intel_encoder_context *encoder_context,
 442                            unsigned int *insert_data, int lenght_in_dws, int data_bits_in_last_dw,
 443                            int skip_emul_byte_count, int is_last_header, int is_end_of_slice, int emulation_flag)
 444 {
 445     struct i965_driver_data *i965 = i965_driver_data(ctx);
 446     struct intel_batchbuffer *batch = encoder_context->base.batch;
 447
 448     BEGIN_BCS_BATCH(batch, lenght_in_dws + 2);
 449
 450     if (IS_GEN7(i965->intel.device_id))
 451         OUT_BCS_BATCH(batch, MFX_INSERT_OBJECT | (lenght_in_dws + 2 - 2));
 452     else
 453         OUT_BCS_BATCH(batch, MFC_AVC_INSERT_OBJECT | (lenght_in_dws + 2 - 2));
 454
 455     OUT_BCS_BATCH(batch,
 456                   (0 << 16) |   /* always start at offset 0 */
 457                   (data_bits_in_last_dw << 8) |
 458                   (skip_emul_byte_count << 4) |
 459                   (!!emulation_flag << 3) |
 460                   ((!!is_last_header) << 2) |
 461                   ((!!is_end_of_slice) << 1) |
 462                   (0 << 0));    /* FIXME: ??? */
 463
 464     intel_batchbuffer_data(batch, insert_data, lenght_in_dws * 4);
 465     ADVANCE_BCS_BATCH(batch);
 466 }
 467
 468 static int
 469 gen6_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb, int qp,unsigned int *msg,
 470                               struct intel_encoder_context *encoder_context,
 471                               unsigned char target_mb_size, unsigned char max_mb_size)
 472 {
 473     struct intel_batchbuffer *batch = encoder_context->base.batch;
 474     int len_in_dwords = 11;
 475
 476     BEGIN_BCS_BATCH(batch, len_in_dwords);
 477
 478     OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
 479     OUT_BCS_BATCH(batch, 0);
 480     OUT_BCS_BATCH(batch, 0);
 481     OUT_BCS_BATCH(batch,
 482                   (0 << 24) |           /* PackedMvNum, Debug*/
 483                   (0 << 20) |           /* No motion vector */
 484                   (1 << 19) |           /* CbpDcY */
 485                   (1 << 18) |           /* CbpDcU */
 486                   (1 << 17) |           /* CbpDcV */
 487                   (msg[0] & 0xFFFF) );
 488
 489     OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x);          /* Code Block Pattern for Y*/
 490     OUT_BCS_BATCH(batch, 0x000F000F);                                                   /* Code Block Pattern */
 491     OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp);      /* Last MB */
 492
 493     /*Stuff for Intra MB*/
 494     OUT_BCS_BATCH(batch, msg[1]);                       /* We using Intra16x16 no 4x4 predmode*/
 495     OUT_BCS_BATCH(batch, msg[2]);
 496     OUT_BCS_BATCH(batch, msg[3]&0xFC);
 497
 498     /*MaxSizeInWord and TargetSzieInWord*/
 499     OUT_BCS_BATCH(batch, (max_mb_size << 24) |
 500                   (target_mb_size << 16) );
 501
 502     ADVANCE_BCS_BATCH(batch);
 503
 504     return len_in_dwords;
 505 }
 506
 507 static int gen6_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, int qp, unsigned int offset,
 508                                          struct intel_encoder_context *encoder_context,
 509                                          unsigned char target_mb_size,unsigned char max_mb_size, int slice_type)
 510 {
 511     struct intel_batchbuffer *batch = encoder_context->base.batch;
 512     int len_in_dwords = 11;
 513
 514     BEGIN_BCS_BATCH(batch, len_in_dwords);
 515
 516     OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
 517
 518     OUT_BCS_BATCH(batch, 32);         /* 32 MV*/
 519     OUT_BCS_BATCH(batch, offset);
 520
 521     OUT_BCS_BATCH(batch,
 522                   (1 << 24) |     /* PackedMvNum, Debug*/
 523                   (4 << 20) |     /* 8 MV, SNB don't use it*/
 524                   (1 << 19) |     /* CbpDcY */
 525                   (1 << 18) |     /* CbpDcU */
 526                   (1 << 17) |     /* CbpDcV */
 527                   (0 << 15) |     /* Transform8x8Flag = 0*/
 528                   (0 << 14) |     /* Frame based*/
 529                   (0 << 13) |     /* Inter MB */
 530                   (1 << 8)  |     /* MbType = P_L0_16x16 */
 531                   (0 << 7)  |     /* MBZ for frame */
 532                   (0 << 6)  |     /* MBZ */
 533                   (2 << 4)  |     /* MBZ for inter*/
 534                   (0 << 3)  |     /* MBZ */
 535                   (0 << 2)  |     /* SkipMbFlag */
 536                   (0 << 0));      /* InterMbMode */
 537
 538     OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x);        /* Code Block Pattern for Y*/
 539     OUT_BCS_BATCH(batch, 0x000F000F);                         /* Code Block Pattern */
 540 #if 0
 541     if ( slice_type == SLICE_TYPE_B) {
 542         OUT_BCS_BATCH(batch, (0xF<<28) | (end_mb << 26) | qp);  /* Last MB */
 543     } else {
 544         OUT_BCS_BATCH(batch, (end_mb << 26) | qp);      /* Last MB */
 545     }
 546 #else
 547     OUT_BCS_BATCH(batch, (end_mb << 26) | qp);  /* Last MB */
 548 #endif
 549
 550
 551     /*Stuff for Inter MB*/
 552     OUT_BCS_BATCH(batch, 0x0);
 553     OUT_BCS_BATCH(batch, 0x0);
 554     OUT_BCS_BATCH(batch, 0x0);
 555
 556     /*MaxSizeInWord and TargetSzieInWord*/
 557     OUT_BCS_BATCH(batch, (max_mb_size << 24) |
 558                   (target_mb_size << 16) );
 559
 560     ADVANCE_BCS_BATCH(batch);
 561
 562     return len_in_dwords;
 563 }
 564
 565 static void gen6_mfc_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 566 {
 567     struct i965_driver_data *i965 = i965_driver_data(ctx);
 568     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 569     dri_bo *bo;
 570     int i;
 571
 572     /*Encode common setup for MFC*/
 573     dri_bo_unreference(mfc_context->post_deblocking_output.bo);
 574     mfc_context->post_deblocking_output.bo = NULL;
 575
 576     dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
 577     mfc_context->pre_deblocking_output.bo = NULL;
 578
 579     dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
 580     mfc_context->uncompressed_picture_source.bo = NULL;
 581
 582     dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
 583     mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
 584
 585     for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
 586         if ( mfc_context->direct_mv_buffers[i].bo != NULL);
 587         dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
 588         mfc_context->direct_mv_buffers[i].bo = NULL;
 589     }
 590
 591     for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
 592         if (mfc_context->reference_surfaces[i].bo != NULL)
 593             dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
 594         mfc_context->reference_surfaces[i].bo = NULL;
 595     }
 596
 597     dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
 598     bo = dri_bo_alloc(i965->intel.bufmgr,
 599                       "Buffer",
 600                       128 * 64,
 601                       64);
 602     assert(bo);
 603     mfc_context->intra_row_store_scratch_buffer.bo = bo;
 604
 605     dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
 606     bo = dri_bo_alloc(i965->intel.bufmgr,
 607                       "Buffer",
 608                       128*128*16,
 609                       64);
 610     assert(bo);
 611     mfc_context->macroblock_status_buffer.bo = bo;
 612
 613     dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
 614     bo = dri_bo_alloc(i965->intel.bufmgr,
 615                       "Buffer",
 616                       49152,  /* 6 * 128 * 64 */
 617                       64);
 618     assert(bo);
 619     mfc_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
 620
 621     dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
 622     bo = dri_bo_alloc(i965->intel.bufmgr,
 623                       "Buffer",
 624                       12288, /* 1.5 * 128 * 64 */
 625                       0x1000);
 626     assert(bo);
 627     mfc_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
 628 }
 629
 630 static void gen6_mfc_avc_pipeline_header_programing(VADriverContextP ctx,
 631                                       struct encode_state *encode_state,
 632                                       struct intel_encoder_context *encoder_context)
 633 {
 634     static int count = 0;
 635     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 636     int rate_control_mode = pSequenceParameter->rate_control_method;
 637
 638     if (encode_state->packed_header_data[VAEncPackedHeaderSPS]) {
 639         VAEncPackedHeaderParameterBuffer *param = NULL;
 640         unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[VAEncPackedHeaderSPS]->buffer;
 641         unsigned int length_in_bits;
 642
 643         assert(encode_state->packed_header_param[VAEncPackedHeaderSPS]);
 644         param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[VAEncPackedHeaderSPS]->buffer;
 645         length_in_bits = param->length_in_bits[0];
 646
 647         gen6_mfc_avc_insert_object(ctx,
 648                 encoder_context,
 649                 header_data,
 650                 ALIGN(length_in_bits, 32) >> 5,
 651                 length_in_bits & 0x1f,
 652                 param->skip_emulation_check_count,
 653                 0,
 654                 0,
 655                 param->insert_emulation_bytes);
 656     }
 657
 658     if (encode_state->packed_header_data[VAEncPackedHeaderPPS]) {
 659         VAEncPackedHeaderParameterBuffer *param = NULL;
 660         unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[VAEncPackedHeaderPPS]->buffer;
 661         unsigned int length_in_bits;
 662
 663         assert(encode_state->packed_header_param[VAEncPackedHeaderPPS]);
 664         param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[VAEncPackedHeaderPPS]->buffer;
 665         length_in_bits = param->length_in_bits[0];
 666
 667         gen6_mfc_avc_insert_object(ctx,
 668                 encoder_context,
 669                 header_data,
 670                 ALIGN(length_in_bits, 32) >> 5,
 671                 length_in_bits & 0x1f,
 672                 param->skip_emulation_check_count,
 673                 0,
 674                 0,
 675                 param->insert_emulation_bytes);
 676     }
 677
 678     if ( (rate_control_mode == 0) && encode_state->packed_header_data[VAEncPackedHeaderSPS]) {       // this is frist AU
 679         struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 680
 681         unsigned char *sei_data = NULL;
 682         int length_in_bits = build_avc_sei_buffering_period(mfc_context->vui_hrd.i_initial_cpb_removal_delay_length,
 683                                                             mfc_context->vui_hrd.i_initial_cpb_removal_delay, 0, &sei_data);
 684         gen6_mfc_avc_insert_object(ctx,
 685                 encoder_context,
 686                 (unsigned int *)sei_data,
 687                 ALIGN(length_in_bits, 32) >> 5,
 688                 length_in_bits & 0x1f,
 689                 4,
 690                 0,
 691                 0,
 692                 1);
 693         free(sei_data);
 694     }
 695
 696     // SEI pic_timing header
 697     if ( rate_control_mode == 0) {
 698         struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 699         unsigned char *sei_data = NULL;
 700         int length_in_bits = build_avc_sei_pic_timing( mfc_context->vui_hrd.i_cpb_removal_delay_length,
 701                                                        mfc_context->vui_hrd.i_cpb_removal_delay * mfc_context->vui_hrd.i_frame_number,
 702                                                        mfc_context->vui_hrd.i_dpb_output_delay_length,
 703                                                        0, &sei_data);
 704         gen6_mfc_avc_insert_object(ctx,
 705                 encoder_context,
 706                 (unsigned int *)sei_data,
 707                 ALIGN(length_in_bits, 32) >> 5,
 708                 length_in_bits & 0x1f,
 709                 4,
 710                 0,
 711                 0,
 712                 1);
 713         free(sei_data);
 714     }
 715
 716     count++;
 717 }
 718
 719 static void gen6_mfc_avc_pipeline_picture_programing( VADriverContextP ctx,
 720                                       struct encode_state *encode_state,
 721                                       struct intel_encoder_context *encoder_context)
 722 {
 723     gen6_mfc_pipe_mode_select(ctx, encoder_context);
 724     gen6_mfc_surface_state(ctx, encoder_context);
 725     gen6_mfc_ind_obj_base_addr_state(ctx, encoder_context);
 726     gen6_mfc_pipe_buf_addr_state(ctx, encoder_context);
 727     gen6_mfc_bsp_buf_base_addr_state(ctx, encoder_context);
 728     gen6_mfc_avc_img_state(ctx, encode_state, encoder_context);
 729     gen6_mfc_avc_qm_state(ctx, encoder_context);
 730     gen6_mfc_avc_fqm_state(ctx, encoder_context);
 731     gen6_mfc_avc_directmode_state(ctx, encoder_context);
 732     gen6_mfc_avc_ref_idx_state(ctx, encoder_context);
 733 }
 734
 735 static void
 736 gen6_mfc_avc_pipeline_slice_programing(VADriverContextP ctx,
 737                                        struct encode_state *encode_state,
 738                                        struct intel_encoder_context *encoder_context,
 739                                        int slice_index)
 740 {
 741     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 742     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 743     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 744     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 745     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
 746     VAEncH264DecRefPicMarkingBuffer *pDecRefPicMarking = NULL;
 747     unsigned int *msg = NULL, offset = 0;
 748     int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
 749     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 750     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 751     int last_slice = (pSliceParameter->starting_macroblock_address + pSliceParameter->number_of_mbs) == (width_in_mbs * height_in_mbs);
 752     int i,x,y;
 753     int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta;
 754     int rate_control_mode = pSequenceParameter->rate_control_method;
 755     unsigned char *slice_header = NULL;
 756     int slice_header_length_in_bits = 0;
 757     unsigned int tail_data[] = { 0x0, 0x0 };
 758
 759     gen6_mfc_avc_slice_state(ctx, pSliceParameter->slice_type,
 760                              encode_state, encoder_context,
 761                              (rate_control_mode == 0), qp, slice_index);
 762
 763     if ( slice_index == 0)
 764         gen6_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context);
 765
 766     if (encode_state->dec_ref_pic_marking)
 767         pDecRefPicMarking = (VAEncH264DecRefPicMarkingBuffer *)encode_state->dec_ref_pic_marking->buffer;
 768     slice_header_length_in_bits = build_avc_slice_header(pSequenceParameter, pPicParameter, pSliceParameter, pDecRefPicMarking, &slice_header);
 769
 770     // slice hander
 771     gen6_mfc_avc_insert_object(ctx, encoder_context,
 772             (unsigned int *)slice_header, ALIGN(slice_header_length_in_bits, 32) >> 5, slice_header_length_in_bits & 0x1f,
 773             5,  /* first 5 bytes are start code + nal unit type */
 774             1, 0, 1);
 775
 776     if ( rate_control_mode == 0) {
 777         qp = mfc_context->bit_rate_control_context[1-is_intra].QpPrimeY;
 778     }
 779
 780     if (is_intra) {
 781         dri_bo_map(vme_context->vme_output.bo , 1);
 782         msg = (unsigned int *)vme_context->vme_output.bo->virtual;
 783     }
 784
 785     for (i = pSliceParameter->starting_macroblock_address;
 786          i < pSliceParameter->starting_macroblock_address + pSliceParameter->number_of_mbs; i++) {
 787         int last_mb = (i == (pSliceParameter->starting_macroblock_address + pSliceParameter->number_of_mbs - 1) );
 788         x = i % width_in_mbs;
 789         y = i / width_in_mbs;
 790
 791         if (is_intra) {
 792             assert(msg);
 793             gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0);
 794             msg += 4;
 795         } else {
 796             gen6_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, offset, encoder_context, 0, 0, pSliceParameter->slice_type);
 797             offset += 64;
 798         }
 799     }
 800
 801     if (is_intra)
 802         dri_bo_unmap(vme_context->vme_output.bo);
 803     if ( last_slice ) {
 804         gen6_mfc_avc_insert_object(ctx, encoder_context,
 805                                tail_data, 2, 8,
 806                                2, 1, 1, 0);
 807     } else {
 808         gen6_mfc_avc_insert_object(ctx, encoder_context,
 809                                tail_data, 1, 8,
 810                                1, 1, 1, 0);
 811     }
 812
 813     free(slice_header);
 814
 815 }
 816
 817 static void
 818 gen6_mfc_avc_pipeline_programing(VADriverContextP ctx,
 819                                  struct encode_state *encode_state,
 820                                  struct intel_encoder_context *encoder_context)
 821 {
 822     struct intel_batchbuffer *batch = encoder_context->base.batch;
 823     int i;
 824
 825     // begin programing
 826     intel_batchbuffer_start_atomic_bcs(batch, 0x4000);
 827     intel_batchbuffer_emit_mi_flush(batch);
 828
 829     // picture level programing
 830     gen6_mfc_avc_pipeline_picture_programing(ctx, encode_state, encoder_context);
 831
 832     for ( i = 0; i < encode_state->num_slice_params_ext; i++) {
 833         // slice level programing
 834         gen6_mfc_avc_pipeline_slice_programing(ctx, encode_state, encoder_context, i);
 835     }
 836
 837     // end programing
 838     intel_batchbuffer_end_atomic(batch);
 839
 840     return;
 841 }
 842
 843 static void
 844 gen6_mfc_free_avc_surface(void **data)
 845 {
 846     struct gen6_mfc_avc_surface_aux *avc_surface = *data;
 847
 848     if (!avc_surface)
 849         return;
 850
 851     dri_bo_unreference(avc_surface->dmv_top);
 852     avc_surface->dmv_top = NULL;
 853     dri_bo_unreference(avc_surface->dmv_bottom);
 854     avc_surface->dmv_bottom = NULL;
 855
 856     free(avc_surface);
 857     *data = NULL;
 858 }
 859
 860 static void gen6_mfc_bit_rate_control_context_init(struct encode_state *encode_state,
 861                                                    struct gen6_mfc_context *mfc_context)
 862 {
 863     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 864
 865     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 866     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 867     float fps =  pSequenceParameter->time_scale * 0.5 / pSequenceParameter->num_units_in_tick ;
 868     int inter_mb_size = pSequenceParameter->bits_per_second * 1.0 / (fps+4.0) / width_in_mbs / height_in_mbs;
 869     int intra_mb_size = inter_mb_size * 5.0;
 870     int i;
 871
 872     mfc_context->bit_rate_control_context[0].target_mb_size = intra_mb_size;
 873     mfc_context->bit_rate_control_context[0].target_frame_size = intra_mb_size * width_in_mbs * height_in_mbs;
 874     mfc_context->bit_rate_control_context[1].target_mb_size = inter_mb_size;
 875     mfc_context->bit_rate_control_context[1].target_frame_size = inter_mb_size * width_in_mbs * height_in_mbs;
 876
 877     for(i = 0 ; i < 2; i++) {
 878         mfc_context->bit_rate_control_context[i].QpPrimeY = 26;
 879         mfc_context->bit_rate_control_context[i].MaxQpNegModifier = 6;
 880         mfc_context->bit_rate_control_context[i].MaxQpPosModifier = 6;
 881         mfc_context->bit_rate_control_context[i].GrowInit = 6;
 882         mfc_context->bit_rate_control_context[i].GrowResistance = 4;
 883         mfc_context->bit_rate_control_context[i].ShrinkInit = 6;
 884         mfc_context->bit_rate_control_context[i].ShrinkResistance = 4;
 885
 886         mfc_context->bit_rate_control_context[i].Correct[0] = 8;
 887         mfc_context->bit_rate_control_context[i].Correct[1] = 4;
 888         mfc_context->bit_rate_control_context[i].Correct[2] = 2;
 889         mfc_context->bit_rate_control_context[i].Correct[3] = 2;
 890         mfc_context->bit_rate_control_context[i].Correct[4] = 4;
 891         mfc_context->bit_rate_control_context[i].Correct[5] = 8;
 892     }
 893
 894     mfc_context->bit_rate_control_context[0].TargetSizeInWord = (intra_mb_size + 16)/ 16;
 895     mfc_context->bit_rate_control_context[1].TargetSizeInWord = (inter_mb_size + 16)/ 16;
 896
 897     mfc_context->bit_rate_control_context[0].MaxSizeInWord = mfc_context->bit_rate_control_context[0].TargetSizeInWord * 1.5;
 898     mfc_context->bit_rate_control_context[1].MaxSizeInWord = mfc_context->bit_rate_control_context[1].TargetSizeInWord * 1.5;
 899 }
 900
 901 static int gen6_mfc_bit_rate_control_context_update(struct encode_state *encode_state,
 902                                                     struct gen6_mfc_context *mfc_context,
 903                                                     int current_frame_size)
 904 {
 905     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
 906     int control_index = 1 - (pSliceParameter->slice_type == SLICE_TYPE_I);
 907     int oldQp = mfc_context->bit_rate_control_context[control_index].QpPrimeY;
 908
 909     /*
 910       printf("conrol_index = %d, start_qp = %d, result = %d, target = %d\n", control_index,
 911       mfc_context->bit_rate_control_context[control_index].QpPrimeY, current_frame_size,
 912       mfc_context->bit_rate_control_context[control_index].target_frame_size );
 913     */
 914
 915     if ( current_frame_size > mfc_context->bit_rate_control_context[control_index].target_frame_size * 4.0 ) {
 916         mfc_context->bit_rate_control_context[control_index].QpPrimeY += 4;
 917     } else if ( current_frame_size > mfc_context->bit_rate_control_context[control_index].target_frame_size * 2.0 ) {
 918         mfc_context->bit_rate_control_context[control_index].QpPrimeY += 3;
 919     } else if ( current_frame_size > mfc_context->bit_rate_control_context[control_index].target_frame_size * 1.50 ) {
 920         mfc_context->bit_rate_control_context[control_index].QpPrimeY += 2;
 921     } else if ( current_frame_size > mfc_context->bit_rate_control_context[control_index].target_frame_size * 1.20 ) {
 922         mfc_context->bit_rate_control_context[control_index].QpPrimeY ++;
 923     } else if (current_frame_size < mfc_context->bit_rate_control_context[control_index].target_frame_size * 0.30 )  {
 924         mfc_context->bit_rate_control_context[control_index].QpPrimeY -= 3;
 925     } else if (current_frame_size < mfc_context->bit_rate_control_context[control_index].target_frame_size * 0.50 )  {
 926         mfc_context->bit_rate_control_context[control_index].QpPrimeY -= 2;
 927     } else if (current_frame_size < mfc_context->bit_rate_control_context[control_index].target_frame_size * 0.80 )  {
 928         mfc_context->bit_rate_control_context[control_index].QpPrimeY --;
 929     }
 930
 931     if ( mfc_context->bit_rate_control_context[control_index].QpPrimeY > 51)
 932         mfc_context->bit_rate_control_context[control_index].QpPrimeY = 51;
 933     if ( mfc_context->bit_rate_control_context[control_index].QpPrimeY < 1)
 934         mfc_context->bit_rate_control_context[control_index].QpPrimeY = 1;
 935
 936     if ( mfc_context->bit_rate_control_context[control_index].QpPrimeY != oldQp)
 937         return 0;
 938
 939     return 1;
 940 }
 941
 942 static void
 943 gen6_mfc_hrd_context_init(struct encode_state *encode_state,
 944                           struct gen6_mfc_context *mfc_context)
 945 {
 946     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 947     int rate_control_mode = pSequenceParameter->rate_control_method;
 948     int target_bit_rate = pSequenceParameter->bits_per_second;
 949
 950     // current we only support CBR mode.
 951     if ( rate_control_mode == 0) {
 952         mfc_context->vui_hrd.i_bit_rate_value = target_bit_rate >> 10;
 953         mfc_context->vui_hrd.i_cpb_size_value = (target_bit_rate * 8) >> 10;
 954         mfc_context->vui_hrd.i_initial_cpb_removal_delay = mfc_context->vui_hrd.i_cpb_size_value * 0.5 * 1024 / target_bit_rate * 90000;
 955         mfc_context->vui_hrd.i_cpb_removal_delay = 2;
 956         mfc_context->vui_hrd.i_frame_number = 0;
 957
 958         mfc_context->vui_hrd.i_initial_cpb_removal_delay_length = 24;
 959         mfc_context->vui_hrd.i_cpb_removal_delay_length = 24;
 960         mfc_context->vui_hrd.i_dpb_output_delay_length = 24;
 961     }
 962
 963 }
 964
 965 static VAStatus
 966 gen6_mfc_hrd_context_check(struct encode_state *encode_state,
 967                           struct gen6_mfc_context *mfc_context)
 968 {
 969     return VA_STATUS_SUCCESS;
 970 }
 971
 972 static void
 973 gen6_mfc_hrd_context_update(struct encode_state *encode_state,
 974                           struct gen6_mfc_context *mfc_context)
 975 {
 976     mfc_context->vui_hrd.i_frame_number++;
 977 }
 978
 979 static VAStatus gen6_mfc_avc_prepare(VADriverContextP ctx,
 980                                      struct encode_state *encode_state,
 981                                      struct intel_encoder_context *encoder_context)
 982 {
 983     struct i965_driver_data *i965 = i965_driver_data(ctx);
 984     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 985     struct object_surface *obj_surface;
 986     struct object_buffer *obj_buffer;
 987     struct gen6_mfc_avc_surface_aux* gen6_avc_surface;
 988     dri_bo *bo;
 989     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 990     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 991     int rate_control_mode = pSequenceParameter->rate_control_method;
 992     VAStatus vaStatus = VA_STATUS_SUCCESS;
 993     int i;
 994
 995     /*Setup all the input&output object*/
 996
 997     /* Setup current frame and current direct mv buffer*/
 998     obj_surface = SURFACE(pPicParameter->CurrPic.picture_id);
 999     assert(obj_surface);
1000     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
1001
1002     if ( obj_surface->private_data == NULL) {
1003         gen6_avc_surface = calloc(sizeof(struct gen6_mfc_avc_surface_aux), 1);
1004         gen6_avc_surface->dmv_top =
1005             dri_bo_alloc(i965->intel.bufmgr,
1006                          "Buffer",
1007                          68*8192,
1008                          64);
1009         gen6_avc_surface->dmv_bottom =
1010             dri_bo_alloc(i965->intel.bufmgr,
1011                          "Buffer",
1012                          68*8192,
1013                          64);
1014         assert(gen6_avc_surface->dmv_top);
1015         assert(gen6_avc_surface->dmv_bottom);
1016         obj_surface->private_data = (void *)gen6_avc_surface;
1017         obj_surface->free_private_data = (void *)gen6_mfc_free_avc_surface;
1018     }
1019     gen6_avc_surface = (struct gen6_mfc_avc_surface_aux*) obj_surface->private_data;
1020     mfc_context->direct_mv_buffers[NUM_MFC_DMV_BUFFERS - 2].bo = gen6_avc_surface->dmv_top;
1021     mfc_context->direct_mv_buffers[NUM_MFC_DMV_BUFFERS - 1].bo = gen6_avc_surface->dmv_bottom;
1022     dri_bo_reference(gen6_avc_surface->dmv_top);
1023     dri_bo_reference(gen6_avc_surface->dmv_bottom);
1024
1025     mfc_context->post_deblocking_output.bo = obj_surface->bo;
1026     dri_bo_reference(mfc_context->post_deblocking_output.bo);
1027
1028     mfc_context->surface_state.width = obj_surface->orig_width;
1029     mfc_context->surface_state.height = obj_surface->orig_height;
1030     mfc_context->surface_state.w_pitch = obj_surface->width;
1031     mfc_context->surface_state.h_pitch = obj_surface->height;
1032
1033     /* Setup reference frames and direct mv buffers*/
1034     for(i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++) {
1035         if ( pPicParameter->ReferenceFrames[i].picture_id != VA_INVALID_ID ) {
1036             obj_surface = SURFACE(pPicParameter->ReferenceFrames[i].picture_id);
1037             assert(obj_surface);
1038             if (obj_surface->bo != NULL) {
1039                 mfc_context->reference_surfaces[i].bo = obj_surface->bo;
1040                 dri_bo_reference(obj_surface->bo);
1041             }
1042             /* Check DMV buffer */
1043             if ( obj_surface->private_data == NULL) {
1044
1045                 gen6_avc_surface = calloc(sizeof(struct gen6_mfc_avc_surface_aux), 1);
1046                 gen6_avc_surface->dmv_top =
1047                     dri_bo_alloc(i965->intel.bufmgr,
1048                                  "Buffer",
1049                                  68*8192,
1050                                  64);
1051                 gen6_avc_surface->dmv_bottom =
1052                     dri_bo_alloc(i965->intel.bufmgr,
1053                                  "Buffer",
1054                                  68*8192,
1055                                  64);
1056                 assert(gen6_avc_surface->dmv_top);
1057                 assert(gen6_avc_surface->dmv_bottom);
1058                 obj_surface->private_data = gen6_avc_surface;
1059                 obj_surface->free_private_data = gen6_mfc_free_avc_surface;
1060             }
1061
1062             gen6_avc_surface = (struct gen6_mfc_avc_surface_aux*) obj_surface->private_data;
1063             /* Setup DMV buffer */
1064             mfc_context->direct_mv_buffers[i*2].bo = gen6_avc_surface->dmv_top;
1065             mfc_context->direct_mv_buffers[i*2+1].bo = gen6_avc_surface->dmv_bottom;
1066             dri_bo_reference(gen6_avc_surface->dmv_top);
1067             dri_bo_reference(gen6_avc_surface->dmv_bottom);
1068         } else {
1069             break;
1070         }
1071     }
1072
1073     obj_surface = SURFACE(encoder_context->input_yuv_surface);
1074     assert(obj_surface && obj_surface->bo);
1075     mfc_context->uncompressed_picture_source.bo = obj_surface->bo;
1076     dri_bo_reference(mfc_context->uncompressed_picture_source.bo);
1077
1078     obj_buffer = BUFFER (pPicParameter->CodedBuf); /* FIXME: fix this later */
1079     bo = obj_buffer->buffer_store->bo;
1080     assert(bo);
1081     mfc_context->mfc_indirect_pak_bse_object.bo = bo;
1082     mfc_context->mfc_indirect_pak_bse_object.offset = ALIGN(sizeof(VACodedBufferSegment), 64);
1083     mfc_context->mfc_indirect_pak_bse_object.end_offset = ALIGN (obj_buffer->size_element - 0x1000, 0x1000);
1084     dri_bo_reference(mfc_context->mfc_indirect_pak_bse_object.bo);
1085
1086     /*Programing bit rate control */
1087     if ( mfc_context->bit_rate_control_context[0].MaxSizeInWord == 0 )
1088         gen6_mfc_bit_rate_control_context_init(encode_state, mfc_context);
1089
1090     /*Programing HRD control */
1091     if ( (rate_control_mode == 0) && (mfc_context->vui_hrd.i_cpb_size_value == 0) )
1092         gen6_mfc_hrd_context_init(encode_state, mfc_context);
1093
1094     /*Programing bcs pipeline*/
1095     gen6_mfc_avc_pipeline_programing(ctx, encode_state, encoder_context);       //filling the pipeline
1096
1097     return vaStatus;
1098 }
1099
1100 static VAStatus gen6_mfc_run(VADriverContextP ctx,
1101                              struct encode_state *encode_state,
1102                              struct intel_encoder_context *encoder_context)
1103 {
1104     struct intel_batchbuffer *batch = encoder_context->base.batch;
1105
1106     intel_batchbuffer_flush(batch);             //run the pipeline
1107
1108     return VA_STATUS_SUCCESS;
1109 }
1110
1111 static VAStatus gen6_mfc_stop(VADriverContextP ctx,
1112                               struct encode_state *encode_state,
1113                               struct intel_encoder_context *encoder_context,
1114                               int *encoded_bits_size)
1115 {
1116     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1117     unsigned int *status_mem;
1118     unsigned int buffer_size_bits = 0;
1119     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
1120     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
1121     int i;
1122
1123     dri_bo_map(mfc_context->macroblock_status_buffer.bo, 1);
1124     status_mem = (unsigned int *)mfc_context->macroblock_status_buffer.bo->virtual;
1125     //Detecting encoder buffer size and bit rate control result
1126     for(i = 0; i < width_in_mbs * height_in_mbs; i++) {
1127         unsigned short current_mb = status_mem[1] >> 16;
1128         buffer_size_bits += current_mb;
1129         status_mem += 4;
1130     }
1131     dri_bo_unmap(mfc_context->macroblock_status_buffer.bo);
1132
1133     *encoded_bits_size = buffer_size_bits;
1134
1135     return VA_STATUS_SUCCESS;
1136 }
1137
1138 static VAStatus
1139 gen6_mfc_avc_encode_picture(VADriverContextP ctx,
1140                             struct encode_state *encode_state,
1141                             struct intel_encoder_context *encoder_context)
1142 {
1143     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
1144     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1145     int rate_control_mode = pSequenceParameter->rate_control_method;
1146     int MAX_CBR_INTERATE = 4;
1147     int current_frame_bits_size;
1148     int i;
1149
1150     for(i = 0; i < MAX_CBR_INTERATE; i++) {
1151         gen6_mfc_init(ctx, encoder_context);
1152         gen6_mfc_avc_prepare(ctx, encode_state, encoder_context);
1153         gen6_mfc_run(ctx, encode_state, encoder_context);
1154         gen6_mfc_stop(ctx, encode_state, encoder_context, &current_frame_bits_size);
1155         if ( rate_control_mode == 0) {
1156             //gen6_mfc_hrd_context_check(encode_state, mfc_context);
1157             if ( gen6_mfc_bit_rate_control_context_update( encode_state, mfc_context, current_frame_bits_size) ) {
1158                 gen6_mfc_hrd_context_update(encode_state, mfc_context);
1159                 break;
1160             }
1161         } else {
1162             break;
1163         }
1164     }
1165
1166     return VA_STATUS_SUCCESS;
1167 }
1168
1169 static VAStatus
1170 gen6_mfc_pipeline(VADriverContextP ctx,
1171                   VAProfile profile,
1172                   struct encode_state *encode_state,
1173                   struct intel_encoder_context *encoder_context)
1174 {
1175     VAStatus vaStatus;
1176
1177     switch (profile) {
1178     case VAProfileH264Baseline:
1179         vaStatus = gen6_mfc_avc_encode_picture(ctx, encode_state, encoder_context);
1180         break;
1181
1182         /* FIXME: add for other profile */
1183     default:
1184         vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
1185         break;
1186     }
1187
1188     return vaStatus;
1189 }
1190
1191 static void
1192 gen6_mfc_context_destroy(void *context)
1193 {
1194     struct gen6_mfc_context *mfc_context = context;
1195     int i;
1196
1197     dri_bo_unreference(mfc_context->post_deblocking_output.bo);
1198     mfc_context->post_deblocking_output.bo = NULL;
1199
1200     dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
1201     mfc_context->pre_deblocking_output.bo = NULL;
1202
1203     dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
1204     mfc_context->uncompressed_picture_source.bo = NULL;
1205
1206     dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
1207     mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
1208
1209     for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
1210         dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
1211         mfc_context->direct_mv_buffers[i].bo = NULL;
1212     }
1213
1214     dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
1215     mfc_context->intra_row_store_scratch_buffer.bo = NULL;
1216
1217     dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
1218     mfc_context->macroblock_status_buffer.bo = NULL;
1219
1220     dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
1221     mfc_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
1222
1223     dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
1224     mfc_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
1225
1226
1227     for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
1228         dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
1229         mfc_context->reference_surfaces[i].bo = NULL;
1230     }
1231
1232     free(mfc_context);
1233 }
1234
1235 Bool gen6_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
1236 {
1237     encoder_context->mfc_context = calloc(1, sizeof(struct gen6_mfc_context));
1238     encoder_context->mfc_context_destroy = gen6_mfc_context_destroy;
1239     encoder_context->mfc_pipeline = gen6_mfc_pipeline;
1240
1241     return True;
1242 }