2 * Copyright © 2010-2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Zhou Chang <chang.zhou@intel.com>
34 #include "intel_batchbuffer.h"
35 #include "i965_defines.h"
36 #include "i965_structs.h"
37 #include "i965_drv_video.h"
38 #include "i965_encoder.h"
39 #include "i965_encoder_utils.h"
43 #define CMD_LEN_IN_OWORD 4
45 static const uint32_t gen6_mfc_batchbuffer_avc_intra[][4] = {
46 #include "shaders/utils/mfc_batchbuffer_avc_intra.g6b"
49 static const uint32_t gen6_mfc_batchbuffer_avc_inter[][4] = {
50 #include "shaders/utils/mfc_batchbuffer_avc_inter.g6b"
53 static struct i965_kernel gen6_mfc_kernels[] = {
55 "MFC AVC INTRA BATCHBUFFER ",
56 MFC_BATCHBUFFER_AVC_INTRA,
57 gen6_mfc_batchbuffer_avc_intra,
58 sizeof(gen6_mfc_batchbuffer_avc_intra),
63 "MFC AVC INTER BATCHBUFFER ",
64 MFC_BATCHBUFFER_AVC_INTER,
65 gen6_mfc_batchbuffer_avc_inter,
66 sizeof(gen6_mfc_batchbuffer_avc_inter),
72 gen6_mfc_pipe_mode_select(VADriverContextP ctx,
74 struct intel_encoder_context *encoder_context)
76 struct intel_batchbuffer *batch = encoder_context->base.batch;
77 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
79 assert(standard_select == MFX_FORMAT_AVC);
81 BEGIN_BCS_BATCH(batch, 4);
83 OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (4 - 2));
85 (1 << 10) | /* disable Stream-Out , advanced QP/bitrate control need enable it*/
86 ((!!mfc_context->post_deblocking_output.bo) << 9) | /* Post Deblocking Output */
87 ((!!mfc_context->pre_deblocking_output.bo) << 8) | /* Pre Deblocking Output */
88 (0 << 7) | /* disable TLB prefectch */
89 (0 << 5) | /* not in stitch mode */
90 (1 << 4) | /* encoding mode */
91 (2 << 0)); /* Standard Select: AVC */
93 (0 << 20) | /* round flag in PB slice */
94 (0 << 19) | /* round flag in Intra8x8 */
95 (0 << 7) | /* expand NOA bus flag */
96 (1 << 6) | /* must be 1 */
97 (0 << 5) | /* disable clock gating for NOA */
98 (0 << 4) | /* terminate if AVC motion and POC table error occurs */
99 (0 << 3) | /* terminate if AVC mbdata error occurs */
100 (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */
101 (0 << 1) | /* AVC long field motion vector */
102 (0 << 0)); /* always calculate AVC ILDB boundary strength */
103 OUT_BCS_BATCH(batch, 0);
105 ADVANCE_BCS_BATCH(batch);
109 gen6_mfc_surface_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
111 struct intel_batchbuffer *batch = encoder_context->base.batch;
112 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
114 BEGIN_BCS_BATCH(batch, 6);
116 OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
117 OUT_BCS_BATCH(batch, 0);
119 ((mfc_context->surface_state.height - 1) << 19) |
120 ((mfc_context->surface_state.width - 1) << 6));
122 (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
123 (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
124 (0 << 22) | /* surface object control state, FIXME??? */
125 ((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */
126 (0 << 2) | /* must be 0 for interleave U/V */
127 (1 << 1) | /* must be y-tiled */
128 (I965_TILEWALK_YMAJOR << 0)); /* tile walk, TILEWALK_YMAJOR */
130 (0 << 16) | /* must be 0 for interleave U/V */
131 (mfc_context->surface_state.h_pitch)); /* y offset for U(cb) */
132 OUT_BCS_BATCH(batch, 0);
133 ADVANCE_BCS_BATCH(batch);
137 gen6_mfc_pipe_buf_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
139 struct intel_batchbuffer *batch = encoder_context->base.batch;
140 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
143 BEGIN_BCS_BATCH(batch, 24);
145 OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
147 if (mfc_context->pre_deblocking_output.bo)
148 OUT_BCS_RELOC(batch, mfc_context->pre_deblocking_output.bo,
149 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
152 OUT_BCS_BATCH(batch, 0); /* pre output addr */
154 if (mfc_context->post_deblocking_output.bo)
155 OUT_BCS_RELOC(batch, mfc_context->post_deblocking_output.bo,
156 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
157 0); /* post output addr */
159 OUT_BCS_BATCH(batch, 0);
161 OUT_BCS_RELOC(batch, mfc_context->uncompressed_picture_source.bo,
162 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
163 0); /* uncompressed data */
164 OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
165 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
166 0); /* StreamOut data*/
167 OUT_BCS_RELOC(batch, mfc_context->intra_row_store_scratch_buffer.bo,
168 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
170 OUT_BCS_RELOC(batch, mfc_context->deblocking_filter_row_store_scratch_buffer.bo,
171 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
173 /* 7..22 Reference pictures*/
174 for (i = 0; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) {
175 if ( mfc_context->reference_surfaces[i].bo != NULL) {
176 OUT_BCS_RELOC(batch, mfc_context->reference_surfaces[i].bo,
177 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
180 OUT_BCS_BATCH(batch, 0);
183 OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
184 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
185 0); /* Macroblock status buffer*/
187 ADVANCE_BCS_BATCH(batch);
191 gen6_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
193 struct intel_batchbuffer *batch = encoder_context->base.batch;
194 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
195 struct gen6_vme_context *vme_context = encoder_context->vme_context;
197 BEGIN_BCS_BATCH(batch, 11);
199 OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
200 OUT_BCS_BATCH(batch, 0);
201 OUT_BCS_BATCH(batch, 0);
202 /* MFX Indirect MV Object Base Address */
203 OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
204 OUT_BCS_BATCH(batch, 0);
205 OUT_BCS_BATCH(batch, 0);
206 OUT_BCS_BATCH(batch, 0);
207 OUT_BCS_BATCH(batch, 0);
208 OUT_BCS_BATCH(batch, 0);
209 /*MFC Indirect PAK-BSE Object Base Address for Encoder*/
211 mfc_context->mfc_indirect_pak_bse_object.bo,
212 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
215 mfc_context->mfc_indirect_pak_bse_object.bo,
216 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
217 mfc_context->mfc_indirect_pak_bse_object.end_offset);
219 ADVANCE_BCS_BATCH(batch);
223 gen6_mfc_bsp_buf_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
225 struct intel_batchbuffer *batch = encoder_context->base.batch;
226 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
228 BEGIN_BCS_BATCH(batch, 4);
230 OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
231 OUT_BCS_RELOC(batch, mfc_context->bsd_mpc_row_store_scratch_buffer.bo,
232 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
234 OUT_BCS_BATCH(batch, 0);
235 OUT_BCS_BATCH(batch, 0);
237 ADVANCE_BCS_BATCH(batch);
241 gen6_mfc_avc_img_state(VADriverContextP ctx,struct encode_state *encode_state,
242 struct intel_encoder_context *encoder_context)
244 struct intel_batchbuffer *batch = encoder_context->base.batch;
245 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
246 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
247 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
248 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
249 int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
251 BEGIN_BCS_BATCH(batch, 13);
252 OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (13 - 2));
254 ((width_in_mbs * height_in_mbs) & 0xFFFF));
256 (height_in_mbs << 16) |
257 (width_in_mbs << 0));
259 (0 << 24) | /*Second Chroma QP Offset*/
260 (0 << 16) | /*Chroma QP Offset*/
261 (0 << 14) | /*Max-bit conformance Intra flag*/
262 (0 << 13) | /*Max Macroblock size conformance Inter flag*/
263 (1 << 12) | /*Should always be written as "1" */
264 (0 << 10) | /*QM Preset FLag */
265 (0 << 8) | /*Image Structure*/
266 (0 << 0) ); /*Current Decoed Image Frame Store ID, reserved in Encode mode*/
268 (400 << 16) | /*Mininum Frame size*/
269 (0 << 15) | /*Disable reading of Macroblock Status Buffer*/
270 (0 << 14) | /*Load BitStream Pointer only once, 1 slic 1 frame*/
271 (0 << 13) | /*CABAC 0 word insertion test enable*/
272 (1 << 12) | /*MVUnpackedEnable,compliant to DXVA*/
273 (1 << 10) | /*Chroma Format IDC, 4:2:0*/
274 (pPicParameter->pic_fields.bits.entropy_coding_mode_flag << 7) | /*0:CAVLC encoding mode,1:CABAC*/
275 (0 << 6) | /*Only valid for VLD decoding mode*/
276 (0 << 5) | /*Constrained Intra Predition Flag, from PPS*/
277 (pSequenceParameter->seq_fields.bits.direct_8x8_inference_flag << 4) | /*Direct 8x8 inference flag*/
278 (pPicParameter->pic_fields.bits.transform_8x8_mode_flag << 3) | /*8x8 or 4x4 IDCT Transform Mode Flag*/
279 (1 << 2) | /*Frame MB only flag*/
280 (0 << 1) | /*MBAFF mode is in active*/
281 (0 << 0) ); /*Field picture flag*/
283 (1<<16) | /*Frame Size Rate Control Flag*/
285 (1<<9) | /*MB level Rate Control Enabling Flag*/
286 (1 << 3) | /*FrameBitRateMinReportMask*/
287 (1 << 2) | /*FrameBitRateMaxReportMask*/
288 (1 << 1) | /*InterMBMaxSizeReportMask*/
289 (1 << 0) ); /*IntraMBMaxSizeReportMask*/
290 OUT_BCS_BATCH(batch, /*Inter and Intra Conformance Max size limit*/
291 (0x0600 << 16) | /*InterMbMaxSz 192 Byte*/
292 (0x0800) ); /*IntraMbMaxSz 256 Byte*/
293 OUT_BCS_BATCH(batch, 0x00000000); /*Reserved : MBZReserved*/
294 OUT_BCS_BATCH(batch, 0x01020304); /*Slice QP Delta for bitrate control*/
295 OUT_BCS_BATCH(batch, 0xFEFDFCFB);
296 OUT_BCS_BATCH(batch, 0x80601004); /*MAX = 128KB, MIN = 64KB*/
297 OUT_BCS_BATCH(batch, 0x00800001);
298 OUT_BCS_BATCH(batch, 0);
300 ADVANCE_BCS_BATCH(batch);
304 gen6_mfc_avc_directmode_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
306 struct intel_batchbuffer *batch = encoder_context->base.batch;
307 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
311 BEGIN_BCS_BATCH(batch, 69);
313 OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
315 /* Reference frames and Current frames */
316 for(i = 0; i < NUM_MFC_DMV_BUFFERS; i++) {
317 if ( mfc_context->direct_mv_buffers[i].bo != NULL) {
318 OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[i].bo,
319 I915_GEM_DOMAIN_INSTRUCTION, 0,
322 OUT_BCS_BATCH(batch, 0);
327 for(i = 0; i < 32; i++) {
328 OUT_BCS_BATCH(batch, i/2);
330 OUT_BCS_BATCH(batch, 0);
331 OUT_BCS_BATCH(batch, 0);
333 ADVANCE_BCS_BATCH(batch);
337 gen6_mfc_avc_slice_state(VADriverContextP ctx,
338 VAEncPictureParameterBufferH264 *pic_param,
339 VAEncSliceParameterBufferH264 *slice_param,
340 struct encode_state *encode_state,
341 struct intel_encoder_context *encoder_context,
342 int rate_control_enable,
344 struct intel_batchbuffer *batch)
346 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
347 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
348 int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
349 int beginmb = slice_param->macroblock_address;
350 int endmb = beginmb + slice_param->num_macroblocks;
351 int beginx = beginmb % width_in_mbs;
352 int beginy = beginmb / width_in_mbs;
353 int nextx = endmb % width_in_mbs;
354 int nexty = endmb / width_in_mbs;
355 int slice_type = slice_param->slice_type;
356 int last_slice = (endmb == (width_in_mbs * height_in_mbs));
357 int bit_rate_control_target, maxQpN, maxQpP;
358 unsigned char correct[6], grow, shrink;
360 int weighted_pred_idc = 0;
363 batch = encoder_context->base.batch;
365 if (slice_type == SLICE_TYPE_I)
366 bit_rate_control_target = 0;
368 bit_rate_control_target = 1;
370 if (slice_type == SLICE_TYPE_P) {
371 weighted_pred_idc = pic_param->pic_fields.bits.weighted_pred_flag;
372 } else if (slice_type == SLICE_TYPE_B) {
373 weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc;
376 maxQpN = mfc_context->bit_rate_control_context[bit_rate_control_target].MaxQpNegModifier;
377 maxQpP = mfc_context->bit_rate_control_context[bit_rate_control_target].MaxQpPosModifier;
379 for (i = 0; i < 6; i++)
380 correct[i] = mfc_context->bit_rate_control_context[bit_rate_control_target].Correct[i];
382 grow = mfc_context->bit_rate_control_context[bit_rate_control_target].GrowInit +
383 (mfc_context->bit_rate_control_context[bit_rate_control_target].GrowResistance << 4);
384 shrink = mfc_context->bit_rate_control_context[bit_rate_control_target].ShrinkInit +
385 (mfc_context->bit_rate_control_context[bit_rate_control_target].ShrinkResistance << 4);
387 BEGIN_BCS_BATCH(batch, 11);;
389 OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) );
390 OUT_BCS_BATCH(batch, slice_type); /*Slice Type: I:P:B Slice*/
392 if (slice_type == SLICE_TYPE_I) {
393 OUT_BCS_BATCH(batch, 0); /*no reference frames and pred_weight_table*/
395 OUT_BCS_BATCH(batch, 0x00010000); /*1 reference frame*/
399 (weighted_pred_idc << 30) |
400 (slice_param->direct_spatial_mv_pred_flag<<29) | /*Direct Prediction Type*/
401 (slice_param->disable_deblocking_filter_idc << 27) |
402 (slice_param->cabac_init_idc << 24) |
403 (qp<<16) | /*Slice Quantization Parameter*/
404 ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
405 ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
407 (beginy << 24) | /*First MB X&Y , the begin postion of current slice*/
409 slice_param->macroblock_address );
410 OUT_BCS_BATCH(batch, (nexty << 16) | nextx); /*Next slice first MB X&Y*/
412 (rate_control_enable << 31) | /*in CBR mode RateControlCounterEnable = enable*/
413 (1 << 30) | /*ResetRateControlCounter*/
414 (0 << 28) | /*RC Triggle Mode = Always Rate Control*/
415 (4 << 24) | /*RC Stable Tolerance, middle level*/
416 (rate_control_enable << 23) | /*RC Panic Enable*/
417 (0 << 22) | /*QP mode, don't modfiy CBP*/
418 (0 << 21) | /*MB Type Direct Conversion Enabled*/
419 (0 << 20) | /*MB Type Skip Conversion Enabled*/
420 (last_slice << 19) | /*IsLastSlice*/
421 (0 << 18) | /*BitstreamOutputFlag Compressed BitStream Output Disable Flag 0:enable 1:disable*/
422 (1 << 17) | /*HeaderPresentFlag*/
423 (1 << 16) | /*SliceData PresentFlag*/
424 (1 << 15) | /*TailPresentFlag*/
425 (1 << 13) | /*RBSP NAL TYPE*/
426 (0 << 12) ); /*CabacZeroWordInsertionEnable*/
427 OUT_BCS_BATCH(batch, mfc_context->mfc_indirect_pak_bse_object.offset);
429 (maxQpN << 24) | /*Target QP - 24 is lowest QP*/
430 (maxQpP << 16) | /*Target QP + 20 is highest QP*/
440 OUT_BCS_BATCH(batch, 0);
442 ADVANCE_BCS_BATCH(batch);
445 static void gen6_mfc_avc_qm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
447 struct intel_batchbuffer *batch = encoder_context->base.batch;
450 BEGIN_BCS_BATCH(batch, 58);
452 OUT_BCS_BATCH(batch, MFX_AVC_QM_STATE | 56);
453 OUT_BCS_BATCH(batch, 0xFF ) ;
454 for( i = 0; i < 56; i++) {
455 OUT_BCS_BATCH(batch, 0x10101010);
458 ADVANCE_BCS_BATCH(batch);
461 static void gen6_mfc_avc_fqm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
463 struct intel_batchbuffer *batch = encoder_context->base.batch;
466 BEGIN_BCS_BATCH(batch, 113);
467 OUT_BCS_BATCH(batch, MFC_AVC_FQM_STATE | (113 - 2));
469 for(i = 0; i < 112;i++) {
470 OUT_BCS_BATCH(batch, 0x10001000);
473 ADVANCE_BCS_BATCH(batch);
477 gen6_mfc_avc_ref_idx_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
479 struct intel_batchbuffer *batch = encoder_context->base.batch;
482 BEGIN_BCS_BATCH(batch, 10);
483 OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
484 OUT_BCS_BATCH(batch, 0); //Select L0
485 OUT_BCS_BATCH(batch, 0x80808020); //Only 1 reference
486 for(i = 0; i < 7; i++) {
487 OUT_BCS_BATCH(batch, 0x80808080);
489 ADVANCE_BCS_BATCH(batch);
491 BEGIN_BCS_BATCH(batch, 10);
492 OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
493 OUT_BCS_BATCH(batch, 1); //Select L1
494 OUT_BCS_BATCH(batch, 0x80808022); //Only 1 reference
495 for(i = 0; i < 7; i++) {
496 OUT_BCS_BATCH(batch, 0x80808080);
498 ADVANCE_BCS_BATCH(batch);
502 gen6_mfc_avc_insert_object(VADriverContextP ctx, struct intel_encoder_context *encoder_context,
503 unsigned int *insert_data, int lenght_in_dws, int data_bits_in_last_dw,
504 int skip_emul_byte_count, int is_last_header, int is_end_of_slice, int emulation_flag,
505 struct intel_batchbuffer *batch)
508 batch = encoder_context->base.batch;
510 BEGIN_BCS_BATCH(batch, lenght_in_dws + 2);
512 OUT_BCS_BATCH(batch, MFC_AVC_INSERT_OBJECT | (lenght_in_dws + 2 - 2));
515 (0 << 16) | /* always start at offset 0 */
516 (data_bits_in_last_dw << 8) |
517 (skip_emul_byte_count << 4) |
518 (!!emulation_flag << 3) |
519 ((!!is_last_header) << 2) |
520 ((!!is_end_of_slice) << 1) |
521 (0 << 0)); /* FIXME: ??? */
523 intel_batchbuffer_data(batch, insert_data, lenght_in_dws * 4);
524 ADVANCE_BCS_BATCH(batch);
527 static void gen6_mfc_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
529 struct i965_driver_data *i965 = i965_driver_data(ctx);
530 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
534 /*Encode common setup for MFC*/
535 dri_bo_unreference(mfc_context->post_deblocking_output.bo);
536 mfc_context->post_deblocking_output.bo = NULL;
538 dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
539 mfc_context->pre_deblocking_output.bo = NULL;
541 dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
542 mfc_context->uncompressed_picture_source.bo = NULL;
544 dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
545 mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
547 for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
548 if ( mfc_context->direct_mv_buffers[i].bo != NULL);
549 dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
550 mfc_context->direct_mv_buffers[i].bo = NULL;
553 for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
554 if (mfc_context->reference_surfaces[i].bo != NULL)
555 dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
556 mfc_context->reference_surfaces[i].bo = NULL;
559 dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
560 bo = dri_bo_alloc(i965->intel.bufmgr,
565 mfc_context->intra_row_store_scratch_buffer.bo = bo;
567 dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
568 bo = dri_bo_alloc(i965->intel.bufmgr,
573 mfc_context->macroblock_status_buffer.bo = bo;
575 dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
576 bo = dri_bo_alloc(i965->intel.bufmgr,
578 49152, /* 6 * 128 * 64 */
581 mfc_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
583 dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
584 bo = dri_bo_alloc(i965->intel.bufmgr,
586 12288, /* 1.5 * 128 * 64 */
589 mfc_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
591 dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo);
592 mfc_context->mfc_batchbuffer_surface.bo = NULL;
594 dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo);
595 mfc_context->aux_batchbuffer_surface.bo = NULL;
597 if (mfc_context->aux_batchbuffer)
598 intel_batchbuffer_free(mfc_context->aux_batchbuffer);
600 mfc_context->aux_batchbuffer = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD);
601 mfc_context->aux_batchbuffer_surface.bo = mfc_context->aux_batchbuffer->buffer;
602 dri_bo_reference(mfc_context->aux_batchbuffer_surface.bo);
603 mfc_context->aux_batchbuffer_surface.pitch = 16;
604 mfc_context->aux_batchbuffer_surface.num_blocks = mfc_context->aux_batchbuffer->size / 16;
605 mfc_context->aux_batchbuffer_surface.size_block = 16;
607 i965_gpe_context_init(ctx, &mfc_context->gpe_context);
610 static void gen6_mfc_avc_pipeline_header_programing(VADriverContextP ctx,
611 struct encode_state *encode_state,
612 struct intel_encoder_context *encoder_context,
613 struct intel_batchbuffer *slice_batch)
615 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
616 static int count = 0;
617 unsigned int rate_control_mode = encoder_context->rate_control_mode;
619 if (encode_state->packed_header_data[VAEncPackedHeaderH264_SPS]) {
620 VAEncPackedHeaderParameterBuffer *param = NULL;
621 unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[VAEncPackedHeaderH264_SPS]->buffer;
622 unsigned int length_in_bits;
624 assert(encode_state->packed_header_param[VAEncPackedHeaderH264_SPS]);
625 param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[VAEncPackedHeaderH264_SPS]->buffer;
626 length_in_bits = param->bit_length;
628 mfc_context->insert_object(ctx,
631 ALIGN(length_in_bits, 32) >> 5,
632 length_in_bits & 0x1f,
633 5, /* FIXME: check it */
636 !param->has_emulation_bytes,
640 if (encode_state->packed_header_data[VAEncPackedHeaderH264_PPS]) {
641 VAEncPackedHeaderParameterBuffer *param = NULL;
642 unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[VAEncPackedHeaderH264_PPS]->buffer;
643 unsigned int length_in_bits;
645 assert(encode_state->packed_header_param[VAEncPackedHeaderH264_PPS]);
646 param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[VAEncPackedHeaderH264_PPS]->buffer;
647 length_in_bits = param->bit_length;
649 mfc_context->insert_object(ctx,
652 ALIGN(length_in_bits, 32) >> 5,
653 length_in_bits & 0x1f,
654 5, /* FIXME: check it */
657 !param->has_emulation_bytes,
661 if ( (rate_control_mode == VA_RC_CBR) && encode_state->packed_header_data[VAEncPackedHeaderH264_SPS]) { // this is frist AU
662 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
664 unsigned char *sei_data = NULL;
665 int length_in_bits = build_avc_sei_buffering_period(mfc_context->vui_hrd.i_initial_cpb_removal_delay_length,
666 mfc_context->vui_hrd.i_initial_cpb_removal_delay, 0, &sei_data);
667 mfc_context->insert_object(ctx,
669 (unsigned int *)sei_data,
670 ALIGN(length_in_bits, 32) >> 5,
671 length_in_bits & 0x1f,
680 // SEI pic_timing header
681 if (rate_control_mode == VA_RC_CBR) {
682 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
683 unsigned char *sei_data = NULL;
684 int length_in_bits = build_avc_sei_pic_timing( mfc_context->vui_hrd.i_cpb_removal_delay_length,
685 mfc_context->vui_hrd.i_cpb_removal_delay * mfc_context->vui_hrd.i_frame_number,
686 mfc_context->vui_hrd.i_dpb_output_delay_length,
688 mfc_context->insert_object(ctx,
690 (unsigned int *)sei_data,
691 ALIGN(length_in_bits, 32) >> 5,
692 length_in_bits & 0x1f,
704 static void gen6_mfc_avc_pipeline_picture_programing( VADriverContextP ctx,
705 struct encode_state *encode_state,
706 struct intel_encoder_context *encoder_context)
708 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
710 mfc_context->pipe_mode_select(ctx, MFX_FORMAT_AVC, encoder_context);
711 mfc_context->set_surface_state(ctx, encoder_context);
712 mfc_context->ind_obj_base_addr_state(ctx, encoder_context);
713 gen6_mfc_pipe_buf_addr_state(ctx, encoder_context);
714 gen6_mfc_bsp_buf_base_addr_state(ctx, encoder_context);
715 mfc_context->avc_img_state(ctx, encode_state, encoder_context);
716 mfc_context->avc_qm_state(ctx, encoder_context);
717 mfc_context->avc_fqm_state(ctx, encoder_context);
718 gen6_mfc_avc_directmode_state(ctx, encoder_context);
719 gen6_mfc_avc_ref_idx_state(ctx, encoder_context);
723 gen6_mfc_free_avc_surface(void **data)
725 struct gen6_mfc_avc_surface_aux *avc_surface = *data;
730 dri_bo_unreference(avc_surface->dmv_top);
731 avc_surface->dmv_top = NULL;
732 dri_bo_unreference(avc_surface->dmv_bottom);
733 avc_surface->dmv_bottom = NULL;
740 gen6_mfc_bit_rate_control_context_init(struct encode_state *encode_state,
741 struct gen6_mfc_context *mfc_context)
743 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
745 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
746 int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
747 float fps = pSequenceParameter->time_scale * 0.5 / pSequenceParameter->num_units_in_tick ;
748 int inter_mb_size = pSequenceParameter->bits_per_second * 1.0 / (fps+4.0) / width_in_mbs / height_in_mbs;
749 int intra_mb_size = inter_mb_size * 5.0;
752 mfc_context->bit_rate_control_context[0].target_mb_size = intra_mb_size;
753 mfc_context->bit_rate_control_context[0].target_frame_size = intra_mb_size * width_in_mbs * height_in_mbs;
754 mfc_context->bit_rate_control_context[1].target_mb_size = inter_mb_size;
755 mfc_context->bit_rate_control_context[1].target_frame_size = inter_mb_size * width_in_mbs * height_in_mbs;
757 for(i = 0 ; i < 2; i++) {
758 mfc_context->bit_rate_control_context[i].QpPrimeY = 26;
759 mfc_context->bit_rate_control_context[i].MaxQpNegModifier = 6;
760 mfc_context->bit_rate_control_context[i].MaxQpPosModifier = 6;
761 mfc_context->bit_rate_control_context[i].GrowInit = 6;
762 mfc_context->bit_rate_control_context[i].GrowResistance = 4;
763 mfc_context->bit_rate_control_context[i].ShrinkInit = 6;
764 mfc_context->bit_rate_control_context[i].ShrinkResistance = 4;
766 mfc_context->bit_rate_control_context[i].Correct[0] = 8;
767 mfc_context->bit_rate_control_context[i].Correct[1] = 4;
768 mfc_context->bit_rate_control_context[i].Correct[2] = 2;
769 mfc_context->bit_rate_control_context[i].Correct[3] = 2;
770 mfc_context->bit_rate_control_context[i].Correct[4] = 4;
771 mfc_context->bit_rate_control_context[i].Correct[5] = 8;
774 mfc_context->bit_rate_control_context[0].TargetSizeInWord = (intra_mb_size + 16)/ 16;
775 mfc_context->bit_rate_control_context[1].TargetSizeInWord = (inter_mb_size + 16)/ 16;
777 mfc_context->bit_rate_control_context[0].MaxSizeInWord = mfc_context->bit_rate_control_context[0].TargetSizeInWord * 1.5;
778 mfc_context->bit_rate_control_context[1].MaxSizeInWord = mfc_context->bit_rate_control_context[1].TargetSizeInWord * 1.5;
781 static int gen6_mfc_bit_rate_control_context_update(struct encode_state *encode_state,
782 struct gen6_mfc_context *mfc_context,
783 int current_frame_size)
785 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
786 int control_index = 1 - (pSliceParameter->slice_type == SLICE_TYPE_I);
787 int oldQp = mfc_context->bit_rate_control_context[control_index].QpPrimeY;
790 printf("conrol_index = %d, start_qp = %d, result = %d, target = %d\n", control_index,
791 mfc_context->bit_rate_control_context[control_index].QpPrimeY, current_frame_size,
792 mfc_context->bit_rate_control_context[control_index].target_frame_size );
795 if ( current_frame_size > mfc_context->bit_rate_control_context[control_index].target_frame_size * 4.0 ) {
796 mfc_context->bit_rate_control_context[control_index].QpPrimeY += 4;
797 } else if ( current_frame_size > mfc_context->bit_rate_control_context[control_index].target_frame_size * 2.0 ) {
798 mfc_context->bit_rate_control_context[control_index].QpPrimeY += 3;
799 } else if ( current_frame_size > mfc_context->bit_rate_control_context[control_index].target_frame_size * 1.50 ) {
800 mfc_context->bit_rate_control_context[control_index].QpPrimeY += 2;
801 } else if ( current_frame_size > mfc_context->bit_rate_control_context[control_index].target_frame_size * 1.20 ) {
802 mfc_context->bit_rate_control_context[control_index].QpPrimeY ++;
803 } else if (current_frame_size < mfc_context->bit_rate_control_context[control_index].target_frame_size * 0.30 ) {
804 mfc_context->bit_rate_control_context[control_index].QpPrimeY -= 3;
805 } else if (current_frame_size < mfc_context->bit_rate_control_context[control_index].target_frame_size * 0.50 ) {
806 mfc_context->bit_rate_control_context[control_index].QpPrimeY -= 2;
807 } else if (current_frame_size < mfc_context->bit_rate_control_context[control_index].target_frame_size * 0.80 ) {
808 mfc_context->bit_rate_control_context[control_index].QpPrimeY --;
811 if ( mfc_context->bit_rate_control_context[control_index].QpPrimeY > 51)
812 mfc_context->bit_rate_control_context[control_index].QpPrimeY = 51;
813 if ( mfc_context->bit_rate_control_context[control_index].QpPrimeY < 1)
814 mfc_context->bit_rate_control_context[control_index].QpPrimeY = 1;
816 if ( mfc_context->bit_rate_control_context[control_index].QpPrimeY != oldQp)
823 gen6_mfc_hrd_context_init(struct encode_state *encode_state,
824 struct intel_encoder_context *encoder_context)
826 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
827 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
828 unsigned int rate_control_mode = encoder_context->rate_control_mode;
829 int target_bit_rate = pSequenceParameter->bits_per_second;
831 // current we only support CBR mode.
832 if (rate_control_mode == VA_RC_CBR) {
833 mfc_context->vui_hrd.i_bit_rate_value = target_bit_rate >> 10;
834 mfc_context->vui_hrd.i_cpb_size_value = (target_bit_rate * 8) >> 10;
835 mfc_context->vui_hrd.i_initial_cpb_removal_delay = mfc_context->vui_hrd.i_cpb_size_value * 0.5 * 1024 / target_bit_rate * 90000;
836 mfc_context->vui_hrd.i_cpb_removal_delay = 2;
837 mfc_context->vui_hrd.i_frame_number = 0;
839 mfc_context->vui_hrd.i_initial_cpb_removal_delay_length = 24;
840 mfc_context->vui_hrd.i_cpb_removal_delay_length = 24;
841 mfc_context->vui_hrd.i_dpb_output_delay_length = 24;
847 gen6_mfc_hrd_context_update(struct encode_state *encode_state,
848 struct gen6_mfc_context *mfc_context)
850 mfc_context->vui_hrd.i_frame_number++;
853 static VAStatus gen6_mfc_avc_prepare(VADriverContextP ctx,
854 struct encode_state *encode_state,
855 struct intel_encoder_context *encoder_context)
857 struct i965_driver_data *i965 = i965_driver_data(ctx);
858 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
859 struct object_surface *obj_surface;
860 struct object_buffer *obj_buffer;
861 struct gen6_mfc_avc_surface_aux* gen6_avc_surface;
863 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
864 unsigned int rate_control_mode = encoder_context->rate_control_mode;
865 VAStatus vaStatus = VA_STATUS_SUCCESS;
866 int i, j, enable_avc_ildb = 0;
867 VAEncSliceParameterBufferH264 *slice_param;
869 for (j = 0; j < encode_state->num_slice_params_ext && enable_avc_ildb == 0; j++) {
870 assert(encode_state->slice_params_ext && encode_state->slice_params_ext[j]->buffer);
871 slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[j]->buffer;
873 for (i = 0; i < encode_state->slice_params_ext[j]->num_elements; i++) {
874 assert((slice_param->slice_type == SLICE_TYPE_I) ||
875 (slice_param->slice_type == SLICE_TYPE_SI) ||
876 (slice_param->slice_type == SLICE_TYPE_P) ||
877 (slice_param->slice_type == SLICE_TYPE_SP) ||
878 (slice_param->slice_type == SLICE_TYPE_B));
880 if (slice_param->disable_deblocking_filter_idc != 1) {
889 /*Setup all the input&output object*/
891 /* Setup current frame and current direct mv buffer*/
892 obj_surface = SURFACE(pPicParameter->CurrPic.picture_id);
894 i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
896 if ( obj_surface->private_data == NULL) {
897 gen6_avc_surface = calloc(sizeof(struct gen6_mfc_avc_surface_aux), 1);
898 gen6_avc_surface->dmv_top =
899 dri_bo_alloc(i965->intel.bufmgr,
903 gen6_avc_surface->dmv_bottom =
904 dri_bo_alloc(i965->intel.bufmgr,
908 assert(gen6_avc_surface->dmv_top);
909 assert(gen6_avc_surface->dmv_bottom);
910 obj_surface->private_data = (void *)gen6_avc_surface;
911 obj_surface->free_private_data = (void *)gen6_mfc_free_avc_surface;
913 gen6_avc_surface = (struct gen6_mfc_avc_surface_aux*) obj_surface->private_data;
914 mfc_context->direct_mv_buffers[NUM_MFC_DMV_BUFFERS - 2].bo = gen6_avc_surface->dmv_top;
915 mfc_context->direct_mv_buffers[NUM_MFC_DMV_BUFFERS - 1].bo = gen6_avc_surface->dmv_bottom;
916 dri_bo_reference(gen6_avc_surface->dmv_top);
917 dri_bo_reference(gen6_avc_surface->dmv_bottom);
919 if (enable_avc_ildb) {
920 mfc_context->post_deblocking_output.bo = obj_surface->bo;
921 dri_bo_reference(mfc_context->post_deblocking_output.bo);
923 mfc_context->pre_deblocking_output.bo = obj_surface->bo;
924 dri_bo_reference(mfc_context->pre_deblocking_output.bo);
927 mfc_context->surface_state.width = obj_surface->orig_width;
928 mfc_context->surface_state.height = obj_surface->orig_height;
929 mfc_context->surface_state.w_pitch = obj_surface->width;
930 mfc_context->surface_state.h_pitch = obj_surface->height;
932 /* Setup reference frames and direct mv buffers*/
933 for(i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++) {
934 if ( pPicParameter->ReferenceFrames[i].picture_id != VA_INVALID_ID ) {
935 obj_surface = SURFACE(pPicParameter->ReferenceFrames[i].picture_id);
937 if (obj_surface->bo != NULL) {
938 mfc_context->reference_surfaces[i].bo = obj_surface->bo;
939 dri_bo_reference(obj_surface->bo);
941 /* Check DMV buffer */
942 if ( obj_surface->private_data == NULL) {
944 gen6_avc_surface = calloc(sizeof(struct gen6_mfc_avc_surface_aux), 1);
945 gen6_avc_surface->dmv_top =
946 dri_bo_alloc(i965->intel.bufmgr,
950 gen6_avc_surface->dmv_bottom =
951 dri_bo_alloc(i965->intel.bufmgr,
955 assert(gen6_avc_surface->dmv_top);
956 assert(gen6_avc_surface->dmv_bottom);
957 obj_surface->private_data = gen6_avc_surface;
958 obj_surface->free_private_data = gen6_mfc_free_avc_surface;
961 gen6_avc_surface = (struct gen6_mfc_avc_surface_aux*) obj_surface->private_data;
962 /* Setup DMV buffer */
963 mfc_context->direct_mv_buffers[i*2].bo = gen6_avc_surface->dmv_top;
964 mfc_context->direct_mv_buffers[i*2+1].bo = gen6_avc_surface->dmv_bottom;
965 dri_bo_reference(gen6_avc_surface->dmv_top);
966 dri_bo_reference(gen6_avc_surface->dmv_bottom);
972 obj_surface = SURFACE(encoder_context->input_yuv_surface);
973 assert(obj_surface && obj_surface->bo);
974 mfc_context->uncompressed_picture_source.bo = obj_surface->bo;
975 dri_bo_reference(mfc_context->uncompressed_picture_source.bo);
977 obj_buffer = BUFFER (pPicParameter->coded_buf); /* FIXME: fix this later */
978 bo = obj_buffer->buffer_store->bo;
980 mfc_context->mfc_indirect_pak_bse_object.bo = bo;
981 mfc_context->mfc_indirect_pak_bse_object.offset = ALIGN(sizeof(VACodedBufferSegment), 64);
982 mfc_context->mfc_indirect_pak_bse_object.end_offset = ALIGN (obj_buffer->size_element - 0x1000, 0x1000);
983 dri_bo_reference(mfc_context->mfc_indirect_pak_bse_object.bo);
985 /*Programing bit rate control */
986 if ( mfc_context->bit_rate_control_context[0].MaxSizeInWord == 0 )
987 gen6_mfc_bit_rate_control_context_init(encode_state, mfc_context);
989 /*Programing HRD control */
990 if ( (rate_control_mode == VA_RC_CBR) && (mfc_context->vui_hrd.i_cpb_size_value == 0) )
991 gen6_mfc_hrd_context_init(encode_state, encoder_context);
996 static VAStatus gen6_mfc_run(VADriverContextP ctx,
997 struct encode_state *encode_state,
998 struct intel_encoder_context *encoder_context)
1000 struct intel_batchbuffer *batch = encoder_context->base.batch;
1002 intel_batchbuffer_flush(batch); //run the pipeline
1004 return VA_STATUS_SUCCESS;
1008 gen6_mfc_stop(VADriverContextP ctx,
1009 struct encode_state *encode_state,
1010 struct intel_encoder_context *encoder_context,
1011 int *encoded_bits_size)
1013 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1014 unsigned int *status_mem;
1015 unsigned int buffer_size_bits = 0;
1016 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
1017 int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
1020 dri_bo_map(mfc_context->macroblock_status_buffer.bo, 1);
1021 status_mem = (unsigned int *)mfc_context->macroblock_status_buffer.bo->virtual;
1022 //Detecting encoder buffer size and bit rate control result
1023 for(i = 0; i < width_in_mbs * height_in_mbs; i++) {
1024 unsigned short current_mb = status_mem[1] >> 16;
1025 buffer_size_bits += current_mb;
1028 dri_bo_unmap(mfc_context->macroblock_status_buffer.bo);
1030 *encoded_bits_size = buffer_size_bits;
1031 if ( buffer_size_bits == 0) { // FIXME: we can't get info in IVB.
1032 struct i965_driver_data *i965 = i965_driver_data(ctx);
1033 struct object_buffer *obj_buffer;
1034 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
1035 obj_buffer = BUFFER (pPicParameter->coded_buf);
1036 dri_bo_map(obj_buffer->buffer_store->bo, 1);
1037 unsigned char *coded_mem = (unsigned char *)(obj_buffer->buffer_store->bo->virtual) + ALIGN(sizeof(VACodedBufferSegment), 64);
1038 for(i = 0; i < obj_buffer->size_element - ALIGN(sizeof(VACodedBufferSegment), 64) - 3 - 0x1000; i++) {
1039 if (!coded_mem[i] &&
1040 !coded_mem[i + 1] &&
1041 !coded_mem[i + 2] &&
1042 !coded_mem[i + 3] &&
1046 dri_bo_unmap(obj_buffer->buffer_store->bo);
1047 *encoded_bits_size = i*8;
1050 return VA_STATUS_SUCCESS;
1056 gen6_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb, int qp,unsigned int *msg,
1057 struct intel_encoder_context *encoder_context,
1058 unsigned char target_mb_size, unsigned char max_mb_size,
1059 struct intel_batchbuffer *batch)
1061 int len_in_dwords = 11;
1064 batch = encoder_context->base.batch;
1066 BEGIN_BCS_BATCH(batch, len_in_dwords);
1068 OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
1069 OUT_BCS_BATCH(batch, 0);
1070 OUT_BCS_BATCH(batch, 0);
1071 OUT_BCS_BATCH(batch,
1072 (0 << 24) | /* PackedMvNum, Debug*/
1073 (0 << 20) | /* No motion vector */
1074 (1 << 19) | /* CbpDcY */
1075 (1 << 18) | /* CbpDcU */
1076 (1 << 17) | /* CbpDcV */
1077 (msg[0] & 0xFFFF) );
1079 OUT_BCS_BATCH(batch, (0xFFFF << 16) | (y << 8) | x); /* Code Block Pattern for Y*/
1080 OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */
1081 OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp); /* Last MB */
1083 /*Stuff for Intra MB*/
1084 OUT_BCS_BATCH(batch, msg[1]); /* We using Intra16x16 no 4x4 predmode*/
1085 OUT_BCS_BATCH(batch, msg[2]);
1086 OUT_BCS_BATCH(batch, msg[3]&0xFC);
1088 /*MaxSizeInWord and TargetSzieInWord*/
1089 OUT_BCS_BATCH(batch, (max_mb_size << 24) |
1090 (target_mb_size << 16) );
1092 ADVANCE_BCS_BATCH(batch);
1094 return len_in_dwords;
1098 gen6_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, int qp,
1099 unsigned int *msg, unsigned int offset,
1100 struct intel_encoder_context *encoder_context,
1101 unsigned char target_mb_size,unsigned char max_mb_size, int slice_type,
1102 struct intel_batchbuffer *batch)
1104 int len_in_dwords = 11;
1107 batch = encoder_context->base.batch;
1109 BEGIN_BCS_BATCH(batch, len_in_dwords);
1111 OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
1113 OUT_BCS_BATCH(batch, msg[2]); /* 32 MV*/
1114 OUT_BCS_BATCH(batch, offset);
1116 OUT_BCS_BATCH(batch, msg[0]);
1118 OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x); /* Code Block Pattern for Y*/
1119 OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */
1121 if ( slice_type == SLICE_TYPE_B) {
1122 OUT_BCS_BATCH(batch, (0xF<<28) | (end_mb << 26) | qp); /* Last MB */
1124 OUT_BCS_BATCH(batch, (end_mb << 26) | qp); /* Last MB */
1127 OUT_BCS_BATCH(batch, (end_mb << 26) | qp); /* Last MB */
1131 /*Stuff for Inter MB*/
1132 OUT_BCS_BATCH(batch, msg[1]);
1133 OUT_BCS_BATCH(batch, 0x0);
1134 OUT_BCS_BATCH(batch, 0x0);
1136 /*MaxSizeInWord and TargetSzieInWord*/
1137 OUT_BCS_BATCH(batch, (max_mb_size << 24) |
1138 (target_mb_size << 16) );
1140 ADVANCE_BCS_BATCH(batch);
1142 return len_in_dwords;
1146 gen6_mfc_avc_pipeline_slice_programing(VADriverContextP ctx,
1147 struct encode_state *encode_state,
1148 struct intel_encoder_context *encoder_context,
1150 struct intel_batchbuffer *slice_batch)
1152 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1153 struct gen6_vme_context *vme_context = encoder_context->vme_context;
1154 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
1155 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
1156 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
1157 unsigned int *msg = NULL, offset = 0;
1158 int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
1159 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
1160 int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
1161 int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs);
1163 int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta;
1164 unsigned int rate_control_mode = encoder_context->rate_control_mode;
1165 unsigned char *slice_header = NULL;
1166 int slice_header_length_in_bits = 0;
1167 unsigned int tail_data[] = { 0x0, 0x0 };
1169 gen6_mfc_avc_slice_state(ctx,
1172 encode_state, encoder_context,
1173 (rate_control_mode == VA_RC_CBR), qp, slice_batch);
1175 if ( slice_index == 0)
1176 gen6_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch);
1178 slice_header_length_in_bits = build_avc_slice_header(pSequenceParameter, pPicParameter, pSliceParameter, &slice_header);
1181 mfc_context->insert_object(ctx, encoder_context,
1182 (unsigned int *)slice_header, ALIGN(slice_header_length_in_bits, 32) >> 5, slice_header_length_in_bits & 0x1f,
1183 5, /* first 5 bytes are start code + nal unit type */
1184 1, 0, 1, slice_batch);
1186 if ( rate_control_mode == VA_RC_CBR) {
1187 qp = mfc_context->bit_rate_control_context[1-is_intra].QpPrimeY;
1190 dri_bo_map(vme_context->vme_output.bo , 1);
1191 msg = (unsigned int *)vme_context->vme_output.bo->virtual;
1194 msg += pSliceParameter->macroblock_address * INTRA_VME_OUTPUT_IN_DWS;
1196 msg += pSliceParameter->macroblock_address * INTER_VME_OUTPUT_IN_DWS;
1197 msg += 32; /* the first 32 DWs are MVs */
1198 offset = pSliceParameter->macroblock_address * INTER_VME_OUTPUT_IN_BYTES;
1201 for (i = pSliceParameter->macroblock_address;
1202 i < pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks; i++) {
1203 int last_mb = (i == (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks - 1) );
1204 x = i % width_in_mbs;
1205 y = i / width_in_mbs;
1209 gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch);
1210 msg += INTRA_VME_OUTPUT_IN_DWS;
1212 if (msg[0] & INTRA_MB_FLAG_MASK) {
1213 gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch);
1215 gen6_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, msg, offset, encoder_context, 0, 0, pSliceParameter->slice_type, slice_batch);
1218 msg += INTER_VME_OUTPUT_IN_DWS;
1219 offset += INTER_VME_OUTPUT_IN_BYTES;
1223 dri_bo_unmap(vme_context->vme_output.bo);
1226 mfc_context->insert_object(ctx, encoder_context,
1228 2, 1, 1, 0, slice_batch);
1230 mfc_context->insert_object(ctx, encoder_context,
1232 1, 1, 1, 0, slice_batch);
1240 gen6_mfc_avc_software_batchbuffer(VADriverContextP ctx,
1241 struct encode_state *encode_state,
1242 struct intel_encoder_context *encoder_context)
1244 struct i965_driver_data *i965 = i965_driver_data(ctx);
1245 struct intel_batchbuffer *batch = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD);
1246 dri_bo *batch_bo = batch->buffer;
1249 for (i = 0; i < encode_state->num_slice_params_ext; i++) {
1250 gen6_mfc_avc_pipeline_slice_programing(ctx, encode_state, encoder_context, i, batch);
1253 intel_batchbuffer_align(batch, 8);
1255 BEGIN_BCS_BATCH(batch, 2);
1256 OUT_BCS_BATCH(batch, 0);
1257 OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_END);
1258 ADVANCE_BCS_BATCH(batch);
1260 dri_bo_reference(batch_bo);
1261 intel_batchbuffer_free(batch);
1269 gen6_mfc_batchbuffer_surfaces_input(VADriverContextP ctx,
1270 struct encode_state *encode_state,
1271 struct intel_encoder_context *encoder_context)
1274 struct gen6_vme_context *vme_context = encoder_context->vme_context;
1275 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1277 assert(vme_context->vme_output.bo);
1278 mfc_context->buffer_suface_setup(ctx,
1279 &mfc_context->gpe_context,
1280 &vme_context->vme_output,
1281 BINDING_TABLE_OFFSET(BIND_IDX_VME_OUTPUT),
1282 SURFACE_STATE_OFFSET(BIND_IDX_VME_OUTPUT));
1283 assert(mfc_context->aux_batchbuffer_surface.bo);
1284 mfc_context->buffer_suface_setup(ctx,
1285 &mfc_context->gpe_context,
1286 &mfc_context->aux_batchbuffer_surface,
1287 BINDING_TABLE_OFFSET(BIND_IDX_MFC_SLICE_HEADER),
1288 SURFACE_STATE_OFFSET(BIND_IDX_MFC_SLICE_HEADER));
1292 gen6_mfc_batchbuffer_surfaces_output(VADriverContextP ctx,
1293 struct encode_state *encode_state,
1294 struct intel_encoder_context *encoder_context)
1297 struct i965_driver_data *i965 = i965_driver_data(ctx);
1298 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1299 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
1300 int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
1301 int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
1302 mfc_context->mfc_batchbuffer_surface.num_blocks = width_in_mbs * height_in_mbs + encode_state->num_slice_params_ext * 8 + 1;
1303 mfc_context->mfc_batchbuffer_surface.size_block = 16 * CMD_LEN_IN_OWORD; /* 3 OWORDs */
1304 mfc_context->mfc_batchbuffer_surface.pitch = 16;
1305 mfc_context->mfc_batchbuffer_surface.bo = dri_bo_alloc(i965->intel.bufmgr,
1307 mfc_context->mfc_batchbuffer_surface.num_blocks * mfc_context->mfc_batchbuffer_surface.size_block,
1309 mfc_context->buffer_suface_setup(ctx,
1310 &mfc_context->gpe_context,
1311 &mfc_context->mfc_batchbuffer_surface,
1312 BINDING_TABLE_OFFSET(BIND_IDX_MFC_BATCHBUFFER),
1313 SURFACE_STATE_OFFSET(BIND_IDX_MFC_BATCHBUFFER));
1317 gen6_mfc_batchbuffer_surfaces_setup(VADriverContextP ctx,
1318 struct encode_state *encode_state,
1319 struct intel_encoder_context *encoder_context)
1321 gen6_mfc_batchbuffer_surfaces_input(ctx, encode_state, encoder_context);
1322 gen6_mfc_batchbuffer_surfaces_output(ctx, encode_state, encoder_context);
1326 gen6_mfc_batchbuffer_idrt_setup(VADriverContextP ctx,
1327 struct encode_state *encode_state,
1328 struct intel_encoder_context *encoder_context)
1330 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1331 struct gen6_interface_descriptor_data *desc;
1335 bo = mfc_context->gpe_context.idrt.bo;
1337 assert(bo->virtual);
1340 for (i = 0; i < mfc_context->gpe_context.num_kernels; i++) {
1341 struct i965_kernel *kernel;
1343 kernel = &mfc_context->gpe_context.kernels[i];
1344 assert(sizeof(*desc) == 32);
1346 /*Setup the descritor table*/
1347 memset(desc, 0, sizeof(*desc));
1348 desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6);
1349 desc->desc2.sampler_count = 0;
1350 desc->desc2.sampler_state_pointer = 0;
1351 desc->desc3.binding_table_entry_count = 2;
1352 desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5);
1353 desc->desc4.constant_urb_entry_read_offset = 0;
1354 desc->desc4.constant_urb_entry_read_length = 4;
1357 dri_bo_emit_reloc(bo,
1358 I915_GEM_DOMAIN_INSTRUCTION, 0,
1360 i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0),
1369 gen6_mfc_batchbuffer_constant_setup(VADriverContextP ctx,
1370 struct encode_state *encode_state,
1371 struct intel_encoder_context *encoder_context)
1373 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1379 gen6_mfc_batchbuffer_emit_object_command(struct intel_batchbuffer *batch,
1382 int batchbuffer_offset,
1394 BEGIN_BATCH(batch, 12);
1396 OUT_BATCH(batch, CMD_MEDIA_OBJECT | (12 - 2));
1397 OUT_BATCH(batch, index);
1398 OUT_BATCH(batch, 0);
1399 OUT_BATCH(batch, 0);
1400 OUT_BATCH(batch, 0);
1401 OUT_BATCH(batch, 0);
1404 OUT_BATCH(batch, head_offset);
1405 OUT_BATCH(batch, batchbuffer_offset);
1410 number_mb_cmds << 16 |
1421 ADVANCE_BATCH(batch);
1425 gen6_mfc_avc_batchbuffer_slice_command(VADriverContextP ctx,
1426 struct intel_encoder_context *encoder_context,
1427 VAEncSliceParameterBufferH264 *slice_param,
1429 unsigned short head_size,
1430 unsigned short tail_size,
1431 int batchbuffer_offset,
1435 struct intel_batchbuffer *batch = encoder_context->base.batch;
1436 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1437 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
1438 int total_mbs = slice_param->num_macroblocks;
1439 int number_mb_cmds = 128;
1440 int starting_mb = 0;
1441 int last_object = 0;
1442 int first_object = 1;
1445 int index = (slice_param->slice_type == SLICE_TYPE_I) ? MFC_BATCHBUFFER_AVC_INTRA : MFC_BATCHBUFFER_AVC_INTER;
1447 for (i = 0; i < total_mbs / number_mb_cmds; i++) {
1448 last_object = (total_mbs - starting_mb) == number_mb_cmds;
1449 mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs;
1450 mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs;
1451 assert(mb_x <= 255 && mb_y <= 255);
1453 starting_mb += number_mb_cmds;
1455 gen6_mfc_batchbuffer_emit_object_command(batch,
1471 head_offset += head_size;
1472 batchbuffer_offset += head_size;
1476 head_offset += tail_size;
1477 batchbuffer_offset += tail_size;
1480 batchbuffer_offset += number_mb_cmds * CMD_LEN_IN_OWORD;
1487 number_mb_cmds = total_mbs % number_mb_cmds;
1488 mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs;
1489 mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs;
1490 assert(mb_x <= 255 && mb_y <= 255);
1491 starting_mb += number_mb_cmds;
1493 gen6_mfc_batchbuffer_emit_object_command(batch,
1511 * return size in Owords (16bytes)
1514 gen6_mfc_avc_batchbuffer_slice(VADriverContextP ctx,
1515 struct encode_state *encode_state,
1516 struct intel_encoder_context *encoder_context,
1518 int batchbuffer_offset)
1520 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1521 struct intel_batchbuffer *slice_batch = mfc_context->aux_batchbuffer;
1522 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
1523 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
1524 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
1525 int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
1526 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
1527 int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
1528 int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs);
1529 int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta;
1530 unsigned int rate_control_mode = encoder_context->rate_control_mode;
1531 unsigned char *slice_header = NULL;
1532 int slice_header_length_in_bits = 0;
1533 unsigned int tail_data[] = { 0x0, 0x0 };
1535 int old_used = intel_batchbuffer_used_size(slice_batch), used;
1536 unsigned short head_size, tail_size;
1538 head_offset = old_used / 16;
1539 gen6_mfc_avc_slice_state(ctx,
1544 (rate_control_mode == VA_RC_CBR),
1548 if (slice_index == 0)
1549 gen6_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch);
1551 slice_header_length_in_bits = build_avc_slice_header(pSequenceParameter, pPicParameter, pSliceParameter, &slice_header);
1554 mfc_context->insert_object(ctx,
1556 (unsigned int *)slice_header,
1557 ALIGN(slice_header_length_in_bits, 32) >> 5,
1558 slice_header_length_in_bits & 0x1f,
1559 5, /* first 5 bytes are start code + nal unit type */
1566 intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */
1567 used = intel_batchbuffer_used_size(slice_batch);
1568 head_size = (used - old_used) / 16;
1571 if (rate_control_mode == VA_RC_CBR) {
1572 qp = mfc_context->bit_rate_control_context[1 - is_intra].QpPrimeY;
1577 mfc_context->insert_object(ctx,
1588 mfc_context->insert_object(ctx,
1600 intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */
1601 used = intel_batchbuffer_used_size(slice_batch);
1602 tail_size = (used - old_used) / 16;
1605 gen6_mfc_avc_batchbuffer_slice_command(ctx,
1615 return head_size + tail_size + pSliceParameter->num_macroblocks * CMD_LEN_IN_OWORD;
1619 gen6_mfc_avc_batchbuffer_pipeline(VADriverContextP ctx,
1620 struct encode_state *encode_state,
1621 struct intel_encoder_context *encoder_context)
1623 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1624 struct intel_batchbuffer *batch = encoder_context->base.batch;
1625 int i, size, offset = 0;
1626 intel_batchbuffer_start_atomic(batch, 0x4000);
1627 gen6_gpe_pipeline_setup(ctx, &mfc_context->gpe_context, batch);
1629 for ( i = 0; i < encode_state->num_slice_params_ext; i++) {
1630 size = gen6_mfc_avc_batchbuffer_slice(ctx, encode_state, encoder_context, i, offset);
1634 intel_batchbuffer_end_atomic(batch);
1635 intel_batchbuffer_flush(batch);
1639 gen6_mfc_build_avc_batchbuffer(VADriverContextP ctx,
1640 struct encode_state *encode_state,
1641 struct intel_encoder_context *encoder_context)
1643 gen6_mfc_batchbuffer_surfaces_setup(ctx, encode_state, encoder_context);
1644 gen6_mfc_batchbuffer_idrt_setup(ctx, encode_state, encoder_context);
1645 gen6_mfc_batchbuffer_constant_setup(ctx, encode_state, encoder_context);
1646 gen6_mfc_avc_batchbuffer_pipeline(ctx, encode_state, encoder_context);
1650 gen6_mfc_avc_hardware_batchbuffer(VADriverContextP ctx,
1651 struct encode_state *encode_state,
1652 struct intel_encoder_context *encoder_context)
1654 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1656 gen6_mfc_build_avc_batchbuffer(ctx, encode_state, encoder_context);
1657 dri_bo_reference(mfc_context->mfc_batchbuffer_surface.bo);
1659 return mfc_context->mfc_batchbuffer_surface.bo;
1664 int interlace_check(VADriverContextP ctx,
1665 struct encode_state *encode_state,
1666 struct intel_encoder_context *encoder_context) {
1667 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1668 VAEncSliceParameterBufferH264 *pSliceParameter;
1671 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
1672 int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
1674 for (i = 0; i < encode_state->num_slice_params_ext; i++) {
1675 pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[i]->buffer;
1676 mbCount += pSliceParameter->num_macroblocks;
1679 if ( mbCount == ( width_in_mbs * height_in_mbs ) )
1687 gen6_mfc_avc_pipeline_programing(VADriverContextP ctx,
1688 struct encode_state *encode_state,
1689 struct intel_encoder_context *encoder_context)
1691 struct intel_batchbuffer *batch = encoder_context->base.batch;
1692 dri_bo *slice_batch_bo;
1694 if ( interlace_check(ctx, encode_state, encoder_context) ) {
1695 fprintf(stderr, "Current VA driver don't support interlace mode!\n");
1701 slice_batch_bo = gen6_mfc_avc_software_batchbuffer(ctx, encode_state, encoder_context);
1703 slice_batch_bo = gen6_mfc_avc_hardware_batchbuffer(ctx, encode_state, encoder_context);
1707 intel_batchbuffer_start_atomic_bcs(batch, 0x4000);
1708 intel_batchbuffer_emit_mi_flush(batch);
1710 // picture level programing
1711 gen6_mfc_avc_pipeline_picture_programing(ctx, encode_state, encoder_context);
1713 BEGIN_BCS_BATCH(batch, 2);
1714 OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8));
1715 OUT_BCS_RELOC(batch,
1717 I915_GEM_DOMAIN_COMMAND, 0,
1719 ADVANCE_BCS_BATCH(batch);
1722 intel_batchbuffer_end_atomic(batch);
1724 dri_bo_unreference(slice_batch_bo);
1728 gen6_mfc_avc_encode_picture(VADriverContextP ctx,
1729 struct encode_state *encode_state,
1730 struct intel_encoder_context *encoder_context)
1732 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1733 unsigned int rate_control_mode = encoder_context->rate_control_mode;
1734 int MAX_CBR_INTERATE = 4;
1735 int current_frame_bits_size;
1738 for(i = 0; i < MAX_CBR_INTERATE; i++) {
1739 gen6_mfc_init(ctx, encoder_context);
1740 gen6_mfc_avc_prepare(ctx, encode_state, encoder_context);
1741 /*Programing bcs pipeline*/
1742 gen6_mfc_avc_pipeline_programing(ctx, encode_state, encoder_context); //filling the pipeline
1743 gen6_mfc_run(ctx, encode_state, encoder_context);
1744 if ( rate_control_mode == VA_RC_CBR) {
1745 gen6_mfc_stop(ctx, encode_state, encoder_context, ¤t_frame_bits_size);
1746 //gen6_mfc_hrd_context_check(encode_state, mfc_context);
1747 if ( gen6_mfc_bit_rate_control_context_update( encode_state, mfc_context, current_frame_bits_size) ) {
1748 gen6_mfc_hrd_context_update(encode_state, mfc_context);
1756 return VA_STATUS_SUCCESS;
1760 gen6_mfc_pipeline(VADriverContextP ctx,
1762 struct encode_state *encode_state,
1763 struct intel_encoder_context *encoder_context)
1768 case VAProfileH264Baseline:
1769 case VAProfileH264Main:
1770 case VAProfileH264High:
1771 vaStatus = gen6_mfc_avc_encode_picture(ctx, encode_state, encoder_context);
1774 /* FIXME: add for other profile */
1776 vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
1784 gen6_mfc_context_destroy(void *context)
1786 struct gen6_mfc_context *mfc_context = context;
1789 dri_bo_unreference(mfc_context->post_deblocking_output.bo);
1790 mfc_context->post_deblocking_output.bo = NULL;
1792 dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
1793 mfc_context->pre_deblocking_output.bo = NULL;
1795 dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
1796 mfc_context->uncompressed_picture_source.bo = NULL;
1798 dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
1799 mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
1801 for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
1802 dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
1803 mfc_context->direct_mv_buffers[i].bo = NULL;
1806 dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
1807 mfc_context->intra_row_store_scratch_buffer.bo = NULL;
1809 dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
1810 mfc_context->macroblock_status_buffer.bo = NULL;
1812 dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
1813 mfc_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
1815 dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
1816 mfc_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
1819 for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
1820 dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
1821 mfc_context->reference_surfaces[i].bo = NULL;
1824 i965_gpe_context_destroy(&mfc_context->gpe_context);
1826 dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo);
1827 mfc_context->mfc_batchbuffer_surface.bo = NULL;
1829 dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo);
1830 mfc_context->aux_batchbuffer_surface.bo = NULL;
1832 if (mfc_context->aux_batchbuffer)
1833 intel_batchbuffer_free(mfc_context->aux_batchbuffer);
1835 mfc_context->aux_batchbuffer = NULL;
1840 Bool gen6_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
1842 struct gen6_mfc_context *mfc_context = calloc(1, sizeof(struct gen6_mfc_context));
1844 mfc_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6;
1846 mfc_context->gpe_context.idrt.max_entries = MAX_GPE_KERNELS;
1847 mfc_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data);
1849 mfc_context->gpe_context.curbe.length = 32 * 4;
1851 mfc_context->gpe_context.vfe_state.max_num_threads = 60 - 1;
1852 mfc_context->gpe_context.vfe_state.num_urb_entries = 16;
1853 mfc_context->gpe_context.vfe_state.gpgpu_mode = 0;
1854 mfc_context->gpe_context.vfe_state.urb_entry_size = 59 - 1;
1855 mfc_context->gpe_context.vfe_state.curbe_allocation_size = 37 - 1;
1857 i965_gpe_load_kernels(ctx,
1858 &mfc_context->gpe_context,
1862 mfc_context->pipe_mode_select = gen6_mfc_pipe_mode_select;
1863 mfc_context->set_surface_state = gen6_mfc_surface_state;
1864 mfc_context->ind_obj_base_addr_state = gen6_mfc_ind_obj_base_addr_state;
1865 mfc_context->avc_img_state = gen6_mfc_avc_img_state;
1866 mfc_context->avc_qm_state = gen6_mfc_avc_qm_state;
1867 mfc_context->avc_fqm_state = gen6_mfc_avc_fqm_state;
1868 mfc_context->insert_object = gen6_mfc_avc_insert_object;
1869 mfc_context->buffer_suface_setup = i965_gpe_buffer_suface_setup;
1871 encoder_context->mfc_context = mfc_context;
1872 encoder_context->mfc_context_destroy = gen6_mfc_context_destroy;
1873 encoder_context->mfc_pipeline = gen6_mfc_pipeline;