src/gen6_mfc.c

   1 /*
   2  * Copyright © 2010-2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Zhou Chang <chang.zhou@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <assert.h>
  33 #include <math.h>
  34
  35 #include "intel_batchbuffer.h"
  36 #include "i965_defines.h"
  37 #include "i965_structs.h"
  38 #include "i965_drv_video.h"
  39 #include "i965_encoder.h"
  40 #include "i965_encoder_utils.h"
  41 #include "gen6_mfc.h"
  42 #include "gen6_vme.h"
  43 #include "intel_media.h"
  44
  45 static const uint32_t gen6_mfc_batchbuffer_avc_intra[][4] = {
  46 #include "shaders/utils/mfc_batchbuffer_avc_intra.g6b"
  47 };
  48
  49 static const uint32_t gen6_mfc_batchbuffer_avc_inter[][4] = {
  50 #include "shaders/utils/mfc_batchbuffer_avc_inter.g6b"
  51 };
  52
  53 static struct i965_kernel gen6_mfc_kernels[] = {
  54     {
  55         "MFC AVC INTRA BATCHBUFFER ",
  56         MFC_BATCHBUFFER_AVC_INTRA,
  57         gen6_mfc_batchbuffer_avc_intra,
  58         sizeof(gen6_mfc_batchbuffer_avc_intra),
  59         NULL
  60     },
  61
  62     {
  63         "MFC AVC INTER BATCHBUFFER ",
  64         MFC_BATCHBUFFER_AVC_INTER,
  65         gen6_mfc_batchbuffer_avc_inter,
  66         sizeof(gen6_mfc_batchbuffer_avc_inter),
  67         NULL
  68     },
  69 };
  70
  71 static void
  72 gen6_mfc_pipe_mode_select(VADriverContextP ctx,
  73                           int standard_select,
  74                           struct intel_encoder_context *encoder_context)
  75 {
  76     struct intel_batchbuffer *batch = encoder_context->base.batch;
  77     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
  78
  79     assert(standard_select == MFX_FORMAT_AVC);
  80
  81     BEGIN_BCS_BATCH(batch, 4);
  82
  83     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (4 - 2));
  84     OUT_BCS_BATCH(batch,
  85                   (1 << 10) | /* disable Stream-Out , advanced QP/bitrate control need enable it*/
  86                   ((!!mfc_context->post_deblocking_output.bo) << 9)  | /* Post Deblocking Output */
  87                   ((!!mfc_context->pre_deblocking_output.bo) << 8)  | /* Pre Deblocking Output */
  88                   (0 << 7)  | /* disable TLB prefectch */
  89                   (0 << 5)  | /* not in stitch mode */
  90                   (1 << 4)  | /* encoding mode */
  91                   (2 << 0));  /* Standard Select: AVC */
  92     OUT_BCS_BATCH(batch,
  93                   (0 << 20) | /* round flag in PB slice */
  94                   (0 << 19) | /* round flag in Intra8x8 */
  95                   (0 << 7)  | /* expand NOA bus flag */
  96                   (1 << 6)  | /* must be 1 */
  97                   (0 << 5)  | /* disable clock gating for NOA */
  98                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
  99                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
 100                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
 101                   (0 << 1)  | /* AVC long field motion vector */
 102                   (0 << 0));  /* always calculate AVC ILDB boundary strength */
 103     OUT_BCS_BATCH(batch, 0);
 104
 105     ADVANCE_BCS_BATCH(batch);
 106 }
 107
 108 static void
 109 gen6_mfc_surface_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 110 {
 111     struct intel_batchbuffer *batch = encoder_context->base.batch;
 112     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 113
 114     BEGIN_BCS_BATCH(batch, 6);
 115
 116     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
 117     OUT_BCS_BATCH(batch, 0);
 118     OUT_BCS_BATCH(batch,
 119                   ((mfc_context->surface_state.height - 1) << 19) |
 120                   ((mfc_context->surface_state.width - 1) << 6));
 121     OUT_BCS_BATCH(batch,
 122                   (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
 123                   (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
 124                   (0 << 22) | /* surface object control state, FIXME??? */
 125                   ((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */
 126                   (0 << 2)  | /* must be 0 for interleave U/V */
 127                   (1 << 1)  | /* must be y-tiled */
 128                   (I965_TILEWALK_YMAJOR << 0));                         /* tile walk, TILEWALK_YMAJOR */
 129     OUT_BCS_BATCH(batch,
 130                   (0 << 16) |                                                           /* must be 0 for interleave U/V */
 131                   (mfc_context->surface_state.h_pitch));                /* y offset for U(cb) */
 132     OUT_BCS_BATCH(batch, 0);
 133     ADVANCE_BCS_BATCH(batch);
 134 }
 135
 136 void
 137 gen6_mfc_pipe_buf_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 138 {
 139     struct intel_batchbuffer *batch = encoder_context->base.batch;
 140     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 141     int i;
 142
 143     BEGIN_BCS_BATCH(batch, 24);
 144
 145     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
 146
 147     if (mfc_context->pre_deblocking_output.bo)
 148         OUT_BCS_RELOC(batch, mfc_context->pre_deblocking_output.bo,
 149                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 150                       0);
 151     else
 152         OUT_BCS_BATCH(batch, 0);                                                                                        /* pre output addr   */
 153
 154     if (mfc_context->post_deblocking_output.bo)
 155         OUT_BCS_RELOC(batch, mfc_context->post_deblocking_output.bo,
 156                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 157                       0);                                                                                       /* post output addr  */
 158     else
 159         OUT_BCS_BATCH(batch, 0);
 160
 161     OUT_BCS_RELOC(batch, mfc_context->uncompressed_picture_source.bo,
 162                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 163                   0);                                                                                   /* uncompressed data */
 164     OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
 165                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 166                   0);                                                                                   /* StreamOut data*/
 167     OUT_BCS_RELOC(batch, mfc_context->intra_row_store_scratch_buffer.bo,
 168                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 169                   0);
 170     OUT_BCS_RELOC(batch, mfc_context->deblocking_filter_row_store_scratch_buffer.bo,
 171                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 172                   0);
 173     /* 7..22 Reference pictures*/
 174     for (i = 0; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) {
 175         if ( mfc_context->reference_surfaces[i].bo != NULL) {
 176             OUT_BCS_RELOC(batch, mfc_context->reference_surfaces[i].bo,
 177                           I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 178                           0);
 179         } else {
 180             OUT_BCS_BATCH(batch, 0);
 181         }
 182     }
 183     OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
 184                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 185                   0);                                                                                   /* Macroblock status buffer*/
 186
 187     ADVANCE_BCS_BATCH(batch);
 188 }
 189
 190 static void
 191 gen6_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 192 {
 193     struct intel_batchbuffer *batch = encoder_context->base.batch;
 194     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 195     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 196
 197     BEGIN_BCS_BATCH(batch, 11);
 198
 199     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
 200     OUT_BCS_BATCH(batch, 0);
 201     OUT_BCS_BATCH(batch, 0);
 202     /* MFX Indirect MV Object Base Address */
 203     OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 204     OUT_BCS_BATCH(batch, 0);
 205     OUT_BCS_BATCH(batch, 0);
 206     OUT_BCS_BATCH(batch, 0);
 207     OUT_BCS_BATCH(batch, 0);
 208     OUT_BCS_BATCH(batch, 0);
 209     /*MFC Indirect PAK-BSE Object Base Address for Encoder*/
 210     OUT_BCS_RELOC(batch,
 211                   mfc_context->mfc_indirect_pak_bse_object.bo,
 212                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 213                   0);
 214     OUT_BCS_RELOC(batch,
 215                   mfc_context->mfc_indirect_pak_bse_object.bo,
 216                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 217                   mfc_context->mfc_indirect_pak_bse_object.end_offset);
 218
 219     ADVANCE_BCS_BATCH(batch);
 220 }
 221
 222 void
 223 gen6_mfc_bsp_buf_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 224 {
 225     struct intel_batchbuffer *batch = encoder_context->base.batch;
 226     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 227
 228     BEGIN_BCS_BATCH(batch, 4);
 229
 230     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
 231     OUT_BCS_RELOC(batch, mfc_context->bsd_mpc_row_store_scratch_buffer.bo,
 232                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 233                   0);
 234     OUT_BCS_BATCH(batch, 0);
 235     OUT_BCS_BATCH(batch, 0);
 236
 237     ADVANCE_BCS_BATCH(batch);
 238 }
 239
 240 static void
 241 gen6_mfc_avc_img_state(VADriverContextP ctx,struct encode_state *encode_state,
 242                        struct intel_encoder_context *encoder_context)
 243 {
 244     struct intel_batchbuffer *batch = encoder_context->base.batch;
 245     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 246     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 247     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 248     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 249     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 250
 251     BEGIN_BCS_BATCH(batch, 13);
 252     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (13 - 2));
 253     OUT_BCS_BATCH(batch,
 254                   ((width_in_mbs * height_in_mbs) & 0xFFFF));
 255     OUT_BCS_BATCH(batch,
 256                   (height_in_mbs << 16) |
 257                   (width_in_mbs << 0));
 258     OUT_BCS_BATCH(batch,
 259                   (0 << 24) |     /*Second Chroma QP Offset*/
 260                   (0 << 16) |     /*Chroma QP Offset*/
 261                   (0 << 14) |   /*Max-bit conformance Intra flag*/
 262                   (0 << 13) |   /*Max Macroblock size conformance Inter flag*/
 263                   (1 << 12) |   /*Should always be written as "1" */
 264                   (0 << 10) |   /*QM Preset FLag */
 265                   (0 << 8)  |   /*Image Structure*/
 266                   (0 << 0) );   /*Current Decoed Image Frame Store ID, reserved in Encode mode*/
 267     OUT_BCS_BATCH(batch,
 268                   (400 << 16) |   /*Mininum Frame size*/
 269                   (0 << 15) |   /*Disable reading of Macroblock Status Buffer*/
 270                   (0 << 14) |   /*Load BitStream Pointer only once, 1 slic 1 frame*/
 271                   (0 << 13) |   /*CABAC 0 word insertion test enable*/
 272                   (1 << 12) |   /*MVUnpackedEnable,compliant to DXVA*/
 273                   (1 << 10) |   /*Chroma Format IDC, 4:2:0*/
 274                   (pPicParameter->pic_fields.bits.entropy_coding_mode_flag << 7)  |   /*0:CAVLC encoding mode,1:CABAC*/
 275                   (0 << 6)  |   /*Only valid for VLD decoding mode*/
 276                   (0 << 5)  |   /*Constrained Intra Predition Flag, from PPS*/
 277                   (pSequenceParameter->seq_fields.bits.direct_8x8_inference_flag << 4)  |   /*Direct 8x8 inference flag*/
 278                   (pPicParameter->pic_fields.bits.transform_8x8_mode_flag << 3)  |   /*8x8 or 4x4 IDCT Transform Mode Flag*/
 279                   (1 << 2)  |   /*Frame MB only flag*/
 280                   (0 << 1)  |   /*MBAFF mode is in active*/
 281                   (0 << 0) );   /*Field picture flag*/
 282     OUT_BCS_BATCH(batch,
 283                   (1<<16)   |   /*Frame Size Rate Control Flag*/
 284                   (1<<12)   |
 285                   (1<<9)    |   /*MB level Rate Control Enabling Flag*/
 286                   (1 << 3)  |   /*FrameBitRateMinReportMask*/
 287                   (1 << 2)  |   /*FrameBitRateMaxReportMask*/
 288                   (1 << 1)  |   /*InterMBMaxSizeReportMask*/
 289                   (1 << 0) );   /*IntraMBMaxSizeReportMask*/
 290     OUT_BCS_BATCH(batch,                        /*Inter and Intra Conformance Max size limit*/
 291                   (0x0600 << 16) |              /*InterMbMaxSz 192 Byte*/
 292                   (0x0800) );                   /*IntraMbMaxSz 256 Byte*/
 293     OUT_BCS_BATCH(batch, 0x00000000);   /*Reserved : MBZReserved*/
 294     OUT_BCS_BATCH(batch, 0x01020304);   /*Slice QP Delta for bitrate control*/
 295     OUT_BCS_BATCH(batch, 0xFEFDFCFB);
 296     OUT_BCS_BATCH(batch, 0x80601004);   /*MAX = 128KB, MIN = 64KB*/
 297     OUT_BCS_BATCH(batch, 0x00800001);
 298     OUT_BCS_BATCH(batch, 0);
 299
 300     ADVANCE_BCS_BATCH(batch);
 301 }
 302
 303 static void
 304 gen6_mfc_avc_directmode_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 305 {
 306     struct intel_batchbuffer *batch = encoder_context->base.batch;
 307     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 308
 309     int i;
 310
 311     BEGIN_BCS_BATCH(batch, 69);
 312
 313     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
 314
 315     /* Reference frames and Current frames */
 316     for(i = 0; i < NUM_MFC_DMV_BUFFERS; i++) {
 317         if ( mfc_context->direct_mv_buffers[i].bo != NULL) {
 318             OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[i].bo,
 319                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 320                           0);
 321         } else {
 322             OUT_BCS_BATCH(batch, 0);
 323         }
 324     }
 325
 326     /* POL list */
 327     for(i = 0; i < 32; i++) {
 328         OUT_BCS_BATCH(batch, i/2);
 329     }
 330     OUT_BCS_BATCH(batch, 0);
 331     OUT_BCS_BATCH(batch, 0);
 332
 333     ADVANCE_BCS_BATCH(batch);
 334 }
 335
 336 static void
 337 gen6_mfc_avc_slice_state(VADriverContextP ctx,
 338                          VAEncPictureParameterBufferH264 *pic_param,
 339                          VAEncSliceParameterBufferH264 *slice_param,
 340                          struct encode_state *encode_state,
 341                          struct intel_encoder_context *encoder_context,
 342                          int rate_control_enable,
 343                          int qp,
 344                          struct intel_batchbuffer *batch)
 345 {
 346     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 347     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 348     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 349     int beginmb = slice_param->macroblock_address;
 350     int endmb = beginmb + slice_param->num_macroblocks;
 351     int beginx = beginmb % width_in_mbs;
 352     int beginy = beginmb / width_in_mbs;
 353     int nextx =  endmb % width_in_mbs;
 354     int nexty = endmb / width_in_mbs;
 355     int slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
 356     int last_slice = (endmb == (width_in_mbs * height_in_mbs));
 357     int maxQpN, maxQpP;
 358     unsigned char correct[6], grow, shrink;
 359     int i;
 360     int weighted_pred_idc = 0;
 361     unsigned int luma_log2_weight_denom = slice_param->luma_log2_weight_denom;
 362     unsigned int chroma_log2_weight_denom = slice_param->chroma_log2_weight_denom;
 363     int bslice = 0;
 364
 365     if (batch == NULL)
 366         batch = encoder_context->base.batch;
 367
 368     if (slice_type == SLICE_TYPE_P) {
 369         weighted_pred_idc = pic_param->pic_fields.bits.weighted_pred_flag;
 370     } else if (slice_type == SLICE_TYPE_B) {
 371         weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc;
 372         bslice = 1;
 373
 374         if (weighted_pred_idc == 2) {
 375             /* 8.4.3 - Derivation process for prediction weights (8-279) */
 376             luma_log2_weight_denom = 5;
 377             chroma_log2_weight_denom = 5;
 378         }
 379     }
 380
 381     maxQpN = mfc_context->bit_rate_control_context[slice_type].MaxQpNegModifier;
 382     maxQpP = mfc_context->bit_rate_control_context[slice_type].MaxQpPosModifier;
 383
 384     for (i = 0; i < 6; i++)
 385         correct[i] = mfc_context->bit_rate_control_context[slice_type].Correct[i];
 386
 387     grow = mfc_context->bit_rate_control_context[slice_type].GrowInit +
 388         (mfc_context->bit_rate_control_context[slice_type].GrowResistance << 4);
 389     shrink = mfc_context->bit_rate_control_context[slice_type].ShrinkInit +
 390         (mfc_context->bit_rate_control_context[slice_type].ShrinkResistance << 4);
 391
 392     BEGIN_BCS_BATCH(batch, 11);;
 393
 394     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) );
 395     OUT_BCS_BATCH(batch, slice_type);                   /*Slice Type: I:P:B Slice*/
 396
 397     if (slice_type == SLICE_TYPE_I) {
 398         OUT_BCS_BATCH(batch, 0);                        /*no reference frames and pred_weight_table*/
 399     } else {
 400         OUT_BCS_BATCH(batch,
 401                       (1 << 16) | (bslice << 24) |     /*1 reference frame*/
 402                       (chroma_log2_weight_denom << 8) |
 403                       (luma_log2_weight_denom << 0));
 404     }
 405
 406     OUT_BCS_BATCH(batch,
 407                   (weighted_pred_idc << 30) |
 408                   (slice_param->direct_spatial_mv_pred_flag<<29) |             /*Direct Prediction Type*/
 409                   (slice_param->disable_deblocking_filter_idc << 27) |
 410                   (slice_param->cabac_init_idc << 24) |
 411                   (qp<<16) |                    /*Slice Quantization Parameter*/
 412                   ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
 413                   ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
 414     OUT_BCS_BATCH(batch,
 415                   (beginy << 24) |                      /*First MB X&Y , the begin postion of current slice*/
 416                   (beginx << 16) |
 417                   slice_param->macroblock_address );
 418     OUT_BCS_BATCH(batch, (nexty << 16) | nextx);                       /*Next slice first MB X&Y*/
 419     OUT_BCS_BATCH(batch,
 420                   (0/*rate_control_enable*/ << 31) |            /*in CBR mode RateControlCounterEnable = enable*/
 421                   (1 << 30) |           /*ResetRateControlCounter*/
 422                   (0 << 28) |           /*RC Triggle Mode = Always Rate Control*/
 423                   (4 << 24) |     /*RC Stable Tolerance, middle level*/
 424                   (0/*rate_control_enable*/ << 23) |     /*RC Panic Enable*/
 425                   (0 << 22) |     /*QP mode, don't modfiy CBP*/
 426                   (0 << 21) |     /*MB Type Direct Conversion Enabled*/
 427                   (0 << 20) |     /*MB Type Skip Conversion Enabled*/
 428                   (last_slice << 19) |     /*IsLastSlice*/
 429                   (0 << 18) |   /*BitstreamOutputFlag Compressed BitStream Output Disable Flag 0:enable 1:disable*/
 430                   (1 << 17) |       /*HeaderPresentFlag*/
 431                   (1 << 16) |       /*SliceData PresentFlag*/
 432                   (1 << 15) |       /*TailPresentFlag*/
 433                   (1 << 13) |       /*RBSP NAL TYPE*/
 434                   (0 << 12) );    /*CabacZeroWordInsertionEnable*/
 435     OUT_BCS_BATCH(batch, mfc_context->mfc_indirect_pak_bse_object.offset);
 436     OUT_BCS_BATCH(batch,
 437                   (maxQpN << 24) |     /*Target QP - 24 is lowest QP*/
 438                   (maxQpP << 16) |     /*Target QP + 20 is highest QP*/
 439                   (shrink << 8)  |
 440                   (grow << 0));
 441     OUT_BCS_BATCH(batch,
 442                   (correct[5] << 20) |
 443                   (correct[4] << 16) |
 444                   (correct[3] << 12) |
 445                   (correct[2] << 8) |
 446                   (correct[1] << 4) |
 447                   (correct[0] << 0));
 448     OUT_BCS_BATCH(batch, 0);
 449
 450     ADVANCE_BCS_BATCH(batch);
 451 }
 452
 453 static void gen6_mfc_avc_qm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 454 {
 455     struct intel_batchbuffer *batch = encoder_context->base.batch;
 456     int i;
 457
 458     BEGIN_BCS_BATCH(batch, 58);
 459
 460     OUT_BCS_BATCH(batch, MFX_AVC_QM_STATE | 56);
 461     OUT_BCS_BATCH(batch, 0xFF ) ;
 462     for( i = 0; i < 56; i++) {
 463         OUT_BCS_BATCH(batch, 0x10101010);
 464     }
 465
 466     ADVANCE_BCS_BATCH(batch);
 467 }
 468
 469 static void gen6_mfc_avc_fqm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 470 {
 471     struct intel_batchbuffer *batch = encoder_context->base.batch;
 472     int i;
 473
 474     BEGIN_BCS_BATCH(batch, 113);
 475     OUT_BCS_BATCH(batch, MFC_AVC_FQM_STATE | (113 - 2));
 476
 477     for(i = 0; i < 112;i++) {
 478         OUT_BCS_BATCH(batch, 0x10001000);
 479     }
 480
 481     ADVANCE_BCS_BATCH(batch);
 482 }
 483
 484 static void
 485 gen6_mfc_avc_ref_idx_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 486 {
 487     struct intel_batchbuffer *batch = encoder_context->base.batch;
 488     int i;
 489
 490     BEGIN_BCS_BATCH(batch, 10);
 491     OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
 492     OUT_BCS_BATCH(batch, 0);                  //Select L0
 493     OUT_BCS_BATCH(batch, 0x80808020);         //Only 1 reference
 494     for(i = 0; i < 7; i++) {
 495         OUT_BCS_BATCH(batch, 0x80808080);
 496     }
 497     ADVANCE_BCS_BATCH(batch);
 498
 499     BEGIN_BCS_BATCH(batch, 10);
 500     OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
 501     OUT_BCS_BATCH(batch, 1);                  //Select L1
 502     OUT_BCS_BATCH(batch, 0x80808022);         //Only 1 reference
 503     for(i = 0; i < 7; i++) {
 504         OUT_BCS_BATCH(batch, 0x80808080);
 505     }
 506     ADVANCE_BCS_BATCH(batch);
 507 }
 508
 509 static void
 510 gen6_mfc_avc_insert_object(VADriverContextP ctx, struct intel_encoder_context *encoder_context,
 511                            unsigned int *insert_data, int lenght_in_dws, int data_bits_in_last_dw,
 512                            int skip_emul_byte_count, int is_last_header, int is_end_of_slice, int emulation_flag,
 513                            struct intel_batchbuffer *batch)
 514 {
 515     if (batch == NULL)
 516         batch = encoder_context->base.batch;
 517
 518     BEGIN_BCS_BATCH(batch, lenght_in_dws + 2);
 519
 520     OUT_BCS_BATCH(batch, MFC_AVC_INSERT_OBJECT | (lenght_in_dws + 2 - 2));
 521
 522     OUT_BCS_BATCH(batch,
 523                   (0 << 16) |   /* always start at offset 0 */
 524                   (data_bits_in_last_dw << 8) |
 525                   (skip_emul_byte_count << 4) |
 526                   (!!emulation_flag << 3) |
 527                   ((!!is_last_header) << 2) |
 528                   ((!!is_end_of_slice) << 1) |
 529                   (0 << 0));    /* FIXME: ??? */
 530
 531     intel_batchbuffer_data(batch, insert_data, lenght_in_dws * 4);
 532     ADVANCE_BCS_BATCH(batch);
 533 }
 534
 535 void
 536 gen6_mfc_init(VADriverContextP ctx,
 537               struct encode_state *encode_state,
 538               struct intel_encoder_context *encoder_context)
 539 {
 540     struct i965_driver_data *i965 = i965_driver_data(ctx);
 541     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 542     dri_bo *bo;
 543     int i;
 544     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 545     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 546     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 547
 548     /*Encode common setup for MFC*/
 549     dri_bo_unreference(mfc_context->post_deblocking_output.bo);
 550     mfc_context->post_deblocking_output.bo = NULL;
 551
 552     dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
 553     mfc_context->pre_deblocking_output.bo = NULL;
 554
 555     dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
 556     mfc_context->uncompressed_picture_source.bo = NULL;
 557
 558     dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
 559     mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
 560
 561     for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
 562         if ( mfc_context->direct_mv_buffers[i].bo != NULL);
 563         dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
 564         mfc_context->direct_mv_buffers[i].bo = NULL;
 565     }
 566
 567     for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
 568         if (mfc_context->reference_surfaces[i].bo != NULL)
 569             dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
 570         mfc_context->reference_surfaces[i].bo = NULL;
 571     }
 572
 573     dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
 574     bo = dri_bo_alloc(i965->intel.bufmgr,
 575                       "Buffer",
 576                       width_in_mbs * 64,
 577                       64);
 578     assert(bo);
 579     mfc_context->intra_row_store_scratch_buffer.bo = bo;
 580
 581     dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
 582     bo = dri_bo_alloc(i965->intel.bufmgr,
 583                       "Buffer",
 584                       width_in_mbs * height_in_mbs * 16,
 585                       64);
 586     assert(bo);
 587     mfc_context->macroblock_status_buffer.bo = bo;
 588
 589     dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
 590     bo = dri_bo_alloc(i965->intel.bufmgr,
 591                       "Buffer",
 592                       4 * width_in_mbs * 64,  /* 4 * width_in_mbs * 64 */
 593                       64);
 594     assert(bo);
 595     mfc_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
 596
 597     dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
 598     bo = dri_bo_alloc(i965->intel.bufmgr,
 599                       "Buffer",
 600                       128 * width_in_mbs, /* 2 * widht_in_mbs * 64 */
 601                       0x1000);
 602     assert(bo);
 603     mfc_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
 604
 605     dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo);
 606     mfc_context->mfc_batchbuffer_surface.bo = NULL;
 607
 608     dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo);
 609     mfc_context->aux_batchbuffer_surface.bo = NULL;
 610
 611     if (mfc_context->aux_batchbuffer)
 612         intel_batchbuffer_free(mfc_context->aux_batchbuffer);
 613
 614     mfc_context->aux_batchbuffer = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD, 0);
 615     mfc_context->aux_batchbuffer_surface.bo = mfc_context->aux_batchbuffer->buffer;
 616     dri_bo_reference(mfc_context->aux_batchbuffer_surface.bo);
 617     mfc_context->aux_batchbuffer_surface.pitch = 16;
 618     mfc_context->aux_batchbuffer_surface.num_blocks = mfc_context->aux_batchbuffer->size / 16;
 619     mfc_context->aux_batchbuffer_surface.size_block = 16;
 620
 621     i965_gpe_context_init(ctx, &mfc_context->gpe_context);
 622 }
 623
 624 static void gen6_mfc_avc_pipeline_picture_programing( VADriverContextP ctx,
 625                                       struct encode_state *encode_state,
 626                                       struct intel_encoder_context *encoder_context)
 627 {
 628     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 629
 630     mfc_context->pipe_mode_select(ctx, MFX_FORMAT_AVC, encoder_context);
 631     mfc_context->set_surface_state(ctx, encoder_context);
 632     mfc_context->ind_obj_base_addr_state(ctx, encoder_context);
 633     gen6_mfc_pipe_buf_addr_state(ctx, encoder_context);
 634     gen6_mfc_bsp_buf_base_addr_state(ctx, encoder_context);
 635     mfc_context->avc_img_state(ctx, encode_state, encoder_context);
 636     mfc_context->avc_qm_state(ctx, encoder_context);
 637     mfc_context->avc_fqm_state(ctx, encoder_context);
 638     gen6_mfc_avc_directmode_state(ctx, encoder_context);
 639     gen6_mfc_avc_ref_idx_state(ctx, encoder_context);
 640 }
 641
 642
 643 VAStatus
 644 gen6_mfc_run(VADriverContextP ctx,
 645              struct encode_state *encode_state,
 646              struct intel_encoder_context *encoder_context)
 647 {
 648     struct intel_batchbuffer *batch = encoder_context->base.batch;
 649
 650     intel_batchbuffer_flush(batch);             //run the pipeline
 651
 652     return VA_STATUS_SUCCESS;
 653 }
 654
 655 VAStatus
 656 gen6_mfc_stop(VADriverContextP ctx,
 657               struct encode_state *encode_state,
 658               struct intel_encoder_context *encoder_context,
 659               int *encoded_bits_size)
 660 {
 661     VAStatus vaStatus = VA_STATUS_ERROR_UNKNOWN;
 662     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 663     VACodedBufferSegment *coded_buffer_segment;
 664
 665     vaStatus = i965_MapBuffer(ctx, pPicParameter->coded_buf, (void **)&coded_buffer_segment);
 666     assert(vaStatus == VA_STATUS_SUCCESS);
 667     *encoded_bits_size = coded_buffer_segment->size * 8;
 668     i965_UnmapBuffer(ctx, pPicParameter->coded_buf);
 669
 670     return VA_STATUS_SUCCESS;
 671 }
 672
 673 #if __SOFTWARE__
 674
 675 static int
 676 gen6_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb, int qp,unsigned int *msg,
 677                               struct intel_encoder_context *encoder_context,
 678                               unsigned char target_mb_size, unsigned char max_mb_size,
 679                               struct intel_batchbuffer *batch)
 680 {
 681     int len_in_dwords = 11;
 682
 683     if (batch == NULL)
 684         batch = encoder_context->base.batch;
 685
 686     BEGIN_BCS_BATCH(batch, len_in_dwords);
 687
 688     OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
 689     OUT_BCS_BATCH(batch, 0);
 690     OUT_BCS_BATCH(batch, 0);
 691     OUT_BCS_BATCH(batch,
 692                   (0 << 24) |           /* PackedMvNum, Debug*/
 693                   (0 << 20) |           /* No motion vector */
 694                   (1 << 19) |           /* CbpDcY */
 695                   (1 << 18) |           /* CbpDcU */
 696                   (1 << 17) |           /* CbpDcV */
 697                   (msg[0] & 0xFFFF) );
 698
 699     OUT_BCS_BATCH(batch, (0xFFFF << 16) | (y << 8) | x);                /* Code Block Pattern for Y*/
 700     OUT_BCS_BATCH(batch, 0x000F000F);                                                   /* Code Block Pattern */
 701     OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp);      /* Last MB */
 702
 703     /*Stuff for Intra MB*/
 704     OUT_BCS_BATCH(batch, msg[1]);                       /* We using Intra16x16 no 4x4 predmode*/
 705     OUT_BCS_BATCH(batch, msg[2]);
 706     OUT_BCS_BATCH(batch, msg[3]&0xFC);
 707
 708     /*MaxSizeInWord and TargetSzieInWord*/
 709     OUT_BCS_BATCH(batch, (max_mb_size << 24) |
 710                   (target_mb_size << 16) );
 711
 712     ADVANCE_BCS_BATCH(batch);
 713
 714     return len_in_dwords;
 715 }
 716
 717 static int
 718 gen6_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, int qp,
 719                               unsigned int *msg, unsigned int offset,
 720                               struct intel_encoder_context *encoder_context,
 721                               unsigned char target_mb_size,unsigned char max_mb_size, int slice_type,
 722                               struct intel_batchbuffer *batch)
 723 {
 724     int len_in_dwords = 11;
 725
 726     if (batch == NULL)
 727         batch = encoder_context->base.batch;
 728
 729     BEGIN_BCS_BATCH(batch, len_in_dwords);
 730
 731     OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
 732
 733     OUT_BCS_BATCH(batch, msg[2]);         /* 32 MV*/
 734     OUT_BCS_BATCH(batch, offset);
 735
 736     OUT_BCS_BATCH(batch, msg[0]);
 737
 738     OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x);        /* Code Block Pattern for Y*/
 739     OUT_BCS_BATCH(batch, 0x000F000F);                         /* Code Block Pattern */
 740 #if 0
 741     if ( slice_type == SLICE_TYPE_B) {
 742         OUT_BCS_BATCH(batch, (0xF<<28) | (end_mb << 26) | qp);  /* Last MB */
 743     } else {
 744         OUT_BCS_BATCH(batch, (end_mb << 26) | qp);      /* Last MB */
 745     }
 746 #else
 747     OUT_BCS_BATCH(batch, (end_mb << 26) | qp);  /* Last MB */
 748 #endif
 749
 750
 751     /*Stuff for Inter MB*/
 752     OUT_BCS_BATCH(batch, msg[1]);
 753     OUT_BCS_BATCH(batch, 0x0);
 754     OUT_BCS_BATCH(batch, 0x0);
 755
 756     /*MaxSizeInWord and TargetSzieInWord*/
 757     OUT_BCS_BATCH(batch, (max_mb_size << 24) |
 758                   (target_mb_size << 16) );
 759
 760     ADVANCE_BCS_BATCH(batch);
 761
 762     return len_in_dwords;
 763 }
 764
 765 static void
 766 gen6_mfc_avc_pipeline_slice_programing(VADriverContextP ctx,
 767                                        struct encode_state *encode_state,
 768                                        struct intel_encoder_context *encoder_context,
 769                                        int slice_index,
 770                                        struct intel_batchbuffer *slice_batch)
 771 {
 772     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 773     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 774     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 775     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 776     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
 777     unsigned int *msg = NULL, offset = 0;
 778     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 779     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 780     int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs);
 781     int i,x,y;
 782     int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta;
 783     unsigned int rate_control_mode = encoder_context->rate_control_mode;
 784     unsigned char *slice_header = NULL;
 785     int slice_header_length_in_bits = 0;
 786     unsigned int tail_data[] = { 0x0, 0x0 };
 787     int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type);
 788     int is_intra = slice_type == SLICE_TYPE_I;
 789
 790     if (rate_control_mode == VA_RC_CBR) {
 791         qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
 792         pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp;
 793     }
 794
 795     /* only support for 8-bit pixel bit-depth */
 796     assert(pSequenceParameter->bit_depth_luma_minus8 == 0);
 797     assert(pSequenceParameter->bit_depth_chroma_minus8 == 0);
 798     assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52);
 799     assert(qp >= 0 && qp < 52);
 800
 801     gen6_mfc_avc_slice_state(ctx,
 802                              pPicParameter,
 803                              pSliceParameter,
 804                              encode_state, encoder_context,
 805                              (rate_control_mode == VA_RC_CBR), qp, slice_batch);
 806
 807     if ( slice_index == 0)
 808         intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch);
 809
 810     slice_header_length_in_bits = build_avc_slice_header(pSequenceParameter, pPicParameter, pSliceParameter, &slice_header);
 811
 812     // slice hander
 813     mfc_context->insert_object(ctx, encoder_context,
 814                                (unsigned int *)slice_header, ALIGN(slice_header_length_in_bits, 32) >> 5, slice_header_length_in_bits & 0x1f,
 815                                5,  /* first 5 bytes are start code + nal unit type */
 816                                1, 0, 1, slice_batch);
 817
 818     dri_bo_map(vme_context->vme_output.bo , 1);
 819     msg = (unsigned int *)vme_context->vme_output.bo->virtual;
 820
 821     if (is_intra) {
 822         msg += pSliceParameter->macroblock_address * INTRA_VME_OUTPUT_IN_DWS;
 823     } else {
 824         msg += pSliceParameter->macroblock_address * INTER_VME_OUTPUT_IN_DWS;
 825         msg += 32; /* the first 32 DWs are MVs */
 826         offset = pSliceParameter->macroblock_address * INTER_VME_OUTPUT_IN_BYTES;
 827     }
 828
 829     for (i = pSliceParameter->macroblock_address;
 830          i < pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks; i++) {
 831         int last_mb = (i == (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks - 1) );
 832         x = i % width_in_mbs;
 833         y = i / width_in_mbs;
 834
 835         if (is_intra) {
 836             assert(msg);
 837             gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch);
 838             msg += INTRA_VME_OUTPUT_IN_DWS;
 839         } else {
 840             if (msg[0] & INTRA_MB_FLAG_MASK) {
 841                 gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch);
 842             } else {
 843                 gen6_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, msg, offset, encoder_context, 0, 0, slice_type, slice_batch);
 844             }
 845
 846             msg += INTER_VME_OUTPUT_IN_DWS;
 847             offset += INTER_VME_OUTPUT_IN_BYTES;
 848         }
 849     }
 850
 851     dri_bo_unmap(vme_context->vme_output.bo);
 852
 853     if ( last_slice ) {
 854         mfc_context->insert_object(ctx, encoder_context,
 855                                    tail_data, 2, 8,
 856                                    2, 1, 1, 0, slice_batch);
 857     } else {
 858         mfc_context->insert_object(ctx, encoder_context,
 859                                    tail_data, 1, 8,
 860                                    1, 1, 1, 0, slice_batch);
 861     }
 862
 863     free(slice_header);
 864
 865 }
 866
 867 static dri_bo *
 868 gen6_mfc_avc_software_batchbuffer(VADriverContextP ctx,
 869                                   struct encode_state *encode_state,
 870                                   struct intel_encoder_context *encoder_context)
 871 {
 872     struct i965_driver_data *i965 = i965_driver_data(ctx);
 873     struct intel_batchbuffer *batch = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD, 0);
 874     dri_bo *batch_bo = batch->buffer;
 875     int i;
 876
 877     for (i = 0; i < encode_state->num_slice_params_ext; i++) {
 878         gen6_mfc_avc_pipeline_slice_programing(ctx, encode_state, encoder_context, i, batch);
 879     }
 880
 881     intel_batchbuffer_align(batch, 8);
 882
 883     BEGIN_BCS_BATCH(batch, 2);
 884     OUT_BCS_BATCH(batch, 0);
 885     OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_END);
 886     ADVANCE_BCS_BATCH(batch);
 887
 888     dri_bo_reference(batch_bo);
 889     intel_batchbuffer_free(batch);
 890
 891     return batch_bo;
 892 }
 893
 894 #else
 895
 896 static void
 897 gen6_mfc_batchbuffer_surfaces_input(VADriverContextP ctx,
 898                                     struct encode_state *encode_state,
 899                                     struct intel_encoder_context *encoder_context)
 900
 901 {
 902     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 903     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 904
 905     assert(vme_context->vme_output.bo);
 906     mfc_context->buffer_suface_setup(ctx,
 907                                      &mfc_context->gpe_context,
 908                                      &vme_context->vme_output,
 909                                      BINDING_TABLE_OFFSET(BIND_IDX_VME_OUTPUT),
 910                                      SURFACE_STATE_OFFSET(BIND_IDX_VME_OUTPUT));
 911     assert(mfc_context->aux_batchbuffer_surface.bo);
 912     mfc_context->buffer_suface_setup(ctx,
 913                                      &mfc_context->gpe_context,
 914                                      &mfc_context->aux_batchbuffer_surface,
 915                                      BINDING_TABLE_OFFSET(BIND_IDX_MFC_SLICE_HEADER),
 916                                      SURFACE_STATE_OFFSET(BIND_IDX_MFC_SLICE_HEADER));
 917 }
 918
 919 static void
 920 gen6_mfc_batchbuffer_surfaces_output(VADriverContextP ctx,
 921                                      struct encode_state *encode_state,
 922                                      struct intel_encoder_context *encoder_context)
 923
 924 {
 925     struct i965_driver_data *i965 = i965_driver_data(ctx);
 926     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 927     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 928     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 929     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 930     mfc_context->mfc_batchbuffer_surface.num_blocks = width_in_mbs * height_in_mbs + encode_state->num_slice_params_ext * 8 + 1;
 931     mfc_context->mfc_batchbuffer_surface.size_block = 16 * CMD_LEN_IN_OWORD; /* 3 OWORDs */
 932     mfc_context->mfc_batchbuffer_surface.pitch = 16;
 933     mfc_context->mfc_batchbuffer_surface.bo = dri_bo_alloc(i965->intel.bufmgr,
 934                                                            "MFC batchbuffer",
 935                                                            mfc_context->mfc_batchbuffer_surface.num_blocks * mfc_context->mfc_batchbuffer_surface.size_block,
 936                                                            0x1000);
 937     mfc_context->buffer_suface_setup(ctx,
 938                                      &mfc_context->gpe_context,
 939                                      &mfc_context->mfc_batchbuffer_surface,
 940                                      BINDING_TABLE_OFFSET(BIND_IDX_MFC_BATCHBUFFER),
 941                                      SURFACE_STATE_OFFSET(BIND_IDX_MFC_BATCHBUFFER));
 942 }
 943
 944 static void
 945 gen6_mfc_batchbuffer_surfaces_setup(VADriverContextP ctx,
 946                                     struct encode_state *encode_state,
 947                                     struct intel_encoder_context *encoder_context)
 948 {
 949     gen6_mfc_batchbuffer_surfaces_input(ctx, encode_state, encoder_context);
 950     gen6_mfc_batchbuffer_surfaces_output(ctx, encode_state, encoder_context);
 951 }
 952
 953 static void
 954 gen6_mfc_batchbuffer_idrt_setup(VADriverContextP ctx,
 955                                 struct encode_state *encode_state,
 956                                 struct intel_encoder_context *encoder_context)
 957 {
 958     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 959     struct gen6_interface_descriptor_data *desc;
 960     int i;
 961     dri_bo *bo;
 962
 963     bo = mfc_context->gpe_context.idrt.bo;
 964     dri_bo_map(bo, 1);
 965     assert(bo->virtual);
 966     desc = bo->virtual;
 967
 968     for (i = 0; i < mfc_context->gpe_context.num_kernels; i++) {
 969         struct i965_kernel *kernel;
 970
 971         kernel = &mfc_context->gpe_context.kernels[i];
 972         assert(sizeof(*desc) == 32);
 973
 974         /*Setup the descritor table*/
 975         memset(desc, 0, sizeof(*desc));
 976         desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6);
 977         desc->desc2.sampler_count = 0;
 978         desc->desc2.sampler_state_pointer = 0;
 979         desc->desc3.binding_table_entry_count = 2;
 980         desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5);
 981         desc->desc4.constant_urb_entry_read_offset = 0;
 982         desc->desc4.constant_urb_entry_read_length = 4;
 983
 984         /*kernel start*/
 985         dri_bo_emit_reloc(bo,
 986                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 987                           0,
 988                           i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0),
 989                           kernel->bo);
 990         desc++;
 991     }
 992
 993     dri_bo_unmap(bo);
 994 }
 995
 996 static void
 997 gen6_mfc_batchbuffer_constant_setup(VADriverContextP ctx,
 998                                     struct encode_state *encode_state,
 999                                     struct intel_encoder_context *encoder_context)
1000 {
1001     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1002
1003     (void)mfc_context;
1004 }
1005
1006 static void
1007 gen6_mfc_batchbuffer_emit_object_command(struct intel_batchbuffer *batch,
1008                                          int index,
1009                                          int head_offset,
1010                                          int batchbuffer_offset,
1011                                          int head_size,
1012                                          int tail_size,
1013                                          int number_mb_cmds,
1014                                          int first_object,
1015                                          int last_object,
1016                                          int last_slice,
1017                                          int mb_x,
1018                                          int mb_y,
1019                                          int width_in_mbs,
1020                                          int qp)
1021 {
1022     BEGIN_BATCH(batch, 12);
1023
1024     OUT_BATCH(batch, CMD_MEDIA_OBJECT | (12 - 2));
1025     OUT_BATCH(batch, index);
1026     OUT_BATCH(batch, 0);
1027     OUT_BATCH(batch, 0);
1028     OUT_BATCH(batch, 0);
1029     OUT_BATCH(batch, 0);
1030
1031     /*inline data */
1032     OUT_BATCH(batch, head_offset);
1033     OUT_BATCH(batch, batchbuffer_offset);
1034     OUT_BATCH(batch,
1035               head_size << 16 |
1036               tail_size);
1037     OUT_BATCH(batch,
1038               number_mb_cmds << 16 |
1039               first_object << 2 |
1040               last_object << 1 |
1041               last_slice);
1042     OUT_BATCH(batch,
1043               mb_y << 8 |
1044               mb_x);
1045     OUT_BATCH(batch,
1046               qp << 16 |
1047               width_in_mbs);
1048
1049     ADVANCE_BATCH(batch);
1050 }
1051
1052 static void
1053 gen6_mfc_avc_batchbuffer_slice_command(VADriverContextP ctx,
1054                                        struct intel_encoder_context *encoder_context,
1055                                        VAEncSliceParameterBufferH264 *slice_param,
1056                                        int head_offset,
1057                                        unsigned short head_size,
1058                                        unsigned short tail_size,
1059                                        int batchbuffer_offset,
1060                                        int qp,
1061                                        int last_slice)
1062 {
1063     struct intel_batchbuffer *batch = encoder_context->base.batch;
1064     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1065     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
1066     int total_mbs = slice_param->num_macroblocks;
1067     int number_mb_cmds = 128;
1068     int starting_mb = 0;
1069     int last_object = 0;
1070     int first_object = 1;
1071     int i;
1072     int mb_x, mb_y;
1073     int index = (slice_param->slice_type == SLICE_TYPE_I) ? MFC_BATCHBUFFER_AVC_INTRA : MFC_BATCHBUFFER_AVC_INTER;
1074
1075     for (i = 0; i < total_mbs / number_mb_cmds; i++) {
1076         last_object = (total_mbs - starting_mb) == number_mb_cmds;
1077         mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs;
1078         mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs;
1079         assert(mb_x <= 255 && mb_y <= 255);
1080
1081         starting_mb += number_mb_cmds;
1082
1083         gen6_mfc_batchbuffer_emit_object_command(batch,
1084                                                  index,
1085                                                  head_offset,
1086                                                  batchbuffer_offset,
1087                                                  head_size,
1088                                                  tail_size,
1089                                                  number_mb_cmds,
1090                                                  first_object,
1091                                                  last_object,
1092                                                  last_slice,
1093                                                  mb_x,
1094                                                  mb_y,
1095                                                  width_in_mbs,
1096                                                  qp);
1097
1098         if (first_object) {
1099             head_offset += head_size;
1100             batchbuffer_offset += head_size;
1101         }
1102
1103         if (last_object) {
1104             head_offset += tail_size;
1105             batchbuffer_offset += tail_size;
1106         }
1107
1108         batchbuffer_offset += number_mb_cmds * CMD_LEN_IN_OWORD;
1109
1110         first_object = 0;
1111     }
1112
1113     if (!last_object) {
1114         last_object = 1;
1115         number_mb_cmds = total_mbs % number_mb_cmds;
1116         mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs;
1117         mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs;
1118         assert(mb_x <= 255 && mb_y <= 255);
1119         starting_mb += number_mb_cmds;
1120
1121         gen6_mfc_batchbuffer_emit_object_command(batch,
1122                                                  index,
1123                                                  head_offset,
1124                                                  batchbuffer_offset,
1125                                                  head_size,
1126                                                  tail_size,
1127                                                  number_mb_cmds,
1128                                                  first_object,
1129                                                  last_object,
1130                                                  last_slice,
1131                                                  mb_x,
1132                                                  mb_y,
1133                                                  width_in_mbs,
1134                                                  qp);
1135     }
1136 }
1137
1138 /*
1139  * return size in Owords (16bytes)
1140  */
1141 static int
1142 gen6_mfc_avc_batchbuffer_slice(VADriverContextP ctx,
1143                                struct encode_state *encode_state,
1144                                struct intel_encoder_context *encoder_context,
1145                                int slice_index,
1146                                int batchbuffer_offset)
1147 {
1148     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1149     struct intel_batchbuffer *slice_batch = mfc_context->aux_batchbuffer;
1150     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
1151     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
1152     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
1153     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
1154     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
1155     int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs);
1156     int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta;
1157     unsigned int rate_control_mode = encoder_context->rate_control_mode;
1158     unsigned char *slice_header = NULL;
1159     int slice_header_length_in_bits = 0;
1160     unsigned int tail_data[] = { 0x0, 0x0 };
1161     long head_offset;
1162     int old_used = intel_batchbuffer_used_size(slice_batch), used;
1163     unsigned short head_size, tail_size;
1164     int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type);
1165
1166     if (rate_control_mode == VA_RC_CBR) {
1167         qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
1168         pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp;
1169     }
1170
1171     /* only support for 8-bit pixel bit-depth */
1172     assert(pSequenceParameter->bit_depth_luma_minus8 == 0);
1173     assert(pSequenceParameter->bit_depth_chroma_minus8 == 0);
1174     assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52);
1175     assert(qp >= 0 && qp < 52);
1176
1177     head_offset = old_used / 16;
1178     gen6_mfc_avc_slice_state(ctx,
1179                              pPicParameter,
1180                              pSliceParameter,
1181                              encode_state,
1182                              encoder_context,
1183                              (rate_control_mode == VA_RC_CBR),
1184                              qp,
1185                              slice_batch);
1186
1187     if (slice_index == 0)
1188         intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch);
1189
1190     slice_header_length_in_bits = build_avc_slice_header(pSequenceParameter, pPicParameter, pSliceParameter, &slice_header);
1191
1192     // slice hander
1193     mfc_context->insert_object(ctx,
1194                                encoder_context,
1195                                (unsigned int *)slice_header,
1196                                ALIGN(slice_header_length_in_bits, 32) >> 5,
1197                                slice_header_length_in_bits & 0x1f,
1198                                5,  /* first 5 bytes are start code + nal unit type */
1199                                1,
1200                                0,
1201                                1,
1202                                slice_batch);
1203     free(slice_header);
1204
1205     intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */
1206     used = intel_batchbuffer_used_size(slice_batch);
1207     head_size = (used - old_used) / 16;
1208     old_used = used;
1209
1210     /* tail */
1211     if (last_slice) {
1212         mfc_context->insert_object(ctx,
1213                                    encoder_context,
1214                                    tail_data,
1215                                    2,
1216                                    8,
1217                                    2,
1218                                    1,
1219                                    1,
1220                                    0,
1221                                    slice_batch);
1222     } else {
1223         mfc_context->insert_object(ctx,
1224                                    encoder_context,
1225                                    tail_data,
1226                                    1,
1227                                    8,
1228                                    1,
1229                                    1,
1230                                    1,
1231                                    0,
1232                                    slice_batch);
1233     }
1234
1235     intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */
1236     used = intel_batchbuffer_used_size(slice_batch);
1237     tail_size = (used - old_used) / 16;
1238
1239
1240     gen6_mfc_avc_batchbuffer_slice_command(ctx,
1241                                            encoder_context,
1242                                            pSliceParameter,
1243                                            head_offset,
1244                                            head_size,
1245                                            tail_size,
1246                                            batchbuffer_offset,
1247                                            qp,
1248                                            last_slice);
1249
1250     return head_size + tail_size + pSliceParameter->num_macroblocks * CMD_LEN_IN_OWORD;
1251 }
1252
1253 static void
1254 gen6_mfc_avc_batchbuffer_pipeline(VADriverContextP ctx,
1255                                   struct encode_state *encode_state,
1256                                   struct intel_encoder_context *encoder_context)
1257 {
1258     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1259     struct intel_batchbuffer *batch = encoder_context->base.batch;
1260     int i, size, offset = 0;
1261     intel_batchbuffer_start_atomic(batch, 0x4000);
1262     gen6_gpe_pipeline_setup(ctx, &mfc_context->gpe_context, batch);
1263
1264     for ( i = 0; i < encode_state->num_slice_params_ext; i++) {
1265         size = gen6_mfc_avc_batchbuffer_slice(ctx, encode_state, encoder_context, i, offset);
1266         offset += size;
1267     }
1268
1269     intel_batchbuffer_end_atomic(batch);
1270     intel_batchbuffer_flush(batch);
1271 }
1272
1273 static void
1274 gen6_mfc_build_avc_batchbuffer(VADriverContextP ctx,
1275                                struct encode_state *encode_state,
1276                                struct intel_encoder_context *encoder_context)
1277 {
1278     gen6_mfc_batchbuffer_surfaces_setup(ctx, encode_state, encoder_context);
1279     gen6_mfc_batchbuffer_idrt_setup(ctx, encode_state, encoder_context);
1280     gen6_mfc_batchbuffer_constant_setup(ctx, encode_state, encoder_context);
1281     gen6_mfc_avc_batchbuffer_pipeline(ctx, encode_state, encoder_context);
1282 }
1283
1284 static dri_bo *
1285 gen6_mfc_avc_hardware_batchbuffer(VADriverContextP ctx,
1286                                   struct encode_state *encode_state,
1287                                   struct intel_encoder_context *encoder_context)
1288 {
1289     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1290
1291     gen6_mfc_build_avc_batchbuffer(ctx, encode_state, encoder_context);
1292     dri_bo_reference(mfc_context->mfc_batchbuffer_surface.bo);
1293
1294     return mfc_context->mfc_batchbuffer_surface.bo;
1295 }
1296
1297 #endif
1298
1299
1300 static void
1301 gen6_mfc_avc_pipeline_programing(VADriverContextP ctx,
1302                                  struct encode_state *encode_state,
1303                                  struct intel_encoder_context *encoder_context)
1304 {
1305     struct intel_batchbuffer *batch = encoder_context->base.batch;
1306     dri_bo *slice_batch_bo;
1307
1308     if ( intel_mfc_interlace_check(ctx, encode_state, encoder_context) ) {
1309         fprintf(stderr, "Current VA driver don't support interlace mode!\n");
1310         assert(0);
1311         return;
1312     }
1313
1314 #if __SOFTWARE__
1315     slice_batch_bo = gen6_mfc_avc_software_batchbuffer(ctx, encode_state, encoder_context);
1316 #else
1317     slice_batch_bo = gen6_mfc_avc_hardware_batchbuffer(ctx, encode_state, encoder_context);
1318 #endif
1319
1320     // begin programing
1321     intel_batchbuffer_start_atomic_bcs(batch, 0x4000);
1322     intel_batchbuffer_emit_mi_flush(batch);
1323
1324     // picture level programing
1325     gen6_mfc_avc_pipeline_picture_programing(ctx, encode_state, encoder_context);
1326
1327     BEGIN_BCS_BATCH(batch, 2);
1328     OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8));
1329     OUT_BCS_RELOC(batch,
1330                   slice_batch_bo,
1331                   I915_GEM_DOMAIN_COMMAND, 0,
1332                   0);
1333     ADVANCE_BCS_BATCH(batch);
1334
1335     // end programing
1336     intel_batchbuffer_end_atomic(batch);
1337
1338     dri_bo_unreference(slice_batch_bo);
1339 }
1340
1341 VAStatus
1342 gen6_mfc_avc_encode_picture(VADriverContextP ctx,
1343                             struct encode_state *encode_state,
1344                             struct intel_encoder_context *encoder_context)
1345 {
1346     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1347     unsigned int rate_control_mode = encoder_context->rate_control_mode;
1348     int current_frame_bits_size;
1349     int sts;
1350
1351     for (;;) {
1352         gen6_mfc_init(ctx, encode_state, encoder_context);
1353         intel_mfc_avc_prepare(ctx, encode_state, encoder_context);
1354         /*Programing bcs pipeline*/
1355         gen6_mfc_avc_pipeline_programing(ctx, encode_state, encoder_context);   //filling the pipeline
1356         gen6_mfc_run(ctx, encode_state, encoder_context);
1357         if (rate_control_mode == VA_RC_CBR /*|| rate_control_mode == VA_RC_VBR*/) {
1358             gen6_mfc_stop(ctx, encode_state, encoder_context, &current_frame_bits_size);
1359             sts = intel_mfc_brc_postpack(encode_state, mfc_context, current_frame_bits_size);
1360             if (sts == BRC_NO_HRD_VIOLATION) {
1361                 intel_mfc_hrd_context_update(encode_state, mfc_context);
1362                 break;
1363             }
1364             else if (sts == BRC_OVERFLOW_WITH_MIN_QP || sts == BRC_UNDERFLOW_WITH_MAX_QP) {
1365                 if (!mfc_context->hrd.violation_noted) {
1366                     fprintf(stderr, "Unrepairable %s!\n", (sts == BRC_OVERFLOW_WITH_MIN_QP)? "overflow": "underflow");
1367                     mfc_context->hrd.violation_noted = 1;
1368                 }
1369                 return VA_STATUS_SUCCESS;
1370             }
1371         } else {
1372             break;
1373         }
1374     }
1375
1376     return VA_STATUS_SUCCESS;
1377 }
1378
1379 VAStatus
1380 gen6_mfc_pipeline(VADriverContextP ctx,
1381                   VAProfile profile,
1382                   struct encode_state *encode_state,
1383                   struct intel_encoder_context *encoder_context)
1384 {
1385     VAStatus vaStatus;
1386
1387     switch (profile) {
1388     case VAProfileH264Baseline:
1389     case VAProfileH264Main:
1390     case VAProfileH264High:
1391         vaStatus = gen6_mfc_avc_encode_picture(ctx, encode_state, encoder_context);
1392         break;
1393
1394         /* FIXME: add for other profile */
1395     default:
1396         vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
1397         break;
1398     }
1399
1400     return vaStatus;
1401 }
1402
1403 void
1404 gen6_mfc_context_destroy(void *context)
1405 {
1406     struct gen6_mfc_context *mfc_context = context;
1407     int i;
1408
1409     dri_bo_unreference(mfc_context->post_deblocking_output.bo);
1410     mfc_context->post_deblocking_output.bo = NULL;
1411
1412     dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
1413     mfc_context->pre_deblocking_output.bo = NULL;
1414
1415     dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
1416     mfc_context->uncompressed_picture_source.bo = NULL;
1417
1418     dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
1419     mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
1420
1421     for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
1422         dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
1423         mfc_context->direct_mv_buffers[i].bo = NULL;
1424     }
1425
1426     dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
1427     mfc_context->intra_row_store_scratch_buffer.bo = NULL;
1428
1429     dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
1430     mfc_context->macroblock_status_buffer.bo = NULL;
1431
1432     dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
1433     mfc_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
1434
1435     dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
1436     mfc_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
1437
1438
1439     for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
1440         dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
1441         mfc_context->reference_surfaces[i].bo = NULL;
1442     }
1443
1444     i965_gpe_context_destroy(&mfc_context->gpe_context);
1445
1446     dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo);
1447     mfc_context->mfc_batchbuffer_surface.bo = NULL;
1448
1449     dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo);
1450     mfc_context->aux_batchbuffer_surface.bo = NULL;
1451
1452     if (mfc_context->aux_batchbuffer)
1453         intel_batchbuffer_free(mfc_context->aux_batchbuffer);
1454
1455     mfc_context->aux_batchbuffer = NULL;
1456
1457     free(mfc_context);
1458 }
1459
1460 Bool gen6_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
1461 {
1462     struct gen6_mfc_context *mfc_context = calloc(1, sizeof(struct gen6_mfc_context));
1463
1464     mfc_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6;
1465
1466     mfc_context->gpe_context.idrt.max_entries = MAX_GPE_KERNELS;
1467     mfc_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data);
1468
1469     mfc_context->gpe_context.curbe.length = 32 * 4;
1470
1471     mfc_context->gpe_context.vfe_state.max_num_threads = 60 - 1;
1472     mfc_context->gpe_context.vfe_state.num_urb_entries = 16;
1473     mfc_context->gpe_context.vfe_state.gpgpu_mode = 0;
1474     mfc_context->gpe_context.vfe_state.urb_entry_size = 59 - 1;
1475     mfc_context->gpe_context.vfe_state.curbe_allocation_size = 37 - 1;
1476
1477     i965_gpe_load_kernels(ctx,
1478                           &mfc_context->gpe_context,
1479                           gen6_mfc_kernels,
1480                           NUM_MFC_KERNEL);
1481
1482     mfc_context->pipe_mode_select = gen6_mfc_pipe_mode_select;
1483     mfc_context->set_surface_state = gen6_mfc_surface_state;
1484     mfc_context->ind_obj_base_addr_state = gen6_mfc_ind_obj_base_addr_state;
1485     mfc_context->avc_img_state = gen6_mfc_avc_img_state;
1486     mfc_context->avc_qm_state = gen6_mfc_avc_qm_state;
1487     mfc_context->avc_fqm_state = gen6_mfc_avc_fqm_state;
1488     mfc_context->insert_object = gen6_mfc_avc_insert_object;
1489     mfc_context->buffer_suface_setup = i965_gpe_buffer_suface_setup;
1490
1491     encoder_context->mfc_context = mfc_context;
1492     encoder_context->mfc_context_destroy = gen6_mfc_context_destroy;
1493     encoder_context->mfc_pipeline = gen6_mfc_pipeline;
1494     encoder_context->mfc_brc_prepare = intel_mfc_brc_prepare;
1495
1496     return True;
1497 }