src/gen6_mfc.c

   1 /*
   2  * Copyright © 2010-2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Zhou Chang <chang.zhou@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <assert.h>
  33 #include <math.h>
  34
  35 #include "intel_batchbuffer.h"
  36 #include "i965_defines.h"
  37 #include "i965_structs.h"
  38 #include "i965_drv_video.h"
  39 #include "i965_encoder.h"
  40 #include "i965_encoder_utils.h"
  41 #include "gen6_mfc.h"
  42 #include "gen6_vme.h"
  43 #include "intel_media.h"
  44
  45 static const uint32_t gen6_mfc_batchbuffer_avc_intra[][4] = {
  46 #include "shaders/utils/mfc_batchbuffer_avc_intra.g6b"
  47 };
  48
  49 static const uint32_t gen6_mfc_batchbuffer_avc_inter[][4] = {
  50 #include "shaders/utils/mfc_batchbuffer_avc_inter.g6b"
  51 };
  52
  53 static struct i965_kernel gen6_mfc_kernels[] = {
  54     {
  55         "MFC AVC INTRA BATCHBUFFER ",
  56         MFC_BATCHBUFFER_AVC_INTRA,
  57         gen6_mfc_batchbuffer_avc_intra,
  58         sizeof(gen6_mfc_batchbuffer_avc_intra),
  59         NULL
  60     },
  61
  62     {
  63         "MFC AVC INTER BATCHBUFFER ",
  64         MFC_BATCHBUFFER_AVC_INTER,
  65         gen6_mfc_batchbuffer_avc_inter,
  66         sizeof(gen6_mfc_batchbuffer_avc_inter),
  67         NULL
  68     },
  69 };
  70
  71 static void
  72 gen6_mfc_pipe_mode_select(VADriverContextP ctx,
  73                           int standard_select,
  74                           struct intel_encoder_context *encoder_context)
  75 {
  76     struct intel_batchbuffer *batch = encoder_context->base.batch;
  77     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
  78
  79     assert(standard_select == MFX_FORMAT_AVC);
  80
  81     BEGIN_BCS_BATCH(batch, 4);
  82
  83     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (4 - 2));
  84     OUT_BCS_BATCH(batch,
  85                   (1 << 10) | /* disable Stream-Out , advanced QP/bitrate control need enable it*/
  86                   ((!!mfc_context->post_deblocking_output.bo) << 9)  | /* Post Deblocking Output */
  87                   ((!!mfc_context->pre_deblocking_output.bo) << 8)  | /* Pre Deblocking Output */
  88                   (0 << 7)  | /* disable TLB prefectch */
  89                   (0 << 5)  | /* not in stitch mode */
  90                   (1 << 4)  | /* encoding mode */
  91                   (2 << 0));  /* Standard Select: AVC */
  92     OUT_BCS_BATCH(batch,
  93                   (0 << 20) | /* round flag in PB slice */
  94                   (0 << 19) | /* round flag in Intra8x8 */
  95                   (0 << 7)  | /* expand NOA bus flag */
  96                   (1 << 6)  | /* must be 1 */
  97                   (0 << 5)  | /* disable clock gating for NOA */
  98                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
  99                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
 100                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
 101                   (0 << 1)  | /* AVC long field motion vector */
 102                   (0 << 0));  /* always calculate AVC ILDB boundary strength */
 103     OUT_BCS_BATCH(batch, 0);
 104
 105     ADVANCE_BCS_BATCH(batch);
 106 }
 107
 108 static void
 109 gen6_mfc_surface_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 110 {
 111     struct intel_batchbuffer *batch = encoder_context->base.batch;
 112     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 113
 114     BEGIN_BCS_BATCH(batch, 6);
 115
 116     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
 117     OUT_BCS_BATCH(batch, 0);
 118     OUT_BCS_BATCH(batch,
 119                   ((mfc_context->surface_state.height - 1) << 19) |
 120                   ((mfc_context->surface_state.width - 1) << 6));
 121     OUT_BCS_BATCH(batch,
 122                   (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
 123                   (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
 124                   (0 << 22) | /* surface object control state, FIXME??? */
 125                   ((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */
 126                   (0 << 2)  | /* must be 0 for interleave U/V */
 127                   (1 << 1)  | /* must be y-tiled */
 128                   (I965_TILEWALK_YMAJOR << 0));                         /* tile walk, TILEWALK_YMAJOR */
 129     OUT_BCS_BATCH(batch,
 130                   (0 << 16) |                                                           /* must be 0 for interleave U/V */
 131                   (mfc_context->surface_state.h_pitch));                /* y offset for U(cb) */
 132     OUT_BCS_BATCH(batch, 0);
 133     ADVANCE_BCS_BATCH(batch);
 134 }
 135
 136 void
 137 gen6_mfc_pipe_buf_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 138 {
 139     struct intel_batchbuffer *batch = encoder_context->base.batch;
 140     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 141     int i;
 142
 143     BEGIN_BCS_BATCH(batch, 24);
 144
 145     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
 146
 147     if (mfc_context->pre_deblocking_output.bo)
 148         OUT_BCS_RELOC(batch, mfc_context->pre_deblocking_output.bo,
 149                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 150                       0);
 151     else
 152         OUT_BCS_BATCH(batch, 0);                                                                                        /* pre output addr   */
 153
 154     if (mfc_context->post_deblocking_output.bo)
 155         OUT_BCS_RELOC(batch, mfc_context->post_deblocking_output.bo,
 156                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 157                       0);                                                                                       /* post output addr  */
 158     else
 159         OUT_BCS_BATCH(batch, 0);
 160
 161     OUT_BCS_RELOC(batch, mfc_context->uncompressed_picture_source.bo,
 162                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 163                   0);                                                                                   /* uncompressed data */
 164     OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
 165                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 166                   0);                                                                                   /* StreamOut data*/
 167     OUT_BCS_RELOC(batch, mfc_context->intra_row_store_scratch_buffer.bo,
 168                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 169                   0);
 170     OUT_BCS_RELOC(batch, mfc_context->deblocking_filter_row_store_scratch_buffer.bo,
 171                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 172                   0);
 173     /* 7..22 Reference pictures*/
 174     for (i = 0; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) {
 175         if ( mfc_context->reference_surfaces[i].bo != NULL) {
 176             OUT_BCS_RELOC(batch, mfc_context->reference_surfaces[i].bo,
 177                           I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 178                           0);
 179         } else {
 180             OUT_BCS_BATCH(batch, 0);
 181         }
 182     }
 183     OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
 184                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 185                   0);                                                                                   /* Macroblock status buffer*/
 186
 187     ADVANCE_BCS_BATCH(batch);
 188 }
 189
 190 static void
 191 gen6_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 192 {
 193     struct intel_batchbuffer *batch = encoder_context->base.batch;
 194     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 195     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 196
 197     BEGIN_BCS_BATCH(batch, 11);
 198
 199     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
 200     OUT_BCS_BATCH(batch, 0);
 201     OUT_BCS_BATCH(batch, 0);
 202     /* MFX Indirect MV Object Base Address */
 203     OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 204     OUT_BCS_BATCH(batch, 0);
 205     OUT_BCS_BATCH(batch, 0);
 206     OUT_BCS_BATCH(batch, 0);
 207     OUT_BCS_BATCH(batch, 0);
 208     OUT_BCS_BATCH(batch, 0);
 209     /*MFC Indirect PAK-BSE Object Base Address for Encoder*/
 210     OUT_BCS_RELOC(batch,
 211                   mfc_context->mfc_indirect_pak_bse_object.bo,
 212                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 213                   0);
 214     OUT_BCS_RELOC(batch,
 215                   mfc_context->mfc_indirect_pak_bse_object.bo,
 216                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 217                   mfc_context->mfc_indirect_pak_bse_object.end_offset);
 218
 219     ADVANCE_BCS_BATCH(batch);
 220 }
 221
 222 void
 223 gen6_mfc_bsp_buf_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 224 {
 225     struct intel_batchbuffer *batch = encoder_context->base.batch;
 226     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 227
 228     BEGIN_BCS_BATCH(batch, 4);
 229
 230     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
 231     OUT_BCS_RELOC(batch, mfc_context->bsd_mpc_row_store_scratch_buffer.bo,
 232                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 233                   0);
 234     OUT_BCS_BATCH(batch, 0);
 235     OUT_BCS_BATCH(batch, 0);
 236
 237     ADVANCE_BCS_BATCH(batch);
 238 }
 239
 240 static void
 241 gen6_mfc_avc_img_state(VADriverContextP ctx,struct encode_state *encode_state,
 242                        struct intel_encoder_context *encoder_context)
 243 {
 244     struct intel_batchbuffer *batch = encoder_context->base.batch;
 245     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 246     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 247     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 248     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 249     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 250
 251     BEGIN_BCS_BATCH(batch, 13);
 252     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (13 - 2));
 253     OUT_BCS_BATCH(batch,
 254                   ((width_in_mbs * height_in_mbs) & 0xFFFF));
 255     OUT_BCS_BATCH(batch,
 256                   (height_in_mbs << 16) |
 257                   (width_in_mbs << 0));
 258     OUT_BCS_BATCH(batch,
 259                   (0 << 24) |     /*Second Chroma QP Offset*/
 260                   (0 << 16) |     /*Chroma QP Offset*/
 261                   (0 << 14) |   /*Max-bit conformance Intra flag*/
 262                   (0 << 13) |   /*Max Macroblock size conformance Inter flag*/
 263                   (1 << 12) |   /*Should always be written as "1" */
 264                   (0 << 10) |   /*QM Preset FLag */
 265                   (0 << 8)  |   /*Image Structure*/
 266                   (0 << 0) );   /*Current Decoed Image Frame Store ID, reserved in Encode mode*/
 267     OUT_BCS_BATCH(batch,
 268                   (400 << 16) |   /*Mininum Frame size*/
 269                   (0 << 15) |   /*Disable reading of Macroblock Status Buffer*/
 270                   (0 << 14) |   /*Load BitStream Pointer only once, 1 slic 1 frame*/
 271                   (0 << 13) |   /*CABAC 0 word insertion test enable*/
 272                   (1 << 12) |   /*MVUnpackedEnable,compliant to DXVA*/
 273                   (1 << 10) |   /*Chroma Format IDC, 4:2:0*/
 274                   (pPicParameter->pic_fields.bits.entropy_coding_mode_flag << 7)  |   /*0:CAVLC encoding mode,1:CABAC*/
 275                   (0 << 6)  |   /*Only valid for VLD decoding mode*/
 276                   (0 << 5)  |   /*Constrained Intra Predition Flag, from PPS*/
 277                   (pSequenceParameter->seq_fields.bits.direct_8x8_inference_flag << 4)  |   /*Direct 8x8 inference flag*/
 278                   (pPicParameter->pic_fields.bits.transform_8x8_mode_flag << 3)  |   /*8x8 or 4x4 IDCT Transform Mode Flag*/
 279                   (1 << 2)  |   /*Frame MB only flag*/
 280                   (0 << 1)  |   /*MBAFF mode is in active*/
 281                   (0 << 0) );   /*Field picture flag*/
 282     OUT_BCS_BATCH(batch,
 283                   (1<<16)   |   /*Frame Size Rate Control Flag*/
 284                   (1<<12)   |
 285                   (1<<9)    |   /*MB level Rate Control Enabling Flag*/
 286                   (1 << 3)  |   /*FrameBitRateMinReportMask*/
 287                   (1 << 2)  |   /*FrameBitRateMaxReportMask*/
 288                   (1 << 1)  |   /*InterMBMaxSizeReportMask*/
 289                   (1 << 0) );   /*IntraMBMaxSizeReportMask*/
 290     OUT_BCS_BATCH(batch,                        /*Inter and Intra Conformance Max size limit*/
 291                   (0x0600 << 16) |              /*InterMbMaxSz 192 Byte*/
 292                   (0x0800) );                   /*IntraMbMaxSz 256 Byte*/
 293     OUT_BCS_BATCH(batch, 0x00000000);   /*Reserved : MBZReserved*/
 294     OUT_BCS_BATCH(batch, 0x01020304);   /*Slice QP Delta for bitrate control*/
 295     OUT_BCS_BATCH(batch, 0xFEFDFCFB);
 296     OUT_BCS_BATCH(batch, 0x80601004);   /*MAX = 128KB, MIN = 64KB*/
 297     OUT_BCS_BATCH(batch, 0x00800001);
 298     OUT_BCS_BATCH(batch, 0);
 299
 300     ADVANCE_BCS_BATCH(batch);
 301 }
 302
 303 static void
 304 gen6_mfc_avc_directmode_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 305 {
 306     struct intel_batchbuffer *batch = encoder_context->base.batch;
 307     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 308
 309     int i;
 310
 311     BEGIN_BCS_BATCH(batch, 69);
 312
 313     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
 314
 315     /* Reference frames and Current frames */
 316     for(i = 0; i < NUM_MFC_DMV_BUFFERS; i++) {
 317         if ( mfc_context->direct_mv_buffers[i].bo != NULL) {
 318             OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[i].bo,
 319                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 320                           0);
 321         } else {
 322             OUT_BCS_BATCH(batch, 0);
 323         }
 324     }
 325
 326     /* POL list */
 327     for(i = 0; i < 32; i++) {
 328         OUT_BCS_BATCH(batch, i/2);
 329     }
 330     OUT_BCS_BATCH(batch, 0);
 331     OUT_BCS_BATCH(batch, 0);
 332
 333     ADVANCE_BCS_BATCH(batch);
 334 }
 335
 336 static void
 337 gen6_mfc_avc_slice_state(VADriverContextP ctx,
 338                          VAEncPictureParameterBufferH264 *pic_param,
 339                          VAEncSliceParameterBufferH264 *slice_param,
 340                          struct encode_state *encode_state,
 341                          struct intel_encoder_context *encoder_context,
 342                          int rate_control_enable,
 343                          int qp,
 344                          struct intel_batchbuffer *batch)
 345 {
 346     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 347     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 348     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 349     int beginmb = slice_param->macroblock_address;
 350     int endmb = beginmb + slice_param->num_macroblocks;
 351     int beginx = beginmb % width_in_mbs;
 352     int beginy = beginmb / width_in_mbs;
 353     int nextx =  endmb % width_in_mbs;
 354     int nexty = endmb / width_in_mbs;
 355     int slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
 356     int last_slice = (endmb == (width_in_mbs * height_in_mbs));
 357     int maxQpN, maxQpP;
 358     unsigned char correct[6], grow, shrink;
 359     int i;
 360     int weighted_pred_idc = 0;
 361     unsigned int luma_log2_weight_denom = slice_param->luma_log2_weight_denom;
 362     unsigned int chroma_log2_weight_denom = slice_param->chroma_log2_weight_denom;
 363     int bslice = 0;
 364
 365     if (batch == NULL)
 366         batch = encoder_context->base.batch;
 367
 368     if (slice_type == SLICE_TYPE_P) {
 369         weighted_pred_idc = pic_param->pic_fields.bits.weighted_pred_flag;
 370     } else if (slice_type == SLICE_TYPE_B) {
 371         weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc;
 372         bslice = 1;
 373
 374         if (weighted_pred_idc == 2) {
 375             /* 8.4.3 - Derivation process for prediction weights (8-279) */
 376             luma_log2_weight_denom = 5;
 377             chroma_log2_weight_denom = 5;
 378         }
 379     }
 380
 381     maxQpN = mfc_context->bit_rate_control_context[slice_type].MaxQpNegModifier;
 382     maxQpP = mfc_context->bit_rate_control_context[slice_type].MaxQpPosModifier;
 383
 384     for (i = 0; i < 6; i++)
 385         correct[i] = mfc_context->bit_rate_control_context[slice_type].Correct[i];
 386
 387     grow = mfc_context->bit_rate_control_context[slice_type].GrowInit +
 388         (mfc_context->bit_rate_control_context[slice_type].GrowResistance << 4);
 389     shrink = mfc_context->bit_rate_control_context[slice_type].ShrinkInit +
 390         (mfc_context->bit_rate_control_context[slice_type].ShrinkResistance << 4);
 391
 392     BEGIN_BCS_BATCH(batch, 11);;
 393
 394     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) );
 395     OUT_BCS_BATCH(batch, slice_type);                   /*Slice Type: I:P:B Slice*/
 396
 397     if (slice_type == SLICE_TYPE_I) {
 398         OUT_BCS_BATCH(batch, 0);                        /*no reference frames and pred_weight_table*/
 399     } else {
 400         OUT_BCS_BATCH(batch,
 401                       (1 << 16) | (bslice << 24) |     /*1 reference frame*/
 402                       (chroma_log2_weight_denom << 8) |
 403                       (luma_log2_weight_denom << 0));
 404     }
 405
 406     OUT_BCS_BATCH(batch,
 407                   (weighted_pred_idc << 30) |
 408                   (slice_param->direct_spatial_mv_pred_flag<<29) |             /*Direct Prediction Type*/
 409                   (slice_param->disable_deblocking_filter_idc << 27) |
 410                   (slice_param->cabac_init_idc << 24) |
 411                   (qp<<16) |                    /*Slice Quantization Parameter*/
 412                   ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
 413                   ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
 414     OUT_BCS_BATCH(batch,
 415                   (beginy << 24) |                      /*First MB X&Y , the begin postion of current slice*/
 416                   (beginx << 16) |
 417                   slice_param->macroblock_address );
 418     OUT_BCS_BATCH(batch, (nexty << 16) | nextx);                       /*Next slice first MB X&Y*/
 419     OUT_BCS_BATCH(batch,
 420                   (0/*rate_control_enable*/ << 31) |            /*in CBR mode RateControlCounterEnable = enable*/
 421                   (1 << 30) |           /*ResetRateControlCounter*/
 422                   (0 << 28) |           /*RC Triggle Mode = Always Rate Control*/
 423                   (4 << 24) |     /*RC Stable Tolerance, middle level*/
 424                   (0/*rate_control_enable*/ << 23) |     /*RC Panic Enable*/
 425                   (0 << 22) |     /*QP mode, don't modfiy CBP*/
 426                   (0 << 21) |     /*MB Type Direct Conversion Enabled*/
 427                   (0 << 20) |     /*MB Type Skip Conversion Enabled*/
 428                   (last_slice << 19) |     /*IsLastSlice*/
 429                   (0 << 18) |   /*BitstreamOutputFlag Compressed BitStream Output Disable Flag 0:enable 1:disable*/
 430                   (1 << 17) |       /*HeaderPresentFlag*/
 431                   (1 << 16) |       /*SliceData PresentFlag*/
 432                   (1 << 15) |       /*TailPresentFlag*/
 433                   (1 << 13) |       /*RBSP NAL TYPE*/
 434                   (0 << 12) );    /*CabacZeroWordInsertionEnable*/
 435     OUT_BCS_BATCH(batch, mfc_context->mfc_indirect_pak_bse_object.offset);
 436     OUT_BCS_BATCH(batch,
 437                   (maxQpN << 24) |     /*Target QP - 24 is lowest QP*/
 438                   (maxQpP << 16) |     /*Target QP + 20 is highest QP*/
 439                   (shrink << 8)  |
 440                   (grow << 0));
 441     OUT_BCS_BATCH(batch,
 442                   (correct[5] << 20) |
 443                   (correct[4] << 16) |
 444                   (correct[3] << 12) |
 445                   (correct[2] << 8) |
 446                   (correct[1] << 4) |
 447                   (correct[0] << 0));
 448     OUT_BCS_BATCH(batch, 0);
 449
 450     ADVANCE_BCS_BATCH(batch);
 451 }
 452
 453 static void gen6_mfc_avc_qm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 454 {
 455     struct intel_batchbuffer *batch = encoder_context->base.batch;
 456     int i;
 457
 458     BEGIN_BCS_BATCH(batch, 58);
 459
 460     OUT_BCS_BATCH(batch, MFX_AVC_QM_STATE | 56);
 461     OUT_BCS_BATCH(batch, 0xFF ) ;
 462     for( i = 0; i < 56; i++) {
 463         OUT_BCS_BATCH(batch, 0x10101010);
 464     }
 465
 466     ADVANCE_BCS_BATCH(batch);
 467 }
 468
 469 static void gen6_mfc_avc_fqm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 470 {
 471     struct intel_batchbuffer *batch = encoder_context->base.batch;
 472     int i;
 473
 474     BEGIN_BCS_BATCH(batch, 113);
 475     OUT_BCS_BATCH(batch, MFC_AVC_FQM_STATE | (113 - 2));
 476
 477     for(i = 0; i < 112;i++) {
 478         OUT_BCS_BATCH(batch, 0x10001000);
 479     }
 480
 481     ADVANCE_BCS_BATCH(batch);
 482 }
 483
 484 static void
 485 gen6_mfc_avc_insert_object(VADriverContextP ctx, struct intel_encoder_context *encoder_context,
 486                            unsigned int *insert_data, int lenght_in_dws, int data_bits_in_last_dw,
 487                            int skip_emul_byte_count, int is_last_header, int is_end_of_slice, int emulation_flag,
 488                            struct intel_batchbuffer *batch)
 489 {
 490     if (batch == NULL)
 491         batch = encoder_context->base.batch;
 492
 493     BEGIN_BCS_BATCH(batch, lenght_in_dws + 2);
 494
 495     OUT_BCS_BATCH(batch, MFC_AVC_INSERT_OBJECT | (lenght_in_dws + 2 - 2));
 496
 497     OUT_BCS_BATCH(batch,
 498                   (0 << 16) |   /* always start at offset 0 */
 499                   (data_bits_in_last_dw << 8) |
 500                   (skip_emul_byte_count << 4) |
 501                   (!!emulation_flag << 3) |
 502                   ((!!is_last_header) << 2) |
 503                   ((!!is_end_of_slice) << 1) |
 504                   (0 << 0));    /* FIXME: ??? */
 505
 506     intel_batchbuffer_data(batch, insert_data, lenght_in_dws * 4);
 507     ADVANCE_BCS_BATCH(batch);
 508 }
 509
 510 void
 511 gen6_mfc_init(VADriverContextP ctx,
 512               struct encode_state *encode_state,
 513               struct intel_encoder_context *encoder_context)
 514 {
 515     struct i965_driver_data *i965 = i965_driver_data(ctx);
 516     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 517     dri_bo *bo;
 518     int i;
 519     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 520     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 521     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 522
 523     /*Encode common setup for MFC*/
 524     dri_bo_unreference(mfc_context->post_deblocking_output.bo);
 525     mfc_context->post_deblocking_output.bo = NULL;
 526
 527     dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
 528     mfc_context->pre_deblocking_output.bo = NULL;
 529
 530     dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
 531     mfc_context->uncompressed_picture_source.bo = NULL;
 532
 533     dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
 534     mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
 535
 536     for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
 537         if ( mfc_context->direct_mv_buffers[i].bo != NULL);
 538         dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
 539         mfc_context->direct_mv_buffers[i].bo = NULL;
 540     }
 541
 542     for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
 543         if (mfc_context->reference_surfaces[i].bo != NULL)
 544             dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
 545         mfc_context->reference_surfaces[i].bo = NULL;
 546     }
 547
 548     dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
 549     bo = dri_bo_alloc(i965->intel.bufmgr,
 550                       "Buffer",
 551                       width_in_mbs * 64,
 552                       64);
 553     assert(bo);
 554     mfc_context->intra_row_store_scratch_buffer.bo = bo;
 555
 556     dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
 557     bo = dri_bo_alloc(i965->intel.bufmgr,
 558                       "Buffer",
 559                       width_in_mbs * height_in_mbs * 16,
 560                       64);
 561     assert(bo);
 562     mfc_context->macroblock_status_buffer.bo = bo;
 563
 564     dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
 565     bo = dri_bo_alloc(i965->intel.bufmgr,
 566                       "Buffer",
 567                       4 * width_in_mbs * 64,  /* 4 * width_in_mbs * 64 */
 568                       64);
 569     assert(bo);
 570     mfc_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
 571
 572     dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
 573     bo = dri_bo_alloc(i965->intel.bufmgr,
 574                       "Buffer",
 575                       128 * width_in_mbs, /* 2 * widht_in_mbs * 64 */
 576                       0x1000);
 577     assert(bo);
 578     mfc_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
 579
 580     dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo);
 581     mfc_context->mfc_batchbuffer_surface.bo = NULL;
 582
 583     dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo);
 584     mfc_context->aux_batchbuffer_surface.bo = NULL;
 585
 586     if (mfc_context->aux_batchbuffer)
 587         intel_batchbuffer_free(mfc_context->aux_batchbuffer);
 588
 589     mfc_context->aux_batchbuffer = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD, 0);
 590     mfc_context->aux_batchbuffer_surface.bo = mfc_context->aux_batchbuffer->buffer;
 591     dri_bo_reference(mfc_context->aux_batchbuffer_surface.bo);
 592     mfc_context->aux_batchbuffer_surface.pitch = 16;
 593     mfc_context->aux_batchbuffer_surface.num_blocks = mfc_context->aux_batchbuffer->size / 16;
 594     mfc_context->aux_batchbuffer_surface.size_block = 16;
 595
 596     i965_gpe_context_init(ctx, &mfc_context->gpe_context);
 597 }
 598
 599 static void gen6_mfc_avc_pipeline_picture_programing( VADriverContextP ctx,
 600                                       struct encode_state *encode_state,
 601                                       struct intel_encoder_context *encoder_context)
 602 {
 603     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 604
 605     mfc_context->pipe_mode_select(ctx, MFX_FORMAT_AVC, encoder_context);
 606     mfc_context->set_surface_state(ctx, encoder_context);
 607     mfc_context->ind_obj_base_addr_state(ctx, encoder_context);
 608     gen6_mfc_pipe_buf_addr_state(ctx, encoder_context);
 609     gen6_mfc_bsp_buf_base_addr_state(ctx, encoder_context);
 610     mfc_context->avc_img_state(ctx, encode_state, encoder_context);
 611     mfc_context->avc_qm_state(ctx, encoder_context);
 612     mfc_context->avc_fqm_state(ctx, encoder_context);
 613     gen6_mfc_avc_directmode_state(ctx, encoder_context);
 614     intel_mfc_avc_ref_idx_state(ctx, encoder_context);
 615 }
 616
 617
 618 VAStatus
 619 gen6_mfc_run(VADriverContextP ctx,
 620              struct encode_state *encode_state,
 621              struct intel_encoder_context *encoder_context)
 622 {
 623     struct intel_batchbuffer *batch = encoder_context->base.batch;
 624
 625     intel_batchbuffer_flush(batch);             //run the pipeline
 626
 627     return VA_STATUS_SUCCESS;
 628 }
 629
 630 VAStatus
 631 gen6_mfc_stop(VADriverContextP ctx,
 632               struct encode_state *encode_state,
 633               struct intel_encoder_context *encoder_context,
 634               int *encoded_bits_size)
 635 {
 636     VAStatus vaStatus = VA_STATUS_ERROR_UNKNOWN;
 637     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 638     VACodedBufferSegment *coded_buffer_segment;
 639
 640     vaStatus = i965_MapBuffer(ctx, pPicParameter->coded_buf, (void **)&coded_buffer_segment);
 641     assert(vaStatus == VA_STATUS_SUCCESS);
 642     *encoded_bits_size = coded_buffer_segment->size * 8;
 643     i965_UnmapBuffer(ctx, pPicParameter->coded_buf);
 644
 645     return VA_STATUS_SUCCESS;
 646 }
 647
 648 #if __SOFTWARE__
 649
 650 static int
 651 gen6_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb, int qp,unsigned int *msg,
 652                               struct intel_encoder_context *encoder_context,
 653                               unsigned char target_mb_size, unsigned char max_mb_size,
 654                               struct intel_batchbuffer *batch)
 655 {
 656     int len_in_dwords = 11;
 657
 658     if (batch == NULL)
 659         batch = encoder_context->base.batch;
 660
 661     BEGIN_BCS_BATCH(batch, len_in_dwords);
 662
 663     OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
 664     OUT_BCS_BATCH(batch, 0);
 665     OUT_BCS_BATCH(batch, 0);
 666     OUT_BCS_BATCH(batch,
 667                   (0 << 24) |           /* PackedMvNum, Debug*/
 668                   (0 << 20) |           /* No motion vector */
 669                   (1 << 19) |           /* CbpDcY */
 670                   (1 << 18) |           /* CbpDcU */
 671                   (1 << 17) |           /* CbpDcV */
 672                   (msg[0] & 0xFFFF) );
 673
 674     OUT_BCS_BATCH(batch, (0xFFFF << 16) | (y << 8) | x);                /* Code Block Pattern for Y*/
 675     OUT_BCS_BATCH(batch, 0x000F000F);                                                   /* Code Block Pattern */
 676     OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp);      /* Last MB */
 677
 678     /*Stuff for Intra MB*/
 679     OUT_BCS_BATCH(batch, msg[1]);                       /* We using Intra16x16 no 4x4 predmode*/
 680     OUT_BCS_BATCH(batch, msg[2]);
 681     OUT_BCS_BATCH(batch, msg[3]&0xFC);
 682
 683     /*MaxSizeInWord and TargetSzieInWord*/
 684     OUT_BCS_BATCH(batch, (max_mb_size << 24) |
 685                   (target_mb_size << 16) );
 686
 687     ADVANCE_BCS_BATCH(batch);
 688
 689     return len_in_dwords;
 690 }
 691
 692 static int
 693 gen6_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, int qp,
 694                               unsigned int *msg, unsigned int offset,
 695                               struct intel_encoder_context *encoder_context,
 696                               unsigned char target_mb_size,unsigned char max_mb_size, int slice_type,
 697                               struct intel_batchbuffer *batch)
 698 {
 699     int len_in_dwords = 11;
 700
 701     if (batch == NULL)
 702         batch = encoder_context->base.batch;
 703
 704     BEGIN_BCS_BATCH(batch, len_in_dwords);
 705
 706     OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
 707
 708     OUT_BCS_BATCH(batch, msg[2]);         /* 32 MV*/
 709     OUT_BCS_BATCH(batch, offset);
 710
 711     OUT_BCS_BATCH(batch, msg[0]);
 712
 713     OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x);        /* Code Block Pattern for Y*/
 714     OUT_BCS_BATCH(batch, 0x000F000F);                         /* Code Block Pattern */
 715 #if 0
 716     if ( slice_type == SLICE_TYPE_B) {
 717         OUT_BCS_BATCH(batch, (0xF<<28) | (end_mb << 26) | qp);  /* Last MB */
 718     } else {
 719         OUT_BCS_BATCH(batch, (end_mb << 26) | qp);      /* Last MB */
 720     }
 721 #else
 722     OUT_BCS_BATCH(batch, (end_mb << 26) | qp);  /* Last MB */
 723 #endif
 724
 725
 726     /*Stuff for Inter MB*/
 727     OUT_BCS_BATCH(batch, msg[1]);
 728     OUT_BCS_BATCH(batch, 0x0);
 729     OUT_BCS_BATCH(batch, 0x0);
 730
 731     /*MaxSizeInWord and TargetSzieInWord*/
 732     OUT_BCS_BATCH(batch, (max_mb_size << 24) |
 733                   (target_mb_size << 16) );
 734
 735     ADVANCE_BCS_BATCH(batch);
 736
 737     return len_in_dwords;
 738 }
 739
 740 static void
 741 gen6_mfc_avc_pipeline_slice_programing(VADriverContextP ctx,
 742                                        struct encode_state *encode_state,
 743                                        struct intel_encoder_context *encoder_context,
 744                                        int slice_index,
 745                                        struct intel_batchbuffer *slice_batch)
 746 {
 747     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 748     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 749     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 750     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 751     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
 752     unsigned int *msg = NULL, offset = 0;
 753     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 754     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 755     int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs);
 756     int i,x,y;
 757     int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta;
 758     unsigned int rate_control_mode = encoder_context->rate_control_mode;
 759     unsigned char *slice_header = NULL;
 760     int slice_header_length_in_bits = 0;
 761     unsigned int tail_data[] = { 0x0, 0x0 };
 762     int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type);
 763     int is_intra = slice_type == SLICE_TYPE_I;
 764
 765     if (rate_control_mode == VA_RC_CBR) {
 766         qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
 767         pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp;
 768     }
 769
 770     /* only support for 8-bit pixel bit-depth */
 771     assert(pSequenceParameter->bit_depth_luma_minus8 == 0);
 772     assert(pSequenceParameter->bit_depth_chroma_minus8 == 0);
 773     assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52);
 774     assert(qp >= 0 && qp < 52);
 775
 776     gen6_mfc_avc_slice_state(ctx,
 777                              pPicParameter,
 778                              pSliceParameter,
 779                              encode_state, encoder_context,
 780                              (rate_control_mode == VA_RC_CBR), qp, slice_batch);
 781
 782     if ( slice_index == 0)
 783         intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch);
 784
 785     slice_header_length_in_bits = build_avc_slice_header(pSequenceParameter, pPicParameter, pSliceParameter, &slice_header);
 786
 787     // slice hander
 788     mfc_context->insert_object(ctx, encoder_context,
 789                                (unsigned int *)slice_header, ALIGN(slice_header_length_in_bits, 32) >> 5, slice_header_length_in_bits & 0x1f,
 790                                5,  /* first 5 bytes are start code + nal unit type */
 791                                1, 0, 1, slice_batch);
 792
 793     dri_bo_map(vme_context->vme_output.bo , 1);
 794     msg = (unsigned int *)vme_context->vme_output.bo->virtual;
 795
 796     if (is_intra) {
 797         msg += pSliceParameter->macroblock_address * INTRA_VME_OUTPUT_IN_DWS;
 798     } else {
 799         msg += pSliceParameter->macroblock_address * INTER_VME_OUTPUT_IN_DWS;
 800         msg += 32; /* the first 32 DWs are MVs */
 801         offset = pSliceParameter->macroblock_address * INTER_VME_OUTPUT_IN_BYTES;
 802     }
 803
 804     for (i = pSliceParameter->macroblock_address;
 805          i < pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks; i++) {
 806         int last_mb = (i == (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks - 1) );
 807         x = i % width_in_mbs;
 808         y = i / width_in_mbs;
 809
 810         if (is_intra) {
 811             assert(msg);
 812             gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch);
 813             msg += INTRA_VME_OUTPUT_IN_DWS;
 814         } else {
 815             if (msg[0] & INTRA_MB_FLAG_MASK) {
 816                 gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch);
 817             } else {
 818                 gen6_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, msg, offset, encoder_context, 0, 0, slice_type, slice_batch);
 819             }
 820
 821             msg += INTER_VME_OUTPUT_IN_DWS;
 822             offset += INTER_VME_OUTPUT_IN_BYTES;
 823         }
 824     }
 825
 826     dri_bo_unmap(vme_context->vme_output.bo);
 827
 828     if ( last_slice ) {
 829         mfc_context->insert_object(ctx, encoder_context,
 830                                    tail_data, 2, 8,
 831                                    2, 1, 1, 0, slice_batch);
 832     } else {
 833         mfc_context->insert_object(ctx, encoder_context,
 834                                    tail_data, 1, 8,
 835                                    1, 1, 1, 0, slice_batch);
 836     }
 837
 838     free(slice_header);
 839
 840 }
 841
 842 static dri_bo *
 843 gen6_mfc_avc_software_batchbuffer(VADriverContextP ctx,
 844                                   struct encode_state *encode_state,
 845                                   struct intel_encoder_context *encoder_context)
 846 {
 847     struct i965_driver_data *i965 = i965_driver_data(ctx);
 848     struct intel_batchbuffer *batch = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD, 0);
 849     dri_bo *batch_bo = batch->buffer;
 850     int i;
 851
 852     for (i = 0; i < encode_state->num_slice_params_ext; i++) {
 853         gen6_mfc_avc_pipeline_slice_programing(ctx, encode_state, encoder_context, i, batch);
 854     }
 855
 856     intel_batchbuffer_align(batch, 8);
 857
 858     BEGIN_BCS_BATCH(batch, 2);
 859     OUT_BCS_BATCH(batch, 0);
 860     OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_END);
 861     ADVANCE_BCS_BATCH(batch);
 862
 863     dri_bo_reference(batch_bo);
 864     intel_batchbuffer_free(batch);
 865
 866     return batch_bo;
 867 }
 868
 869 #else
 870
 871 static void
 872 gen6_mfc_batchbuffer_surfaces_input(VADriverContextP ctx,
 873                                     struct encode_state *encode_state,
 874                                     struct intel_encoder_context *encoder_context)
 875
 876 {
 877     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 878     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 879
 880     assert(vme_context->vme_output.bo);
 881     mfc_context->buffer_suface_setup(ctx,
 882                                      &mfc_context->gpe_context,
 883                                      &vme_context->vme_output,
 884                                      BINDING_TABLE_OFFSET(BIND_IDX_VME_OUTPUT),
 885                                      SURFACE_STATE_OFFSET(BIND_IDX_VME_OUTPUT));
 886     assert(mfc_context->aux_batchbuffer_surface.bo);
 887     mfc_context->buffer_suface_setup(ctx,
 888                                      &mfc_context->gpe_context,
 889                                      &mfc_context->aux_batchbuffer_surface,
 890                                      BINDING_TABLE_OFFSET(BIND_IDX_MFC_SLICE_HEADER),
 891                                      SURFACE_STATE_OFFSET(BIND_IDX_MFC_SLICE_HEADER));
 892 }
 893
 894 static void
 895 gen6_mfc_batchbuffer_surfaces_output(VADriverContextP ctx,
 896                                      struct encode_state *encode_state,
 897                                      struct intel_encoder_context *encoder_context)
 898
 899 {
 900     struct i965_driver_data *i965 = i965_driver_data(ctx);
 901     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 902     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 903     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 904     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 905     mfc_context->mfc_batchbuffer_surface.num_blocks = width_in_mbs * height_in_mbs + encode_state->num_slice_params_ext * 8 + 1;
 906     mfc_context->mfc_batchbuffer_surface.size_block = 16 * CMD_LEN_IN_OWORD; /* 3 OWORDs */
 907     mfc_context->mfc_batchbuffer_surface.pitch = 16;
 908     mfc_context->mfc_batchbuffer_surface.bo = dri_bo_alloc(i965->intel.bufmgr,
 909                                                            "MFC batchbuffer",
 910                                                            mfc_context->mfc_batchbuffer_surface.num_blocks * mfc_context->mfc_batchbuffer_surface.size_block,
 911                                                            0x1000);
 912     mfc_context->buffer_suface_setup(ctx,
 913                                      &mfc_context->gpe_context,
 914                                      &mfc_context->mfc_batchbuffer_surface,
 915                                      BINDING_TABLE_OFFSET(BIND_IDX_MFC_BATCHBUFFER),
 916                                      SURFACE_STATE_OFFSET(BIND_IDX_MFC_BATCHBUFFER));
 917 }
 918
 919 static void
 920 gen6_mfc_batchbuffer_surfaces_setup(VADriverContextP ctx,
 921                                     struct encode_state *encode_state,
 922                                     struct intel_encoder_context *encoder_context)
 923 {
 924     gen6_mfc_batchbuffer_surfaces_input(ctx, encode_state, encoder_context);
 925     gen6_mfc_batchbuffer_surfaces_output(ctx, encode_state, encoder_context);
 926 }
 927
 928 static void
 929 gen6_mfc_batchbuffer_idrt_setup(VADriverContextP ctx,
 930                                 struct encode_state *encode_state,
 931                                 struct intel_encoder_context *encoder_context)
 932 {
 933     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 934     struct gen6_interface_descriptor_data *desc;
 935     int i;
 936     dri_bo *bo;
 937
 938     bo = mfc_context->gpe_context.idrt.bo;
 939     dri_bo_map(bo, 1);
 940     assert(bo->virtual);
 941     desc = bo->virtual;
 942
 943     for (i = 0; i < mfc_context->gpe_context.num_kernels; i++) {
 944         struct i965_kernel *kernel;
 945
 946         kernel = &mfc_context->gpe_context.kernels[i];
 947         assert(sizeof(*desc) == 32);
 948
 949         /*Setup the descritor table*/
 950         memset(desc, 0, sizeof(*desc));
 951         desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6);
 952         desc->desc2.sampler_count = 0;
 953         desc->desc2.sampler_state_pointer = 0;
 954         desc->desc3.binding_table_entry_count = 2;
 955         desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5);
 956         desc->desc4.constant_urb_entry_read_offset = 0;
 957         desc->desc4.constant_urb_entry_read_length = 4;
 958
 959         /*kernel start*/
 960         dri_bo_emit_reloc(bo,
 961                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 962                           0,
 963                           i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0),
 964                           kernel->bo);
 965         desc++;
 966     }
 967
 968     dri_bo_unmap(bo);
 969 }
 970
 971 static void
 972 gen6_mfc_batchbuffer_constant_setup(VADriverContextP ctx,
 973                                     struct encode_state *encode_state,
 974                                     struct intel_encoder_context *encoder_context)
 975 {
 976     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 977
 978     (void)mfc_context;
 979 }
 980
 981 static void
 982 gen6_mfc_batchbuffer_emit_object_command(struct intel_batchbuffer *batch,
 983                                          int index,
 984                                          int head_offset,
 985                                          int batchbuffer_offset,
 986                                          int head_size,
 987                                          int tail_size,
 988                                          int number_mb_cmds,
 989                                          int first_object,
 990                                          int last_object,
 991                                          int last_slice,
 992                                          int mb_x,
 993                                          int mb_y,
 994                                          int width_in_mbs,
 995                                          int qp)
 996 {
 997     BEGIN_BATCH(batch, 12);
 998
 999     OUT_BATCH(batch, CMD_MEDIA_OBJECT | (12 - 2));
1000     OUT_BATCH(batch, index);
1001     OUT_BATCH(batch, 0);
1002     OUT_BATCH(batch, 0);
1003     OUT_BATCH(batch, 0);
1004     OUT_BATCH(batch, 0);
1005
1006     /*inline data */
1007     OUT_BATCH(batch, head_offset);
1008     OUT_BATCH(batch, batchbuffer_offset);
1009     OUT_BATCH(batch,
1010               head_size << 16 |
1011               tail_size);
1012     OUT_BATCH(batch,
1013               number_mb_cmds << 16 |
1014               first_object << 2 |
1015               last_object << 1 |
1016               last_slice);
1017     OUT_BATCH(batch,
1018               mb_y << 8 |
1019               mb_x);
1020     OUT_BATCH(batch,
1021               qp << 16 |
1022               width_in_mbs);
1023
1024     ADVANCE_BATCH(batch);
1025 }
1026
1027 static void
1028 gen6_mfc_avc_batchbuffer_slice_command(VADriverContextP ctx,
1029                                        struct intel_encoder_context *encoder_context,
1030                                        VAEncSliceParameterBufferH264 *slice_param,
1031                                        int head_offset,
1032                                        unsigned short head_size,
1033                                        unsigned short tail_size,
1034                                        int batchbuffer_offset,
1035                                        int qp,
1036                                        int last_slice)
1037 {
1038     struct intel_batchbuffer *batch = encoder_context->base.batch;
1039     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1040     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
1041     int total_mbs = slice_param->num_macroblocks;
1042     int number_mb_cmds = 128;
1043     int starting_mb = 0;
1044     int last_object = 0;
1045     int first_object = 1;
1046     int i;
1047     int mb_x, mb_y;
1048     int index = (slice_param->slice_type == SLICE_TYPE_I) ? MFC_BATCHBUFFER_AVC_INTRA : MFC_BATCHBUFFER_AVC_INTER;
1049
1050     for (i = 0; i < total_mbs / number_mb_cmds; i++) {
1051         last_object = (total_mbs - starting_mb) == number_mb_cmds;
1052         mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs;
1053         mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs;
1054         assert(mb_x <= 255 && mb_y <= 255);
1055
1056         starting_mb += number_mb_cmds;
1057
1058         gen6_mfc_batchbuffer_emit_object_command(batch,
1059                                                  index,
1060                                                  head_offset,
1061                                                  batchbuffer_offset,
1062                                                  head_size,
1063                                                  tail_size,
1064                                                  number_mb_cmds,
1065                                                  first_object,
1066                                                  last_object,
1067                                                  last_slice,
1068                                                  mb_x,
1069                                                  mb_y,
1070                                                  width_in_mbs,
1071                                                  qp);
1072
1073         if (first_object) {
1074             head_offset += head_size;
1075             batchbuffer_offset += head_size;
1076         }
1077
1078         if (last_object) {
1079             head_offset += tail_size;
1080             batchbuffer_offset += tail_size;
1081         }
1082
1083         batchbuffer_offset += number_mb_cmds * CMD_LEN_IN_OWORD;
1084
1085         first_object = 0;
1086     }
1087
1088     if (!last_object) {
1089         last_object = 1;
1090         number_mb_cmds = total_mbs % number_mb_cmds;
1091         mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs;
1092         mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs;
1093         assert(mb_x <= 255 && mb_y <= 255);
1094         starting_mb += number_mb_cmds;
1095
1096         gen6_mfc_batchbuffer_emit_object_command(batch,
1097                                                  index,
1098                                                  head_offset,
1099                                                  batchbuffer_offset,
1100                                                  head_size,
1101                                                  tail_size,
1102                                                  number_mb_cmds,
1103                                                  first_object,
1104                                                  last_object,
1105                                                  last_slice,
1106                                                  mb_x,
1107                                                  mb_y,
1108                                                  width_in_mbs,
1109                                                  qp);
1110     }
1111 }
1112
1113 /*
1114  * return size in Owords (16bytes)
1115  */
1116 static int
1117 gen6_mfc_avc_batchbuffer_slice(VADriverContextP ctx,
1118                                struct encode_state *encode_state,
1119                                struct intel_encoder_context *encoder_context,
1120                                int slice_index,
1121                                int batchbuffer_offset)
1122 {
1123     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1124     struct intel_batchbuffer *slice_batch = mfc_context->aux_batchbuffer;
1125     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
1126     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
1127     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
1128     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
1129     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
1130     int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs);
1131     int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta;
1132     unsigned int rate_control_mode = encoder_context->rate_control_mode;
1133     unsigned char *slice_header = NULL;
1134     int slice_header_length_in_bits = 0;
1135     unsigned int tail_data[] = { 0x0, 0x0 };
1136     long head_offset;
1137     int old_used = intel_batchbuffer_used_size(slice_batch), used;
1138     unsigned short head_size, tail_size;
1139     int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type);
1140
1141     if (rate_control_mode == VA_RC_CBR) {
1142         qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
1143         pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp;
1144     }
1145
1146     /* only support for 8-bit pixel bit-depth */
1147     assert(pSequenceParameter->bit_depth_luma_minus8 == 0);
1148     assert(pSequenceParameter->bit_depth_chroma_minus8 == 0);
1149     assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52);
1150     assert(qp >= 0 && qp < 52);
1151
1152     head_offset = old_used / 16;
1153     gen6_mfc_avc_slice_state(ctx,
1154                              pPicParameter,
1155                              pSliceParameter,
1156                              encode_state,
1157                              encoder_context,
1158                              (rate_control_mode == VA_RC_CBR),
1159                              qp,
1160                              slice_batch);
1161
1162     if (slice_index == 0)
1163         intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch);
1164
1165     slice_header_length_in_bits = build_avc_slice_header(pSequenceParameter, pPicParameter, pSliceParameter, &slice_header);
1166
1167     // slice hander
1168     mfc_context->insert_object(ctx,
1169                                encoder_context,
1170                                (unsigned int *)slice_header,
1171                                ALIGN(slice_header_length_in_bits, 32) >> 5,
1172                                slice_header_length_in_bits & 0x1f,
1173                                5,  /* first 5 bytes are start code + nal unit type */
1174                                1,
1175                                0,
1176                                1,
1177                                slice_batch);
1178     free(slice_header);
1179
1180     intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */
1181     used = intel_batchbuffer_used_size(slice_batch);
1182     head_size = (used - old_used) / 16;
1183     old_used = used;
1184
1185     /* tail */
1186     if (last_slice) {
1187         mfc_context->insert_object(ctx,
1188                                    encoder_context,
1189                                    tail_data,
1190                                    2,
1191                                    8,
1192                                    2,
1193                                    1,
1194                                    1,
1195                                    0,
1196                                    slice_batch);
1197     } else {
1198         mfc_context->insert_object(ctx,
1199                                    encoder_context,
1200                                    tail_data,
1201                                    1,
1202                                    8,
1203                                    1,
1204                                    1,
1205                                    1,
1206                                    0,
1207                                    slice_batch);
1208     }
1209
1210     intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */
1211     used = intel_batchbuffer_used_size(slice_batch);
1212     tail_size = (used - old_used) / 16;
1213
1214
1215     gen6_mfc_avc_batchbuffer_slice_command(ctx,
1216                                            encoder_context,
1217                                            pSliceParameter,
1218                                            head_offset,
1219                                            head_size,
1220                                            tail_size,
1221                                            batchbuffer_offset,
1222                                            qp,
1223                                            last_slice);
1224
1225     return head_size + tail_size + pSliceParameter->num_macroblocks * CMD_LEN_IN_OWORD;
1226 }
1227
1228 static void
1229 gen6_mfc_avc_batchbuffer_pipeline(VADriverContextP ctx,
1230                                   struct encode_state *encode_state,
1231                                   struct intel_encoder_context *encoder_context)
1232 {
1233     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1234     struct intel_batchbuffer *batch = encoder_context->base.batch;
1235     int i, size, offset = 0;
1236     intel_batchbuffer_start_atomic(batch, 0x4000);
1237     gen6_gpe_pipeline_setup(ctx, &mfc_context->gpe_context, batch);
1238
1239     for ( i = 0; i < encode_state->num_slice_params_ext; i++) {
1240         size = gen6_mfc_avc_batchbuffer_slice(ctx, encode_state, encoder_context, i, offset);
1241         offset += size;
1242     }
1243
1244     intel_batchbuffer_end_atomic(batch);
1245     intel_batchbuffer_flush(batch);
1246 }
1247
1248 static void
1249 gen6_mfc_build_avc_batchbuffer(VADriverContextP ctx,
1250                                struct encode_state *encode_state,
1251                                struct intel_encoder_context *encoder_context)
1252 {
1253     gen6_mfc_batchbuffer_surfaces_setup(ctx, encode_state, encoder_context);
1254     gen6_mfc_batchbuffer_idrt_setup(ctx, encode_state, encoder_context);
1255     gen6_mfc_batchbuffer_constant_setup(ctx, encode_state, encoder_context);
1256     gen6_mfc_avc_batchbuffer_pipeline(ctx, encode_state, encoder_context);
1257 }
1258
1259 static dri_bo *
1260 gen6_mfc_avc_hardware_batchbuffer(VADriverContextP ctx,
1261                                   struct encode_state *encode_state,
1262                                   struct intel_encoder_context *encoder_context)
1263 {
1264     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1265
1266     gen6_mfc_build_avc_batchbuffer(ctx, encode_state, encoder_context);
1267     dri_bo_reference(mfc_context->mfc_batchbuffer_surface.bo);
1268
1269     return mfc_context->mfc_batchbuffer_surface.bo;
1270 }
1271
1272 #endif
1273
1274
1275 static void
1276 gen6_mfc_avc_pipeline_programing(VADriverContextP ctx,
1277                                  struct encode_state *encode_state,
1278                                  struct intel_encoder_context *encoder_context)
1279 {
1280     struct intel_batchbuffer *batch = encoder_context->base.batch;
1281     dri_bo *slice_batch_bo;
1282
1283     if ( intel_mfc_interlace_check(ctx, encode_state, encoder_context) ) {
1284         fprintf(stderr, "Current VA driver don't support interlace mode!\n");
1285         assert(0);
1286         return;
1287     }
1288
1289 #if __SOFTWARE__
1290     slice_batch_bo = gen6_mfc_avc_software_batchbuffer(ctx, encode_state, encoder_context);
1291 #else
1292     slice_batch_bo = gen6_mfc_avc_hardware_batchbuffer(ctx, encode_state, encoder_context);
1293 #endif
1294
1295     // begin programing
1296     intel_batchbuffer_start_atomic_bcs(batch, 0x4000);
1297     intel_batchbuffer_emit_mi_flush(batch);
1298
1299     // picture level programing
1300     gen6_mfc_avc_pipeline_picture_programing(ctx, encode_state, encoder_context);
1301
1302     BEGIN_BCS_BATCH(batch, 2);
1303     OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8));
1304     OUT_BCS_RELOC(batch,
1305                   slice_batch_bo,
1306                   I915_GEM_DOMAIN_COMMAND, 0,
1307                   0);
1308     ADVANCE_BCS_BATCH(batch);
1309
1310     // end programing
1311     intel_batchbuffer_end_atomic(batch);
1312
1313     dri_bo_unreference(slice_batch_bo);
1314 }
1315
1316 VAStatus
1317 gen6_mfc_avc_encode_picture(VADriverContextP ctx,
1318                             struct encode_state *encode_state,
1319                             struct intel_encoder_context *encoder_context)
1320 {
1321     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1322     unsigned int rate_control_mode = encoder_context->rate_control_mode;
1323     int current_frame_bits_size;
1324     int sts;
1325
1326     for (;;) {
1327         gen6_mfc_init(ctx, encode_state, encoder_context);
1328         intel_mfc_avc_prepare(ctx, encode_state, encoder_context);
1329         /*Programing bcs pipeline*/
1330         gen6_mfc_avc_pipeline_programing(ctx, encode_state, encoder_context);   //filling the pipeline
1331         gen6_mfc_run(ctx, encode_state, encoder_context);
1332         if (rate_control_mode == VA_RC_CBR /*|| rate_control_mode == VA_RC_VBR*/) {
1333             gen6_mfc_stop(ctx, encode_state, encoder_context, &current_frame_bits_size);
1334             sts = intel_mfc_brc_postpack(encode_state, mfc_context, current_frame_bits_size);
1335             if (sts == BRC_NO_HRD_VIOLATION) {
1336                 intel_mfc_hrd_context_update(encode_state, mfc_context);
1337                 break;
1338             }
1339             else if (sts == BRC_OVERFLOW_WITH_MIN_QP || sts == BRC_UNDERFLOW_WITH_MAX_QP) {
1340                 if (!mfc_context->hrd.violation_noted) {
1341                     fprintf(stderr, "Unrepairable %s!\n", (sts == BRC_OVERFLOW_WITH_MIN_QP)? "overflow": "underflow");
1342                     mfc_context->hrd.violation_noted = 1;
1343                 }
1344                 return VA_STATUS_SUCCESS;
1345             }
1346         } else {
1347             break;
1348         }
1349     }
1350
1351     return VA_STATUS_SUCCESS;
1352 }
1353
1354 VAStatus
1355 gen6_mfc_pipeline(VADriverContextP ctx,
1356                   VAProfile profile,
1357                   struct encode_state *encode_state,
1358                   struct intel_encoder_context *encoder_context)
1359 {
1360     VAStatus vaStatus;
1361
1362     switch (profile) {
1363     case VAProfileH264Baseline:
1364     case VAProfileH264Main:
1365     case VAProfileH264High:
1366         vaStatus = gen6_mfc_avc_encode_picture(ctx, encode_state, encoder_context);
1367         break;
1368
1369         /* FIXME: add for other profile */
1370     default:
1371         vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
1372         break;
1373     }
1374
1375     return vaStatus;
1376 }
1377
1378 void
1379 gen6_mfc_context_destroy(void *context)
1380 {
1381     struct gen6_mfc_context *mfc_context = context;
1382     int i;
1383
1384     dri_bo_unreference(mfc_context->post_deblocking_output.bo);
1385     mfc_context->post_deblocking_output.bo = NULL;
1386
1387     dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
1388     mfc_context->pre_deblocking_output.bo = NULL;
1389
1390     dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
1391     mfc_context->uncompressed_picture_source.bo = NULL;
1392
1393     dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
1394     mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
1395
1396     for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
1397         dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
1398         mfc_context->direct_mv_buffers[i].bo = NULL;
1399     }
1400
1401     dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
1402     mfc_context->intra_row_store_scratch_buffer.bo = NULL;
1403
1404     dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
1405     mfc_context->macroblock_status_buffer.bo = NULL;
1406
1407     dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
1408     mfc_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
1409
1410     dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
1411     mfc_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
1412
1413
1414     for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
1415         dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
1416         mfc_context->reference_surfaces[i].bo = NULL;
1417     }
1418
1419     i965_gpe_context_destroy(&mfc_context->gpe_context);
1420
1421     dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo);
1422     mfc_context->mfc_batchbuffer_surface.bo = NULL;
1423
1424     dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo);
1425     mfc_context->aux_batchbuffer_surface.bo = NULL;
1426
1427     if (mfc_context->aux_batchbuffer)
1428         intel_batchbuffer_free(mfc_context->aux_batchbuffer);
1429
1430     mfc_context->aux_batchbuffer = NULL;
1431
1432     free(mfc_context);
1433 }
1434
1435 Bool gen6_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
1436 {
1437     struct gen6_mfc_context *mfc_context = calloc(1, sizeof(struct gen6_mfc_context));
1438
1439     mfc_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6;
1440
1441     mfc_context->gpe_context.idrt.max_entries = MAX_GPE_KERNELS;
1442     mfc_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data);
1443
1444     mfc_context->gpe_context.curbe.length = 32 * 4;
1445
1446     mfc_context->gpe_context.vfe_state.max_num_threads = 60 - 1;
1447     mfc_context->gpe_context.vfe_state.num_urb_entries = 16;
1448     mfc_context->gpe_context.vfe_state.gpgpu_mode = 0;
1449     mfc_context->gpe_context.vfe_state.urb_entry_size = 59 - 1;
1450     mfc_context->gpe_context.vfe_state.curbe_allocation_size = 37 - 1;
1451
1452     i965_gpe_load_kernels(ctx,
1453                           &mfc_context->gpe_context,
1454                           gen6_mfc_kernels,
1455                           NUM_MFC_KERNEL);
1456
1457     mfc_context->pipe_mode_select = gen6_mfc_pipe_mode_select;
1458     mfc_context->set_surface_state = gen6_mfc_surface_state;
1459     mfc_context->ind_obj_base_addr_state = gen6_mfc_ind_obj_base_addr_state;
1460     mfc_context->avc_img_state = gen6_mfc_avc_img_state;
1461     mfc_context->avc_qm_state = gen6_mfc_avc_qm_state;
1462     mfc_context->avc_fqm_state = gen6_mfc_avc_fqm_state;
1463     mfc_context->insert_object = gen6_mfc_avc_insert_object;
1464     mfc_context->buffer_suface_setup = i965_gpe_buffer_suface_setup;
1465
1466     encoder_context->mfc_context = mfc_context;
1467     encoder_context->mfc_context_destroy = gen6_mfc_context_destroy;
1468     encoder_context->mfc_pipeline = gen6_mfc_pipeline;
1469     encoder_context->mfc_brc_prepare = intel_mfc_brc_prepare;
1470
1471     return True;
1472 }