src/gen6_mfc.c

   1 /*
   2  * Copyright © 2010-2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Zhou Chang <chang.zhou@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <assert.h>
  33 #include <math.h>
  34
  35 #include "intel_batchbuffer.h"
  36 #include "i965_defines.h"
  37 #include "i965_structs.h"
  38 #include "i965_drv_video.h"
  39 #include "i965_encoder.h"
  40 #include "i965_encoder_utils.h"
  41 #include "gen6_mfc.h"
  42 #include "gen6_vme.h"
  43 #include "intel_media.h"
  44
  45 static const uint32_t gen6_mfc_batchbuffer_avc_intra[][4] = {
  46 #include "shaders/utils/mfc_batchbuffer_avc_intra.g6b"
  47 };
  48
  49 static const uint32_t gen6_mfc_batchbuffer_avc_inter[][4] = {
  50 #include "shaders/utils/mfc_batchbuffer_avc_inter.g6b"
  51 };
  52
  53 static struct i965_kernel gen6_mfc_kernels[] = {
  54     {
  55         "MFC AVC INTRA BATCHBUFFER ",
  56         MFC_BATCHBUFFER_AVC_INTRA,
  57         gen6_mfc_batchbuffer_avc_intra,
  58         sizeof(gen6_mfc_batchbuffer_avc_intra),
  59         NULL
  60     },
  61
  62     {
  63         "MFC AVC INTER BATCHBUFFER ",
  64         MFC_BATCHBUFFER_AVC_INTER,
  65         gen6_mfc_batchbuffer_avc_inter,
  66         sizeof(gen6_mfc_batchbuffer_avc_inter),
  67         NULL
  68     },
  69 };
  70
  71 static void
  72 gen6_mfc_pipe_mode_select(VADriverContextP ctx,
  73                           int standard_select,
  74                           struct intel_encoder_context *encoder_context)
  75 {
  76     struct intel_batchbuffer *batch = encoder_context->base.batch;
  77     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
  78
  79     assert(standard_select == MFX_FORMAT_AVC);
  80
  81     BEGIN_BCS_BATCH(batch, 4);
  82
  83     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (4 - 2));
  84     OUT_BCS_BATCH(batch,
  85                   (1 << 10) | /* disable Stream-Out , advanced QP/bitrate control need enable it*/
  86                   ((!!mfc_context->post_deblocking_output.bo) << 9)  | /* Post Deblocking Output */
  87                   ((!!mfc_context->pre_deblocking_output.bo) << 8)  | /* Pre Deblocking Output */
  88                   (0 << 7)  | /* disable TLB prefectch */
  89                   (0 << 5)  | /* not in stitch mode */
  90                   (1 << 4)  | /* encoding mode */
  91                   (2 << 0));  /* Standard Select: AVC */
  92     OUT_BCS_BATCH(batch,
  93                   (0 << 20) | /* round flag in PB slice */
  94                   (0 << 19) | /* round flag in Intra8x8 */
  95                   (0 << 7)  | /* expand NOA bus flag */
  96                   (1 << 6)  | /* must be 1 */
  97                   (0 << 5)  | /* disable clock gating for NOA */
  98                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
  99                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
 100                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
 101                   (0 << 1)  | /* AVC long field motion vector */
 102                   (0 << 0));  /* always calculate AVC ILDB boundary strength */
 103     OUT_BCS_BATCH(batch, 0);
 104
 105     ADVANCE_BCS_BATCH(batch);
 106 }
 107
 108 static void
 109 gen6_mfc_surface_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 110 {
 111     struct intel_batchbuffer *batch = encoder_context->base.batch;
 112     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 113
 114     BEGIN_BCS_BATCH(batch, 6);
 115
 116     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
 117     OUT_BCS_BATCH(batch, 0);
 118     OUT_BCS_BATCH(batch,
 119                   ((mfc_context->surface_state.height - 1) << 19) |
 120                   ((mfc_context->surface_state.width - 1) << 6));
 121     OUT_BCS_BATCH(batch,
 122                   (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
 123                   (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
 124                   (0 << 22) | /* surface object control state, FIXME??? */
 125                   ((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */
 126                   (0 << 2)  | /* must be 0 for interleave U/V */
 127                   (1 << 1)  | /* must be y-tiled */
 128                   (I965_TILEWALK_YMAJOR << 0));                         /* tile walk, TILEWALK_YMAJOR */
 129     OUT_BCS_BATCH(batch,
 130                   (0 << 16) |                                                           /* must be 0 for interleave U/V */
 131                   (mfc_context->surface_state.h_pitch));                /* y offset for U(cb) */
 132     OUT_BCS_BATCH(batch, 0);
 133     ADVANCE_BCS_BATCH(batch);
 134 }
 135
 136 void
 137 gen6_mfc_pipe_buf_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 138 {
 139     struct intel_batchbuffer *batch = encoder_context->base.batch;
 140     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 141     int i;
 142
 143     BEGIN_BCS_BATCH(batch, 24);
 144
 145     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
 146
 147     if (mfc_context->pre_deblocking_output.bo)
 148         OUT_BCS_RELOC(batch, mfc_context->pre_deblocking_output.bo,
 149                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 150                       0);
 151     else
 152         OUT_BCS_BATCH(batch, 0);                                                                                        /* pre output addr   */
 153
 154     if (mfc_context->post_deblocking_output.bo)
 155         OUT_BCS_RELOC(batch, mfc_context->post_deblocking_output.bo,
 156                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 157                       0);                                                                                       /* post output addr  */
 158     else
 159         OUT_BCS_BATCH(batch, 0);
 160
 161     OUT_BCS_RELOC(batch, mfc_context->uncompressed_picture_source.bo,
 162                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 163                   0);                                                                                   /* uncompressed data */
 164     OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
 165                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 166                   0);                                                                                   /* StreamOut data*/
 167     OUT_BCS_RELOC(batch, mfc_context->intra_row_store_scratch_buffer.bo,
 168                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 169                   0);
 170     OUT_BCS_RELOC(batch, mfc_context->deblocking_filter_row_store_scratch_buffer.bo,
 171                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 172                   0);
 173     /* 7..22 Reference pictures*/
 174     for (i = 0; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) {
 175         if ( mfc_context->reference_surfaces[i].bo != NULL) {
 176             OUT_BCS_RELOC(batch, mfc_context->reference_surfaces[i].bo,
 177                           I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 178                           0);
 179         } else {
 180             OUT_BCS_BATCH(batch, 0);
 181         }
 182     }
 183     OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
 184                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 185                   0);                                                                                   /* Macroblock status buffer*/
 186
 187     ADVANCE_BCS_BATCH(batch);
 188 }
 189
 190 static void
 191 gen6_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 192 {
 193     struct intel_batchbuffer *batch = encoder_context->base.batch;
 194     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 195     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 196
 197     BEGIN_BCS_BATCH(batch, 11);
 198
 199     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
 200     OUT_BCS_BATCH(batch, 0);
 201     OUT_BCS_BATCH(batch, 0);
 202     /* MFX Indirect MV Object Base Address */
 203     OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 204     OUT_BCS_BATCH(batch, 0);
 205     OUT_BCS_BATCH(batch, 0);
 206     OUT_BCS_BATCH(batch, 0);
 207     OUT_BCS_BATCH(batch, 0);
 208     OUT_BCS_BATCH(batch, 0);
 209     /*MFC Indirect PAK-BSE Object Base Address for Encoder*/
 210     OUT_BCS_RELOC(batch,
 211                   mfc_context->mfc_indirect_pak_bse_object.bo,
 212                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 213                   0);
 214     OUT_BCS_RELOC(batch,
 215                   mfc_context->mfc_indirect_pak_bse_object.bo,
 216                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 217                   mfc_context->mfc_indirect_pak_bse_object.end_offset);
 218
 219     ADVANCE_BCS_BATCH(batch);
 220 }
 221
 222 void
 223 gen6_mfc_bsp_buf_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 224 {
 225     struct intel_batchbuffer *batch = encoder_context->base.batch;
 226     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 227
 228     BEGIN_BCS_BATCH(batch, 4);
 229
 230     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
 231     OUT_BCS_RELOC(batch, mfc_context->bsd_mpc_row_store_scratch_buffer.bo,
 232                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 233                   0);
 234     OUT_BCS_BATCH(batch, 0);
 235     OUT_BCS_BATCH(batch, 0);
 236
 237     ADVANCE_BCS_BATCH(batch);
 238 }
 239
 240 static void
 241 gen6_mfc_avc_img_state(VADriverContextP ctx,struct encode_state *encode_state,
 242                        struct intel_encoder_context *encoder_context)
 243 {
 244     struct intel_batchbuffer *batch = encoder_context->base.batch;
 245     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 246     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 247     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 248     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 249     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 250
 251     BEGIN_BCS_BATCH(batch, 13);
 252     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (13 - 2));
 253     OUT_BCS_BATCH(batch,
 254                   ((width_in_mbs * height_in_mbs) & 0xFFFF));
 255     OUT_BCS_BATCH(batch,
 256                   (height_in_mbs << 16) |
 257                   (width_in_mbs << 0));
 258     OUT_BCS_BATCH(batch,
 259                   (0 << 24) |     /*Second Chroma QP Offset*/
 260                   (0 << 16) |     /*Chroma QP Offset*/
 261                   (0 << 14) |   /*Max-bit conformance Intra flag*/
 262                   (0 << 13) |   /*Max Macroblock size conformance Inter flag*/
 263                   (1 << 12) |   /*Should always be written as "1" */
 264                   (0 << 10) |   /*QM Preset FLag */
 265                   (0 << 8)  |   /*Image Structure*/
 266                   (0 << 0) );   /*Current Decoed Image Frame Store ID, reserved in Encode mode*/
 267     OUT_BCS_BATCH(batch,
 268                   (400 << 16) |   /*Mininum Frame size*/
 269                   (0 << 15) |   /*Disable reading of Macroblock Status Buffer*/
 270                   (0 << 14) |   /*Load BitStream Pointer only once, 1 slic 1 frame*/
 271                   (0 << 13) |   /*CABAC 0 word insertion test enable*/
 272                   (1 << 12) |   /*MVUnpackedEnable,compliant to DXVA*/
 273                   (1 << 10) |   /*Chroma Format IDC, 4:2:0*/
 274                   (pPicParameter->pic_fields.bits.entropy_coding_mode_flag << 7)  |   /*0:CAVLC encoding mode,1:CABAC*/
 275                   (0 << 6)  |   /*Only valid for VLD decoding mode*/
 276                   (0 << 5)  |   /*Constrained Intra Predition Flag, from PPS*/
 277                   (pSequenceParameter->seq_fields.bits.direct_8x8_inference_flag << 4)  |   /*Direct 8x8 inference flag*/
 278                   (pPicParameter->pic_fields.bits.transform_8x8_mode_flag << 3)  |   /*8x8 or 4x4 IDCT Transform Mode Flag*/
 279                   (1 << 2)  |   /*Frame MB only flag*/
 280                   (0 << 1)  |   /*MBAFF mode is in active*/
 281                   (0 << 0) );   /*Field picture flag*/
 282     OUT_BCS_BATCH(batch,
 283                   (1<<16)   |   /*Frame Size Rate Control Flag*/
 284                   (1<<12)   |
 285                   (1<<9)    |   /*MB level Rate Control Enabling Flag*/
 286                   (1 << 3)  |   /*FrameBitRateMinReportMask*/
 287                   (1 << 2)  |   /*FrameBitRateMaxReportMask*/
 288                   (1 << 1)  |   /*InterMBMaxSizeReportMask*/
 289                   (1 << 0) );   /*IntraMBMaxSizeReportMask*/
 290     OUT_BCS_BATCH(batch,                        /*Inter and Intra Conformance Max size limit*/
 291                   (0x0600 << 16) |              /*InterMbMaxSz 192 Byte*/
 292                   (0x0800) );                   /*IntraMbMaxSz 256 Byte*/
 293     OUT_BCS_BATCH(batch, 0x00000000);   /*Reserved : MBZReserved*/
 294     OUT_BCS_BATCH(batch, 0x01020304);   /*Slice QP Delta for bitrate control*/
 295     OUT_BCS_BATCH(batch, 0xFEFDFCFB);
 296     OUT_BCS_BATCH(batch, 0x80601004);   /*MAX = 128KB, MIN = 64KB*/
 297     OUT_BCS_BATCH(batch, 0x00800001);
 298     OUT_BCS_BATCH(batch, 0);
 299
 300     ADVANCE_BCS_BATCH(batch);
 301 }
 302
 303 static void
 304 gen6_mfc_avc_directmode_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 305 {
 306     struct intel_batchbuffer *batch = encoder_context->base.batch;
 307     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 308
 309     int i;
 310
 311     BEGIN_BCS_BATCH(batch, 69);
 312
 313     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
 314
 315     /* Reference frames and Current frames */
 316     for(i = 0; i < NUM_MFC_DMV_BUFFERS; i++) {
 317         if ( mfc_context->direct_mv_buffers[i].bo != NULL) {
 318             OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[i].bo,
 319                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 320                           0);
 321         } else {
 322             OUT_BCS_BATCH(batch, 0);
 323         }
 324     }
 325
 326     /* POL list */
 327     for(i = 0; i < 32; i++) {
 328         OUT_BCS_BATCH(batch, i/2);
 329     }
 330     OUT_BCS_BATCH(batch, 0);
 331     OUT_BCS_BATCH(batch, 0);
 332
 333     ADVANCE_BCS_BATCH(batch);
 334 }
 335
 336 static void
 337 gen6_mfc_avc_slice_state(VADriverContextP ctx,
 338                          VAEncPictureParameterBufferH264 *pic_param,
 339                          VAEncSliceParameterBufferH264 *slice_param,
 340                          struct encode_state *encode_state,
 341                          struct intel_encoder_context *encoder_context,
 342                          int rate_control_enable,
 343                          int qp,
 344                          struct intel_batchbuffer *batch)
 345 {
 346     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 347     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 348     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 349     int beginmb = slice_param->macroblock_address;
 350     int endmb = beginmb + slice_param->num_macroblocks;
 351     int beginx = beginmb % width_in_mbs;
 352     int beginy = beginmb / width_in_mbs;
 353     int nextx =  endmb % width_in_mbs;
 354     int nexty = endmb / width_in_mbs;
 355     int slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
 356     int last_slice = (endmb == (width_in_mbs * height_in_mbs));
 357     int maxQpN, maxQpP;
 358     unsigned char correct[6], grow, shrink;
 359     int i;
 360     int weighted_pred_idc = 0;
 361     unsigned int luma_log2_weight_denom = slice_param->luma_log2_weight_denom;
 362     unsigned int chroma_log2_weight_denom = slice_param->chroma_log2_weight_denom;
 363     int bslice = 0;
 364
 365     if (batch == NULL)
 366         batch = encoder_context->base.batch;
 367
 368     if (slice_type == SLICE_TYPE_P) {
 369         weighted_pred_idc = pic_param->pic_fields.bits.weighted_pred_flag;
 370     } else if (slice_type == SLICE_TYPE_B) {
 371         weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc;
 372         bslice = 1;
 373
 374         if (weighted_pred_idc == 2) {
 375             /* 8.4.3 - Derivation process for prediction weights (8-279) */
 376             luma_log2_weight_denom = 5;
 377             chroma_log2_weight_denom = 5;
 378         }
 379     }
 380
 381     maxQpN = mfc_context->bit_rate_control_context[slice_type].MaxQpNegModifier;
 382     maxQpP = mfc_context->bit_rate_control_context[slice_type].MaxQpPosModifier;
 383
 384     for (i = 0; i < 6; i++)
 385         correct[i] = mfc_context->bit_rate_control_context[slice_type].Correct[i];
 386
 387     grow = mfc_context->bit_rate_control_context[slice_type].GrowInit +
 388         (mfc_context->bit_rate_control_context[slice_type].GrowResistance << 4);
 389     shrink = mfc_context->bit_rate_control_context[slice_type].ShrinkInit +
 390         (mfc_context->bit_rate_control_context[slice_type].ShrinkResistance << 4);
 391
 392     BEGIN_BCS_BATCH(batch, 11);;
 393
 394     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) );
 395     OUT_BCS_BATCH(batch, slice_type);                   /*Slice Type: I:P:B Slice*/
 396
 397     if (slice_type == SLICE_TYPE_I) {
 398         OUT_BCS_BATCH(batch, 0);                        /*no reference frames and pred_weight_table*/
 399     } else {
 400         OUT_BCS_BATCH(batch,
 401                       (1 << 16) | (bslice << 24) |     /*1 reference frame*/
 402                       (chroma_log2_weight_denom << 8) |
 403                       (luma_log2_weight_denom << 0));
 404     }
 405
 406     OUT_BCS_BATCH(batch,
 407                   (weighted_pred_idc << 30) |
 408                   (slice_param->direct_spatial_mv_pred_flag<<29) |             /*Direct Prediction Type*/
 409                   (slice_param->disable_deblocking_filter_idc << 27) |
 410                   (slice_param->cabac_init_idc << 24) |
 411                   (qp<<16) |                    /*Slice Quantization Parameter*/
 412                   ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
 413                   ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
 414     OUT_BCS_BATCH(batch,
 415                   (beginy << 24) |                      /*First MB X&Y , the begin postion of current slice*/
 416                   (beginx << 16) |
 417                   slice_param->macroblock_address );
 418     OUT_BCS_BATCH(batch, (nexty << 16) | nextx);                       /*Next slice first MB X&Y*/
 419     OUT_BCS_BATCH(batch,
 420                   (0/*rate_control_enable*/ << 31) |            /*in CBR mode RateControlCounterEnable = enable*/
 421                   (1 << 30) |           /*ResetRateControlCounter*/
 422                   (0 << 28) |           /*RC Triggle Mode = Always Rate Control*/
 423                   (4 << 24) |     /*RC Stable Tolerance, middle level*/
 424                   (0/*rate_control_enable*/ << 23) |     /*RC Panic Enable*/
 425                   (0 << 22) |     /*QP mode, don't modfiy CBP*/
 426                   (0 << 21) |     /*MB Type Direct Conversion Enabled*/
 427                   (0 << 20) |     /*MB Type Skip Conversion Enabled*/
 428                   (last_slice << 19) |     /*IsLastSlice*/
 429                   (0 << 18) |   /*BitstreamOutputFlag Compressed BitStream Output Disable Flag 0:enable 1:disable*/
 430                   (1 << 17) |       /*HeaderPresentFlag*/
 431                   (1 << 16) |       /*SliceData PresentFlag*/
 432                   (1 << 15) |       /*TailPresentFlag*/
 433                   (1 << 13) |       /*RBSP NAL TYPE*/
 434                   (0 << 12) );    /*CabacZeroWordInsertionEnable*/
 435     OUT_BCS_BATCH(batch, mfc_context->mfc_indirect_pak_bse_object.offset);
 436     OUT_BCS_BATCH(batch,
 437                   (maxQpN << 24) |     /*Target QP - 24 is lowest QP*/
 438                   (maxQpP << 16) |     /*Target QP + 20 is highest QP*/
 439                   (shrink << 8)  |
 440                   (grow << 0));
 441     OUT_BCS_BATCH(batch,
 442                   (correct[5] << 20) |
 443                   (correct[4] << 16) |
 444                   (correct[3] << 12) |
 445                   (correct[2] << 8) |
 446                   (correct[1] << 4) |
 447                   (correct[0] << 0));
 448     OUT_BCS_BATCH(batch, 0);
 449
 450     ADVANCE_BCS_BATCH(batch);
 451 }
 452
 453 static void gen6_mfc_avc_qm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 454 {
 455     struct intel_batchbuffer *batch = encoder_context->base.batch;
 456     int i;
 457
 458     BEGIN_BCS_BATCH(batch, 58);
 459
 460     OUT_BCS_BATCH(batch, MFX_AVC_QM_STATE | 56);
 461     OUT_BCS_BATCH(batch, 0xFF ) ;
 462     for( i = 0; i < 56; i++) {
 463         OUT_BCS_BATCH(batch, 0x10101010);
 464     }
 465
 466     ADVANCE_BCS_BATCH(batch);
 467 }
 468
 469 static void gen6_mfc_avc_fqm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 470 {
 471     struct intel_batchbuffer *batch = encoder_context->base.batch;
 472     int i;
 473
 474     BEGIN_BCS_BATCH(batch, 113);
 475     OUT_BCS_BATCH(batch, MFC_AVC_FQM_STATE | (113 - 2));
 476
 477     for(i = 0; i < 112;i++) {
 478         OUT_BCS_BATCH(batch, 0x10001000);
 479     }
 480
 481     ADVANCE_BCS_BATCH(batch);
 482 }
 483
 484 static void
 485 gen6_mfc_avc_insert_object(VADriverContextP ctx, struct intel_encoder_context *encoder_context,
 486                            unsigned int *insert_data, int lenght_in_dws, int data_bits_in_last_dw,
 487                            int skip_emul_byte_count, int is_last_header, int is_end_of_slice, int emulation_flag,
 488                            struct intel_batchbuffer *batch)
 489 {
 490     if (batch == NULL)
 491         batch = encoder_context->base.batch;
 492
 493     BEGIN_BCS_BATCH(batch, lenght_in_dws + 2);
 494
 495     OUT_BCS_BATCH(batch, MFC_AVC_INSERT_OBJECT | (lenght_in_dws + 2 - 2));
 496
 497     OUT_BCS_BATCH(batch,
 498                   (0 << 16) |   /* always start at offset 0 */
 499                   (data_bits_in_last_dw << 8) |
 500                   (skip_emul_byte_count << 4) |
 501                   (!!emulation_flag << 3) |
 502                   ((!!is_last_header) << 2) |
 503                   ((!!is_end_of_slice) << 1) |
 504                   (0 << 0));    /* FIXME: ??? */
 505
 506     intel_batchbuffer_data(batch, insert_data, lenght_in_dws * 4);
 507     ADVANCE_BCS_BATCH(batch);
 508 }
 509
 510 void
 511 gen6_mfc_init(VADriverContextP ctx,
 512               struct encode_state *encode_state,
 513               struct intel_encoder_context *encoder_context)
 514 {
 515     struct i965_driver_data *i965 = i965_driver_data(ctx);
 516     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 517     dri_bo *bo;
 518     int i;
 519     int width_in_mbs = 0;
 520     int height_in_mbs = 0;
 521
 522     if (encoder_context->codec == CODEC_H264) {
 523         VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 524         width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 525         height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 526     } else {
 527         VAEncSequenceParameterBufferMPEG2 *pSequenceParameter = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
 528
 529         assert(encoder_context->codec == CODEC_MPEG2);
 530
 531         width_in_mbs = ALIGN(pSequenceParameter->picture_width, 16) / 16;
 532         height_in_mbs = ALIGN(pSequenceParameter->picture_height, 16) / 16;
 533     }
 534
 535     /*Encode common setup for MFC*/
 536     dri_bo_unreference(mfc_context->post_deblocking_output.bo);
 537     mfc_context->post_deblocking_output.bo = NULL;
 538
 539     dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
 540     mfc_context->pre_deblocking_output.bo = NULL;
 541
 542     dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
 543     mfc_context->uncompressed_picture_source.bo = NULL;
 544
 545     dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
 546     mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
 547
 548     for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
 549         if ( mfc_context->direct_mv_buffers[i].bo != NULL);
 550         dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
 551         mfc_context->direct_mv_buffers[i].bo = NULL;
 552     }
 553
 554     for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
 555         if (mfc_context->reference_surfaces[i].bo != NULL)
 556             dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
 557         mfc_context->reference_surfaces[i].bo = NULL;
 558     }
 559
 560     dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
 561     bo = dri_bo_alloc(i965->intel.bufmgr,
 562                       "Buffer",
 563                       width_in_mbs * 64,
 564                       64);
 565     assert(bo);
 566     mfc_context->intra_row_store_scratch_buffer.bo = bo;
 567
 568     dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
 569     bo = dri_bo_alloc(i965->intel.bufmgr,
 570                       "Buffer",
 571                       width_in_mbs * height_in_mbs * 16,
 572                       64);
 573     assert(bo);
 574     mfc_context->macroblock_status_buffer.bo = bo;
 575
 576     dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
 577     bo = dri_bo_alloc(i965->intel.bufmgr,
 578                       "Buffer",
 579                       4 * width_in_mbs * 64,  /* 4 * width_in_mbs * 64 */
 580                       64);
 581     assert(bo);
 582     mfc_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
 583
 584     dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
 585     bo = dri_bo_alloc(i965->intel.bufmgr,
 586                       "Buffer",
 587                       128 * width_in_mbs, /* 2 * widht_in_mbs * 64 */
 588                       0x1000);
 589     assert(bo);
 590     mfc_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
 591
 592     dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo);
 593     mfc_context->mfc_batchbuffer_surface.bo = NULL;
 594
 595     dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo);
 596     mfc_context->aux_batchbuffer_surface.bo = NULL;
 597
 598     if (mfc_context->aux_batchbuffer)
 599         intel_batchbuffer_free(mfc_context->aux_batchbuffer);
 600
 601     mfc_context->aux_batchbuffer = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD, 0);
 602     mfc_context->aux_batchbuffer_surface.bo = mfc_context->aux_batchbuffer->buffer;
 603     dri_bo_reference(mfc_context->aux_batchbuffer_surface.bo);
 604     mfc_context->aux_batchbuffer_surface.pitch = 16;
 605     mfc_context->aux_batchbuffer_surface.num_blocks = mfc_context->aux_batchbuffer->size / 16;
 606     mfc_context->aux_batchbuffer_surface.size_block = 16;
 607
 608     i965_gpe_context_init(ctx, &mfc_context->gpe_context);
 609 }
 610
 611 static void gen6_mfc_avc_pipeline_picture_programing( VADriverContextP ctx,
 612                                                       struct encode_state *encode_state,
 613                                                       struct intel_encoder_context *encoder_context)
 614 {
 615     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 616
 617     mfc_context->pipe_mode_select(ctx, MFX_FORMAT_AVC, encoder_context);
 618     mfc_context->set_surface_state(ctx, encoder_context);
 619     mfc_context->ind_obj_base_addr_state(ctx, encoder_context);
 620     gen6_mfc_pipe_buf_addr_state(ctx, encoder_context);
 621     gen6_mfc_bsp_buf_base_addr_state(ctx, encoder_context);
 622     mfc_context->avc_img_state(ctx, encode_state, encoder_context);
 623     mfc_context->avc_qm_state(ctx, encoder_context);
 624     mfc_context->avc_fqm_state(ctx, encoder_context);
 625     gen6_mfc_avc_directmode_state(ctx, encoder_context);
 626     intel_mfc_avc_ref_idx_state(ctx, encode_state, encoder_context);
 627 }
 628
 629
 630 VAStatus
 631 gen6_mfc_run(VADriverContextP ctx,
 632              struct encode_state *encode_state,
 633              struct intel_encoder_context *encoder_context)
 634 {
 635     struct intel_batchbuffer *batch = encoder_context->base.batch;
 636
 637     intel_batchbuffer_flush(batch);             //run the pipeline
 638
 639     return VA_STATUS_SUCCESS;
 640 }
 641
 642 VAStatus
 643 gen6_mfc_stop(VADriverContextP ctx,
 644               struct encode_state *encode_state,
 645               struct intel_encoder_context *encoder_context,
 646               int *encoded_bits_size)
 647 {
 648     VAStatus vaStatus = VA_STATUS_ERROR_UNKNOWN;
 649     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 650     VACodedBufferSegment *coded_buffer_segment;
 651
 652     vaStatus = i965_MapBuffer(ctx, pPicParameter->coded_buf, (void **)&coded_buffer_segment);
 653     assert(vaStatus == VA_STATUS_SUCCESS);
 654     *encoded_bits_size = coded_buffer_segment->size * 8;
 655     i965_UnmapBuffer(ctx, pPicParameter->coded_buf);
 656
 657     return VA_STATUS_SUCCESS;
 658 }
 659
 660 #if __SOFTWARE__
 661
 662 static int
 663 gen6_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb, int qp,unsigned int *msg,
 664                               struct intel_encoder_context *encoder_context,
 665                               unsigned char target_mb_size, unsigned char max_mb_size,
 666                               struct intel_batchbuffer *batch)
 667 {
 668     int len_in_dwords = 11;
 669
 670     if (batch == NULL)
 671         batch = encoder_context->base.batch;
 672
 673     BEGIN_BCS_BATCH(batch, len_in_dwords);
 674
 675     OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
 676     OUT_BCS_BATCH(batch, 0);
 677     OUT_BCS_BATCH(batch, 0);
 678     OUT_BCS_BATCH(batch,
 679                   (0 << 24) |           /* PackedMvNum, Debug*/
 680                   (0 << 20) |           /* No motion vector */
 681                   (1 << 19) |           /* CbpDcY */
 682                   (1 << 18) |           /* CbpDcU */
 683                   (1 << 17) |           /* CbpDcV */
 684                   (msg[0] & 0xFFFF) );
 685
 686     OUT_BCS_BATCH(batch, (0xFFFF << 16) | (y << 8) | x);                /* Code Block Pattern for Y*/
 687     OUT_BCS_BATCH(batch, 0x000F000F);                                                   /* Code Block Pattern */
 688     OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp);      /* Last MB */
 689
 690     /*Stuff for Intra MB*/
 691     OUT_BCS_BATCH(batch, msg[1]);                       /* We using Intra16x16 no 4x4 predmode*/
 692     OUT_BCS_BATCH(batch, msg[2]);
 693     OUT_BCS_BATCH(batch, msg[3]&0xFC);
 694
 695     /*MaxSizeInWord and TargetSzieInWord*/
 696     OUT_BCS_BATCH(batch, (max_mb_size << 24) |
 697                   (target_mb_size << 16) );
 698
 699     ADVANCE_BCS_BATCH(batch);
 700
 701     return len_in_dwords;
 702 }
 703
 704 static int
 705 gen6_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, int qp,
 706                               unsigned int *msg, unsigned int offset,
 707                               struct intel_encoder_context *encoder_context,
 708                               unsigned char target_mb_size,unsigned char max_mb_size, int slice_type,
 709                               struct intel_batchbuffer *batch)
 710 {
 711     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 712     int len_in_dwords = 11;
 713
 714     if (batch == NULL)
 715         batch = encoder_context->base.batch;
 716
 717     BEGIN_BCS_BATCH(batch, len_in_dwords);
 718
 719     OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
 720
 721     OUT_BCS_BATCH(batch, msg[2]);         /* 32 MV*/
 722     OUT_BCS_BATCH(batch, offset);
 723
 724     OUT_BCS_BATCH(batch, msg[0]);
 725
 726     OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x);        /* Code Block Pattern for Y*/
 727     OUT_BCS_BATCH(batch, 0x000F000F);                         /* Code Block Pattern */
 728 #if 0
 729     if ( slice_type == SLICE_TYPE_B) {
 730         OUT_BCS_BATCH(batch, (0xF<<28) | (end_mb << 26) | qp);  /* Last MB */
 731     } else {
 732         OUT_BCS_BATCH(batch, (end_mb << 26) | qp);      /* Last MB */
 733     }
 734 #else
 735     OUT_BCS_BATCH(batch, (end_mb << 26) | qp);  /* Last MB */
 736 #endif
 737
 738
 739     /*Stuff for Inter MB*/
 740     OUT_BCS_BATCH(batch, msg[1]);
 741     OUT_BCS_BATCH(batch, vme_context->ref_index_in_mb[0]);
 742     OUT_BCS_BATCH(batch, vme_context->ref_index_in_mb[1]);
 743
 744     /*MaxSizeInWord and TargetSzieInWord*/
 745     OUT_BCS_BATCH(batch, (max_mb_size << 24) |
 746                   (target_mb_size << 16) );
 747
 748     ADVANCE_BCS_BATCH(batch);
 749
 750     return len_in_dwords;
 751 }
 752
 753 static void
 754 gen6_mfc_avc_pipeline_slice_programing(VADriverContextP ctx,
 755                                        struct encode_state *encode_state,
 756                                        struct intel_encoder_context *encoder_context,
 757                                        int slice_index,
 758                                        struct intel_batchbuffer *slice_batch)
 759 {
 760     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 761     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 762     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 763     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 764     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
 765     unsigned int *msg = NULL, offset = 0;
 766     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 767     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 768     int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs);
 769     int i,x,y;
 770     int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta;
 771     unsigned int rate_control_mode = encoder_context->rate_control_mode;
 772     unsigned char *slice_header = NULL;
 773     int slice_header_length_in_bits = 0;
 774     unsigned int tail_data[] = { 0x0, 0x0 };
 775     int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type);
 776     int is_intra = slice_type == SLICE_TYPE_I;
 777
 778     if (rate_control_mode == VA_RC_CBR) {
 779         qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
 780         pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp;
 781     }
 782
 783     /* only support for 8-bit pixel bit-depth */
 784     assert(pSequenceParameter->bit_depth_luma_minus8 == 0);
 785     assert(pSequenceParameter->bit_depth_chroma_minus8 == 0);
 786     assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52);
 787     assert(qp >= 0 && qp < 52);
 788
 789     gen6_mfc_avc_slice_state(ctx,
 790                              pPicParameter,
 791                              pSliceParameter,
 792                              encode_state, encoder_context,
 793                              (rate_control_mode == VA_RC_CBR), qp, slice_batch);
 794
 795     if ( slice_index == 0)
 796         intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch);
 797
 798     slice_header_length_in_bits = build_avc_slice_header(pSequenceParameter, pPicParameter, pSliceParameter, &slice_header);
 799
 800     // slice hander
 801     mfc_context->insert_object(ctx, encoder_context,
 802                                (unsigned int *)slice_header, ALIGN(slice_header_length_in_bits, 32) >> 5, slice_header_length_in_bits & 0x1f,
 803                                5,  /* first 5 bytes are start code + nal unit type */
 804                                1, 0, 1, slice_batch);
 805
 806     dri_bo_map(vme_context->vme_output.bo , 1);
 807     msg = (unsigned int *)vme_context->vme_output.bo->virtual;
 808
 809     if (is_intra) {
 810         msg += pSliceParameter->macroblock_address * INTRA_VME_OUTPUT_IN_DWS;
 811     } else {
 812         msg += pSliceParameter->macroblock_address * INTER_VME_OUTPUT_IN_DWS;
 813         msg += 32; /* the first 32 DWs are MVs */
 814         offset = pSliceParameter->macroblock_address * INTER_VME_OUTPUT_IN_BYTES;
 815     }
 816
 817     for (i = pSliceParameter->macroblock_address;
 818          i < pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks; i++) {
 819         int last_mb = (i == (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks - 1) );
 820         x = i % width_in_mbs;
 821         y = i / width_in_mbs;
 822
 823         if (is_intra) {
 824             assert(msg);
 825             gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch);
 826             msg += INTRA_VME_OUTPUT_IN_DWS;
 827         } else {
 828             if (msg[0] & INTRA_MB_FLAG_MASK) {
 829                 gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch);
 830             } else {
 831                 gen6_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, msg, offset, encoder_context, 0, 0, slice_type, slice_batch);
 832             }
 833
 834             msg += INTER_VME_OUTPUT_IN_DWS;
 835             offset += INTER_VME_OUTPUT_IN_BYTES;
 836         }
 837     }
 838
 839     dri_bo_unmap(vme_context->vme_output.bo);
 840
 841     if ( last_slice ) {
 842         mfc_context->insert_object(ctx, encoder_context,
 843                                    tail_data, 2, 8,
 844                                    2, 1, 1, 0, slice_batch);
 845     } else {
 846         mfc_context->insert_object(ctx, encoder_context,
 847                                    tail_data, 1, 8,
 848                                    1, 1, 1, 0, slice_batch);
 849     }
 850
 851     free(slice_header);
 852
 853 }
 854
 855 static dri_bo *
 856 gen6_mfc_avc_software_batchbuffer(VADriverContextP ctx,
 857                                   struct encode_state *encode_state,
 858                                   struct intel_encoder_context *encoder_context)
 859 {
 860     struct i965_driver_data *i965 = i965_driver_data(ctx);
 861     struct intel_batchbuffer *batch = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD, 0);
 862     dri_bo *batch_bo = batch->buffer;
 863     int i;
 864
 865     for (i = 0; i < encode_state->num_slice_params_ext; i++) {
 866         gen6_mfc_avc_pipeline_slice_programing(ctx, encode_state, encoder_context, i, batch);
 867     }
 868
 869     intel_batchbuffer_align(batch, 8);
 870
 871     BEGIN_BCS_BATCH(batch, 2);
 872     OUT_BCS_BATCH(batch, 0);
 873     OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_END);
 874     ADVANCE_BCS_BATCH(batch);
 875
 876     dri_bo_reference(batch_bo);
 877     intel_batchbuffer_free(batch);
 878
 879     return batch_bo;
 880 }
 881
 882 #else
 883
 884 static void
 885 gen6_mfc_batchbuffer_surfaces_input(VADriverContextP ctx,
 886                                     struct encode_state *encode_state,
 887                                     struct intel_encoder_context *encoder_context)
 888
 889 {
 890     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 891     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 892
 893     assert(vme_context->vme_output.bo);
 894     mfc_context->buffer_suface_setup(ctx,
 895                                      &mfc_context->gpe_context,
 896                                      &vme_context->vme_output,
 897                                      BINDING_TABLE_OFFSET(BIND_IDX_VME_OUTPUT),
 898                                      SURFACE_STATE_OFFSET(BIND_IDX_VME_OUTPUT));
 899     assert(mfc_context->aux_batchbuffer_surface.bo);
 900     mfc_context->buffer_suface_setup(ctx,
 901                                      &mfc_context->gpe_context,
 902                                      &mfc_context->aux_batchbuffer_surface,
 903                                      BINDING_TABLE_OFFSET(BIND_IDX_MFC_SLICE_HEADER),
 904                                      SURFACE_STATE_OFFSET(BIND_IDX_MFC_SLICE_HEADER));
 905 }
 906
 907 static void
 908 gen6_mfc_batchbuffer_surfaces_output(VADriverContextP ctx,
 909                                      struct encode_state *encode_state,
 910                                      struct intel_encoder_context *encoder_context)
 911
 912 {
 913     struct i965_driver_data *i965 = i965_driver_data(ctx);
 914     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 915     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 916     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 917     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 918     mfc_context->mfc_batchbuffer_surface.num_blocks = width_in_mbs * height_in_mbs + encode_state->num_slice_params_ext * 8 + 1;
 919     mfc_context->mfc_batchbuffer_surface.size_block = 16 * CMD_LEN_IN_OWORD; /* 3 OWORDs */
 920     mfc_context->mfc_batchbuffer_surface.pitch = 16;
 921     mfc_context->mfc_batchbuffer_surface.bo = dri_bo_alloc(i965->intel.bufmgr,
 922                                                            "MFC batchbuffer",
 923                                                            mfc_context->mfc_batchbuffer_surface.num_blocks * mfc_context->mfc_batchbuffer_surface.size_block,
 924                                                            0x1000);
 925     mfc_context->buffer_suface_setup(ctx,
 926                                      &mfc_context->gpe_context,
 927                                      &mfc_context->mfc_batchbuffer_surface,
 928                                      BINDING_TABLE_OFFSET(BIND_IDX_MFC_BATCHBUFFER),
 929                                      SURFACE_STATE_OFFSET(BIND_IDX_MFC_BATCHBUFFER));
 930 }
 931
 932 static void
 933 gen6_mfc_batchbuffer_surfaces_setup(VADriverContextP ctx,
 934                                     struct encode_state *encode_state,
 935                                     struct intel_encoder_context *encoder_context)
 936 {
 937     gen6_mfc_batchbuffer_surfaces_input(ctx, encode_state, encoder_context);
 938     gen6_mfc_batchbuffer_surfaces_output(ctx, encode_state, encoder_context);
 939 }
 940
 941 static void
 942 gen6_mfc_batchbuffer_idrt_setup(VADriverContextP ctx,
 943                                 struct encode_state *encode_state,
 944                                 struct intel_encoder_context *encoder_context)
 945 {
 946     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 947     struct gen6_interface_descriptor_data *desc;
 948     int i;
 949     dri_bo *bo;
 950
 951     bo = mfc_context->gpe_context.idrt.bo;
 952     dri_bo_map(bo, 1);
 953     assert(bo->virtual);
 954     desc = bo->virtual;
 955
 956     for (i = 0; i < mfc_context->gpe_context.num_kernels; i++) {
 957         struct i965_kernel *kernel;
 958
 959         kernel = &mfc_context->gpe_context.kernels[i];
 960         assert(sizeof(*desc) == 32);
 961
 962         /*Setup the descritor table*/
 963         memset(desc, 0, sizeof(*desc));
 964         desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6);
 965         desc->desc2.sampler_count = 0;
 966         desc->desc2.sampler_state_pointer = 0;
 967         desc->desc3.binding_table_entry_count = 2;
 968         desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5);
 969         desc->desc4.constant_urb_entry_read_offset = 0;
 970         desc->desc4.constant_urb_entry_read_length = 4;
 971
 972         /*kernel start*/
 973         dri_bo_emit_reloc(bo,
 974                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 975                           0,
 976                           i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0),
 977                           kernel->bo);
 978         desc++;
 979     }
 980
 981     dri_bo_unmap(bo);
 982 }
 983
 984 static void
 985 gen6_mfc_batchbuffer_constant_setup(VADriverContextP ctx,
 986                                     struct encode_state *encode_state,
 987                                     struct intel_encoder_context *encoder_context)
 988 {
 989     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 990
 991     (void)mfc_context;
 992 }
 993
 994 static void
 995 gen6_mfc_batchbuffer_emit_object_command(struct intel_batchbuffer *batch,
 996                                          int index,
 997                                          int head_offset,
 998                                          int batchbuffer_offset,
 999                                          int head_size,
1000                                          int tail_size,
1001                                          int number_mb_cmds,
1002                                          int first_object,
1003                                          int last_object,
1004                                          int last_slice,
1005                                          int mb_x,
1006                                          int mb_y,
1007                                          int width_in_mbs,
1008                                          int qp,
1009                                          unsigned int ref_index[2])
1010 {
1011     BEGIN_BATCH(batch, 14);
1012
1013     OUT_BATCH(batch, CMD_MEDIA_OBJECT | (14 - 2));
1014     OUT_BATCH(batch, index);
1015     OUT_BATCH(batch, 0);
1016     OUT_BATCH(batch, 0);
1017     OUT_BATCH(batch, 0);
1018     OUT_BATCH(batch, 0);
1019
1020     /*inline data */
1021     OUT_BATCH(batch, head_offset);
1022     OUT_BATCH(batch, batchbuffer_offset);
1023     OUT_BATCH(batch,
1024               head_size << 16 |
1025               tail_size);
1026     OUT_BATCH(batch,
1027               number_mb_cmds << 16 |
1028               first_object << 2 |
1029               last_object << 1 |
1030               last_slice);
1031     OUT_BATCH(batch,
1032               mb_y << 8 |
1033               mb_x);
1034     OUT_BATCH(batch,
1035               qp << 16 |
1036               width_in_mbs);
1037     OUT_BATCH(batch, ref_index[0]);
1038     OUT_BATCH(batch, ref_index[1]);
1039
1040     ADVANCE_BATCH(batch);
1041 }
1042
1043 static void
1044 gen6_mfc_avc_batchbuffer_slice_command(VADriverContextP ctx,
1045                                        struct intel_encoder_context *encoder_context,
1046                                        VAEncSliceParameterBufferH264 *slice_param,
1047                                        int head_offset,
1048                                        unsigned short head_size,
1049                                        unsigned short tail_size,
1050                                        int batchbuffer_offset,
1051                                        int qp,
1052                                        int last_slice)
1053 {
1054     struct intel_batchbuffer *batch = encoder_context->base.batch;
1055     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1056     struct gen6_vme_context *vme_context = encoder_context->vme_context;
1057     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
1058     int total_mbs = slice_param->num_macroblocks;
1059     int number_mb_cmds = 128;
1060     int starting_mb = 0;
1061     int last_object = 0;
1062     int first_object = 1;
1063     int i;
1064     int mb_x, mb_y;
1065     int index = (slice_param->slice_type == SLICE_TYPE_I) ? MFC_BATCHBUFFER_AVC_INTRA : MFC_BATCHBUFFER_AVC_INTER;
1066
1067     for (i = 0; i < total_mbs / number_mb_cmds; i++) {
1068         last_object = (total_mbs - starting_mb) == number_mb_cmds;
1069         mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs;
1070         mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs;
1071         assert(mb_x <= 255 && mb_y <= 255);
1072
1073         starting_mb += number_mb_cmds;
1074
1075         gen6_mfc_batchbuffer_emit_object_command(batch,
1076                                                  index,
1077                                                  head_offset,
1078                                                  batchbuffer_offset,
1079                                                  head_size,
1080                                                  tail_size,
1081                                                  number_mb_cmds,
1082                                                  first_object,
1083                                                  last_object,
1084                                                  last_slice,
1085                                                  mb_x,
1086                                                  mb_y,
1087                                                  width_in_mbs,
1088                                                  qp,
1089                                                  vme_context->ref_index_in_mb);
1090
1091         if (first_object) {
1092             head_offset += head_size;
1093             batchbuffer_offset += head_size;
1094         }
1095
1096         if (last_object) {
1097             head_offset += tail_size;
1098             batchbuffer_offset += tail_size;
1099         }
1100
1101         batchbuffer_offset += number_mb_cmds * CMD_LEN_IN_OWORD;
1102
1103         first_object = 0;
1104     }
1105
1106     if (!last_object) {
1107         last_object = 1;
1108         number_mb_cmds = total_mbs % number_mb_cmds;
1109         mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs;
1110         mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs;
1111         assert(mb_x <= 255 && mb_y <= 255);
1112         starting_mb += number_mb_cmds;
1113
1114         gen6_mfc_batchbuffer_emit_object_command(batch,
1115                                                  index,
1116                                                  head_offset,
1117                                                  batchbuffer_offset,
1118                                                  head_size,
1119                                                  tail_size,
1120                                                  number_mb_cmds,
1121                                                  first_object,
1122                                                  last_object,
1123                                                  last_slice,
1124                                                  mb_x,
1125                                                  mb_y,
1126                                                  width_in_mbs,
1127                                                  qp,
1128                                                  vme_context->ref_index_in_mb);
1129     }
1130 }
1131
1132 /*
1133  * return size in Owords (16bytes)
1134  */
1135 static int
1136 gen6_mfc_avc_batchbuffer_slice(VADriverContextP ctx,
1137                                struct encode_state *encode_state,
1138                                struct intel_encoder_context *encoder_context,
1139                                int slice_index,
1140                                int batchbuffer_offset)
1141 {
1142     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1143     struct intel_batchbuffer *slice_batch = mfc_context->aux_batchbuffer;
1144     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
1145     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
1146     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
1147     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
1148     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
1149     int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs);
1150     int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta;
1151     unsigned int rate_control_mode = encoder_context->rate_control_mode;
1152     unsigned char *slice_header = NULL;
1153     int slice_header_length_in_bits = 0;
1154     unsigned int tail_data[] = { 0x0, 0x0 };
1155     long head_offset;
1156     int old_used = intel_batchbuffer_used_size(slice_batch), used;
1157     unsigned short head_size, tail_size;
1158     int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type);
1159
1160     if (rate_control_mode == VA_RC_CBR) {
1161         qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
1162         pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp;
1163     }
1164
1165     /* only support for 8-bit pixel bit-depth */
1166     assert(pSequenceParameter->bit_depth_luma_minus8 == 0);
1167     assert(pSequenceParameter->bit_depth_chroma_minus8 == 0);
1168     assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52);
1169     assert(qp >= 0 && qp < 52);
1170
1171     head_offset = old_used / 16;
1172     gen6_mfc_avc_slice_state(ctx,
1173                              pPicParameter,
1174                              pSliceParameter,
1175                              encode_state,
1176                              encoder_context,
1177                              (rate_control_mode == VA_RC_CBR),
1178                              qp,
1179                              slice_batch);
1180
1181     if (slice_index == 0)
1182         intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch);
1183
1184     slice_header_length_in_bits = build_avc_slice_header(pSequenceParameter, pPicParameter, pSliceParameter, &slice_header);
1185
1186     // slice hander
1187     mfc_context->insert_object(ctx,
1188                                encoder_context,
1189                                (unsigned int *)slice_header,
1190                                ALIGN(slice_header_length_in_bits, 32) >> 5,
1191                                slice_header_length_in_bits & 0x1f,
1192                                5,  /* first 5 bytes are start code + nal unit type */
1193                                1,
1194                                0,
1195                                1,
1196                                slice_batch);
1197     free(slice_header);
1198
1199     intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */
1200     used = intel_batchbuffer_used_size(slice_batch);
1201     head_size = (used - old_used) / 16;
1202     old_used = used;
1203
1204     /* tail */
1205     if (last_slice) {
1206         mfc_context->insert_object(ctx,
1207                                    encoder_context,
1208                                    tail_data,
1209                                    2,
1210                                    8,
1211                                    2,
1212                                    1,
1213                                    1,
1214                                    0,
1215                                    slice_batch);
1216     } else {
1217         mfc_context->insert_object(ctx,
1218                                    encoder_context,
1219                                    tail_data,
1220                                    1,
1221                                    8,
1222                                    1,
1223                                    1,
1224                                    1,
1225                                    0,
1226                                    slice_batch);
1227     }
1228
1229     intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */
1230     used = intel_batchbuffer_used_size(slice_batch);
1231     tail_size = (used - old_used) / 16;
1232
1233
1234     gen6_mfc_avc_batchbuffer_slice_command(ctx,
1235                                            encoder_context,
1236                                            pSliceParameter,
1237                                            head_offset,
1238                                            head_size,
1239                                            tail_size,
1240                                            batchbuffer_offset,
1241                                            qp,
1242                                            last_slice);
1243
1244     return head_size + tail_size + pSliceParameter->num_macroblocks * CMD_LEN_IN_OWORD;
1245 }
1246
1247 static void
1248 gen6_mfc_avc_batchbuffer_pipeline(VADriverContextP ctx,
1249                                   struct encode_state *encode_state,
1250                                   struct intel_encoder_context *encoder_context)
1251 {
1252     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1253     struct intel_batchbuffer *batch = encoder_context->base.batch;
1254     int i, size, offset = 0;
1255     intel_batchbuffer_start_atomic(batch, 0x4000);
1256     gen6_gpe_pipeline_setup(ctx, &mfc_context->gpe_context, batch);
1257
1258     for ( i = 0; i < encode_state->num_slice_params_ext; i++) {
1259         size = gen6_mfc_avc_batchbuffer_slice(ctx, encode_state, encoder_context, i, offset);
1260         offset += size;
1261     }
1262
1263     intel_batchbuffer_end_atomic(batch);
1264     intel_batchbuffer_flush(batch);
1265 }
1266
1267 static void
1268 gen6_mfc_build_avc_batchbuffer(VADriverContextP ctx,
1269                                struct encode_state *encode_state,
1270                                struct intel_encoder_context *encoder_context)
1271 {
1272     gen6_mfc_batchbuffer_surfaces_setup(ctx, encode_state, encoder_context);
1273     gen6_mfc_batchbuffer_idrt_setup(ctx, encode_state, encoder_context);
1274     gen6_mfc_batchbuffer_constant_setup(ctx, encode_state, encoder_context);
1275     gen6_mfc_avc_batchbuffer_pipeline(ctx, encode_state, encoder_context);
1276 }
1277
1278 static dri_bo *
1279 gen6_mfc_avc_hardware_batchbuffer(VADriverContextP ctx,
1280                                   struct encode_state *encode_state,
1281                                   struct intel_encoder_context *encoder_context)
1282 {
1283     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1284
1285     gen6_mfc_build_avc_batchbuffer(ctx, encode_state, encoder_context);
1286     dri_bo_reference(mfc_context->mfc_batchbuffer_surface.bo);
1287
1288     return mfc_context->mfc_batchbuffer_surface.bo;
1289 }
1290
1291 #endif
1292
1293
1294 static void
1295 gen6_mfc_avc_pipeline_programing(VADriverContextP ctx,
1296                                  struct encode_state *encode_state,
1297                                  struct intel_encoder_context *encoder_context)
1298 {
1299     struct intel_batchbuffer *batch = encoder_context->base.batch;
1300     dri_bo *slice_batch_bo;
1301
1302     if ( intel_mfc_interlace_check(ctx, encode_state, encoder_context) ) {
1303         fprintf(stderr, "Current VA driver don't support interlace mode!\n");
1304         assert(0);
1305         return;
1306     }
1307
1308 #if __SOFTWARE__
1309     slice_batch_bo = gen6_mfc_avc_software_batchbuffer(ctx, encode_state, encoder_context);
1310 #else
1311     slice_batch_bo = gen6_mfc_avc_hardware_batchbuffer(ctx, encode_state, encoder_context);
1312 #endif
1313
1314     // begin programing
1315     intel_batchbuffer_start_atomic_bcs(batch, 0x4000);
1316     intel_batchbuffer_emit_mi_flush(batch);
1317
1318     // picture level programing
1319     gen6_mfc_avc_pipeline_picture_programing(ctx, encode_state, encoder_context);
1320
1321     BEGIN_BCS_BATCH(batch, 2);
1322     OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8));
1323     OUT_BCS_RELOC(batch,
1324                   slice_batch_bo,
1325                   I915_GEM_DOMAIN_COMMAND, 0,
1326                   0);
1327     ADVANCE_BCS_BATCH(batch);
1328
1329     // end programing
1330     intel_batchbuffer_end_atomic(batch);
1331
1332     dri_bo_unreference(slice_batch_bo);
1333 }
1334
1335 VAStatus
1336 gen6_mfc_avc_encode_picture(VADriverContextP ctx,
1337                             struct encode_state *encode_state,
1338                             struct intel_encoder_context *encoder_context)
1339 {
1340     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1341     unsigned int rate_control_mode = encoder_context->rate_control_mode;
1342     int current_frame_bits_size;
1343     int sts;
1344
1345     for (;;) {
1346         gen6_mfc_init(ctx, encode_state, encoder_context);
1347         intel_mfc_avc_prepare(ctx, encode_state, encoder_context);
1348         /*Programing bcs pipeline*/
1349         gen6_mfc_avc_pipeline_programing(ctx, encode_state, encoder_context);   //filling the pipeline
1350         gen6_mfc_run(ctx, encode_state, encoder_context);
1351         if (rate_control_mode == VA_RC_CBR /*|| rate_control_mode == VA_RC_VBR*/) {
1352             gen6_mfc_stop(ctx, encode_state, encoder_context, &current_frame_bits_size);
1353             sts = intel_mfc_brc_postpack(encode_state, mfc_context, current_frame_bits_size);
1354             if (sts == BRC_NO_HRD_VIOLATION) {
1355                 intel_mfc_hrd_context_update(encode_state, mfc_context);
1356                 break;
1357             }
1358             else if (sts == BRC_OVERFLOW_WITH_MIN_QP || sts == BRC_UNDERFLOW_WITH_MAX_QP) {
1359                 if (!mfc_context->hrd.violation_noted) {
1360                     fprintf(stderr, "Unrepairable %s!\n", (sts == BRC_OVERFLOW_WITH_MIN_QP)? "overflow": "underflow");
1361                     mfc_context->hrd.violation_noted = 1;
1362                 }
1363                 return VA_STATUS_SUCCESS;
1364             }
1365         } else {
1366             break;
1367         }
1368     }
1369
1370     return VA_STATUS_SUCCESS;
1371 }
1372
1373 VAStatus
1374 gen6_mfc_pipeline(VADriverContextP ctx,
1375                   VAProfile profile,
1376                   struct encode_state *encode_state,
1377                   struct intel_encoder_context *encoder_context)
1378 {
1379     VAStatus vaStatus;
1380
1381     switch (profile) {
1382     case VAProfileH264Baseline:
1383     case VAProfileH264Main:
1384     case VAProfileH264High:
1385         vaStatus = gen6_mfc_avc_encode_picture(ctx, encode_state, encoder_context);
1386         break;
1387
1388         /* FIXME: add for other profile */
1389     default:
1390         vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
1391         break;
1392     }
1393
1394     return vaStatus;
1395 }
1396
1397 void
1398 gen6_mfc_context_destroy(void *context)
1399 {
1400     struct gen6_mfc_context *mfc_context = context;
1401     int i;
1402
1403     dri_bo_unreference(mfc_context->post_deblocking_output.bo);
1404     mfc_context->post_deblocking_output.bo = NULL;
1405
1406     dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
1407     mfc_context->pre_deblocking_output.bo = NULL;
1408
1409     dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
1410     mfc_context->uncompressed_picture_source.bo = NULL;
1411
1412     dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
1413     mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
1414
1415     for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
1416         dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
1417         mfc_context->direct_mv_buffers[i].bo = NULL;
1418     }
1419
1420     dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
1421     mfc_context->intra_row_store_scratch_buffer.bo = NULL;
1422
1423     dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
1424     mfc_context->macroblock_status_buffer.bo = NULL;
1425
1426     dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
1427     mfc_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
1428
1429     dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
1430     mfc_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
1431
1432
1433     for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
1434         dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
1435         mfc_context->reference_surfaces[i].bo = NULL;
1436     }
1437
1438     i965_gpe_context_destroy(&mfc_context->gpe_context);
1439
1440     dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo);
1441     mfc_context->mfc_batchbuffer_surface.bo = NULL;
1442
1443     dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo);
1444     mfc_context->aux_batchbuffer_surface.bo = NULL;
1445
1446     if (mfc_context->aux_batchbuffer)
1447         intel_batchbuffer_free(mfc_context->aux_batchbuffer);
1448
1449     mfc_context->aux_batchbuffer = NULL;
1450
1451     free(mfc_context);
1452 }
1453
1454 Bool gen6_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
1455 {
1456     struct gen6_mfc_context *mfc_context = calloc(1, sizeof(struct gen6_mfc_context));
1457
1458     mfc_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6;
1459
1460     mfc_context->gpe_context.idrt.max_entries = MAX_GPE_KERNELS;
1461     mfc_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data);
1462
1463     mfc_context->gpe_context.curbe.length = 32 * 4;
1464
1465     mfc_context->gpe_context.vfe_state.max_num_threads = 60 - 1;
1466     mfc_context->gpe_context.vfe_state.num_urb_entries = 16;
1467     mfc_context->gpe_context.vfe_state.gpgpu_mode = 0;
1468     mfc_context->gpe_context.vfe_state.urb_entry_size = 59 - 1;
1469     mfc_context->gpe_context.vfe_state.curbe_allocation_size = 37 - 1;
1470
1471     i965_gpe_load_kernels(ctx,
1472                           &mfc_context->gpe_context,
1473                           gen6_mfc_kernels,
1474                           NUM_MFC_KERNEL);
1475
1476     mfc_context->pipe_mode_select = gen6_mfc_pipe_mode_select;
1477     mfc_context->set_surface_state = gen6_mfc_surface_state;
1478     mfc_context->ind_obj_base_addr_state = gen6_mfc_ind_obj_base_addr_state;
1479     mfc_context->avc_img_state = gen6_mfc_avc_img_state;
1480     mfc_context->avc_qm_state = gen6_mfc_avc_qm_state;
1481     mfc_context->avc_fqm_state = gen6_mfc_avc_fqm_state;
1482     mfc_context->insert_object = gen6_mfc_avc_insert_object;
1483     mfc_context->buffer_suface_setup = i965_gpe_buffer_suface_setup;
1484
1485     encoder_context->mfc_context = mfc_context;
1486     encoder_context->mfc_context_destroy = gen6_mfc_context_destroy;
1487     encoder_context->mfc_pipeline = gen6_mfc_pipeline;
1488     encoder_context->mfc_brc_prepare = intel_mfc_brc_prepare;
1489
1490     return True;
1491 }