2 * Copyright © 2010-2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Zhou Chang <chang.zhou@intel.com>
34 #include "intel_batchbuffer.h"
35 #include "i965_defines.h"
36 #include "i965_structs.h"
37 #include "i965_drv_video.h"
38 #include "i965_encoder.h"
39 #include "i965_encoder_utils.h"
44 gen6_mfc_pipe_mode_select(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
46 struct intel_batchbuffer *batch = encoder_context->base.batch;
48 BEGIN_BCS_BATCH(batch, 4);
50 OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (4 - 2));
52 (1 << 10) | /* disable Stream-Out , advanced QP/bitrate control need enable it*/
53 (1 << 9) | /* Post Deblocking Output */
54 (0 << 8) | /* Pre Deblocking Output */
55 (0 << 7) | /* disable TLB prefectch */
56 (0 << 5) | /* not in stitch mode */
57 (1 << 4) | /* encoding mode */
58 (2 << 0)); /* Standard Select: AVC */
60 (0 << 20) | /* round flag in PB slice */
61 (0 << 19) | /* round flag in Intra8x8 */
62 (0 << 7) | /* expand NOA bus flag */
63 (1 << 6) | /* must be 1 */
64 (0 << 5) | /* disable clock gating for NOA */
65 (0 << 4) | /* terminate if AVC motion and POC table error occurs */
66 (0 << 3) | /* terminate if AVC mbdata error occurs */
67 (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */
68 (0 << 1) | /* AVC long field motion vector */
69 (0 << 0)); /* always calculate AVC ILDB boundary strength */
70 OUT_BCS_BATCH(batch, 0);
72 ADVANCE_BCS_BATCH(batch);
76 gen6_mfc_surface_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
78 struct intel_batchbuffer *batch = encoder_context->base.batch;
79 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
81 BEGIN_BCS_BATCH(batch, 6);
83 OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
84 OUT_BCS_BATCH(batch, 0);
86 ((mfc_context->surface_state.height - 1) << 19) |
87 ((mfc_context->surface_state.width - 1) << 6));
89 (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
90 (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
91 (0 << 22) | /* surface object control state, FIXME??? */
92 ((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */
93 (0 << 2) | /* must be 0 for interleave U/V */
94 (1 << 1) | /* must be y-tiled */
95 (I965_TILEWALK_YMAJOR << 0)); /* tile walk, TILEWALK_YMAJOR */
97 (0 << 16) | /* must be 0 for interleave U/V */
98 (mfc_context->surface_state.h_pitch)); /* y offset for U(cb) */
99 OUT_BCS_BATCH(batch, 0);
100 ADVANCE_BCS_BATCH(batch);
104 gen6_mfc_pipe_buf_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
106 struct intel_batchbuffer *batch = encoder_context->base.batch;
107 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
110 BEGIN_BCS_BATCH(batch, 24);
112 OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
114 OUT_BCS_BATCH(batch, 0); /* pre output addr */
116 OUT_BCS_RELOC(batch, mfc_context->post_deblocking_output.bo,
117 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
118 0); /* post output addr */
120 OUT_BCS_RELOC(batch, mfc_context->uncompressed_picture_source.bo,
121 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
122 0); /* uncompressed data */
123 OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
124 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
125 0); /* StreamOut data*/
126 OUT_BCS_RELOC(batch, mfc_context->intra_row_store_scratch_buffer.bo,
127 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
129 OUT_BCS_RELOC(batch, mfc_context->deblocking_filter_row_store_scratch_buffer.bo,
130 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
132 /* 7..22 Reference pictures*/
133 for (i = 0; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) {
134 if ( mfc_context->reference_surfaces[i].bo != NULL) {
135 OUT_BCS_RELOC(batch, mfc_context->reference_surfaces[i].bo,
136 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
139 OUT_BCS_BATCH(batch, 0);
142 OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
143 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
144 0); /* Macroblock status buffer*/
146 ADVANCE_BCS_BATCH(batch);
150 gen6_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
152 struct intel_batchbuffer *batch = encoder_context->base.batch;
153 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
154 struct gen6_vme_context *vme_context = encoder_context->vme_context;
156 BEGIN_BCS_BATCH(batch, 11);
158 OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
159 OUT_BCS_BATCH(batch, 0);
160 OUT_BCS_BATCH(batch, 0);
161 /* MFX Indirect MV Object Base Address */
162 OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
163 OUT_BCS_BATCH(batch, 0);
164 OUT_BCS_BATCH(batch, 0);
165 OUT_BCS_BATCH(batch, 0);
166 OUT_BCS_BATCH(batch, 0);
167 OUT_BCS_BATCH(batch, 0);
168 /*MFC Indirect PAK-BSE Object Base Address for Encoder*/
170 mfc_context->mfc_indirect_pak_bse_object.bo,
171 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
174 mfc_context->mfc_indirect_pak_bse_object.bo,
175 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
176 mfc_context->mfc_indirect_pak_bse_object.end_offset);
178 ADVANCE_BCS_BATCH(batch);
182 gen6_mfc_bsp_buf_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
184 struct intel_batchbuffer *batch = encoder_context->base.batch;
185 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
187 BEGIN_BCS_BATCH(batch, 4);
189 OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
190 OUT_BCS_RELOC(batch, mfc_context->bsd_mpc_row_store_scratch_buffer.bo,
191 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
193 OUT_BCS_BATCH(batch, 0);
194 OUT_BCS_BATCH(batch, 0);
196 ADVANCE_BCS_BATCH(batch);
200 gen6_mfc_avc_img_state(VADriverContextP ctx,struct encode_state *encode_state,
201 struct intel_encoder_context *encoder_context)
203 struct intel_batchbuffer *batch = encoder_context->base.batch;
204 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
205 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
206 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
207 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
208 int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
210 BEGIN_BCS_BATCH(batch, 13);
211 OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (13 - 2));
213 ((width_in_mbs * height_in_mbs) & 0xFFFF));
215 (height_in_mbs << 16) |
216 (width_in_mbs << 0));
218 (0 << 24) | /*Second Chroma QP Offset*/
219 (0 << 16) | /*Chroma QP Offset*/
220 (0 << 14) | /*Max-bit conformance Intra flag*/
221 (0 << 13) | /*Max Macroblock size conformance Inter flag*/
222 (1 << 12) | /*Should always be written as "1" */
223 (0 << 10) | /*QM Preset FLag */
224 (0 << 8) | /*Image Structure*/
225 (0 << 0) ); /*Current Decoed Image Frame Store ID, reserved in Encode mode*/
227 (400 << 16) | /*Mininum Frame size*/
228 (0 << 15) | /*Disable reading of Macroblock Status Buffer*/
229 (0 << 14) | /*Load BitStream Pointer only once, 1 slic 1 frame*/
230 (0 << 13) | /*CABAC 0 word insertion test enable*/
231 (1 << 12) | /*MVUnpackedEnable,compliant to DXVA*/
232 (1 << 10) | /*Chroma Format IDC, 4:2:0*/
233 (pPicParameter->pic_fields.bits.entropy_coding_mode_flag << 7) | /*0:CAVLC encoding mode,1:CABAC*/
234 (0 << 6) | /*Only valid for VLD decoding mode*/
235 (0 << 5) | /*Constrained Intra Predition Flag, from PPS*/
236 (pSequenceParameter->seq_fields.bits.direct_8x8_inference_flag << 4) | /*Direct 8x8 inference flag*/
237 (pPicParameter->pic_fields.bits.transform_8x8_mode_flag << 3) | /*8x8 or 4x4 IDCT Transform Mode Flag*/
238 (1 << 2) | /*Frame MB only flag*/
239 (0 << 1) | /*MBAFF mode is in active*/
240 (0 << 0) ); /*Field picture flag*/
242 (1<<16) | /*Frame Size Rate Control Flag*/
244 (1<<9) | /*MB level Rate Control Enabling Flag*/
245 (1 << 3) | /*FrameBitRateMinReportMask*/
246 (1 << 2) | /*FrameBitRateMaxReportMask*/
247 (1 << 1) | /*InterMBMaxSizeReportMask*/
248 (1 << 0) ); /*IntraMBMaxSizeReportMask*/
249 OUT_BCS_BATCH(batch, /*Inter and Intra Conformance Max size limit*/
250 (0x0600 << 16) | /*InterMbMaxSz 192 Byte*/
251 (0x0800) ); /*IntraMbMaxSz 256 Byte*/
252 OUT_BCS_BATCH(batch, 0x00000000); /*Reserved : MBZReserved*/
253 OUT_BCS_BATCH(batch, 0x01020304); /*Slice QP Delta for bitrate control*/
254 OUT_BCS_BATCH(batch, 0xFEFDFCFB);
255 OUT_BCS_BATCH(batch, 0x80601004); /*MAX = 128KB, MIN = 64KB*/
256 OUT_BCS_BATCH(batch, 0x00800001);
257 OUT_BCS_BATCH(batch, 0);
259 ADVANCE_BCS_BATCH(batch);
262 static void gen6_mfc_avc_directmode_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
264 struct intel_batchbuffer *batch = encoder_context->base.batch;
265 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
269 BEGIN_BCS_BATCH(batch, 69);
271 OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
273 /* Reference frames and Current frames */
274 for(i = 0; i < NUM_MFC_DMV_BUFFERS; i++) {
275 if ( mfc_context->direct_mv_buffers[i].bo != NULL) {
276 OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[i].bo,
277 I915_GEM_DOMAIN_INSTRUCTION, 0,
280 OUT_BCS_BATCH(batch, 0);
285 for(i = 0; i < 32; i++) {
286 OUT_BCS_BATCH(batch, i/2);
288 OUT_BCS_BATCH(batch, 0);
289 OUT_BCS_BATCH(batch, 0);
291 ADVANCE_BCS_BATCH(batch);
294 static void gen6_mfc_avc_slice_state(VADriverContextP ctx,
296 struct encode_state *encode_state,
297 struct intel_encoder_context *encoder_context,
298 int rate_control_enable,
302 struct intel_batchbuffer *batch = encoder_context->base.batch;
303 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
304 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer; /* TODO: multi slices support */
305 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
306 int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
307 int beginmb = pSliceParameter->macroblock_address;
308 int endmb = beginmb + pSliceParameter->num_macroblocks;
309 int beginx = beginmb % width_in_mbs;
310 int beginy = beginmb / width_in_mbs;
311 int nextx = endmb % width_in_mbs;
312 int nexty = endmb / width_in_mbs;
313 int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs);
314 int bit_rate_control_target;
315 if ( slice_type == SLICE_TYPE_I )
316 bit_rate_control_target = 0;
318 bit_rate_control_target = 1;
319 int maxQpN = mfc_context->bit_rate_control_context[bit_rate_control_target].MaxQpNegModifier;
320 int maxQpP = mfc_context->bit_rate_control_context[bit_rate_control_target].MaxQpPosModifier;
321 unsigned char correct[6];
324 for (i = 0; i < 6; i++)
325 correct[i] = mfc_context->bit_rate_control_context[bit_rate_control_target].Correct[i];
326 unsigned char grow = mfc_context->bit_rate_control_context[bit_rate_control_target].GrowInit +
327 (mfc_context->bit_rate_control_context[bit_rate_control_target].GrowResistance << 4);
328 unsigned char shrink = mfc_context->bit_rate_control_context[bit_rate_control_target].ShrinkInit +
329 (mfc_context->bit_rate_control_context[bit_rate_control_target].ShrinkResistance << 4);
331 BEGIN_BCS_BATCH(batch, 11);;
333 OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) );
335 OUT_BCS_BATCH(batch, slice_type); /*Slice Type: I:P:B Slice*/
337 if ( slice_type == SLICE_TYPE_I ) {
338 OUT_BCS_BATCH(batch, 0); /*no reference frames and pred_weight_table*/
340 OUT_BCS_BATCH(batch, 0x00010000); /*1 reference frame*/
344 (pSliceParameter->direct_spatial_mv_pred_flag<<29) | /*Direct Prediction Type*/
345 (0<<24) | /*Enable deblocking operation*/
346 (qp<<16) | /*Slice Quantization Parameter*/
348 OUT_BCS_BATCH(batch, (beginy << 24) | /*First MB X&Y , the begin postion of current slice*/
350 pSliceParameter->macroblock_address );
351 OUT_BCS_BATCH(batch, (nexty << 16) | nextx); /*Next slice first MB X&Y*/
353 (rate_control_enable<<31) | /*in CBR mode RateControlCounterEnable = enable*/
354 (1<<30) | /*ResetRateControlCounter*/
355 (0<<28) | /*RC Triggle Mode = Always Rate Control*/
356 (4<<24) | /*RC Stable Tolerance, middle level*/
357 (rate_control_enable<<23) | /*RC Panic Enable*/
358 (0<<22) | /*QP mode, don't modfiy CBP*/
359 (0<<21) | /*MB Type Direct Conversion Enabled*/
360 (0<<20) | /*MB Type Skip Conversion Enabled*/
361 (last_slice << 19) | /*IsLastSlice*/
362 (0<<18) | /*BitstreamOutputFlag Compressed BitStream Output Disable Flag 0:enable 1:disable*/
363 (1<<17) | /*HeaderPresentFlag*/
364 (1<<16) | /*SliceData PresentFlag*/
365 (1<<15) | /*TailPresentFlag*/
366 (1<<13) | /*RBSP NAL TYPE*/
367 (0<<12) ); /*CabacZeroWordInsertionEnable*/
369 OUT_BCS_BATCH(batch, mfc_context->mfc_indirect_pak_bse_object.offset);
371 OUT_BCS_BATCH(batch, (maxQpN<<24) | /*Target QP - 24 is lowest QP*/
372 (maxQpP<<16) | /*Target QP + 20 is highest QP*/
375 OUT_BCS_BATCH(batch, (correct[5] << 20) |
381 OUT_BCS_BATCH(batch, 0);
383 ADVANCE_BCS_BATCH(batch);
385 static void gen6_mfc_avc_qm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
387 struct intel_batchbuffer *batch = encoder_context->base.batch;
390 BEGIN_BCS_BATCH(batch, 58);
392 OUT_BCS_BATCH(batch, MFX_AVC_QM_STATE | 56);
393 OUT_BCS_BATCH(batch, 0xFF ) ;
394 for( i = 0; i < 56; i++) {
395 OUT_BCS_BATCH(batch, 0x10101010);
398 ADVANCE_BCS_BATCH(batch);
401 static void gen6_mfc_avc_fqm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
403 struct intel_batchbuffer *batch = encoder_context->base.batch;
406 BEGIN_BCS_BATCH(batch, 113);
407 OUT_BCS_BATCH(batch, MFC_AVC_FQM_STATE | (113 - 2));
409 for(i = 0; i < 112;i++) {
410 OUT_BCS_BATCH(batch, 0x10001000);
413 ADVANCE_BCS_BATCH(batch);
416 static void gen6_mfc_avc_ref_idx_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
418 struct intel_batchbuffer *batch = encoder_context->base.batch;
421 BEGIN_BCS_BATCH(batch, 10);
422 OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
423 OUT_BCS_BATCH(batch, 0); //Select L0
424 OUT_BCS_BATCH(batch, 0x80808020); //Only 1 reference
425 for(i = 0; i < 7; i++) {
426 OUT_BCS_BATCH(batch, 0x80808080);
428 ADVANCE_BCS_BATCH(batch);
430 BEGIN_BCS_BATCH(batch, 10);
431 OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
432 OUT_BCS_BATCH(batch, 1); //Select L1
433 OUT_BCS_BATCH(batch, 0x80808022); //Only 1 reference
434 for(i = 0; i < 7; i++) {
435 OUT_BCS_BATCH(batch, 0x80808080);
437 ADVANCE_BCS_BATCH(batch);
441 gen6_mfc_avc_insert_object(VADriverContextP ctx, struct intel_encoder_context *encoder_context,
442 unsigned int *insert_data, int lenght_in_dws, int data_bits_in_last_dw,
443 int skip_emul_byte_count, int is_last_header, int is_end_of_slice, int emulation_flag)
445 struct i965_driver_data *i965 = i965_driver_data(ctx);
446 struct intel_batchbuffer *batch = encoder_context->base.batch;
448 BEGIN_BCS_BATCH(batch, lenght_in_dws + 2);
450 if (IS_GEN7(i965->intel.device_id))
451 OUT_BCS_BATCH(batch, MFX_INSERT_OBJECT | (lenght_in_dws + 2 - 2));
453 OUT_BCS_BATCH(batch, MFC_AVC_INSERT_OBJECT | (lenght_in_dws + 2 - 2));
456 (0 << 16) | /* always start at offset 0 */
457 (data_bits_in_last_dw << 8) |
458 (skip_emul_byte_count << 4) |
459 (!!emulation_flag << 3) |
460 ((!!is_last_header) << 2) |
461 ((!!is_end_of_slice) << 1) |
462 (0 << 0)); /* FIXME: ??? */
464 intel_batchbuffer_data(batch, insert_data, lenght_in_dws * 4);
465 ADVANCE_BCS_BATCH(batch);
469 gen6_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb, int qp,unsigned int *msg,
470 struct intel_encoder_context *encoder_context,
471 unsigned char target_mb_size, unsigned char max_mb_size)
473 struct intel_batchbuffer *batch = encoder_context->base.batch;
474 int len_in_dwords = 11;
476 BEGIN_BCS_BATCH(batch, len_in_dwords);
478 OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
479 OUT_BCS_BATCH(batch, 0);
480 OUT_BCS_BATCH(batch, 0);
482 (0 << 24) | /* PackedMvNum, Debug*/
483 (0 << 20) | /* No motion vector */
484 (1 << 19) | /* CbpDcY */
485 (1 << 18) | /* CbpDcU */
486 (1 << 17) | /* CbpDcV */
489 OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x); /* Code Block Pattern for Y*/
490 OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */
491 OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp); /* Last MB */
493 /*Stuff for Intra MB*/
494 OUT_BCS_BATCH(batch, msg[1]); /* We using Intra16x16 no 4x4 predmode*/
495 OUT_BCS_BATCH(batch, msg[2]);
496 OUT_BCS_BATCH(batch, msg[3]&0xFC);
498 /*MaxSizeInWord and TargetSzieInWord*/
499 OUT_BCS_BATCH(batch, (max_mb_size << 24) |
500 (target_mb_size << 16) );
502 ADVANCE_BCS_BATCH(batch);
504 return len_in_dwords;
507 static int gen6_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, int qp, unsigned int offset,
508 struct intel_encoder_context *encoder_context,
509 unsigned char target_mb_size,unsigned char max_mb_size, int slice_type)
511 struct intel_batchbuffer *batch = encoder_context->base.batch;
512 int len_in_dwords = 11;
514 BEGIN_BCS_BATCH(batch, len_in_dwords);
516 OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
518 OUT_BCS_BATCH(batch, 32); /* 32 MV*/
519 OUT_BCS_BATCH(batch, offset);
522 (1 << 24) | /* PackedMvNum, Debug*/
523 (4 << 20) | /* 8 MV, SNB don't use it*/
524 (1 << 19) | /* CbpDcY */
525 (1 << 18) | /* CbpDcU */
526 (1 << 17) | /* CbpDcV */
527 (0 << 15) | /* Transform8x8Flag = 0*/
528 (0 << 14) | /* Frame based*/
529 (0 << 13) | /* Inter MB */
530 (1 << 8) | /* MbType = P_L0_16x16 */
531 (0 << 7) | /* MBZ for frame */
533 (2 << 4) | /* MBZ for inter*/
535 (0 << 2) | /* SkipMbFlag */
536 (0 << 0)); /* InterMbMode */
538 OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x); /* Code Block Pattern for Y*/
539 OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */
541 if ( slice_type == SLICE_TYPE_B) {
542 OUT_BCS_BATCH(batch, (0xF<<28) | (end_mb << 26) | qp); /* Last MB */
544 OUT_BCS_BATCH(batch, (end_mb << 26) | qp); /* Last MB */
547 OUT_BCS_BATCH(batch, (end_mb << 26) | qp); /* Last MB */
551 /*Stuff for Inter MB*/
552 OUT_BCS_BATCH(batch, 0x0);
553 OUT_BCS_BATCH(batch, 0x0);
554 OUT_BCS_BATCH(batch, 0x0);
556 /*MaxSizeInWord and TargetSzieInWord*/
557 OUT_BCS_BATCH(batch, (max_mb_size << 24) |
558 (target_mb_size << 16) );
560 ADVANCE_BCS_BATCH(batch);
562 return len_in_dwords;
565 static void gen6_mfc_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
567 struct i965_driver_data *i965 = i965_driver_data(ctx);
568 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
572 /*Encode common setup for MFC*/
573 dri_bo_unreference(mfc_context->post_deblocking_output.bo);
574 mfc_context->post_deblocking_output.bo = NULL;
576 dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
577 mfc_context->pre_deblocking_output.bo = NULL;
579 dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
580 mfc_context->uncompressed_picture_source.bo = NULL;
582 dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
583 mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
585 for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
586 if ( mfc_context->direct_mv_buffers[i].bo != NULL);
587 dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
588 mfc_context->direct_mv_buffers[i].bo = NULL;
591 for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
592 if (mfc_context->reference_surfaces[i].bo != NULL)
593 dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
594 mfc_context->reference_surfaces[i].bo = NULL;
597 dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
598 bo = dri_bo_alloc(i965->intel.bufmgr,
603 mfc_context->intra_row_store_scratch_buffer.bo = bo;
605 dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
606 bo = dri_bo_alloc(i965->intel.bufmgr,
611 mfc_context->macroblock_status_buffer.bo = bo;
613 dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
614 bo = dri_bo_alloc(i965->intel.bufmgr,
616 49152, /* 6 * 128 * 64 */
619 mfc_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
621 dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
622 bo = dri_bo_alloc(i965->intel.bufmgr,
624 12288, /* 1.5 * 128 * 64 */
627 mfc_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
630 static void gen6_mfc_avc_pipeline_header_programing(VADriverContextP ctx,
631 struct encode_state *encode_state,
632 struct intel_encoder_context *encoder_context)
634 static int count = 0;
635 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
636 unsigned int rate_control_mode = encoder_context->rate_control_mode;
638 if (encode_state->packed_header_data[VAEncPackedHeaderH264_SPS]) {
639 VAEncPackedHeaderParameterBuffer *param = NULL;
640 unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[VAEncPackedHeaderH264_SPS]->buffer;
641 unsigned int length_in_bits;
643 assert(encode_state->packed_header_param[VAEncPackedHeaderH264_SPS]);
644 param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[VAEncPackedHeaderH264_SPS]->buffer;
645 length_in_bits = param->bit_length;
647 gen6_mfc_avc_insert_object(ctx,
650 ALIGN(length_in_bits, 32) >> 5,
651 length_in_bits & 0x1f,
652 5, /* FIXME: check it */
655 !param->has_emulation_bytes);
658 if (encode_state->packed_header_data[VAEncPackedHeaderH264_PPS]) {
659 VAEncPackedHeaderParameterBuffer *param = NULL;
660 unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[VAEncPackedHeaderH264_PPS]->buffer;
661 unsigned int length_in_bits;
663 assert(encode_state->packed_header_param[VAEncPackedHeaderH264_PPS]);
664 param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[VAEncPackedHeaderH264_PPS]->buffer;
665 length_in_bits = param->bit_length;
667 gen6_mfc_avc_insert_object(ctx,
670 ALIGN(length_in_bits, 32) >> 5,
671 length_in_bits & 0x1f,
672 5, /* FIXME: check it */
675 !param->has_emulation_bytes);
678 if ( (rate_control_mode == VA_RC_CBR) && encode_state->packed_header_data[VAEncPackedHeaderH264_SPS]) { // this is frist AU
679 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
681 unsigned char *sei_data = NULL;
682 int length_in_bits = build_avc_sei_buffering_period(mfc_context->vui_hrd.i_initial_cpb_removal_delay_length,
683 mfc_context->vui_hrd.i_initial_cpb_removal_delay, 0, &sei_data);
684 gen6_mfc_avc_insert_object(ctx,
686 (unsigned int *)sei_data,
687 ALIGN(length_in_bits, 32) >> 5,
688 length_in_bits & 0x1f,
696 // SEI pic_timing header
697 if (rate_control_mode == VA_RC_CBR) {
698 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
699 unsigned char *sei_data = NULL;
700 int length_in_bits = build_avc_sei_pic_timing( mfc_context->vui_hrd.i_cpb_removal_delay_length,
701 mfc_context->vui_hrd.i_cpb_removal_delay * mfc_context->vui_hrd.i_frame_number,
702 mfc_context->vui_hrd.i_dpb_output_delay_length,
704 gen6_mfc_avc_insert_object(ctx,
706 (unsigned int *)sei_data,
707 ALIGN(length_in_bits, 32) >> 5,
708 length_in_bits & 0x1f,
719 static void gen6_mfc_avc_pipeline_picture_programing( VADriverContextP ctx,
720 struct encode_state *encode_state,
721 struct intel_encoder_context *encoder_context)
723 gen6_mfc_pipe_mode_select(ctx, encoder_context);
724 gen6_mfc_surface_state(ctx, encoder_context);
725 gen6_mfc_ind_obj_base_addr_state(ctx, encoder_context);
726 gen6_mfc_pipe_buf_addr_state(ctx, encoder_context);
727 gen6_mfc_bsp_buf_base_addr_state(ctx, encoder_context);
728 gen6_mfc_avc_img_state(ctx, encode_state, encoder_context);
729 gen6_mfc_avc_qm_state(ctx, encoder_context);
730 gen6_mfc_avc_fqm_state(ctx, encoder_context);
731 gen6_mfc_avc_directmode_state(ctx, encoder_context);
732 gen6_mfc_avc_ref_idx_state(ctx, encoder_context);
736 gen6_mfc_avc_pipeline_slice_programing(VADriverContextP ctx,
737 struct encode_state *encode_state,
738 struct intel_encoder_context *encoder_context,
741 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
742 struct gen6_vme_context *vme_context = encoder_context->vme_context;
743 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
744 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
745 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
746 unsigned int *msg = NULL, offset = 0;
747 int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
748 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
749 int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
750 int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs);
752 int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta;
753 unsigned int rate_control_mode = encoder_context->rate_control_mode;
754 unsigned char *slice_header = NULL;
755 int slice_header_length_in_bits = 0;
756 unsigned int tail_data[] = { 0x0, 0x0 };
758 gen6_mfc_avc_slice_state(ctx, pSliceParameter->slice_type,
759 encode_state, encoder_context,
760 (rate_control_mode == VA_RC_CBR), qp, slice_index);
762 if ( slice_index == 0)
763 gen6_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context);
765 slice_header_length_in_bits = build_avc_slice_header(pSequenceParameter, pPicParameter, pSliceParameter, &slice_header);
768 gen6_mfc_avc_insert_object(ctx, encoder_context,
769 (unsigned int *)slice_header, ALIGN(slice_header_length_in_bits, 32) >> 5, slice_header_length_in_bits & 0x1f,
770 5, /* first 5 bytes are start code + nal unit type */
773 if (rate_control_mode == VA_RC_CBR) {
774 qp = mfc_context->bit_rate_control_context[1-is_intra].QpPrimeY;
778 dri_bo_map(vme_context->vme_output.bo , 1);
779 msg = (unsigned int *)vme_context->vme_output.bo->virtual;
782 for (i = pSliceParameter->macroblock_address;
783 i < pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks; i++) {
784 int last_mb = (i == (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks - 1) );
785 x = i % width_in_mbs;
786 y = i / width_in_mbs;
790 gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0);
793 gen6_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, offset, encoder_context, 0, 0, pSliceParameter->slice_type);
799 dri_bo_unmap(vme_context->vme_output.bo);
801 gen6_mfc_avc_insert_object(ctx, encoder_context,
805 gen6_mfc_avc_insert_object(ctx, encoder_context,
815 gen6_mfc_avc_pipeline_programing(VADriverContextP ctx,
816 struct encode_state *encode_state,
817 struct intel_encoder_context *encoder_context)
819 struct intel_batchbuffer *batch = encoder_context->base.batch;
823 intel_batchbuffer_start_atomic_bcs(batch, 0x4000);
824 intel_batchbuffer_emit_mi_flush(batch);
826 // picture level programing
827 gen6_mfc_avc_pipeline_picture_programing(ctx, encode_state, encoder_context);
829 for ( i = 0; i < encode_state->num_slice_params_ext; i++) {
830 // slice level programing
831 gen6_mfc_avc_pipeline_slice_programing(ctx, encode_state, encoder_context, i);
835 intel_batchbuffer_end_atomic(batch);
841 gen6_mfc_free_avc_surface(void **data)
843 struct gen6_mfc_avc_surface_aux *avc_surface = *data;
848 dri_bo_unreference(avc_surface->dmv_top);
849 avc_surface->dmv_top = NULL;
850 dri_bo_unreference(avc_surface->dmv_bottom);
851 avc_surface->dmv_bottom = NULL;
857 static void gen6_mfc_bit_rate_control_context_init(struct encode_state *encode_state,
858 struct gen6_mfc_context *mfc_context)
860 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
862 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
863 int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
864 float fps = pSequenceParameter->time_scale * 0.5 / pSequenceParameter->num_units_in_tick ;
865 int inter_mb_size = pSequenceParameter->bits_per_second * 1.0 / (fps+4.0) / width_in_mbs / height_in_mbs;
866 int intra_mb_size = inter_mb_size * 5.0;
869 mfc_context->bit_rate_control_context[0].target_mb_size = intra_mb_size;
870 mfc_context->bit_rate_control_context[0].target_frame_size = intra_mb_size * width_in_mbs * height_in_mbs;
871 mfc_context->bit_rate_control_context[1].target_mb_size = inter_mb_size;
872 mfc_context->bit_rate_control_context[1].target_frame_size = inter_mb_size * width_in_mbs * height_in_mbs;
874 for(i = 0 ; i < 2; i++) {
875 mfc_context->bit_rate_control_context[i].QpPrimeY = 26;
876 mfc_context->bit_rate_control_context[i].MaxQpNegModifier = 6;
877 mfc_context->bit_rate_control_context[i].MaxQpPosModifier = 6;
878 mfc_context->bit_rate_control_context[i].GrowInit = 6;
879 mfc_context->bit_rate_control_context[i].GrowResistance = 4;
880 mfc_context->bit_rate_control_context[i].ShrinkInit = 6;
881 mfc_context->bit_rate_control_context[i].ShrinkResistance = 4;
883 mfc_context->bit_rate_control_context[i].Correct[0] = 8;
884 mfc_context->bit_rate_control_context[i].Correct[1] = 4;
885 mfc_context->bit_rate_control_context[i].Correct[2] = 2;
886 mfc_context->bit_rate_control_context[i].Correct[3] = 2;
887 mfc_context->bit_rate_control_context[i].Correct[4] = 4;
888 mfc_context->bit_rate_control_context[i].Correct[5] = 8;
891 mfc_context->bit_rate_control_context[0].TargetSizeInWord = (intra_mb_size + 16)/ 16;
892 mfc_context->bit_rate_control_context[1].TargetSizeInWord = (inter_mb_size + 16)/ 16;
894 mfc_context->bit_rate_control_context[0].MaxSizeInWord = mfc_context->bit_rate_control_context[0].TargetSizeInWord * 1.5;
895 mfc_context->bit_rate_control_context[1].MaxSizeInWord = mfc_context->bit_rate_control_context[1].TargetSizeInWord * 1.5;
898 static int gen6_mfc_bit_rate_control_context_update(struct encode_state *encode_state,
899 struct gen6_mfc_context *mfc_context,
900 int current_frame_size)
902 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[0]->buffer;
903 int control_index = 1 - (pSliceParameter->slice_type == SLICE_TYPE_I);
904 int oldQp = mfc_context->bit_rate_control_context[control_index].QpPrimeY;
907 printf("conrol_index = %d, start_qp = %d, result = %d, target = %d\n", control_index,
908 mfc_context->bit_rate_control_context[control_index].QpPrimeY, current_frame_size,
909 mfc_context->bit_rate_control_context[control_index].target_frame_size );
912 if ( current_frame_size > mfc_context->bit_rate_control_context[control_index].target_frame_size * 4.0 ) {
913 mfc_context->bit_rate_control_context[control_index].QpPrimeY += 4;
914 } else if ( current_frame_size > mfc_context->bit_rate_control_context[control_index].target_frame_size * 2.0 ) {
915 mfc_context->bit_rate_control_context[control_index].QpPrimeY += 3;
916 } else if ( current_frame_size > mfc_context->bit_rate_control_context[control_index].target_frame_size * 1.50 ) {
917 mfc_context->bit_rate_control_context[control_index].QpPrimeY += 2;
918 } else if ( current_frame_size > mfc_context->bit_rate_control_context[control_index].target_frame_size * 1.20 ) {
919 mfc_context->bit_rate_control_context[control_index].QpPrimeY ++;
920 } else if (current_frame_size < mfc_context->bit_rate_control_context[control_index].target_frame_size * 0.30 ) {
921 mfc_context->bit_rate_control_context[control_index].QpPrimeY -= 3;
922 } else if (current_frame_size < mfc_context->bit_rate_control_context[control_index].target_frame_size * 0.50 ) {
923 mfc_context->bit_rate_control_context[control_index].QpPrimeY -= 2;
924 } else if (current_frame_size < mfc_context->bit_rate_control_context[control_index].target_frame_size * 0.80 ) {
925 mfc_context->bit_rate_control_context[control_index].QpPrimeY --;
928 if ( mfc_context->bit_rate_control_context[control_index].QpPrimeY > 51)
929 mfc_context->bit_rate_control_context[control_index].QpPrimeY = 51;
930 if ( mfc_context->bit_rate_control_context[control_index].QpPrimeY < 1)
931 mfc_context->bit_rate_control_context[control_index].QpPrimeY = 1;
933 if ( mfc_context->bit_rate_control_context[control_index].QpPrimeY != oldQp)
940 gen6_mfc_hrd_context_init(struct encode_state *encode_state,
941 struct intel_encoder_context *encoder_context)
943 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
944 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
945 unsigned int rate_control_mode = encoder_context->rate_control_mode;
946 int target_bit_rate = pSequenceParameter->bits_per_second;
948 // current we only support CBR mode.
949 if (rate_control_mode == VA_RC_CBR) {
950 mfc_context->vui_hrd.i_bit_rate_value = target_bit_rate >> 10;
951 mfc_context->vui_hrd.i_cpb_size_value = (target_bit_rate * 8) >> 10;
952 mfc_context->vui_hrd.i_initial_cpb_removal_delay = mfc_context->vui_hrd.i_cpb_size_value * 0.5 * 1024 / target_bit_rate * 90000;
953 mfc_context->vui_hrd.i_cpb_removal_delay = 2;
954 mfc_context->vui_hrd.i_frame_number = 0;
956 mfc_context->vui_hrd.i_initial_cpb_removal_delay_length = 24;
957 mfc_context->vui_hrd.i_cpb_removal_delay_length = 24;
958 mfc_context->vui_hrd.i_dpb_output_delay_length = 24;
964 gen6_mfc_hrd_context_check(struct encode_state *encode_state,
965 struct gen6_mfc_context *mfc_context)
967 return VA_STATUS_SUCCESS;
971 gen6_mfc_hrd_context_update(struct encode_state *encode_state,
972 struct gen6_mfc_context *mfc_context)
974 mfc_context->vui_hrd.i_frame_number++;
977 static VAStatus gen6_mfc_avc_prepare(VADriverContextP ctx,
978 struct encode_state *encode_state,
979 struct intel_encoder_context *encoder_context)
981 struct i965_driver_data *i965 = i965_driver_data(ctx);
982 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
983 struct object_surface *obj_surface;
984 struct object_buffer *obj_buffer;
985 struct gen6_mfc_avc_surface_aux* gen6_avc_surface;
987 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
988 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
989 unsigned int rate_control_mode = encoder_context->rate_control_mode;
990 VAStatus vaStatus = VA_STATUS_SUCCESS;
993 /*Setup all the input&output object*/
995 /* Setup current frame and current direct mv buffer*/
996 obj_surface = SURFACE(pPicParameter->CurrPic.picture_id);
998 i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
1000 if ( obj_surface->private_data == NULL) {
1001 gen6_avc_surface = calloc(sizeof(struct gen6_mfc_avc_surface_aux), 1);
1002 gen6_avc_surface->dmv_top =
1003 dri_bo_alloc(i965->intel.bufmgr,
1007 gen6_avc_surface->dmv_bottom =
1008 dri_bo_alloc(i965->intel.bufmgr,
1012 assert(gen6_avc_surface->dmv_top);
1013 assert(gen6_avc_surface->dmv_bottom);
1014 obj_surface->private_data = (void *)gen6_avc_surface;
1015 obj_surface->free_private_data = (void *)gen6_mfc_free_avc_surface;
1017 gen6_avc_surface = (struct gen6_mfc_avc_surface_aux*) obj_surface->private_data;
1018 mfc_context->direct_mv_buffers[NUM_MFC_DMV_BUFFERS - 2].bo = gen6_avc_surface->dmv_top;
1019 mfc_context->direct_mv_buffers[NUM_MFC_DMV_BUFFERS - 1].bo = gen6_avc_surface->dmv_bottom;
1020 dri_bo_reference(gen6_avc_surface->dmv_top);
1021 dri_bo_reference(gen6_avc_surface->dmv_bottom);
1023 mfc_context->post_deblocking_output.bo = obj_surface->bo;
1024 dri_bo_reference(mfc_context->post_deblocking_output.bo);
1026 mfc_context->surface_state.width = obj_surface->orig_width;
1027 mfc_context->surface_state.height = obj_surface->orig_height;
1028 mfc_context->surface_state.w_pitch = obj_surface->width;
1029 mfc_context->surface_state.h_pitch = obj_surface->height;
1031 /* Setup reference frames and direct mv buffers*/
1032 for(i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++) {
1033 if ( pPicParameter->ReferenceFrames[i].picture_id != VA_INVALID_ID ) {
1034 obj_surface = SURFACE(pPicParameter->ReferenceFrames[i].picture_id);
1035 assert(obj_surface);
1036 if (obj_surface->bo != NULL) {
1037 mfc_context->reference_surfaces[i].bo = obj_surface->bo;
1038 dri_bo_reference(obj_surface->bo);
1040 /* Check DMV buffer */
1041 if ( obj_surface->private_data == NULL) {
1043 gen6_avc_surface = calloc(sizeof(struct gen6_mfc_avc_surface_aux), 1);
1044 gen6_avc_surface->dmv_top =
1045 dri_bo_alloc(i965->intel.bufmgr,
1049 gen6_avc_surface->dmv_bottom =
1050 dri_bo_alloc(i965->intel.bufmgr,
1054 assert(gen6_avc_surface->dmv_top);
1055 assert(gen6_avc_surface->dmv_bottom);
1056 obj_surface->private_data = gen6_avc_surface;
1057 obj_surface->free_private_data = gen6_mfc_free_avc_surface;
1060 gen6_avc_surface = (struct gen6_mfc_avc_surface_aux*) obj_surface->private_data;
1061 /* Setup DMV buffer */
1062 mfc_context->direct_mv_buffers[i*2].bo = gen6_avc_surface->dmv_top;
1063 mfc_context->direct_mv_buffers[i*2+1].bo = gen6_avc_surface->dmv_bottom;
1064 dri_bo_reference(gen6_avc_surface->dmv_top);
1065 dri_bo_reference(gen6_avc_surface->dmv_bottom);
1071 obj_surface = SURFACE(encoder_context->input_yuv_surface);
1072 assert(obj_surface && obj_surface->bo);
1073 mfc_context->uncompressed_picture_source.bo = obj_surface->bo;
1074 dri_bo_reference(mfc_context->uncompressed_picture_source.bo);
1076 obj_buffer = BUFFER (pPicParameter->coded_buf); /* FIXME: fix this later */
1077 bo = obj_buffer->buffer_store->bo;
1079 mfc_context->mfc_indirect_pak_bse_object.bo = bo;
1080 mfc_context->mfc_indirect_pak_bse_object.offset = ALIGN(sizeof(VACodedBufferSegment), 64);
1081 mfc_context->mfc_indirect_pak_bse_object.end_offset = ALIGN (obj_buffer->size_element - 0x1000, 0x1000);
1082 dri_bo_reference(mfc_context->mfc_indirect_pak_bse_object.bo);
1084 /*Programing bit rate control */
1085 if ( mfc_context->bit_rate_control_context[0].MaxSizeInWord == 0 )
1086 gen6_mfc_bit_rate_control_context_init(encode_state, mfc_context);
1088 /*Programing HRD control */
1089 if ( (rate_control_mode == VA_RC_CBR) && (mfc_context->vui_hrd.i_cpb_size_value == 0) )
1090 gen6_mfc_hrd_context_init(encode_state, encoder_context);
1092 /*Programing bcs pipeline*/
1093 gen6_mfc_avc_pipeline_programing(ctx, encode_state, encoder_context); //filling the pipeline
1098 static VAStatus gen6_mfc_run(VADriverContextP ctx,
1099 struct encode_state *encode_state,
1100 struct intel_encoder_context *encoder_context)
1102 struct intel_batchbuffer *batch = encoder_context->base.batch;
1104 intel_batchbuffer_flush(batch); //run the pipeline
1106 return VA_STATUS_SUCCESS;
1109 static VAStatus gen6_mfc_stop(VADriverContextP ctx,
1110 struct encode_state *encode_state,
1111 struct intel_encoder_context *encoder_context,
1112 int *encoded_bits_size)
1114 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1115 unsigned int *status_mem;
1116 unsigned int buffer_size_bits = 0;
1117 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
1118 int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
1121 dri_bo_map(mfc_context->macroblock_status_buffer.bo, 1);
1122 status_mem = (unsigned int *)mfc_context->macroblock_status_buffer.bo->virtual;
1123 //Detecting encoder buffer size and bit rate control result
1124 for(i = 0; i < width_in_mbs * height_in_mbs; i++) {
1125 unsigned short current_mb = status_mem[1] >> 16;
1126 buffer_size_bits += current_mb;
1129 dri_bo_unmap(mfc_context->macroblock_status_buffer.bo);
1131 *encoded_bits_size = buffer_size_bits;
1133 return VA_STATUS_SUCCESS;
1137 gen6_mfc_avc_encode_picture(VADriverContextP ctx,
1138 struct encode_state *encode_state,
1139 struct intel_encoder_context *encoder_context)
1141 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
1142 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1143 int rate_control_mode = encoder_context->rate_control_mode;
1144 int MAX_CBR_INTERATE = 4;
1145 int current_frame_bits_size;
1148 for(i = 0; i < MAX_CBR_INTERATE; i++) {
1149 gen6_mfc_init(ctx, encoder_context);
1150 gen6_mfc_avc_prepare(ctx, encode_state, encoder_context);
1151 gen6_mfc_run(ctx, encode_state, encoder_context);
1152 gen6_mfc_stop(ctx, encode_state, encoder_context, ¤t_frame_bits_size);
1153 if (rate_control_mode == VA_RC_CBR) {
1154 //gen6_mfc_hrd_context_check(encode_state, mfc_context);
1155 if ( gen6_mfc_bit_rate_control_context_update( encode_state, mfc_context, current_frame_bits_size) ) {
1156 gen6_mfc_hrd_context_update(encode_state, mfc_context);
1164 return VA_STATUS_SUCCESS;
1168 gen6_mfc_pipeline(VADriverContextP ctx,
1170 struct encode_state *encode_state,
1171 struct intel_encoder_context *encoder_context)
1176 case VAProfileH264Baseline:
1177 vaStatus = gen6_mfc_avc_encode_picture(ctx, encode_state, encoder_context);
1180 /* FIXME: add for other profile */
1182 vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
1190 gen6_mfc_context_destroy(void *context)
1192 struct gen6_mfc_context *mfc_context = context;
1195 dri_bo_unreference(mfc_context->post_deblocking_output.bo);
1196 mfc_context->post_deblocking_output.bo = NULL;
1198 dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
1199 mfc_context->pre_deblocking_output.bo = NULL;
1201 dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
1202 mfc_context->uncompressed_picture_source.bo = NULL;
1204 dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
1205 mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
1207 for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
1208 dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
1209 mfc_context->direct_mv_buffers[i].bo = NULL;
1212 dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
1213 mfc_context->intra_row_store_scratch_buffer.bo = NULL;
1215 dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
1216 mfc_context->macroblock_status_buffer.bo = NULL;
1218 dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
1219 mfc_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
1221 dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
1222 mfc_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
1225 for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
1226 dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
1227 mfc_context->reference_surfaces[i].bo = NULL;
1233 Bool gen6_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
1235 encoder_context->mfc_context = calloc(1, sizeof(struct gen6_mfc_context));
1236 encoder_context->mfc_context_destroy = gen6_mfc_context_destroy;
1237 encoder_context->mfc_pipeline = gen6_mfc_pipeline;