src/gen6_mfc.c

   1 /*
   2  * Copyright © 2010-2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Zhou Chang <chang.zhou@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <assert.h>
  33
  34 #include "assert.h"
  35 #include "intel_batchbuffer.h"
  36 #include "i965_defines.h"
  37 #include "i965_structs.h"
  38 #include "i965_drv_video.h"
  39 #include "i965_encoder.h"
  40
  41 static void
  42 gen6_mfc_pipe_mode_select(VADriverContextP ctx,
  43                           struct gen6_encoder_context *gen6_encoder_context,
  44                           struct intel_batchbuffer *batch)
  45 {
  46     if (batch == NULL)
  47         batch = gen6_encoder_context->base.batch;
  48
  49     BEGIN_BCS_BATCH(batch, 4);
  50
  51     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (4 - 2));
  52     OUT_BCS_BATCH(batch,
  53                   (0 << 10) | /* disable Stream-Out */
  54                   (1 << 9)  | /* Post Deblocking Output */
  55                   (0 << 8)  | /* Pre Deblocking Output */
  56                   (0 << 7)  | /* disable TLB prefectch */
  57                   (0 << 5)  | /* not in stitch mode */
  58                   (1 << 4)  | /* encoding mode */
  59                   (2 << 0));  /* Standard Select: AVC */
  60     OUT_BCS_BATCH(batch,
  61                   (0 << 20) | /* round flag in PB slice */
  62                   (0 << 19) | /* round flag in Intra8x8 */
  63                   (0 << 7)  | /* expand NOA bus flag */
  64                   (1 << 6)  | /* must be 1 */
  65                   (0 << 5)  | /* disable clock gating for NOA */
  66                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
  67                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
  68                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
  69                   (0 << 1)  | /* AVC long field motion vector */
  70                   (0 << 0));  /* always calculate AVC ILDB boundary strength */
  71     OUT_BCS_BATCH(batch, 0);
  72
  73     ADVANCE_BCS_BATCH(batch);
  74 }
  75
  76 static void
  77 gen7_mfc_pipe_mode_select(VADriverContextP ctx,
  78                           int standard_select,
  79                           struct gen6_encoder_context *gen6_encoder_context,
  80                           struct intel_batchbuffer *batch)
  81 {
  82     if (batch == NULL)
  83         batch = gen6_encoder_context->base.batch;
  84
  85     assert(standard_select == MFX_FORMAT_MPEG2 ||
  86            standard_select == MFX_FORMAT_AVC);
  87
  88     BEGIN_BCS_BATCH(batch, 5);
  89     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (5 - 2));
  90     OUT_BCS_BATCH(batch,
  91                   (MFX_LONG_MODE << 17) | /* Must be long format for encoder */
  92                   (MFD_MODE_VLD << 15) | /* VLD mode */
  93                   (0 << 10) | /* disable Stream-Out */
  94                   (1 << 9)  | /* Post Deblocking Output */
  95                   (0 << 8)  | /* Pre Deblocking Output */
  96                   (0 << 5)  | /* not in stitch mode */
  97                   (1 << 4)  | /* encoding mode */
  98                   (standard_select << 0));  /* standard select: avc or mpeg2 */
  99     OUT_BCS_BATCH(batch,
 100                   (0 << 7)  | /* expand NOA bus flag */
 101                   (0 << 6)  | /* disable slice-level clock gating */
 102                   (0 << 5)  | /* disable clock gating for NOA */
 103                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
 104                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
 105                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
 106                   (0 << 1)  |
 107                   (0 << 0));
 108     OUT_BCS_BATCH(batch, 0);
 109     OUT_BCS_BATCH(batch, 0);
 110
 111     ADVANCE_BCS_BATCH(batch);
 112 }
 113
 114 static void
 115 gen6_mfc_surface_state(VADriverContextP ctx,
 116                        struct gen6_encoder_context *gen6_encoder_context,
 117                        struct intel_batchbuffer *batch)
 118 {
 119     struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
 120
 121     if (batch == NULL)
 122         batch = gen6_encoder_context->base.batch;
 123
 124     BEGIN_BCS_BATCH(batch, 6);
 125
 126     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
 127     OUT_BCS_BATCH(batch, 0);
 128     OUT_BCS_BATCH(batch,
 129                   ((mfc_context->surface_state.height - 1) << 19) |
 130                   ((mfc_context->surface_state.width - 1) << 6));
 131     OUT_BCS_BATCH(batch,
 132                   (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
 133                   (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
 134                   (0 << 22) | /* surface object control state, FIXME??? */
 135                   ((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */
 136                   (0 << 2)  | /* must be 0 for interleave U/V */
 137                   (1 << 1)  | /* must be y-tiled */
 138                   (I965_TILEWALK_YMAJOR << 0));                         /* tile walk, TILEWALK_YMAJOR */
 139     OUT_BCS_BATCH(batch,
 140                   (0 << 16) |                                                           /* must be 0 for interleave U/V */
 141                   (mfc_context->surface_state.h_pitch));                /* y offset for U(cb) */
 142     OUT_BCS_BATCH(batch, 0);
 143     ADVANCE_BCS_BATCH(batch);
 144 }
 145
 146 static void
 147 gen7_mfc_surface_state(VADriverContextP ctx,
 148                        struct gen6_encoder_context *gen6_encoder_context,
 149                        struct intel_batchbuffer *batch)
 150 {
 151     struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
 152
 153     if (batch == NULL)
 154         batch = gen6_encoder_context->base.batch;
 155
 156     BEGIN_BCS_BATCH(batch, 6);
 157
 158     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
 159     OUT_BCS_BATCH(batch, 0);
 160     OUT_BCS_BATCH(batch,
 161                   ((mfc_context->surface_state.height - 1) << 18) |
 162                   ((mfc_context->surface_state.width - 1) << 4));
 163     OUT_BCS_BATCH(batch,
 164                   (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
 165                   (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
 166                   (0 << 22) | /* surface object control state, FIXME??? */
 167                   ((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */
 168                   (0 << 2)  | /* must be 0 for interleave U/V */
 169                   (1 << 1)  | /* must be tiled */
 170                   (I965_TILEWALK_YMAJOR << 0));  /* tile walk, TILEWALK_YMAJOR */
 171     OUT_BCS_BATCH(batch,
 172                   (0 << 16) |                                                           /* must be 0 for interleave U/V */
 173                   (mfc_context->surface_state.h_pitch));                /* y offset for U(cb) */
 174     OUT_BCS_BATCH(batch, 0);
 175     ADVANCE_BCS_BATCH(batch);
 176 }
 177
 178 static void
 179 gen6_mfc_pipe_buf_addr_state(VADriverContextP ctx,
 180                              struct gen6_encoder_context *gen6_encoder_context,
 181                              struct intel_batchbuffer *batch)
 182 {
 183     struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
 184     int i;
 185
 186     if (batch == NULL)
 187         batch = gen6_encoder_context->base.batch;
 188
 189     BEGIN_BCS_BATCH(batch, 24);
 190
 191     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
 192
 193     OUT_BCS_BATCH(batch, 0);                                                                                    /* pre output addr   */
 194
 195     OUT_BCS_RELOC(batch, mfc_context->post_deblocking_output.bo,
 196                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 197                   0);                                                                                   /* post output addr  */
 198
 199     OUT_BCS_RELOC(batch, mfc_context->uncompressed_picture_source.bo,
 200                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 201                   0);                                                                                   /* uncompressed data */
 202
 203     OUT_BCS_BATCH(batch, 0);                                                                                    /* StreamOut data*/
 204     OUT_BCS_RELOC(batch, mfc_context->intra_row_store_scratch_buffer.bo,
 205                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 206                   0);
 207     OUT_BCS_RELOC(batch, mfc_context->deblocking_filter_row_store_scratch_buffer.bo,
 208                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 209                   0);
 210     /* 7..22 Reference pictures*/
 211     for (i = 0; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) {
 212         if ( mfc_context->reference_surfaces[i].bo != NULL) {
 213             OUT_BCS_RELOC(batch, mfc_context->reference_surfaces[i].bo,
 214                           I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 215                           0);
 216         } else {
 217             OUT_BCS_BATCH(batch, 0);
 218         }
 219     }
 220     OUT_BCS_BATCH(batch, 0);                                                                                    /* no block status  */
 221
 222     ADVANCE_BCS_BATCH(batch);
 223 }
 224
 225 static void
 226 gen6_mfc_ind_obj_base_addr_state(VADriverContextP ctx,
 227                                  struct gen6_encoder_context *gen6_encoder_context,
 228                                  struct intel_batchbuffer *batch)
 229 {
 230     struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
 231
 232     if (batch == NULL)
 233         batch = gen6_encoder_context->base.batch;
 234
 235     BEGIN_BCS_BATCH(batch, 11);
 236
 237     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
 238     OUT_BCS_BATCH(batch, 0);
 239     OUT_BCS_BATCH(batch, 0);
 240     /* MFX Indirect MV Object Base Address */
 241     OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 242     OUT_BCS_BATCH(batch, 0);
 243     OUT_BCS_BATCH(batch, 0);
 244     OUT_BCS_BATCH(batch, 0);
 245     OUT_BCS_BATCH(batch, 0);
 246     OUT_BCS_BATCH(batch, 0);
 247     /*MFC Indirect PAK-BSE Object Base Address for Encoder*/
 248     OUT_BCS_BATCH(batch, 0);
 249     OUT_BCS_BATCH(batch, 0);
 250
 251     ADVANCE_BCS_BATCH(batch);
 252 }
 253
 254 static void
 255 gen7_mfc_ind_obj_base_addr_state(VADriverContextP ctx,
 256                                  struct gen6_encoder_context *gen6_encoder_context,
 257                                  struct intel_batchbuffer *batch)
 258 {
 259     struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
 260
 261     if (batch == NULL)
 262         batch = gen6_encoder_context->base.batch;
 263
 264     BEGIN_BCS_BATCH(batch, 11);
 265
 266     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
 267     OUT_BCS_BATCH(batch, 0);
 268     OUT_BCS_BATCH(batch, 0);
 269     /* MFX Indirect MV Object Base Address */
 270     OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 271     OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
 272     OUT_BCS_BATCH(batch, 0);
 273     OUT_BCS_BATCH(batch, 0);
 274     OUT_BCS_BATCH(batch, 0);
 275     OUT_BCS_BATCH(batch, 0);
 276     /*MFC Indirect PAK-BSE Object Base Address for Encoder*/
 277     OUT_BCS_BATCH(batch, 0);
 278     OUT_BCS_BATCH(batch, 0x80000000); /* must set, up to 2G */
 279
 280     ADVANCE_BCS_BATCH(batch);
 281 }
 282
 283 static void
 284 gen6_mfc_bsp_buf_base_addr_state(VADriverContextP ctx,
 285                                  struct gen6_encoder_context *gen6_encoder_context,
 286                                  struct intel_batchbuffer *batch)
 287 {
 288     struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
 289
 290     if (batch == NULL)
 291         batch = gen6_encoder_context->base.batch;
 292
 293     BEGIN_BCS_BATCH(batch, 4);
 294
 295     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
 296     OUT_BCS_RELOC(batch, mfc_context->bsd_mpc_row_store_scratch_buffer.bo,
 297                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 298                   0);
 299     OUT_BCS_BATCH(batch, 0);
 300     OUT_BCS_BATCH(batch, 0);
 301
 302     ADVANCE_BCS_BATCH(batch);
 303 }
 304
 305 static void
 306 gen6_mfc_avc_img_state(VADriverContextP ctx,
 307                        struct gen6_encoder_context *gen6_encoder_context,
 308                        struct intel_batchbuffer *batch)
 309 {
 310     struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
 311     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 312     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 313
 314     if (batch == NULL)
 315         batch = gen6_encoder_context->base.batch;
 316
 317     BEGIN_BCS_BATCH(batch, 13);
 318     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (13 - 2));
 319     OUT_BCS_BATCH(batch,
 320                   ((width_in_mbs * height_in_mbs) & 0xFFFF));
 321     OUT_BCS_BATCH(batch,
 322                   (height_in_mbs << 16) |
 323                   (width_in_mbs << 0));
 324     OUT_BCS_BATCH(batch,
 325                   (0 << 24) |     /*Second Chroma QP Offset*/
 326                   (0 << 16) |     /*Chroma QP Offset*/
 327                   (0 << 14) |   /*Max-bit conformance Intra flag*/
 328                   (0 << 13) |   /*Max Macroblock size conformance Inter flag*/
 329                   (1 << 12) |   /*Should always be written as "1" */
 330                   (0 << 10) |   /*QM Preset FLag */
 331                   (0 << 8)  |   /*Image Structure*/
 332                   (0 << 0) );   /*Current Decoed Image Frame Store ID, reserved in Encode mode*/
 333     OUT_BCS_BATCH(batch,
 334                   (0 << 16) |   /*Mininum Frame size*/
 335                   (0 << 15) |     /*Disable reading of Macroblock Status Buffer*/
 336                   (0 << 14) |   /*Load BitStream Pointer only once, 1 slic 1 frame*/
 337                   (0 << 13) |   /*CABAC 0 word insertion test enable*/
 338                   (1 << 12) |   /*MVUnpackedEnable,compliant to DXVA*/
 339                   (1 << 10) |   /*Chroma Format IDC, 4:2:0*/
 340                   (1 << 7)  |   /*0:CAVLC encoding mode,1:CABAC*/
 341                   (0 << 6)  |   /*Only valid for VLD decoding mode*/
 342                   (0 << 5)  |   /*Constrained Intra Predition Flag, from PPS*/
 343                   (0 << 4)  |   /*Direct 8x8 inference flag*/
 344                   (0 << 3)  |   /*Only 8x8 IDCT Transform Mode Flag*/
 345                   (1 << 2)  |   /*Frame MB only flag*/
 346                   (0 << 1)  |   /*MBAFF mode is in active*/
 347                   (0 << 0) );   /*Field picture flag*/
 348     OUT_BCS_BATCH(batch, 0);            /*Mainly about MB rate control and debug, just ignoring*/
 349     OUT_BCS_BATCH(batch,                        /*Inter and Intra Conformance Max size limit*/
 350                   (0xBB8 << 16) |               /*InterMbMaxSz*/
 351                   (0xEE8) );                    /*IntraMbMaxSz*/
 352     OUT_BCS_BATCH(batch, 0);            /*Reserved*/
 353     OUT_BCS_BATCH(batch, 0);            /*Slice QP Delta for bitrate control*/
 354     OUT_BCS_BATCH(batch, 0);            /*Slice QP Delta for bitrate control*/
 355     OUT_BCS_BATCH(batch, 0x8C000000);
 356     OUT_BCS_BATCH(batch, 0x00010000);
 357     OUT_BCS_BATCH(batch, 0);
 358
 359     ADVANCE_BCS_BATCH(batch);
 360 }
 361
 362 static void
 363 gen7_mfc_avc_img_state(VADriverContextP ctx,
 364                        struct gen6_encoder_context *gen6_encoder_context,
 365                        struct intel_batchbuffer *batch)
 366 {
 367     struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
 368     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 369     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 370
 371     if (batch == NULL)
 372         batch = gen6_encoder_context->base.batch;
 373
 374     BEGIN_BCS_BATCH(batch, 16);
 375     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (16 - 2));
 376     OUT_BCS_BATCH(batch,
 377                   ((width_in_mbs * height_in_mbs) & 0xFFFF));
 378     OUT_BCS_BATCH(batch,
 379                   ((height_in_mbs - 1) << 16) |
 380                   ((width_in_mbs - 1) << 0));
 381     OUT_BCS_BATCH(batch,
 382                   (0 << 24) |   /* Second Chroma QP Offset */
 383                   (0 << 16) |   /* Chroma QP Offset */
 384                   (0 << 14) |   /* Max-bit conformance Intra flag */
 385                   (0 << 13) |   /* Max Macroblock size conformance Inter flag */
 386                   (0 << 12) |   /* FIXME: Weighted_Pred_Flag */
 387                   (0 << 10) |   /* FIXME: Weighted_BiPred_Idc */
 388                   (0 << 8)  |   /* FIXME: Image Structure */
 389                   (0 << 0) );   /* Current Decoed Image Frame Store ID, reserved in Encode mode */
 390     OUT_BCS_BATCH(batch,
 391                   (0 << 16) |   /* Mininum Frame size */
 392                   (0 << 15) |   /* Disable reading of Macroblock Status Buffer */
 393                   (0 << 14) |   /* Load BitStream Pointer only once, 1 slic 1 frame */
 394                   (0 << 13) |   /* CABAC 0 word insertion test enable */
 395                   (1 << 12) |   /* MVUnpackedEnable,compliant to DXVA */
 396                   (1 << 10) |   /* Chroma Format IDC, 4:2:0 */
 397                   (0 << 9)  |   /* FIXME: MbMvFormatFlag */
 398                   (1 << 7)  |   /* 0:CAVLC encoding mode,1:CABAC */
 399                   (0 << 6)  |   /* Only valid for VLD decoding mode */
 400                   (0 << 5)  |   /* Constrained Intra Predition Flag, from PPS */
 401                   (0 << 4)  |   /* Direct 8x8 inference flag */
 402                   (0 << 3)  |   /* Only 8x8 IDCT Transform Mode Flag */
 403                   (1 << 2)  |   /* Frame MB only flag */
 404                   (0 << 1)  |   /* MBAFF mode is in active */
 405                   (0 << 0));    /* Field picture flag */
 406     OUT_BCS_BATCH(batch, 0);    /* Mainly about MB rate control and debug, just ignoring */
 407     OUT_BCS_BATCH(batch,        /* Inter and Intra Conformance Max size limit */
 408                   (0xBB8 << 16) |       /* InterMbMaxSz */
 409                   (0xEE8) );            /* IntraMbMaxSz */
 410     OUT_BCS_BATCH(batch, 0);            /* Reserved */
 411     OUT_BCS_BATCH(batch, 0);            /* Slice QP Delta for bitrate control */
 412     OUT_BCS_BATCH(batch, 0);            /* Slice QP Delta for bitrate control */
 413     OUT_BCS_BATCH(batch, 0x8C000000);
 414     OUT_BCS_BATCH(batch, 0x00010000);
 415     OUT_BCS_BATCH(batch, 0);
 416     OUT_BCS_BATCH(batch, 0);
 417     OUT_BCS_BATCH(batch, 0);
 418     OUT_BCS_BATCH(batch, 0);
 419
 420     ADVANCE_BCS_BATCH(batch);
 421 }
 422
 423 static void gen6_mfc_avc_directmode_state(VADriverContextP ctx,
 424                                           struct gen6_encoder_context *gen6_encoder_context,
 425                                           struct intel_batchbuffer *batch)
 426 {
 427     int i;
 428
 429     if (batch == NULL)
 430         batch = gen6_encoder_context->base.batch;
 431
 432     BEGIN_BCS_BATCH(batch, 69);
 433
 434     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
 435     //TODO: reference DMV
 436     for(i = 0; i < 16; i++){
 437         OUT_BCS_BATCH(batch, 0);
 438         OUT_BCS_BATCH(batch, 0);
 439     }
 440
 441     //TODO: current DMV just for test
 442 #if 0
 443     OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[0].bo,
 444                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 445                   0);
 446 #else
 447     //drm_intel_bo_pin(mfc_context->direct_mv_buffers[0].bo, 0x1000);
 448     //OUT_BCS_BATCH(batch, mfc_context->direct_mv_buffers[0].bo->offset);
 449     OUT_BCS_BATCH(batch, 0);
 450 #endif
 451
 452
 453     OUT_BCS_BATCH(batch, 0);
 454
 455     //TODO: POL list
 456     for(i = 0; i < 34; i++) {
 457         OUT_BCS_BATCH(batch, 0);
 458     }
 459
 460     ADVANCE_BCS_BATCH(batch);
 461 }
 462
 463 static void gen6_mfc_avc_slice_state(VADriverContextP ctx,
 464                                      int intra_slice,
 465                                      struct gen6_encoder_context *gen6_encoder_context,
 466                                      struct intel_batchbuffer *batch)
 467 {
 468     struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
 469
 470     if (batch == NULL)
 471         batch = gen6_encoder_context->base.batch;
 472
 473     BEGIN_BCS_BATCH(batch, 11);;
 474
 475     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) );
 476
 477     if ( intra_slice )
 478         OUT_BCS_BATCH(batch, 2);                        /*Slice Type: I Slice*/
 479     else
 480         OUT_BCS_BATCH(batch, 0);                        /*Slice Type: P Slice*/
 481
 482     if ( intra_slice )
 483         OUT_BCS_BATCH(batch, 0);                        /*no reference frames and pred_weight_table*/
 484     else
 485         OUT_BCS_BATCH(batch, 0x00010000);       /*1 reference frame*/
 486
 487     OUT_BCS_BATCH(batch, (0<<24) |                /*Enable deblocking operation*/
 488                   (26<<16) |                    /*Slice Quantization Parameter*/
 489                   0x0202 );
 490     OUT_BCS_BATCH(batch, 0);                    /*First MB X&Y , the postion of current slice*/
 491     OUT_BCS_BATCH(batch, ( ((mfc_context->surface_state.height+15)/16) << 16) );
 492
 493     OUT_BCS_BATCH(batch,
 494                   (0<<31) |             /*RateControlCounterEnable = disable*/
 495                   (1<<30) |             /*ResetRateControlCounter*/
 496                   (2<<28) |             /*RC Triggle Mode = Loose Rate Control*/
 497                   (1<<19) |             /*IsLastSlice*/
 498                   (0<<18) |             /*BitstreamOutputFlag Compressed BitStream Output Disable Flag 0:enable 1:disable*/
 499                   (0<<17) |             /*HeaderPresentFlag*/
 500                   (1<<16) |             /*SliceData PresentFlag*/
 501                   (0<<15) |             /*TailPresentFlag*/
 502                   (1<<13) |             /*RBSP NAL TYPE*/
 503                   (0<<12) );            /*CabacZeroWordInsertionEnable*/
 504
 505     OUT_BCS_RELOC(batch, mfc_context->mfc_indirect_pak_bse_object.bo,
 506                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 507                   mfc_context->mfc_indirect_pak_bse_object.offset);
 508
 509     OUT_BCS_BATCH(batch, 0);
 510     OUT_BCS_BATCH(batch, 0);
 511     OUT_BCS_BATCH(batch, 0);
 512
 513     ADVANCE_BCS_BATCH(batch);
 514 }
 515 static void gen6_mfc_avc_qm_state(VADriverContextP ctx,
 516                                   struct gen6_encoder_context *gen6_encoder_context,
 517                                   struct intel_batchbuffer *batch)
 518 {
 519     int i;
 520
 521     if (batch == NULL)
 522         batch = gen6_encoder_context->base.batch;
 523
 524     BEGIN_BCS_BATCH(batch, 58);
 525
 526     OUT_BCS_BATCH(batch, MFX_AVC_QM_STATE | 56);
 527     OUT_BCS_BATCH(batch, 0xFF ) ;
 528     for( i = 0; i < 56; i++) {
 529         OUT_BCS_BATCH(batch, 0x10101010);
 530     }
 531
 532     ADVANCE_BCS_BATCH(batch);
 533 }
 534
 535 static void gen6_mfc_avc_fqm_state(VADriverContextP ctx,
 536                                    struct gen6_encoder_context *gen6_encoder_context,
 537                                    struct intel_batchbuffer *batch)
 538 {
 539     int i;
 540
 541     if (batch == NULL)
 542         batch = gen6_encoder_context->base.batch;
 543
 544     BEGIN_BCS_BATCH(batch, 113);
 545     OUT_BCS_BATCH(batch, MFC_AVC_FQM_STATE | (113 - 2));
 546
 547     for(i = 0; i < 112;i++) {
 548         OUT_BCS_BATCH(batch, 0x10001000);
 549     }
 550
 551     ADVANCE_BCS_BATCH(batch);
 552 }
 553
 554 static void
 555 gen7_mfc_qm_state(VADriverContextP ctx,
 556                   int qm_type,
 557                   unsigned int *qm,
 558                   int qm_length,
 559                   struct gen6_encoder_context *gen6_encoder_context,
 560                   struct intel_batchbuffer *batch)
 561 {
 562     unsigned int qm_buffer[16];
 563
 564     if (batch == NULL)
 565         batch = gen6_encoder_context->base.batch;
 566
 567     assert(qm_length <= 16);
 568     assert(sizeof(*qm) == 4);
 569     memcpy(qm_buffer, qm, qm_length * 4);
 570
 571     BEGIN_BCS_BATCH(batch, 18);
 572     OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2));
 573     OUT_BCS_BATCH(batch, qm_type << 0);
 574     intel_batchbuffer_data(batch, qm_buffer, 16 * 4);
 575     ADVANCE_BCS_BATCH(batch);
 576 }
 577
 578 static void gen7_mfc_avc_qm_state(VADriverContextP ctx,
 579                                   struct gen6_encoder_context *gen6_encoder_context,
 580                                   struct intel_batchbuffer *batch)
 581 {
 582     unsigned int qm[16] = {
 583         0x10101010, 0x10101010, 0x10101010, 0x10101010,
 584         0x10101010, 0x10101010, 0x10101010, 0x10101010,
 585         0x10101010, 0x10101010, 0x10101010, 0x10101010,
 586         0x10101010, 0x10101010, 0x10101010, 0x10101010
 587     };
 588
 589     gen7_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 12, gen6_encoder_context, batch);
 590     gen7_mfc_qm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 12, gen6_encoder_context, batch);
 591     gen7_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 16, gen6_encoder_context, batch);
 592     gen7_mfc_qm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 16, gen6_encoder_context, batch);
 593 }
 594
 595 static void
 596 gen7_mfc_fqm_state(VADriverContextP ctx,
 597                    int fqm_type,
 598                    unsigned int *fqm,
 599                    int fqm_length,
 600                    struct gen6_encoder_context *gen6_encoder_context,
 601                    struct intel_batchbuffer *batch)
 602 {
 603     unsigned int fqm_buffer[32];
 604
 605     if (batch == NULL)
 606         batch = gen6_encoder_context->base.batch;
 607
 608     assert(fqm_length <= 32);
 609     assert(sizeof(*fqm) == 4);
 610     memcpy(fqm_buffer, fqm, fqm_length * 4);
 611
 612     BEGIN_BCS_BATCH(batch, 34);
 613     OUT_BCS_BATCH(batch, MFX_FQM_STATE | (34 - 2));
 614     OUT_BCS_BATCH(batch, fqm_type << 0);
 615     intel_batchbuffer_data(batch, fqm_buffer, 32 * 4);
 616     ADVANCE_BCS_BATCH(batch);
 617 }
 618
 619 static void gen7_mfc_avc_fqm_state(VADriverContextP ctx,
 620                                    struct gen6_encoder_context *gen6_encoder_context,
 621                                    struct intel_batchbuffer *batch)
 622 {
 623     unsigned int qm[32] = {
 624         0x10001000, 0x10001000, 0x10001000, 0x10001000,
 625         0x10001000, 0x10001000, 0x10001000, 0x10001000,
 626         0x10001000, 0x10001000, 0x10001000, 0x10001000,
 627         0x10001000, 0x10001000, 0x10001000, 0x10001000,
 628         0x10001000, 0x10001000, 0x10001000, 0x10001000,
 629         0x10001000, 0x10001000, 0x10001000, 0x10001000,
 630         0x10001000, 0x10001000, 0x10001000, 0x10001000,
 631         0x10001000, 0x10001000, 0x10001000, 0x10001000
 632     };
 633
 634     gen7_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTRA_MATRIX, qm, 24, gen6_encoder_context, batch);
 635     gen7_mfc_fqm_state(ctx, MFX_QM_AVC_4X4_INTER_MATRIX, qm, 24, gen6_encoder_context, batch);
 636     gen7_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTRA_MATRIX, qm, 32, gen6_encoder_context, batch);
 637     gen7_mfc_fqm_state(ctx, MFX_QM_AVC_8x8_INTER_MATRIX, qm, 32, gen6_encoder_context, batch);
 638 }
 639
 640 static void gen6_mfc_avc_ref_idx_state(VADriverContextP ctx,
 641                                        struct gen6_encoder_context *gen6_encoder_context,
 642                                        struct intel_batchbuffer *batch)
 643 {
 644     int i;
 645
 646     if (batch == NULL)
 647         batch = gen6_encoder_context->base.batch;
 648
 649     BEGIN_BCS_BATCH(batch, 10);
 650
 651     OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
 652     OUT_BCS_BATCH(batch, 0);                  //Select L0
 653
 654     OUT_BCS_BATCH(batch, 0x80808000);         //Only 1 reference
 655     for(i = 0; i < 7; i++) {
 656         OUT_BCS_BATCH(batch, 0x80808080);
 657     }
 658
 659     ADVANCE_BCS_BATCH(batch);
 660 }
 661
 662 static void
 663 gen6_mfc_avc_insert_object(VADriverContextP ctx, int flush_data,
 664                            struct gen6_encoder_context *gen6_encoder_context,
 665                            struct intel_batchbuffer *batch)
 666 {
 667     if (batch == NULL)
 668         batch = gen6_encoder_context->base.batch;
 669
 670     BEGIN_BCS_BATCH(batch, 4);
 671
 672     OUT_BCS_BATCH(batch, MFC_AVC_INSERT_OBJECT | (4 -2 ) );
 673     OUT_BCS_BATCH(batch, (32<<8) |
 674                   (1 << 3) |
 675                   (1 << 2) |
 676                   (flush_data << 1) |
 677                   (1<<0) );
 678     OUT_BCS_BATCH(batch, 0x00000003);
 679     OUT_BCS_BATCH(batch, 0xABCD1234);
 680
 681     ADVANCE_BCS_BATCH(batch);
 682 }
 683
 684 static int
 685 gen6_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb, int qp,unsigned int *msg,
 686                               struct gen6_encoder_context *gen6_encoder_context,
 687                               struct intel_batchbuffer *batch)
 688 {
 689     int len_in_dwords = 11;
 690
 691     if (batch == NULL)
 692         batch = gen6_encoder_context->base.batch;
 693
 694     BEGIN_BCS_BATCH(batch, len_in_dwords);
 695
 696     OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
 697     OUT_BCS_BATCH(batch, 0);
 698     OUT_BCS_BATCH(batch, 0);
 699     OUT_BCS_BATCH(batch,
 700                   (0 << 24) |           /* PackedMvNum, Debug*/
 701                   (0 << 20) |           /* No motion vector */
 702                   (1 << 19) |           /* CbpDcY */
 703                   (1 << 18) |           /* CbpDcU */
 704                   (1 << 17) |           /* CbpDcV */
 705                   (msg[0] & 0xFFFF) );
 706
 707     OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x);          /* Code Block Pattern for Y*/
 708     OUT_BCS_BATCH(batch, 0x000F000F);                                                   /* Code Block Pattern */
 709     OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp);      /* Last MB */
 710
 711     /*Stuff for Intra MB*/
 712     OUT_BCS_BATCH(batch, msg[1]);                       /* We using Intra16x16 no 4x4 predmode*/
 713     OUT_BCS_BATCH(batch, msg[2]);
 714     OUT_BCS_BATCH(batch, msg[3]&0xFC);
 715
 716     OUT_BCS_BATCH(batch, 0x8040000);    /*MaxSizeInWord and TargetSzieInWord*/
 717
 718     ADVANCE_BCS_BATCH(batch);
 719
 720     return len_in_dwords;
 721 }
 722
 723 static int gen6_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, int qp, unsigned int offset,
 724                                          struct gen6_encoder_context *gen6_encoder_context, struct intel_batchbuffer *batch)
 725 {
 726     int len_in_dwords = 11;
 727
 728     if (batch == NULL)
 729         batch = gen6_encoder_context->base.batch;
 730
 731     BEGIN_BCS_BATCH(batch, len_in_dwords);
 732
 733     OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
 734
 735     OUT_BCS_BATCH(batch, 32);         /* 32 MV*/
 736     OUT_BCS_BATCH(batch, offset);
 737
 738     OUT_BCS_BATCH(batch,
 739                   (1 << 24) |     /* PackedMvNum, Debug*/
 740                   (4 << 20) |     /* 8 MV, SNB don't use it*/
 741                   (1 << 19) |     /* CbpDcY */
 742                   (1 << 18) |     /* CbpDcU */
 743                   (1 << 17) |     /* CbpDcV */
 744                   (0 << 15) |     /* Transform8x8Flag = 0*/
 745                   (0 << 14) |     /* Frame based*/
 746                   (0 << 13) |     /* Inter MB */
 747                   (1 << 8)  |     /* MbType = P_L0_16x16 */
 748                   (0 << 7)  |     /* MBZ for frame */
 749                   (0 << 6)  |     /* MBZ */
 750                   (2 << 4)  |     /* MBZ for inter*/
 751                   (0 << 3)  |     /* MBZ */
 752                   (0 << 2)  |     /* SkipMbFlag */
 753                   (0 << 0));      /* InterMbMode */
 754
 755     OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x);        /* Code Block Pattern for Y*/
 756     OUT_BCS_BATCH(batch, 0x000F000F);                         /* Code Block Pattern */
 757     OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp);    /* Last MB */
 758
 759     /*Stuff for Inter MB*/
 760     OUT_BCS_BATCH(batch, 0x0);
 761     OUT_BCS_BATCH(batch, 0x0);
 762     OUT_BCS_BATCH(batch, 0x0);
 763
 764     OUT_BCS_BATCH(batch, 0xF0020000); /*MaxSizeInWord and TargetSzieInWord*/
 765
 766     ADVANCE_BCS_BATCH(batch);
 767
 768     return len_in_dwords;
 769 }
 770
 771 static void gen6_mfc_init(VADriverContextP ctx,
 772                           struct encode_state *encode_state,
 773                           struct gen6_encoder_context *gen6_encoder_context)
 774 {
 775     struct i965_driver_data *i965 = i965_driver_data(ctx);
 776     struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
 777     dri_bo *bo;
 778     int i;
 779     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param->buffer;
 780     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 781     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 782
 783     /*Encode common setup for MFC*/
 784     dri_bo_unreference(mfc_context->post_deblocking_output.bo);
 785     mfc_context->post_deblocking_output.bo = NULL;
 786
 787     dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
 788     mfc_context->pre_deblocking_output.bo = NULL;
 789
 790     dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
 791     mfc_context->uncompressed_picture_source.bo = NULL;
 792
 793     dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
 794     mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
 795
 796     for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
 797         dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
 798         mfc_context->direct_mv_buffers[i].bo = NULL;
 799     }
 800
 801     for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
 802         if (mfc_context->reference_surfaces[i].bo != NULL)
 803             dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
 804         mfc_context->reference_surfaces[i].bo = NULL;
 805     }
 806
 807     dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
 808     bo = dri_bo_alloc(i965->intel.bufmgr,
 809                       "Buffer",
 810                       width_in_mbs * 64,
 811                       64);
 812     assert(bo);
 813     mfc_context->intra_row_store_scratch_buffer.bo = bo;
 814
 815     dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
 816     bo = dri_bo_alloc(i965->intel.bufmgr,
 817                       "Buffer",
 818                       4 * width_in_mbs * 64,  /* 4 * width_in_mbs * 64 */
 819                       64);
 820     assert(bo);
 821     mfc_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
 822
 823     dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
 824     bo = dri_bo_alloc(i965->intel.bufmgr,
 825                       "Buffer",
 826                       128 * width_in_mbs, /* 2 * widht_in_mbs * 64 */
 827                       0x1000);
 828     assert(bo);
 829     mfc_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
 830 }
 831
 832 void gen6_mfc_avc_pipeline_programing(VADriverContextP ctx,
 833                                       struct encode_state *encode_state,
 834                                       struct gen6_encoder_context *gen6_encoder_context)
 835 {
 836     struct i965_driver_data *i965 = i965_driver_data(ctx);
 837     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 838     struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
 839     struct gen6_vme_context *vme_context = &gen6_encoder_context->vme_context;
 840     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param->buffer;
 841     VAEncSliceParameterBuffer *pSliceParameter = (VAEncSliceParameterBuffer *)encode_state->slice_params[0]->buffer; /* FIXME: multi slices */
 842     unsigned int *msg = NULL, offset = 0;
 843     int emit_new_state = 1, object_len_in_bytes;
 844     int is_intra = pSliceParameter->slice_flags.bits.is_intra;
 845     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 846     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 847     int x,y;
 848
 849     intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
 850
 851     if (is_intra) {
 852         dri_bo_map(vme_context->vme_output.bo , 1);
 853         msg = (unsigned int *)vme_context->vme_output.bo->virtual;
 854     }
 855
 856     for (y = 0; y < height_in_mbs; y++) {
 857         for (x = 0; x < width_in_mbs; x++) {
 858             int last_mb = (y == (height_in_mbs-1)) && ( x == (width_in_mbs-1) );
 859             int qp = pSequenceParameter->initial_qp;
 860
 861             if (emit_new_state) {
 862                 intel_batchbuffer_emit_mi_flush(batch);
 863
 864                 if (IS_GEN7(i965->intel.device_id)) {
 865                     gen7_mfc_pipe_mode_select(ctx, MFX_FORMAT_AVC, gen6_encoder_context, batch);
 866                     gen7_mfc_surface_state(ctx, gen6_encoder_context, batch);
 867                     gen7_mfc_ind_obj_base_addr_state(ctx, gen6_encoder_context, batch);
 868                 } else {
 869                     gen6_mfc_pipe_mode_select(ctx, gen6_encoder_context, batch);
 870                     gen6_mfc_surface_state(ctx, gen6_encoder_context, batch);
 871                     gen6_mfc_ind_obj_base_addr_state(ctx, gen6_encoder_context, batch);
 872                 }
 873
 874                 gen6_mfc_pipe_buf_addr_state(ctx, gen6_encoder_context, batch);
 875                 gen6_mfc_bsp_buf_base_addr_state(ctx, gen6_encoder_context, batch);
 876
 877                 if (IS_GEN7(i965->intel.device_id)) {
 878                     gen7_mfc_avc_img_state(ctx, gen6_encoder_context, batch);
 879                     gen7_mfc_avc_qm_state(ctx, gen6_encoder_context, batch);
 880                     gen7_mfc_avc_fqm_state(ctx, gen6_encoder_context, batch);
 881                 } else {
 882                     gen6_mfc_avc_img_state(ctx, gen6_encoder_context, batch);
 883                     gen6_mfc_avc_qm_state(ctx, gen6_encoder_context, batch);
 884                     gen6_mfc_avc_fqm_state(ctx, gen6_encoder_context, batch);
 885                 }
 886
 887                 gen6_mfc_avc_ref_idx_state(ctx, gen6_encoder_context, batch);
 888                 gen6_mfc_avc_slice_state(ctx, is_intra, gen6_encoder_context, batch);
 889                 emit_new_state = 0;
 890             }
 891
 892             if (is_intra) {
 893                 assert(msg);
 894                 object_len_in_bytes = gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, gen6_encoder_context, batch);
 895                 msg += 4;
 896             } else {
 897                 object_len_in_bytes = gen6_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, offset, gen6_encoder_context, batch);
 898                 offset += 64;
 899             }
 900
 901             if (intel_batchbuffer_check_free_space(batch, object_len_in_bytes) == 0) {
 902                 intel_batchbuffer_end_atomic(batch);
 903                 intel_batchbuffer_flush(batch);
 904                 emit_new_state = 1;
 905                 intel_batchbuffer_start_atomic_bcs(batch, 0x1000);
 906             }
 907         }
 908     }
 909
 910     if (is_intra)
 911         dri_bo_unmap(vme_context->vme_output.bo);
 912
 913     intel_batchbuffer_end_atomic(batch);
 914 }
 915
 916 static VAStatus gen6_mfc_avc_prepare(VADriverContextP ctx,
 917                                      struct encode_state *encode_state,
 918                                      struct gen6_encoder_context *gen6_encoder_context)
 919 {
 920     struct i965_driver_data *i965 = i965_driver_data(ctx);
 921     struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
 922     struct object_surface *obj_surface;
 923     struct object_buffer *obj_buffer;
 924     dri_bo *bo;
 925     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param->buffer;
 926     VAStatus vaStatus = VA_STATUS_SUCCESS;
 927
 928     /*Setup all the input&output object*/
 929     obj_surface = SURFACE(pPicParameter->reconstructed_picture);
 930     assert(obj_surface);
 931     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
 932     mfc_context->post_deblocking_output.bo = obj_surface->bo;
 933     dri_bo_reference(mfc_context->post_deblocking_output.bo);
 934
 935     mfc_context->surface_state.width = obj_surface->orig_width;
 936     mfc_context->surface_state.height = obj_surface->orig_height;
 937     mfc_context->surface_state.w_pitch = obj_surface->width;
 938     mfc_context->surface_state.h_pitch = obj_surface->height;
 939
 940     obj_surface = SURFACE(pPicParameter->reference_picture);
 941     assert(obj_surface);
 942     if (obj_surface->bo != NULL) {
 943         mfc_context->reference_surfaces[0].bo = obj_surface->bo;
 944         dri_bo_reference(obj_surface->bo);
 945     }
 946
 947     obj_surface = SURFACE(encode_state->current_render_target);
 948     assert(obj_surface && obj_surface->bo);
 949     mfc_context->uncompressed_picture_source.bo = obj_surface->bo;
 950     dri_bo_reference(mfc_context->uncompressed_picture_source.bo);
 951
 952     obj_buffer = BUFFER (pPicParameter->coded_buf); /* FIXME: fix this later */
 953     bo = obj_buffer->buffer_store->bo;
 954     assert(bo);
 955     mfc_context->mfc_indirect_pak_bse_object.bo = bo;
 956     mfc_context->mfc_indirect_pak_bse_object.offset = ALIGN(sizeof(VACodedBufferSegment), 64);
 957     dri_bo_reference(mfc_context->mfc_indirect_pak_bse_object.bo);
 958
 959     /*Programing bcs pipeline*/
 960     gen6_mfc_avc_pipeline_programing(ctx, encode_state, gen6_encoder_context);  //filling the pipeline
 961
 962     return vaStatus;
 963 }
 964
 965 static VAStatus gen6_mfc_run(VADriverContextP ctx,
 966                              struct encode_state *encode_state,
 967                              struct gen6_encoder_context *gen6_encoder_context)
 968 {
 969     struct intel_batchbuffer *batch = gen6_encoder_context->base.batch;
 970
 971     intel_batchbuffer_flush(batch);             //run the pipeline
 972
 973     return VA_STATUS_SUCCESS;
 974 }
 975
 976 static VAStatus gen6_mfc_stop(VADriverContextP ctx,
 977                               struct encode_state *encode_state,
 978                               struct gen6_encoder_context *gen6_encoder_context)
 979 {
 980 #if 0
 981     struct i965_driver_data *i965 = i965_driver_data(ctx);
 982     struct gen6_mfc_context *mfc_context = &gen6_encoder_context->mfc_context;
 983
 984     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param->buffer;
 985
 986     struct object_surface *obj_surface = SURFACE(pPicParameter->reconstructed_picture);
 987     //struct object_surface *obj_surface = SURFACE(pPicParameter->reference_picture[0]);
 988     //struct object_surface *obj_surface = SURFACE(encode_state->current_render_target);
 989     my_debug(obj_surface);
 990
 991 #endif
 992
 993     return VA_STATUS_SUCCESS;
 994 }
 995
 996 static VAStatus
 997 gen6_mfc_avc_encode_picture(VADriverContextP ctx,
 998                             struct encode_state *encode_state,
 999                             struct gen6_encoder_context *gen6_encoder_context)
1000 {
1001     gen6_mfc_init(ctx, encode_state, gen6_encoder_context);
1002     gen6_mfc_avc_prepare(ctx, encode_state, gen6_encoder_context);
1003     gen6_mfc_run(ctx, encode_state, gen6_encoder_context);
1004     gen6_mfc_stop(ctx, encode_state, gen6_encoder_context);
1005
1006     return VA_STATUS_SUCCESS;
1007 }
1008
1009 VAStatus
1010 gen6_mfc_pipeline(VADriverContextP ctx,
1011                   VAProfile profile,
1012                   struct encode_state *encode_state,
1013                   struct gen6_encoder_context *gen6_encoder_context)
1014 {
1015     VAStatus vaStatus;
1016
1017     switch (profile) {
1018     case VAProfileH264Baseline:
1019         vaStatus = gen6_mfc_avc_encode_picture(ctx, encode_state, gen6_encoder_context);
1020         break;
1021
1022         /* FIXME: add for other profile */
1023     default:
1024         vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
1025         break;
1026     }
1027
1028     return vaStatus;
1029 }
1030
1031 Bool gen6_mfc_context_init(VADriverContextP ctx, struct gen6_mfc_context *mfc_context)
1032 {
1033     return True;
1034 }
1035
1036 Bool gen6_mfc_context_destroy(struct gen6_mfc_context *mfc_context)
1037 {
1038     int i;
1039
1040     dri_bo_unreference(mfc_context->post_deblocking_output.bo);
1041     mfc_context->post_deblocking_output.bo = NULL;
1042
1043     dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
1044     mfc_context->pre_deblocking_output.bo = NULL;
1045
1046     dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
1047     mfc_context->uncompressed_picture_source.bo = NULL;
1048
1049     dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
1050     mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
1051
1052     for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
1053         dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
1054         mfc_context->direct_mv_buffers[i].bo = NULL;
1055     }
1056
1057     dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
1058     mfc_context->intra_row_store_scratch_buffer.bo = NULL;
1059
1060     dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
1061     mfc_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
1062
1063     dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
1064     mfc_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
1065
1066     return True;
1067 }