src/gen6_mfc.c

   1 /*
   2  * Copyright © 2010-2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Zhou Chang <chang.zhou@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <assert.h>
  33 #include <math.h>
  34
  35 #include "intel_batchbuffer.h"
  36 #include "i965_defines.h"
  37 #include "i965_structs.h"
  38 #include "i965_drv_video.h"
  39 #include "i965_encoder.h"
  40 #include "i965_encoder_utils.h"
  41 #include "gen6_mfc.h"
  42 #include "gen6_vme.h"
  43
  44
  45 static const uint32_t gen6_mfc_batchbuffer_avc_intra[][4] = {
  46 #include "shaders/utils/mfc_batchbuffer_avc_intra.g6b"
  47 };
  48
  49 static const uint32_t gen6_mfc_batchbuffer_avc_inter[][4] = {
  50 #include "shaders/utils/mfc_batchbuffer_avc_inter.g6b"
  51 };
  52
  53 static struct i965_kernel gen6_mfc_kernels[] = {
  54     {
  55         "MFC AVC INTRA BATCHBUFFER ",
  56         MFC_BATCHBUFFER_AVC_INTRA,
  57         gen6_mfc_batchbuffer_avc_intra,
  58         sizeof(gen6_mfc_batchbuffer_avc_intra),
  59         NULL
  60     },
  61
  62     {
  63         "MFC AVC INTER BATCHBUFFER ",
  64         MFC_BATCHBUFFER_AVC_INTER,
  65         gen6_mfc_batchbuffer_avc_inter,
  66         sizeof(gen6_mfc_batchbuffer_avc_inter),
  67         NULL
  68     },
  69 };
  70
  71 static void
  72 gen6_mfc_pipe_mode_select(VADriverContextP ctx,
  73                           int standard_select,
  74                           struct intel_encoder_context *encoder_context)
  75 {
  76     struct intel_batchbuffer *batch = encoder_context->base.batch;
  77     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
  78
  79     assert(standard_select == MFX_FORMAT_AVC);
  80
  81     BEGIN_BCS_BATCH(batch, 4);
  82
  83     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (4 - 2));
  84     OUT_BCS_BATCH(batch,
  85                   (1 << 10) | /* disable Stream-Out , advanced QP/bitrate control need enable it*/
  86                   ((!!mfc_context->post_deblocking_output.bo) << 9)  | /* Post Deblocking Output */
  87                   ((!!mfc_context->pre_deblocking_output.bo) << 8)  | /* Pre Deblocking Output */
  88                   (0 << 7)  | /* disable TLB prefectch */
  89                   (0 << 5)  | /* not in stitch mode */
  90                   (1 << 4)  | /* encoding mode */
  91                   (2 << 0));  /* Standard Select: AVC */
  92     OUT_BCS_BATCH(batch,
  93                   (0 << 20) | /* round flag in PB slice */
  94                   (0 << 19) | /* round flag in Intra8x8 */
  95                   (0 << 7)  | /* expand NOA bus flag */
  96                   (1 << 6)  | /* must be 1 */
  97                   (0 << 5)  | /* disable clock gating for NOA */
  98                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
  99                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
 100                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
 101                   (0 << 1)  | /* AVC long field motion vector */
 102                   (0 << 0));  /* always calculate AVC ILDB boundary strength */
 103     OUT_BCS_BATCH(batch, 0);
 104
 105     ADVANCE_BCS_BATCH(batch);
 106 }
 107
 108 static void
 109 gen6_mfc_surface_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 110 {
 111     struct intel_batchbuffer *batch = encoder_context->base.batch;
 112     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 113
 114     BEGIN_BCS_BATCH(batch, 6);
 115
 116     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
 117     OUT_BCS_BATCH(batch, 0);
 118     OUT_BCS_BATCH(batch,
 119                   ((mfc_context->surface_state.height - 1) << 19) |
 120                   ((mfc_context->surface_state.width - 1) << 6));
 121     OUT_BCS_BATCH(batch,
 122                   (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
 123                   (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
 124                   (0 << 22) | /* surface object control state, FIXME??? */
 125                   ((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */
 126                   (0 << 2)  | /* must be 0 for interleave U/V */
 127                   (1 << 1)  | /* must be y-tiled */
 128                   (I965_TILEWALK_YMAJOR << 0));                         /* tile walk, TILEWALK_YMAJOR */
 129     OUT_BCS_BATCH(batch,
 130                   (0 << 16) |                                                           /* must be 0 for interleave U/V */
 131                   (mfc_context->surface_state.h_pitch));                /* y offset for U(cb) */
 132     OUT_BCS_BATCH(batch, 0);
 133     ADVANCE_BCS_BATCH(batch);
 134 }
 135
 136 static void
 137 gen6_mfc_pipe_buf_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 138 {
 139     struct intel_batchbuffer *batch = encoder_context->base.batch;
 140     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 141     int i;
 142
 143     BEGIN_BCS_BATCH(batch, 24);
 144
 145     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
 146
 147     if (mfc_context->pre_deblocking_output.bo)
 148         OUT_BCS_RELOC(batch, mfc_context->pre_deblocking_output.bo,
 149                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 150                       0);
 151     else
 152         OUT_BCS_BATCH(batch, 0);                                                                                        /* pre output addr   */
 153
 154     if (mfc_context->post_deblocking_output.bo)
 155         OUT_BCS_RELOC(batch, mfc_context->post_deblocking_output.bo,
 156                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 157                       0);                                                                                       /* post output addr  */
 158     else
 159         OUT_BCS_BATCH(batch, 0);
 160
 161     OUT_BCS_RELOC(batch, mfc_context->uncompressed_picture_source.bo,
 162                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 163                   0);                                                                                   /* uncompressed data */
 164     OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
 165                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 166                   0);                                                                                   /* StreamOut data*/
 167     OUT_BCS_RELOC(batch, mfc_context->intra_row_store_scratch_buffer.bo,
 168                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 169                   0);
 170     OUT_BCS_RELOC(batch, mfc_context->deblocking_filter_row_store_scratch_buffer.bo,
 171                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 172                   0);
 173     /* 7..22 Reference pictures*/
 174     for (i = 0; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) {
 175         if ( mfc_context->reference_surfaces[i].bo != NULL) {
 176             OUT_BCS_RELOC(batch, mfc_context->reference_surfaces[i].bo,
 177                           I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 178                           0);
 179         } else {
 180             OUT_BCS_BATCH(batch, 0);
 181         }
 182     }
 183     OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
 184                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 185                   0);                                                                                   /* Macroblock status buffer*/
 186
 187     ADVANCE_BCS_BATCH(batch);
 188 }
 189
 190 static void
 191 gen6_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 192 {
 193     struct intel_batchbuffer *batch = encoder_context->base.batch;
 194     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 195     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 196
 197     BEGIN_BCS_BATCH(batch, 11);
 198
 199     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
 200     OUT_BCS_BATCH(batch, 0);
 201     OUT_BCS_BATCH(batch, 0);
 202     /* MFX Indirect MV Object Base Address */
 203     OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 204     OUT_BCS_BATCH(batch, 0);
 205     OUT_BCS_BATCH(batch, 0);
 206     OUT_BCS_BATCH(batch, 0);
 207     OUT_BCS_BATCH(batch, 0);
 208     OUT_BCS_BATCH(batch, 0);
 209     /*MFC Indirect PAK-BSE Object Base Address for Encoder*/
 210     OUT_BCS_RELOC(batch,
 211                   mfc_context->mfc_indirect_pak_bse_object.bo,
 212                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 213                   0);
 214     OUT_BCS_RELOC(batch,
 215                   mfc_context->mfc_indirect_pak_bse_object.bo,
 216                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 217                   mfc_context->mfc_indirect_pak_bse_object.end_offset);
 218
 219     ADVANCE_BCS_BATCH(batch);
 220 }
 221
 222 static void
 223 gen6_mfc_bsp_buf_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 224 {
 225     struct intel_batchbuffer *batch = encoder_context->base.batch;
 226     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 227
 228     BEGIN_BCS_BATCH(batch, 4);
 229
 230     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
 231     OUT_BCS_RELOC(batch, mfc_context->bsd_mpc_row_store_scratch_buffer.bo,
 232                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 233                   0);
 234     OUT_BCS_BATCH(batch, 0);
 235     OUT_BCS_BATCH(batch, 0);
 236
 237     ADVANCE_BCS_BATCH(batch);
 238 }
 239
 240 static void
 241 gen6_mfc_avc_img_state(VADriverContextP ctx,struct encode_state *encode_state,
 242                        struct intel_encoder_context *encoder_context)
 243 {
 244     struct intel_batchbuffer *batch = encoder_context->base.batch;
 245     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 246     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 247     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 248     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 249     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 250
 251     BEGIN_BCS_BATCH(batch, 13);
 252     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (13 - 2));
 253     OUT_BCS_BATCH(batch,
 254                   ((width_in_mbs * height_in_mbs) & 0xFFFF));
 255     OUT_BCS_BATCH(batch,
 256                   (height_in_mbs << 16) |
 257                   (width_in_mbs << 0));
 258     OUT_BCS_BATCH(batch,
 259                   (0 << 24) |     /*Second Chroma QP Offset*/
 260                   (0 << 16) |     /*Chroma QP Offset*/
 261                   (0 << 14) |   /*Max-bit conformance Intra flag*/
 262                   (0 << 13) |   /*Max Macroblock size conformance Inter flag*/
 263                   (1 << 12) |   /*Should always be written as "1" */
 264                   (0 << 10) |   /*QM Preset FLag */
 265                   (0 << 8)  |   /*Image Structure*/
 266                   (0 << 0) );   /*Current Decoed Image Frame Store ID, reserved in Encode mode*/
 267     OUT_BCS_BATCH(batch,
 268                   (400 << 16) |   /*Mininum Frame size*/
 269                   (0 << 15) |   /*Disable reading of Macroblock Status Buffer*/
 270                   (0 << 14) |   /*Load BitStream Pointer only once, 1 slic 1 frame*/
 271                   (0 << 13) |   /*CABAC 0 word insertion test enable*/
 272                   (1 << 12) |   /*MVUnpackedEnable,compliant to DXVA*/
 273                   (1 << 10) |   /*Chroma Format IDC, 4:2:0*/
 274                   (pPicParameter->pic_fields.bits.entropy_coding_mode_flag << 7)  |   /*0:CAVLC encoding mode,1:CABAC*/
 275                   (0 << 6)  |   /*Only valid for VLD decoding mode*/
 276                   (0 << 5)  |   /*Constrained Intra Predition Flag, from PPS*/
 277                   (pSequenceParameter->seq_fields.bits.direct_8x8_inference_flag << 4)  |   /*Direct 8x8 inference flag*/
 278                   (pPicParameter->pic_fields.bits.transform_8x8_mode_flag << 3)  |   /*8x8 or 4x4 IDCT Transform Mode Flag*/
 279                   (1 << 2)  |   /*Frame MB only flag*/
 280                   (0 << 1)  |   /*MBAFF mode is in active*/
 281                   (0 << 0) );   /*Field picture flag*/
 282     OUT_BCS_BATCH(batch,
 283                   (1<<16)   |   /*Frame Size Rate Control Flag*/
 284                   (1<<12)   |
 285                   (1<<9)    |   /*MB level Rate Control Enabling Flag*/
 286                   (1 << 3)  |   /*FrameBitRateMinReportMask*/
 287                   (1 << 2)  |   /*FrameBitRateMaxReportMask*/
 288                   (1 << 1)  |   /*InterMBMaxSizeReportMask*/
 289                   (1 << 0) );   /*IntraMBMaxSizeReportMask*/
 290     OUT_BCS_BATCH(batch,                        /*Inter and Intra Conformance Max size limit*/
 291                   (0x0600 << 16) |              /*InterMbMaxSz 192 Byte*/
 292                   (0x0800) );                   /*IntraMbMaxSz 256 Byte*/
 293     OUT_BCS_BATCH(batch, 0x00000000);   /*Reserved : MBZReserved*/
 294     OUT_BCS_BATCH(batch, 0x01020304);   /*Slice QP Delta for bitrate control*/
 295     OUT_BCS_BATCH(batch, 0xFEFDFCFB);
 296     OUT_BCS_BATCH(batch, 0x80601004);   /*MAX = 128KB, MIN = 64KB*/
 297     OUT_BCS_BATCH(batch, 0x00800001);
 298     OUT_BCS_BATCH(batch, 0);
 299
 300     ADVANCE_BCS_BATCH(batch);
 301 }
 302
 303 static void
 304 gen6_mfc_avc_directmode_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 305 {
 306     struct intel_batchbuffer *batch = encoder_context->base.batch;
 307     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 308
 309     int i;
 310
 311     BEGIN_BCS_BATCH(batch, 69);
 312
 313     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
 314
 315     /* Reference frames and Current frames */
 316     for(i = 0; i < NUM_MFC_DMV_BUFFERS; i++) {
 317         if ( mfc_context->direct_mv_buffers[i].bo != NULL) {
 318             OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[i].bo,
 319                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 320                           0);
 321         } else {
 322             OUT_BCS_BATCH(batch, 0);
 323         }
 324     }
 325
 326     /* POL list */
 327     for(i = 0; i < 32; i++) {
 328         OUT_BCS_BATCH(batch, i/2);
 329     }
 330     OUT_BCS_BATCH(batch, 0);
 331     OUT_BCS_BATCH(batch, 0);
 332
 333     ADVANCE_BCS_BATCH(batch);
 334 }
 335
 336 static void
 337 gen6_mfc_avc_slice_state(VADriverContextP ctx,
 338                          VAEncPictureParameterBufferH264 *pic_param,
 339                          VAEncSliceParameterBufferH264 *slice_param,
 340                          struct encode_state *encode_state,
 341                          struct intel_encoder_context *encoder_context,
 342                          int rate_control_enable,
 343                          int qp,
 344                          struct intel_batchbuffer *batch)
 345 {
 346     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 347     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 348     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 349     int beginmb = slice_param->macroblock_address;
 350     int endmb = beginmb + slice_param->num_macroblocks;
 351     int beginx = beginmb % width_in_mbs;
 352     int beginy = beginmb / width_in_mbs;
 353     int nextx =  endmb % width_in_mbs;
 354     int nexty = endmb / width_in_mbs;
 355     int slice_type = slice_param->slice_type;
 356     int last_slice = (endmb == (width_in_mbs * height_in_mbs));
 357     int bit_rate_control_target, maxQpN, maxQpP;
 358     unsigned char correct[6], grow, shrink;
 359     int i;
 360     int weighted_pred_idc = 0;
 361     unsigned int luma_log2_weight_denom = slice_param->luma_log2_weight_denom;
 362     unsigned int chroma_log2_weight_denom = slice_param->chroma_log2_weight_denom;
 363
 364     if (batch == NULL)
 365         batch = encoder_context->base.batch;
 366
 367     bit_rate_control_target = slice_type;
 368     if (slice_type == SLICE_TYPE_SP)
 369         bit_rate_control_target = SLICE_TYPE_P;
 370     else if (slice_type == SLICE_TYPE_SI)
 371         bit_rate_control_target = SLICE_TYPE_I;
 372
 373     if (slice_type == SLICE_TYPE_P) {
 374         weighted_pred_idc = pic_param->pic_fields.bits.weighted_pred_flag;
 375     } else if (slice_type == SLICE_TYPE_B) {
 376         weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc;
 377
 378         if (weighted_pred_idc == 2) {
 379             /* 8.4.3 - Derivation process for prediction weights (8-279) */
 380             luma_log2_weight_denom = 5;
 381             chroma_log2_weight_denom = 5;
 382         }
 383     }
 384
 385     maxQpN = mfc_context->bit_rate_control_context[bit_rate_control_target].MaxQpNegModifier;
 386     maxQpP = mfc_context->bit_rate_control_context[bit_rate_control_target].MaxQpPosModifier;
 387
 388     for (i = 0; i < 6; i++)
 389         correct[i] = mfc_context->bit_rate_control_context[bit_rate_control_target].Correct[i];
 390
 391     grow = mfc_context->bit_rate_control_context[bit_rate_control_target].GrowInit +
 392         (mfc_context->bit_rate_control_context[bit_rate_control_target].GrowResistance << 4);
 393     shrink = mfc_context->bit_rate_control_context[bit_rate_control_target].ShrinkInit +
 394         (mfc_context->bit_rate_control_context[bit_rate_control_target].ShrinkResistance << 4);
 395
 396     BEGIN_BCS_BATCH(batch, 11);;
 397
 398     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) );
 399     OUT_BCS_BATCH(batch, slice_type);                   /*Slice Type: I:P:B Slice*/
 400
 401     if (slice_type == SLICE_TYPE_I) {
 402         OUT_BCS_BATCH(batch, 0);                        /*no reference frames and pred_weight_table*/
 403     } else {
 404         OUT_BCS_BATCH(batch,
 405                       (1 << 16) |                       /*1 reference frame*/
 406                       (chroma_log2_weight_denom << 8) |
 407                       (luma_log2_weight_denom << 0));
 408     }
 409
 410     OUT_BCS_BATCH(batch,
 411                   (weighted_pred_idc << 30) |
 412                   (slice_param->direct_spatial_mv_pred_flag<<29) |             /*Direct Prediction Type*/
 413                   (slice_param->disable_deblocking_filter_idc << 27) |
 414                   (slice_param->cabac_init_idc << 24) |
 415                   (qp<<16) |                    /*Slice Quantization Parameter*/
 416                   ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
 417                   ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
 418     OUT_BCS_BATCH(batch,
 419                   (beginy << 24) |                      /*First MB X&Y , the begin postion of current slice*/
 420                   (beginx << 16) |
 421                   slice_param->macroblock_address );
 422     OUT_BCS_BATCH(batch, (nexty << 16) | nextx);                       /*Next slice first MB X&Y*/
 423     OUT_BCS_BATCH(batch,
 424                   (0/*rate_control_enable*/ << 31) |            /*in CBR mode RateControlCounterEnable = enable*/
 425                   (1 << 30) |           /*ResetRateControlCounter*/
 426                   (0 << 28) |           /*RC Triggle Mode = Always Rate Control*/
 427                   (4 << 24) |     /*RC Stable Tolerance, middle level*/
 428                   (0/*rate_control_enable*/ << 23) |     /*RC Panic Enable*/
 429                   (0 << 22) |     /*QP mode, don't modfiy CBP*/
 430                   (0 << 21) |     /*MB Type Direct Conversion Enabled*/
 431                   (0 << 20) |     /*MB Type Skip Conversion Enabled*/
 432                   (last_slice << 19) |     /*IsLastSlice*/
 433                   (0 << 18) |   /*BitstreamOutputFlag Compressed BitStream Output Disable Flag 0:enable 1:disable*/
 434                   (1 << 17) |       /*HeaderPresentFlag*/
 435                   (1 << 16) |       /*SliceData PresentFlag*/
 436                   (1 << 15) |       /*TailPresentFlag*/
 437                   (1 << 13) |       /*RBSP NAL TYPE*/
 438                   (0 << 12) );    /*CabacZeroWordInsertionEnable*/
 439     OUT_BCS_BATCH(batch, mfc_context->mfc_indirect_pak_bse_object.offset);
 440     OUT_BCS_BATCH(batch,
 441                   (maxQpN << 24) |     /*Target QP - 24 is lowest QP*/
 442                   (maxQpP << 16) |     /*Target QP + 20 is highest QP*/
 443                   (shrink << 8)  |
 444                   (grow << 0));
 445     OUT_BCS_BATCH(batch,
 446                   (correct[5] << 20) |
 447                   (correct[4] << 16) |
 448                   (correct[3] << 12) |
 449                   (correct[2] << 8) |
 450                   (correct[1] << 4) |
 451                   (correct[0] << 0));
 452     OUT_BCS_BATCH(batch, 0);
 453
 454     ADVANCE_BCS_BATCH(batch);
 455 }
 456
 457 static void gen6_mfc_avc_qm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 458 {
 459     struct intel_batchbuffer *batch = encoder_context->base.batch;
 460     int i;
 461
 462     BEGIN_BCS_BATCH(batch, 58);
 463
 464     OUT_BCS_BATCH(batch, MFX_AVC_QM_STATE | 56);
 465     OUT_BCS_BATCH(batch, 0xFF ) ;
 466     for( i = 0; i < 56; i++) {
 467         OUT_BCS_BATCH(batch, 0x10101010);
 468     }
 469
 470     ADVANCE_BCS_BATCH(batch);
 471 }
 472
 473 static void gen6_mfc_avc_fqm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 474 {
 475     struct intel_batchbuffer *batch = encoder_context->base.batch;
 476     int i;
 477
 478     BEGIN_BCS_BATCH(batch, 113);
 479     OUT_BCS_BATCH(batch, MFC_AVC_FQM_STATE | (113 - 2));
 480
 481     for(i = 0; i < 112;i++) {
 482         OUT_BCS_BATCH(batch, 0x10001000);
 483     }
 484
 485     ADVANCE_BCS_BATCH(batch);
 486 }
 487
 488 static void
 489 gen6_mfc_avc_ref_idx_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 490 {
 491     struct intel_batchbuffer *batch = encoder_context->base.batch;
 492     int i;
 493
 494     BEGIN_BCS_BATCH(batch, 10);
 495     OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
 496     OUT_BCS_BATCH(batch, 0);                  //Select L0
 497     OUT_BCS_BATCH(batch, 0x80808020);         //Only 1 reference
 498     for(i = 0; i < 7; i++) {
 499         OUT_BCS_BATCH(batch, 0x80808080);
 500     }
 501     ADVANCE_BCS_BATCH(batch);
 502
 503     BEGIN_BCS_BATCH(batch, 10);
 504     OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
 505     OUT_BCS_BATCH(batch, 1);                  //Select L1
 506     OUT_BCS_BATCH(batch, 0x80808022);         //Only 1 reference
 507     for(i = 0; i < 7; i++) {
 508         OUT_BCS_BATCH(batch, 0x80808080);
 509     }
 510     ADVANCE_BCS_BATCH(batch);
 511 }
 512
 513 static void
 514 gen6_mfc_avc_insert_object(VADriverContextP ctx, struct intel_encoder_context *encoder_context,
 515                            unsigned int *insert_data, int lenght_in_dws, int data_bits_in_last_dw,
 516                            int skip_emul_byte_count, int is_last_header, int is_end_of_slice, int emulation_flag,
 517                            struct intel_batchbuffer *batch)
 518 {
 519     if (batch == NULL)
 520         batch = encoder_context->base.batch;
 521
 522     BEGIN_BCS_BATCH(batch, lenght_in_dws + 2);
 523
 524     OUT_BCS_BATCH(batch, MFC_AVC_INSERT_OBJECT | (lenght_in_dws + 2 - 2));
 525
 526     OUT_BCS_BATCH(batch,
 527                   (0 << 16) |   /* always start at offset 0 */
 528                   (data_bits_in_last_dw << 8) |
 529                   (skip_emul_byte_count << 4) |
 530                   (!!emulation_flag << 3) |
 531                   ((!!is_last_header) << 2) |
 532                   ((!!is_end_of_slice) << 1) |
 533                   (0 << 0));    /* FIXME: ??? */
 534
 535     intel_batchbuffer_data(batch, insert_data, lenght_in_dws * 4);
 536     ADVANCE_BCS_BATCH(batch);
 537 }
 538
 539 static void gen6_mfc_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 540 {
 541     struct i965_driver_data *i965 = i965_driver_data(ctx);
 542     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 543     dri_bo *bo;
 544     int i;
 545
 546     /*Encode common setup for MFC*/
 547     dri_bo_unreference(mfc_context->post_deblocking_output.bo);
 548     mfc_context->post_deblocking_output.bo = NULL;
 549
 550     dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
 551     mfc_context->pre_deblocking_output.bo = NULL;
 552
 553     dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
 554     mfc_context->uncompressed_picture_source.bo = NULL;
 555
 556     dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
 557     mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
 558
 559     for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
 560         if ( mfc_context->direct_mv_buffers[i].bo != NULL);
 561         dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
 562         mfc_context->direct_mv_buffers[i].bo = NULL;
 563     }
 564
 565     for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
 566         if (mfc_context->reference_surfaces[i].bo != NULL)
 567             dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
 568         mfc_context->reference_surfaces[i].bo = NULL;
 569     }
 570
 571     dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
 572     bo = dri_bo_alloc(i965->intel.bufmgr,
 573                       "Buffer",
 574                       128 * 64,
 575                       64);
 576     assert(bo);
 577     mfc_context->intra_row_store_scratch_buffer.bo = bo;
 578
 579     dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
 580     bo = dri_bo_alloc(i965->intel.bufmgr,
 581                       "Buffer",
 582                       128*128*16,
 583                       64);
 584     assert(bo);
 585     mfc_context->macroblock_status_buffer.bo = bo;
 586
 587     dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
 588     bo = dri_bo_alloc(i965->intel.bufmgr,
 589                       "Buffer",
 590                       49152,  /* 6 * 128 * 64 */
 591                       64);
 592     assert(bo);
 593     mfc_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
 594
 595     dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
 596     bo = dri_bo_alloc(i965->intel.bufmgr,
 597                       "Buffer",
 598                       12288, /* 1.5 * 128 * 64 */
 599                       0x1000);
 600     assert(bo);
 601     mfc_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
 602
 603     dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo);
 604     mfc_context->mfc_batchbuffer_surface.bo = NULL;
 605
 606     dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo);
 607     mfc_context->aux_batchbuffer_surface.bo = NULL;
 608
 609     if (mfc_context->aux_batchbuffer)
 610         intel_batchbuffer_free(mfc_context->aux_batchbuffer);
 611
 612     mfc_context->aux_batchbuffer = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD);
 613     mfc_context->aux_batchbuffer_surface.bo = mfc_context->aux_batchbuffer->buffer;
 614     dri_bo_reference(mfc_context->aux_batchbuffer_surface.bo);
 615     mfc_context->aux_batchbuffer_surface.pitch = 16;
 616     mfc_context->aux_batchbuffer_surface.num_blocks = mfc_context->aux_batchbuffer->size / 16;
 617     mfc_context->aux_batchbuffer_surface.size_block = 16;
 618
 619     i965_gpe_context_init(ctx, &mfc_context->gpe_context);
 620 }
 621
 622 static void gen6_mfc_avc_pipeline_header_programing(VADriverContextP ctx,
 623                                                     struct encode_state *encode_state,
 624                                                     struct intel_encoder_context *encoder_context,
 625                                                     struct intel_batchbuffer *slice_batch)
 626 {
 627     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 628     int idx = va_enc_packed_type_to_idx(VAEncPackedHeaderH264_SPS);
 629
 630     if (encode_state->packed_header_data[idx]) {
 631         VAEncPackedHeaderParameterBuffer *param = NULL;
 632         unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[idx]->buffer;
 633         unsigned int length_in_bits;
 634
 635         assert(encode_state->packed_header_param[idx]);
 636         param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer;
 637         length_in_bits = param->bit_length;
 638
 639         mfc_context->insert_object(ctx,
 640                                    encoder_context,
 641                                    header_data,
 642                                    ALIGN(length_in_bits, 32) >> 5,
 643                                    length_in_bits & 0x1f,
 644                                    5,   /* FIXME: check it */
 645                                    0,
 646                                    0,
 647                                    !param->has_emulation_bytes,
 648                                    slice_batch);
 649     }
 650
 651     idx = va_enc_packed_type_to_idx(VAEncPackedHeaderH264_PPS);
 652
 653     if (encode_state->packed_header_data[idx]) {
 654         VAEncPackedHeaderParameterBuffer *param = NULL;
 655         unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[idx]->buffer;
 656         unsigned int length_in_bits;
 657
 658         assert(encode_state->packed_header_param[idx]);
 659         param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer;
 660         length_in_bits = param->bit_length;
 661
 662         mfc_context->insert_object(ctx,
 663                                    encoder_context,
 664                                    header_data,
 665                                    ALIGN(length_in_bits, 32) >> 5,
 666                                    length_in_bits & 0x1f,
 667                                    5, /* FIXME: check it */
 668                                    0,
 669                                    0,
 670                                    !param->has_emulation_bytes,
 671                                    slice_batch);
 672     }
 673
 674     idx = va_enc_packed_type_to_idx(VAEncPackedHeaderH264_SEI);
 675
 676     if (encode_state->packed_header_data[idx]) {
 677         VAEncPackedHeaderParameterBuffer *param = NULL;
 678         unsigned int *header_data = (unsigned int *)encode_state->packed_header_data[idx]->buffer;
 679         unsigned int length_in_bits;
 680
 681         assert(encode_state->packed_header_param[idx]);
 682         param = (VAEncPackedHeaderParameterBuffer *)encode_state->packed_header_param[idx]->buffer;
 683         length_in_bits = param->bit_length;
 684
 685         mfc_context->insert_object(ctx,
 686                                    encoder_context,
 687                                    header_data,
 688                                    ALIGN(length_in_bits, 32) >> 5,
 689                                    length_in_bits & 0x1f,
 690                                    5, /* FIXME: check it */
 691                                    0,
 692                                    0,
 693                                    !param->has_emulation_bytes,
 694                                    slice_batch);
 695     }
 696 }
 697
 698 static void gen6_mfc_avc_pipeline_picture_programing( VADriverContextP ctx,
 699                                       struct encode_state *encode_state,
 700                                       struct intel_encoder_context *encoder_context)
 701 {
 702     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 703
 704     mfc_context->pipe_mode_select(ctx, MFX_FORMAT_AVC, encoder_context);
 705     mfc_context->set_surface_state(ctx, encoder_context);
 706     mfc_context->ind_obj_base_addr_state(ctx, encoder_context);
 707     gen6_mfc_pipe_buf_addr_state(ctx, encoder_context);
 708     gen6_mfc_bsp_buf_base_addr_state(ctx, encoder_context);
 709     mfc_context->avc_img_state(ctx, encode_state, encoder_context);
 710     mfc_context->avc_qm_state(ctx, encoder_context);
 711     mfc_context->avc_fqm_state(ctx, encoder_context);
 712     gen6_mfc_avc_directmode_state(ctx, encoder_context);
 713     gen6_mfc_avc_ref_idx_state(ctx, encoder_context);
 714 }
 715
 716 static void
 717 gen6_mfc_free_avc_surface(void **data)
 718 {
 719     struct gen6_mfc_avc_surface_aux *avc_surface = *data;
 720
 721     if (!avc_surface)
 722         return;
 723
 724     dri_bo_unreference(avc_surface->dmv_top);
 725     avc_surface->dmv_top = NULL;
 726     dri_bo_unreference(avc_surface->dmv_bottom);
 727     avc_surface->dmv_bottom = NULL;
 728
 729     free(avc_surface);
 730     *data = NULL;
 731 }
 732
 733
 734
 735
 736 static VAStatus gen6_mfc_avc_prepare(VADriverContextP ctx,
 737                                      struct encode_state *encode_state,
 738                                      struct intel_encoder_context *encoder_context)
 739 {
 740     struct i965_driver_data *i965 = i965_driver_data(ctx);
 741     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 742     struct object_surface *obj_surface;
 743     struct object_buffer *obj_buffer;
 744     struct gen6_mfc_avc_surface_aux* gen6_avc_surface;
 745     dri_bo *bo;
 746     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 747     VAStatus vaStatus = VA_STATUS_SUCCESS;
 748     int i, j, enable_avc_ildb = 0;
 749     VAEncSliceParameterBufferH264 *slice_param;
 750     VACodedBufferSegment *coded_buffer_segment;
 751     unsigned char *flag = NULL;
 752
 753     for (j = 0; j < encode_state->num_slice_params_ext && enable_avc_ildb == 0; j++) {
 754         assert(encode_state->slice_params_ext && encode_state->slice_params_ext[j]->buffer);
 755         slice_param = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[j]->buffer;
 756
 757         for (i = 0; i < encode_state->slice_params_ext[j]->num_elements; i++) {
 758             assert((slice_param->slice_type == SLICE_TYPE_I) ||
 759                    (slice_param->slice_type == SLICE_TYPE_SI) ||
 760                    (slice_param->slice_type == SLICE_TYPE_P) ||
 761                    (slice_param->slice_type == SLICE_TYPE_SP) ||
 762                    (slice_param->slice_type == SLICE_TYPE_B));
 763
 764             if (slice_param->disable_deblocking_filter_idc != 1) {
 765                 enable_avc_ildb = 1;
 766                 break;
 767             }
 768
 769             slice_param++;
 770         }
 771     }
 772
 773     /*Setup all the input&output object*/
 774
 775     /* Setup current frame and current direct mv buffer*/
 776     obj_surface = SURFACE(pPicParameter->CurrPic.picture_id);
 777     assert(obj_surface);
 778     i965_check_alloc_surface_bo(ctx, obj_surface, 1, VA_FOURCC('N','V','1','2'), SUBSAMPLE_YUV420);
 779
 780     if ( obj_surface->private_data == NULL) {
 781         gen6_avc_surface = calloc(sizeof(struct gen6_mfc_avc_surface_aux), 1);
 782         gen6_avc_surface->dmv_top =
 783             dri_bo_alloc(i965->intel.bufmgr,
 784                          "Buffer",
 785                          68*8192,
 786                          64);
 787         gen6_avc_surface->dmv_bottom =
 788             dri_bo_alloc(i965->intel.bufmgr,
 789                          "Buffer",
 790                          68*8192,
 791                          64);
 792         assert(gen6_avc_surface->dmv_top);
 793         assert(gen6_avc_surface->dmv_bottom);
 794         obj_surface->private_data = (void *)gen6_avc_surface;
 795         obj_surface->free_private_data = (void *)gen6_mfc_free_avc_surface;
 796     }
 797     gen6_avc_surface = (struct gen6_mfc_avc_surface_aux*) obj_surface->private_data;
 798     mfc_context->direct_mv_buffers[NUM_MFC_DMV_BUFFERS - 2].bo = gen6_avc_surface->dmv_top;
 799     mfc_context->direct_mv_buffers[NUM_MFC_DMV_BUFFERS - 1].bo = gen6_avc_surface->dmv_bottom;
 800     dri_bo_reference(gen6_avc_surface->dmv_top);
 801     dri_bo_reference(gen6_avc_surface->dmv_bottom);
 802
 803     if (enable_avc_ildb) {
 804         mfc_context->post_deblocking_output.bo = obj_surface->bo;
 805         dri_bo_reference(mfc_context->post_deblocking_output.bo);
 806     } else {
 807         mfc_context->pre_deblocking_output.bo = obj_surface->bo;
 808         dri_bo_reference(mfc_context->pre_deblocking_output.bo);
 809     }
 810
 811     mfc_context->surface_state.width = obj_surface->orig_width;
 812     mfc_context->surface_state.height = obj_surface->orig_height;
 813     mfc_context->surface_state.w_pitch = obj_surface->width;
 814     mfc_context->surface_state.h_pitch = obj_surface->height;
 815
 816     /* Setup reference frames and direct mv buffers*/
 817     for(i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++) {
 818         if ( pPicParameter->ReferenceFrames[i].picture_id != VA_INVALID_ID ) {
 819             obj_surface = SURFACE(pPicParameter->ReferenceFrames[i].picture_id);
 820             assert(obj_surface);
 821             if (obj_surface->bo != NULL) {
 822                 mfc_context->reference_surfaces[i].bo = obj_surface->bo;
 823                 dri_bo_reference(obj_surface->bo);
 824             }
 825             /* Check DMV buffer */
 826             if ( obj_surface->private_data == NULL) {
 827
 828                 gen6_avc_surface = calloc(sizeof(struct gen6_mfc_avc_surface_aux), 1);
 829                 gen6_avc_surface->dmv_top =
 830                     dri_bo_alloc(i965->intel.bufmgr,
 831                                  "Buffer",
 832                                  68*8192,
 833                                  64);
 834                 gen6_avc_surface->dmv_bottom =
 835                     dri_bo_alloc(i965->intel.bufmgr,
 836                                  "Buffer",
 837                                  68*8192,
 838                                  64);
 839                 assert(gen6_avc_surface->dmv_top);
 840                 assert(gen6_avc_surface->dmv_bottom);
 841                 obj_surface->private_data = gen6_avc_surface;
 842                 obj_surface->free_private_data = gen6_mfc_free_avc_surface;
 843             }
 844
 845             gen6_avc_surface = (struct gen6_mfc_avc_surface_aux*) obj_surface->private_data;
 846             /* Setup DMV buffer */
 847             mfc_context->direct_mv_buffers[i*2].bo = gen6_avc_surface->dmv_top;
 848             mfc_context->direct_mv_buffers[i*2+1].bo = gen6_avc_surface->dmv_bottom;
 849             dri_bo_reference(gen6_avc_surface->dmv_top);
 850             dri_bo_reference(gen6_avc_surface->dmv_bottom);
 851         } else {
 852             break;
 853         }
 854     }
 855
 856     obj_surface = SURFACE(encoder_context->input_yuv_surface);
 857     assert(obj_surface && obj_surface->bo);
 858     mfc_context->uncompressed_picture_source.bo = obj_surface->bo;
 859     dri_bo_reference(mfc_context->uncompressed_picture_source.bo);
 860
 861     obj_buffer = BUFFER (pPicParameter->coded_buf); /* FIXME: fix this later */
 862     bo = obj_buffer->buffer_store->bo;
 863     assert(bo);
 864     mfc_context->mfc_indirect_pak_bse_object.bo = bo;
 865     mfc_context->mfc_indirect_pak_bse_object.offset = I965_CODEDBUFFER_SIZE;
 866     mfc_context->mfc_indirect_pak_bse_object.end_offset = ALIGN(obj_buffer->size_element - 0x1000, 0x1000);
 867     dri_bo_reference(mfc_context->mfc_indirect_pak_bse_object.bo);
 868
 869     dri_bo_map(bo, 1);
 870     coded_buffer_segment = (VACodedBufferSegment *)bo->virtual;
 871     flag = (unsigned char *)(coded_buffer_segment + 1);
 872     *flag = 0;
 873     dri_bo_unmap(bo);
 874
 875     return vaStatus;
 876 }
 877
 878 static VAStatus gen6_mfc_run(VADriverContextP ctx,
 879                              struct encode_state *encode_state,
 880                              struct intel_encoder_context *encoder_context)
 881 {
 882     struct intel_batchbuffer *batch = encoder_context->base.batch;
 883
 884     intel_batchbuffer_flush(batch);             //run the pipeline
 885
 886     return VA_STATUS_SUCCESS;
 887 }
 888
 889 static VAStatus
 890 gen6_mfc_stop(VADriverContextP ctx,
 891               struct encode_state *encode_state,
 892               struct intel_encoder_context *encoder_context,
 893               int *encoded_bits_size)
 894 {
 895     VAStatus vaStatus = VA_STATUS_ERROR_UNKNOWN;
 896     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 897     VACodedBufferSegment *coded_buffer_segment;
 898
 899     vaStatus = i965_MapBuffer(ctx, pPicParameter->coded_buf, (void **)&coded_buffer_segment);
 900     assert(vaStatus == VA_STATUS_SUCCESS);
 901     *encoded_bits_size = coded_buffer_segment->size * 8;
 902     i965_UnmapBuffer(ctx, pPicParameter->coded_buf);
 903
 904     return VA_STATUS_SUCCESS;
 905 }
 906
 907 #if __SOFTWARE__
 908
 909 static int
 910 gen6_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb, int qp,unsigned int *msg,
 911                               struct intel_encoder_context *encoder_context,
 912                               unsigned char target_mb_size, unsigned char max_mb_size,
 913                               struct intel_batchbuffer *batch)
 914 {
 915     int len_in_dwords = 11;
 916
 917     if (batch == NULL)
 918         batch = encoder_context->base.batch;
 919
 920     BEGIN_BCS_BATCH(batch, len_in_dwords);
 921
 922     OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
 923     OUT_BCS_BATCH(batch, 0);
 924     OUT_BCS_BATCH(batch, 0);
 925     OUT_BCS_BATCH(batch,
 926                   (0 << 24) |           /* PackedMvNum, Debug*/
 927                   (0 << 20) |           /* No motion vector */
 928                   (1 << 19) |           /* CbpDcY */
 929                   (1 << 18) |           /* CbpDcU */
 930                   (1 << 17) |           /* CbpDcV */
 931                   (msg[0] & 0xFFFF) );
 932
 933     OUT_BCS_BATCH(batch, (0xFFFF << 16) | (y << 8) | x);                /* Code Block Pattern for Y*/
 934     OUT_BCS_BATCH(batch, 0x000F000F);                                                   /* Code Block Pattern */
 935     OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp);      /* Last MB */
 936
 937     /*Stuff for Intra MB*/
 938     OUT_BCS_BATCH(batch, msg[1]);                       /* We using Intra16x16 no 4x4 predmode*/
 939     OUT_BCS_BATCH(batch, msg[2]);
 940     OUT_BCS_BATCH(batch, msg[3]&0xFC);
 941
 942     /*MaxSizeInWord and TargetSzieInWord*/
 943     OUT_BCS_BATCH(batch, (max_mb_size << 24) |
 944                   (target_mb_size << 16) );
 945
 946     ADVANCE_BCS_BATCH(batch);
 947
 948     return len_in_dwords;
 949 }
 950
 951 static int
 952 gen6_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, int qp,
 953                               unsigned int *msg, unsigned int offset,
 954                               struct intel_encoder_context *encoder_context,
 955                               unsigned char target_mb_size,unsigned char max_mb_size, int slice_type,
 956                               struct intel_batchbuffer *batch)
 957 {
 958     int len_in_dwords = 11;
 959
 960     if (batch == NULL)
 961         batch = encoder_context->base.batch;
 962
 963     BEGIN_BCS_BATCH(batch, len_in_dwords);
 964
 965     OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
 966
 967     OUT_BCS_BATCH(batch, msg[2]);         /* 32 MV*/
 968     OUT_BCS_BATCH(batch, offset);
 969
 970     OUT_BCS_BATCH(batch, msg[0]);
 971
 972     OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x);        /* Code Block Pattern for Y*/
 973     OUT_BCS_BATCH(batch, 0x000F000F);                         /* Code Block Pattern */
 974 #if 0
 975     if ( slice_type == SLICE_TYPE_B) {
 976         OUT_BCS_BATCH(batch, (0xF<<28) | (end_mb << 26) | qp);  /* Last MB */
 977     } else {
 978         OUT_BCS_BATCH(batch, (end_mb << 26) | qp);      /* Last MB */
 979     }
 980 #else
 981     OUT_BCS_BATCH(batch, (end_mb << 26) | qp);  /* Last MB */
 982 #endif
 983
 984
 985     /*Stuff for Inter MB*/
 986     OUT_BCS_BATCH(batch, msg[1]);
 987     OUT_BCS_BATCH(batch, 0x0);
 988     OUT_BCS_BATCH(batch, 0x0);
 989
 990     /*MaxSizeInWord and TargetSzieInWord*/
 991     OUT_BCS_BATCH(batch, (max_mb_size << 24) |
 992                   (target_mb_size << 16) );
 993
 994     ADVANCE_BCS_BATCH(batch);
 995
 996     return len_in_dwords;
 997 }
 998
 999 static void
1000 gen6_mfc_avc_pipeline_slice_programing(VADriverContextP ctx,
1001                                        struct encode_state *encode_state,
1002                                        struct intel_encoder_context *encoder_context,
1003                                        int slice_index,
1004                                        struct intel_batchbuffer *slice_batch)
1005 {
1006     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1007     struct gen6_vme_context *vme_context = encoder_context->vme_context;
1008     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
1009     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
1010     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
1011     unsigned int *msg = NULL, offset = 0;
1012     int is_intra = pSliceParameter->slice_type == SLICE_TYPE_I;
1013     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
1014     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
1015     int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs);
1016     int i,x,y;
1017     int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta;
1018     unsigned int rate_control_mode = encoder_context->rate_control_mode;
1019     unsigned char *slice_header = NULL;
1020     int slice_header_length_in_bits = 0;
1021     unsigned int tail_data[] = { 0x0, 0x0 };
1022     int slice_type = pSliceParameter->slice_type;
1023
1024
1025     if (rate_control_mode == VA_RC_CBR) {
1026         qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
1027         pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp;
1028     }
1029
1030     /* only support for 8-bit pixel bit-depth */
1031     assert(pSequenceParameter->bit_depth_luma_minus8 == 0);
1032     assert(pSequenceParameter->bit_depth_chroma_minus8 == 0);
1033     assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52);
1034     assert(qp >= 0 && qp < 52);
1035
1036     gen6_mfc_avc_slice_state(ctx,
1037                              pPicParameter,
1038                              pSliceParameter,
1039                              encode_state, encoder_context,
1040                              (rate_control_mode == VA_RC_CBR), qp, slice_batch);
1041
1042     if ( slice_index == 0)
1043         gen6_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch);
1044
1045     slice_header_length_in_bits = build_avc_slice_header(pSequenceParameter, pPicParameter, pSliceParameter, &slice_header);
1046
1047     // slice hander
1048     mfc_context->insert_object(ctx, encoder_context,
1049                                (unsigned int *)slice_header, ALIGN(slice_header_length_in_bits, 32) >> 5, slice_header_length_in_bits & 0x1f,
1050                                5,  /* first 5 bytes are start code + nal unit type */
1051                                1, 0, 1, slice_batch);
1052
1053     dri_bo_map(vme_context->vme_output.bo , 1);
1054     msg = (unsigned int *)vme_context->vme_output.bo->virtual;
1055
1056     if (is_intra) {
1057         msg += pSliceParameter->macroblock_address * INTRA_VME_OUTPUT_IN_DWS;
1058     } else {
1059         msg += pSliceParameter->macroblock_address * INTER_VME_OUTPUT_IN_DWS;
1060         msg += 32; /* the first 32 DWs are MVs */
1061         offset = pSliceParameter->macroblock_address * INTER_VME_OUTPUT_IN_BYTES;
1062     }
1063
1064     for (i = pSliceParameter->macroblock_address;
1065          i < pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks; i++) {
1066         int last_mb = (i == (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks - 1) );
1067         x = i % width_in_mbs;
1068         y = i / width_in_mbs;
1069
1070         if (is_intra) {
1071             assert(msg);
1072             gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch);
1073             msg += INTRA_VME_OUTPUT_IN_DWS;
1074         } else {
1075             if (msg[0] & INTRA_MB_FLAG_MASK) {
1076                 gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch);
1077             } else {
1078                 gen6_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, msg, offset, encoder_context, 0, 0, pSliceParameter->slice_type, slice_batch);
1079             }
1080
1081             msg += INTER_VME_OUTPUT_IN_DWS;
1082             offset += INTER_VME_OUTPUT_IN_BYTES;
1083         }
1084     }
1085
1086     dri_bo_unmap(vme_context->vme_output.bo);
1087
1088     if ( last_slice ) {
1089         mfc_context->insert_object(ctx, encoder_context,
1090                                    tail_data, 2, 8,
1091                                    2, 1, 1, 0, slice_batch);
1092     } else {
1093         mfc_context->insert_object(ctx, encoder_context,
1094                                    tail_data, 1, 8,
1095                                    1, 1, 1, 0, slice_batch);
1096     }
1097
1098     free(slice_header);
1099
1100 }
1101
1102 static dri_bo *
1103 gen6_mfc_avc_software_batchbuffer(VADriverContextP ctx,
1104                                   struct encode_state *encode_state,
1105                                   struct intel_encoder_context *encoder_context)
1106 {
1107     struct i965_driver_data *i965 = i965_driver_data(ctx);
1108     struct intel_batchbuffer *batch = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD);
1109     dri_bo *batch_bo = batch->buffer;
1110     int i;
1111
1112     for (i = 0; i < encode_state->num_slice_params_ext; i++) {
1113         gen6_mfc_avc_pipeline_slice_programing(ctx, encode_state, encoder_context, i, batch);
1114     }
1115
1116     intel_batchbuffer_align(batch, 8);
1117
1118     BEGIN_BCS_BATCH(batch, 2);
1119     OUT_BCS_BATCH(batch, 0);
1120     OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_END);
1121     ADVANCE_BCS_BATCH(batch);
1122
1123     dri_bo_reference(batch_bo);
1124     intel_batchbuffer_free(batch);
1125
1126     return batch_bo;
1127 }
1128
1129 #else
1130
1131 static void
1132 gen6_mfc_batchbuffer_surfaces_input(VADriverContextP ctx,
1133                                     struct encode_state *encode_state,
1134                                     struct intel_encoder_context *encoder_context)
1135
1136 {
1137     struct gen6_vme_context *vme_context = encoder_context->vme_context;
1138     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1139
1140     assert(vme_context->vme_output.bo);
1141     mfc_context->buffer_suface_setup(ctx,
1142                                      &mfc_context->gpe_context,
1143                                      &vme_context->vme_output,
1144                                      BINDING_TABLE_OFFSET(BIND_IDX_VME_OUTPUT),
1145                                      SURFACE_STATE_OFFSET(BIND_IDX_VME_OUTPUT));
1146     assert(mfc_context->aux_batchbuffer_surface.bo);
1147     mfc_context->buffer_suface_setup(ctx,
1148                                      &mfc_context->gpe_context,
1149                                      &mfc_context->aux_batchbuffer_surface,
1150                                      BINDING_TABLE_OFFSET(BIND_IDX_MFC_SLICE_HEADER),
1151                                      SURFACE_STATE_OFFSET(BIND_IDX_MFC_SLICE_HEADER));
1152 }
1153
1154 static void
1155 gen6_mfc_batchbuffer_surfaces_output(VADriverContextP ctx,
1156                                      struct encode_state *encode_state,
1157                                      struct intel_encoder_context *encoder_context)
1158
1159 {
1160     struct i965_driver_data *i965 = i965_driver_data(ctx);
1161     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1162     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
1163     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
1164     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
1165     mfc_context->mfc_batchbuffer_surface.num_blocks = width_in_mbs * height_in_mbs + encode_state->num_slice_params_ext * 8 + 1;
1166     mfc_context->mfc_batchbuffer_surface.size_block = 16 * CMD_LEN_IN_OWORD; /* 3 OWORDs */
1167     mfc_context->mfc_batchbuffer_surface.pitch = 16;
1168     mfc_context->mfc_batchbuffer_surface.bo = dri_bo_alloc(i965->intel.bufmgr,
1169                                                            "MFC batchbuffer",
1170                                                            mfc_context->mfc_batchbuffer_surface.num_blocks * mfc_context->mfc_batchbuffer_surface.size_block,
1171                                                            0x1000);
1172     mfc_context->buffer_suface_setup(ctx,
1173                                      &mfc_context->gpe_context,
1174                                      &mfc_context->mfc_batchbuffer_surface,
1175                                      BINDING_TABLE_OFFSET(BIND_IDX_MFC_BATCHBUFFER),
1176                                      SURFACE_STATE_OFFSET(BIND_IDX_MFC_BATCHBUFFER));
1177 }
1178
1179 static void
1180 gen6_mfc_batchbuffer_surfaces_setup(VADriverContextP ctx,
1181                                     struct encode_state *encode_state,
1182                                     struct intel_encoder_context *encoder_context)
1183 {
1184     gen6_mfc_batchbuffer_surfaces_input(ctx, encode_state, encoder_context);
1185     gen6_mfc_batchbuffer_surfaces_output(ctx, encode_state, encoder_context);
1186 }
1187
1188 static void
1189 gen6_mfc_batchbuffer_idrt_setup(VADriverContextP ctx,
1190                                 struct encode_state *encode_state,
1191                                 struct intel_encoder_context *encoder_context)
1192 {
1193     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1194     struct gen6_interface_descriptor_data *desc;
1195     int i;
1196     dri_bo *bo;
1197
1198     bo = mfc_context->gpe_context.idrt.bo;
1199     dri_bo_map(bo, 1);
1200     assert(bo->virtual);
1201     desc = bo->virtual;
1202
1203     for (i = 0; i < mfc_context->gpe_context.num_kernels; i++) {
1204         struct i965_kernel *kernel;
1205
1206         kernel = &mfc_context->gpe_context.kernels[i];
1207         assert(sizeof(*desc) == 32);
1208
1209         /*Setup the descritor table*/
1210         memset(desc, 0, sizeof(*desc));
1211         desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6);
1212         desc->desc2.sampler_count = 0;
1213         desc->desc2.sampler_state_pointer = 0;
1214         desc->desc3.binding_table_entry_count = 2;
1215         desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5);
1216         desc->desc4.constant_urb_entry_read_offset = 0;
1217         desc->desc4.constant_urb_entry_read_length = 4;
1218
1219         /*kernel start*/
1220         dri_bo_emit_reloc(bo,
1221                           I915_GEM_DOMAIN_INSTRUCTION, 0,
1222                           0,
1223                           i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0),
1224                           kernel->bo);
1225         desc++;
1226     }
1227
1228     dri_bo_unmap(bo);
1229 }
1230
1231 static void
1232 gen6_mfc_batchbuffer_constant_setup(VADriverContextP ctx,
1233                                     struct encode_state *encode_state,
1234                                     struct intel_encoder_context *encoder_context)
1235 {
1236     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1237
1238     (void)mfc_context;
1239 }
1240
1241 static void
1242 gen6_mfc_batchbuffer_emit_object_command(struct intel_batchbuffer *batch,
1243                                          int index,
1244                                          int head_offset,
1245                                          int batchbuffer_offset,
1246                                          int head_size,
1247                                          int tail_size,
1248                                          int number_mb_cmds,
1249                                          int first_object,
1250                                          int last_object,
1251                                          int last_slice,
1252                                          int mb_x,
1253                                          int mb_y,
1254                                          int width_in_mbs,
1255                                          int qp)
1256 {
1257     BEGIN_BATCH(batch, 12);
1258
1259     OUT_BATCH(batch, CMD_MEDIA_OBJECT | (12 - 2));
1260     OUT_BATCH(batch, index);
1261     OUT_BATCH(batch, 0);
1262     OUT_BATCH(batch, 0);
1263     OUT_BATCH(batch, 0);
1264     OUT_BATCH(batch, 0);
1265
1266     /*inline data */
1267     OUT_BATCH(batch, head_offset);
1268     OUT_BATCH(batch, batchbuffer_offset);
1269     OUT_BATCH(batch,
1270               head_size << 16 |
1271               tail_size);
1272     OUT_BATCH(batch,
1273               number_mb_cmds << 16 |
1274               first_object << 2 |
1275               last_object << 1 |
1276               last_slice);
1277     OUT_BATCH(batch,
1278               mb_y << 8 |
1279               mb_x);
1280     OUT_BATCH(batch,
1281               qp << 16 |
1282               width_in_mbs);
1283
1284     ADVANCE_BATCH(batch);
1285 }
1286
1287 static void
1288 gen6_mfc_avc_batchbuffer_slice_command(VADriverContextP ctx,
1289                                        struct intel_encoder_context *encoder_context,
1290                                        VAEncSliceParameterBufferH264 *slice_param,
1291                                        int head_offset,
1292                                        unsigned short head_size,
1293                                        unsigned short tail_size,
1294                                        int batchbuffer_offset,
1295                                        int qp,
1296                                        int last_slice)
1297 {
1298     struct intel_batchbuffer *batch = encoder_context->base.batch;
1299     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1300     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
1301     int total_mbs = slice_param->num_macroblocks;
1302     int number_mb_cmds = 128;
1303     int starting_mb = 0;
1304     int last_object = 0;
1305     int first_object = 1;
1306     int i;
1307     int mb_x, mb_y;
1308     int index = (slice_param->slice_type == SLICE_TYPE_I) ? MFC_BATCHBUFFER_AVC_INTRA : MFC_BATCHBUFFER_AVC_INTER;
1309
1310     for (i = 0; i < total_mbs / number_mb_cmds; i++) {
1311         last_object = (total_mbs - starting_mb) == number_mb_cmds;
1312         mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs;
1313         mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs;
1314         assert(mb_x <= 255 && mb_y <= 255);
1315
1316         starting_mb += number_mb_cmds;
1317
1318         gen6_mfc_batchbuffer_emit_object_command(batch,
1319                                                  index,
1320                                                  head_offset,
1321                                                  batchbuffer_offset,
1322                                                  head_size,
1323                                                  tail_size,
1324                                                  number_mb_cmds,
1325                                                  first_object,
1326                                                  last_object,
1327                                                  last_slice,
1328                                                  mb_x,
1329                                                  mb_y,
1330                                                  width_in_mbs,
1331                                                  qp);
1332
1333         if (first_object) {
1334             head_offset += head_size;
1335             batchbuffer_offset += head_size;
1336         }
1337
1338         if (last_object) {
1339             head_offset += tail_size;
1340             batchbuffer_offset += tail_size;
1341         }
1342
1343         batchbuffer_offset += number_mb_cmds * CMD_LEN_IN_OWORD;
1344
1345         first_object = 0;
1346     }
1347
1348     if (!last_object) {
1349         last_object = 1;
1350         number_mb_cmds = total_mbs % number_mb_cmds;
1351         mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs;
1352         mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs;
1353         assert(mb_x <= 255 && mb_y <= 255);
1354         starting_mb += number_mb_cmds;
1355
1356         gen6_mfc_batchbuffer_emit_object_command(batch,
1357                                                  index,
1358                                                  head_offset,
1359                                                  batchbuffer_offset,
1360                                                  head_size,
1361                                                  tail_size,
1362                                                  number_mb_cmds,
1363                                                  first_object,
1364                                                  last_object,
1365                                                  last_slice,
1366                                                  mb_x,
1367                                                  mb_y,
1368                                                  width_in_mbs,
1369                                                  qp);
1370     }
1371 }
1372
1373 /*
1374  * return size in Owords (16bytes)
1375  */
1376 static int
1377 gen6_mfc_avc_batchbuffer_slice(VADriverContextP ctx,
1378                                struct encode_state *encode_state,
1379                                struct intel_encoder_context *encoder_context,
1380                                int slice_index,
1381                                int batchbuffer_offset)
1382 {
1383     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1384     struct intel_batchbuffer *slice_batch = mfc_context->aux_batchbuffer;
1385     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
1386     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
1387     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
1388     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
1389     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
1390     int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs);
1391     int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta;
1392     unsigned int rate_control_mode = encoder_context->rate_control_mode;
1393     unsigned char *slice_header = NULL;
1394     int slice_header_length_in_bits = 0;
1395     unsigned int tail_data[] = { 0x0, 0x0 };
1396     long head_offset;
1397     int old_used = intel_batchbuffer_used_size(slice_batch), used;
1398     unsigned short head_size, tail_size;
1399     int slice_type = pSliceParameter->slice_type;
1400
1401     if (rate_control_mode == VA_RC_CBR) {
1402         qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
1403         pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp;
1404     }
1405
1406     /* only support for 8-bit pixel bit-depth */
1407     assert(pSequenceParameter->bit_depth_luma_minus8 == 0);
1408     assert(pSequenceParameter->bit_depth_chroma_minus8 == 0);
1409     assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52);
1410     assert(qp >= 0 && qp < 52);
1411
1412     head_offset = old_used / 16;
1413     gen6_mfc_avc_slice_state(ctx,
1414                              pPicParameter,
1415                              pSliceParameter,
1416                              encode_state,
1417                              encoder_context,
1418                              (rate_control_mode == VA_RC_CBR),
1419                              qp,
1420                              slice_batch);
1421
1422     if (slice_index == 0)
1423         gen6_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch);
1424
1425     slice_header_length_in_bits = build_avc_slice_header(pSequenceParameter, pPicParameter, pSliceParameter, &slice_header);
1426
1427     // slice hander
1428     mfc_context->insert_object(ctx,
1429                                encoder_context,
1430                                (unsigned int *)slice_header,
1431                                ALIGN(slice_header_length_in_bits, 32) >> 5,
1432                                slice_header_length_in_bits & 0x1f,
1433                                5,  /* first 5 bytes are start code + nal unit type */
1434                                1,
1435                                0,
1436                                1,
1437                                slice_batch);
1438     free(slice_header);
1439
1440     intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */
1441     used = intel_batchbuffer_used_size(slice_batch);
1442     head_size = (used - old_used) / 16;
1443     old_used = used;
1444
1445     /* tail */
1446     if (last_slice) {
1447         mfc_context->insert_object(ctx,
1448                                    encoder_context,
1449                                    tail_data,
1450                                    2,
1451                                    8,
1452                                    2,
1453                                    1,
1454                                    1,
1455                                    0,
1456                                    slice_batch);
1457     } else {
1458         mfc_context->insert_object(ctx,
1459                                    encoder_context,
1460                                    tail_data,
1461                                    1,
1462                                    8,
1463                                    1,
1464                                    1,
1465                                    1,
1466                                    0,
1467                                    slice_batch);
1468     }
1469
1470     intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */
1471     used = intel_batchbuffer_used_size(slice_batch);
1472     tail_size = (used - old_used) / 16;
1473
1474
1475     gen6_mfc_avc_batchbuffer_slice_command(ctx,
1476                                            encoder_context,
1477                                            pSliceParameter,
1478                                            head_offset,
1479                                            head_size,
1480                                            tail_size,
1481                                            batchbuffer_offset,
1482                                            qp,
1483                                            last_slice);
1484
1485     return head_size + tail_size + pSliceParameter->num_macroblocks * CMD_LEN_IN_OWORD;
1486 }
1487
1488 static void
1489 gen6_mfc_avc_batchbuffer_pipeline(VADriverContextP ctx,
1490                                   struct encode_state *encode_state,
1491                                   struct intel_encoder_context *encoder_context)
1492 {
1493     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1494     struct intel_batchbuffer *batch = encoder_context->base.batch;
1495     int i, size, offset = 0;
1496     intel_batchbuffer_start_atomic(batch, 0x4000);
1497     gen6_gpe_pipeline_setup(ctx, &mfc_context->gpe_context, batch);
1498
1499     for ( i = 0; i < encode_state->num_slice_params_ext; i++) {
1500         size = gen6_mfc_avc_batchbuffer_slice(ctx, encode_state, encoder_context, i, offset);
1501         offset += size;
1502     }
1503
1504     intel_batchbuffer_end_atomic(batch);
1505     intel_batchbuffer_flush(batch);
1506 }
1507
1508 static void
1509 gen6_mfc_build_avc_batchbuffer(VADriverContextP ctx,
1510                                struct encode_state *encode_state,
1511                                struct intel_encoder_context *encoder_context)
1512 {
1513     gen6_mfc_batchbuffer_surfaces_setup(ctx, encode_state, encoder_context);
1514     gen6_mfc_batchbuffer_idrt_setup(ctx, encode_state, encoder_context);
1515     gen6_mfc_batchbuffer_constant_setup(ctx, encode_state, encoder_context);
1516     gen6_mfc_avc_batchbuffer_pipeline(ctx, encode_state, encoder_context);
1517 }
1518
1519 static dri_bo *
1520 gen6_mfc_avc_hardware_batchbuffer(VADriverContextP ctx,
1521                                   struct encode_state *encode_state,
1522                                   struct intel_encoder_context *encoder_context)
1523 {
1524     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1525
1526     gen6_mfc_build_avc_batchbuffer(ctx, encode_state, encoder_context);
1527     dri_bo_reference(mfc_context->mfc_batchbuffer_surface.bo);
1528
1529     return mfc_context->mfc_batchbuffer_surface.bo;
1530 }
1531
1532 #endif
1533
1534
1535 static void
1536 gen6_mfc_avc_pipeline_programing(VADriverContextP ctx,
1537                                  struct encode_state *encode_state,
1538                                  struct intel_encoder_context *encoder_context)
1539 {
1540     struct intel_batchbuffer *batch = encoder_context->base.batch;
1541     dri_bo *slice_batch_bo;
1542
1543     if ( intel_mfc_interlace_check(ctx, encode_state, encoder_context) ) {
1544         fprintf(stderr, "Current VA driver don't support interlace mode!\n");
1545         assert(0);
1546         return;
1547     }
1548
1549 #if __SOFTWARE__
1550     slice_batch_bo = gen6_mfc_avc_software_batchbuffer(ctx, encode_state, encoder_context);
1551 #else
1552     slice_batch_bo = gen6_mfc_avc_hardware_batchbuffer(ctx, encode_state, encoder_context);
1553 #endif
1554
1555     // begin programing
1556     intel_batchbuffer_start_atomic_bcs(batch, 0x4000);
1557     intel_batchbuffer_emit_mi_flush(batch);
1558
1559     // picture level programing
1560     gen6_mfc_avc_pipeline_picture_programing(ctx, encode_state, encoder_context);
1561
1562     BEGIN_BCS_BATCH(batch, 2);
1563     OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8));
1564     OUT_BCS_RELOC(batch,
1565                   slice_batch_bo,
1566                   I915_GEM_DOMAIN_COMMAND, 0,
1567                   0);
1568     ADVANCE_BCS_BATCH(batch);
1569
1570     // end programing
1571     intel_batchbuffer_end_atomic(batch);
1572
1573     dri_bo_unreference(slice_batch_bo);
1574 }
1575
1576 static VAStatus
1577 gen6_mfc_avc_encode_picture(VADriverContextP ctx,
1578                             struct encode_state *encode_state,
1579                             struct intel_encoder_context *encoder_context)
1580 {
1581     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1582     unsigned int rate_control_mode = encoder_context->rate_control_mode;
1583     int current_frame_bits_size;
1584     int sts;
1585
1586     for (;;) {
1587         gen6_mfc_init(ctx, encoder_context);
1588         gen6_mfc_avc_prepare(ctx, encode_state, encoder_context);
1589         /*Programing bcs pipeline*/
1590         gen6_mfc_avc_pipeline_programing(ctx, encode_state, encoder_context);   //filling the pipeline
1591         gen6_mfc_run(ctx, encode_state, encoder_context);
1592         if (rate_control_mode == VA_RC_CBR /*|| rate_control_mode == VA_RC_VBR*/) {
1593             gen6_mfc_stop(ctx, encode_state, encoder_context, &current_frame_bits_size);
1594             sts = intel_mfc_brc_postpack(encode_state, mfc_context, current_frame_bits_size);
1595             if (sts == BRC_NO_HRD_VIOLATION) {
1596                 intel_mfc_hrd_context_update(encode_state, mfc_context);
1597                 break;
1598             }
1599             else if (sts == BRC_OVERFLOW_WITH_MIN_QP || sts == BRC_UNDERFLOW_WITH_MAX_QP) {
1600                 if (!mfc_context->hrd.violation_noted) {
1601                     fprintf(stderr, "Unrepairable %s!\n", (sts == BRC_OVERFLOW_WITH_MIN_QP)? "overflow": "underflow");
1602                     mfc_context->hrd.violation_noted = 1;
1603                 }
1604                 return VA_STATUS_SUCCESS;
1605             }
1606         } else {
1607             break;
1608         }
1609     }
1610
1611     return VA_STATUS_SUCCESS;
1612 }
1613
1614 VAStatus
1615 gen6_mfc_pipeline(VADriverContextP ctx,
1616                   VAProfile profile,
1617                   struct encode_state *encode_state,
1618                   struct intel_encoder_context *encoder_context)
1619 {
1620     VAStatus vaStatus;
1621
1622     switch (profile) {
1623     case VAProfileH264Baseline:
1624     case VAProfileH264Main:
1625     case VAProfileH264High:
1626         vaStatus = gen6_mfc_avc_encode_picture(ctx, encode_state, encoder_context);
1627         break;
1628
1629         /* FIXME: add for other profile */
1630     default:
1631         vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
1632         break;
1633     }
1634
1635     return vaStatus;
1636 }
1637
1638 void
1639 gen6_mfc_context_destroy(void *context)
1640 {
1641     struct gen6_mfc_context *mfc_context = context;
1642     int i;
1643
1644     dri_bo_unreference(mfc_context->post_deblocking_output.bo);
1645     mfc_context->post_deblocking_output.bo = NULL;
1646
1647     dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
1648     mfc_context->pre_deblocking_output.bo = NULL;
1649
1650     dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
1651     mfc_context->uncompressed_picture_source.bo = NULL;
1652
1653     dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
1654     mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
1655
1656     for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
1657         dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
1658         mfc_context->direct_mv_buffers[i].bo = NULL;
1659     }
1660
1661     dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
1662     mfc_context->intra_row_store_scratch_buffer.bo = NULL;
1663
1664     dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
1665     mfc_context->macroblock_status_buffer.bo = NULL;
1666
1667     dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
1668     mfc_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
1669
1670     dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
1671     mfc_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
1672
1673
1674     for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
1675         dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
1676         mfc_context->reference_surfaces[i].bo = NULL;
1677     }
1678
1679     i965_gpe_context_destroy(&mfc_context->gpe_context);
1680
1681     dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo);
1682     mfc_context->mfc_batchbuffer_surface.bo = NULL;
1683
1684     dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo);
1685     mfc_context->aux_batchbuffer_surface.bo = NULL;
1686
1687     if (mfc_context->aux_batchbuffer)
1688         intel_batchbuffer_free(mfc_context->aux_batchbuffer);
1689
1690     mfc_context->aux_batchbuffer = NULL;
1691
1692     free(mfc_context);
1693 }
1694
1695 Bool gen6_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
1696 {
1697     struct gen6_mfc_context *mfc_context = calloc(1, sizeof(struct gen6_mfc_context));
1698
1699     mfc_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6;
1700
1701     mfc_context->gpe_context.idrt.max_entries = MAX_GPE_KERNELS;
1702     mfc_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data);
1703
1704     mfc_context->gpe_context.curbe.length = 32 * 4;
1705
1706     mfc_context->gpe_context.vfe_state.max_num_threads = 60 - 1;
1707     mfc_context->gpe_context.vfe_state.num_urb_entries = 16;
1708     mfc_context->gpe_context.vfe_state.gpgpu_mode = 0;
1709     mfc_context->gpe_context.vfe_state.urb_entry_size = 59 - 1;
1710     mfc_context->gpe_context.vfe_state.curbe_allocation_size = 37 - 1;
1711
1712     i965_gpe_load_kernels(ctx,
1713                           &mfc_context->gpe_context,
1714                           gen6_mfc_kernels,
1715                           NUM_MFC_KERNEL);
1716
1717     mfc_context->pipe_mode_select = gen6_mfc_pipe_mode_select;
1718     mfc_context->set_surface_state = gen6_mfc_surface_state;
1719     mfc_context->ind_obj_base_addr_state = gen6_mfc_ind_obj_base_addr_state;
1720     mfc_context->avc_img_state = gen6_mfc_avc_img_state;
1721     mfc_context->avc_qm_state = gen6_mfc_avc_qm_state;
1722     mfc_context->avc_fqm_state = gen6_mfc_avc_fqm_state;
1723     mfc_context->insert_object = gen6_mfc_avc_insert_object;
1724     mfc_context->buffer_suface_setup = i965_gpe_buffer_suface_setup;
1725
1726     encoder_context->mfc_context = mfc_context;
1727     encoder_context->mfc_context_destroy = gen6_mfc_context_destroy;
1728     encoder_context->mfc_pipeline = gen6_mfc_pipeline;
1729     encoder_context->mfc_brc_prepare = intel_mfc_brc_prepare;
1730
1731     return True;
1732 }