src/gen6_mfc.c

   1 /*
   2  * Copyright © 2010-2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Zhou Chang <chang.zhou@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <assert.h>
  33 #include <math.h>
  34
  35 #include "intel_batchbuffer.h"
  36 #include "i965_defines.h"
  37 #include "i965_structs.h"
  38 #include "i965_drv_video.h"
  39 #include "i965_encoder.h"
  40 #include "i965_encoder_utils.h"
  41 #include "gen6_mfc.h"
  42 #include "gen6_vme.h"
  43 #include "intel_media.h"
  44
  45 static const uint32_t gen6_mfc_batchbuffer_avc_intra[][4] = {
  46 #include "shaders/utils/mfc_batchbuffer_avc_intra.g6b"
  47 };
  48
  49 static const uint32_t gen6_mfc_batchbuffer_avc_inter[][4] = {
  50 #include "shaders/utils/mfc_batchbuffer_avc_inter.g6b"
  51 };
  52
  53 static struct i965_kernel gen6_mfc_kernels[] = {
  54     {
  55         "MFC AVC INTRA BATCHBUFFER ",
  56         MFC_BATCHBUFFER_AVC_INTRA,
  57         gen6_mfc_batchbuffer_avc_intra,
  58         sizeof(gen6_mfc_batchbuffer_avc_intra),
  59         NULL
  60     },
  61
  62     {
  63         "MFC AVC INTER BATCHBUFFER ",
  64         MFC_BATCHBUFFER_AVC_INTER,
  65         gen6_mfc_batchbuffer_avc_inter,
  66         sizeof(gen6_mfc_batchbuffer_avc_inter),
  67         NULL
  68     },
  69 };
  70
  71 static void
  72 gen6_mfc_pipe_mode_select(VADriverContextP ctx,
  73                           int standard_select,
  74                           struct intel_encoder_context *encoder_context)
  75 {
  76     struct intel_batchbuffer *batch = encoder_context->base.batch;
  77     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
  78
  79     assert(standard_select == MFX_FORMAT_AVC);
  80
  81     BEGIN_BCS_BATCH(batch, 4);
  82
  83     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (4 - 2));
  84     OUT_BCS_BATCH(batch,
  85                   (1 << 10) | /* disable Stream-Out , advanced QP/bitrate control need enable it*/
  86                   ((!!mfc_context->post_deblocking_output.bo) << 9)  | /* Post Deblocking Output */
  87                   ((!!mfc_context->pre_deblocking_output.bo) << 8)  | /* Pre Deblocking Output */
  88                   (0 << 7)  | /* disable TLB prefectch */
  89                   (0 << 5)  | /* not in stitch mode */
  90                   (1 << 4)  | /* encoding mode */
  91                   (2 << 0));  /* Standard Select: AVC */
  92     OUT_BCS_BATCH(batch,
  93                   (0 << 20) | /* round flag in PB slice */
  94                   (0 << 19) | /* round flag in Intra8x8 */
  95                   (0 << 7)  | /* expand NOA bus flag */
  96                   (1 << 6)  | /* must be 1 */
  97                   (0 << 5)  | /* disable clock gating for NOA */
  98                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
  99                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
 100                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
 101                   (0 << 1)  | /* AVC long field motion vector */
 102                   (0 << 0));  /* always calculate AVC ILDB boundary strength */
 103     OUT_BCS_BATCH(batch, 0);
 104
 105     ADVANCE_BCS_BATCH(batch);
 106 }
 107
 108 static void
 109 gen6_mfc_surface_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 110 {
 111     struct intel_batchbuffer *batch = encoder_context->base.batch;
 112     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 113
 114     BEGIN_BCS_BATCH(batch, 6);
 115
 116     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
 117     OUT_BCS_BATCH(batch, 0);
 118     OUT_BCS_BATCH(batch,
 119                   ((mfc_context->surface_state.height - 1) << 19) |
 120                   ((mfc_context->surface_state.width - 1) << 6));
 121     OUT_BCS_BATCH(batch,
 122                   (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
 123                   (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
 124                   (0 << 22) | /* surface object control state, FIXME??? */
 125                   ((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */
 126                   (0 << 2)  | /* must be 0 for interleave U/V */
 127                   (1 << 1)  | /* must be y-tiled */
 128                   (I965_TILEWALK_YMAJOR << 0));                         /* tile walk, TILEWALK_YMAJOR */
 129     OUT_BCS_BATCH(batch,
 130                   (0 << 16) |                                                           /* must be 0 for interleave U/V */
 131                   (mfc_context->surface_state.h_pitch));                /* y offset for U(cb) */
 132     OUT_BCS_BATCH(batch, 0);
 133     ADVANCE_BCS_BATCH(batch);
 134 }
 135
 136 void
 137 gen6_mfc_pipe_buf_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 138 {
 139     struct intel_batchbuffer *batch = encoder_context->base.batch;
 140     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 141     int i;
 142
 143     BEGIN_BCS_BATCH(batch, 24);
 144
 145     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
 146
 147     if (mfc_context->pre_deblocking_output.bo)
 148         OUT_BCS_RELOC(batch, mfc_context->pre_deblocking_output.bo,
 149                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 150                       0);
 151     else
 152         OUT_BCS_BATCH(batch, 0);                                                                                        /* pre output addr   */
 153
 154     if (mfc_context->post_deblocking_output.bo)
 155         OUT_BCS_RELOC(batch, mfc_context->post_deblocking_output.bo,
 156                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 157                       0);                                                                                       /* post output addr  */
 158     else
 159         OUT_BCS_BATCH(batch, 0);
 160
 161     OUT_BCS_RELOC(batch, mfc_context->uncompressed_picture_source.bo,
 162                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 163                   0);                                                                                   /* uncompressed data */
 164     OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
 165                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 166                   0);                                                                                   /* StreamOut data*/
 167     OUT_BCS_RELOC(batch, mfc_context->intra_row_store_scratch_buffer.bo,
 168                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 169                   0);
 170     OUT_BCS_RELOC(batch, mfc_context->deblocking_filter_row_store_scratch_buffer.bo,
 171                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 172                   0);
 173     /* 7..22 Reference pictures*/
 174     for (i = 0; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) {
 175         if ( mfc_context->reference_surfaces[i].bo != NULL) {
 176             OUT_BCS_RELOC(batch, mfc_context->reference_surfaces[i].bo,
 177                           I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 178                           0);
 179         } else {
 180             OUT_BCS_BATCH(batch, 0);
 181         }
 182     }
 183     OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
 184                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 185                   0);                                                                                   /* Macroblock status buffer*/
 186
 187     ADVANCE_BCS_BATCH(batch);
 188 }
 189
 190 static void
 191 gen6_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 192 {
 193     struct intel_batchbuffer *batch = encoder_context->base.batch;
 194     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 195     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 196
 197     BEGIN_BCS_BATCH(batch, 11);
 198
 199     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
 200     OUT_BCS_BATCH(batch, 0);
 201     OUT_BCS_BATCH(batch, 0);
 202     /* MFX Indirect MV Object Base Address */
 203     OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 204     OUT_BCS_BATCH(batch, 0);
 205     OUT_BCS_BATCH(batch, 0);
 206     OUT_BCS_BATCH(batch, 0);
 207     OUT_BCS_BATCH(batch, 0);
 208     OUT_BCS_BATCH(batch, 0);
 209     /*MFC Indirect PAK-BSE Object Base Address for Encoder*/
 210     OUT_BCS_RELOC(batch,
 211                   mfc_context->mfc_indirect_pak_bse_object.bo,
 212                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 213                   0);
 214     OUT_BCS_RELOC(batch,
 215                   mfc_context->mfc_indirect_pak_bse_object.bo,
 216                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 217                   mfc_context->mfc_indirect_pak_bse_object.end_offset);
 218
 219     ADVANCE_BCS_BATCH(batch);
 220 }
 221
 222 void
 223 gen6_mfc_bsp_buf_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 224 {
 225     struct intel_batchbuffer *batch = encoder_context->base.batch;
 226     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 227
 228     BEGIN_BCS_BATCH(batch, 4);
 229
 230     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
 231     OUT_BCS_RELOC(batch, mfc_context->bsd_mpc_row_store_scratch_buffer.bo,
 232                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 233                   0);
 234     OUT_BCS_BATCH(batch, 0);
 235     OUT_BCS_BATCH(batch, 0);
 236
 237     ADVANCE_BCS_BATCH(batch);
 238 }
 239
 240 static void
 241 gen6_mfc_avc_img_state(VADriverContextP ctx,struct encode_state *encode_state,
 242                        struct intel_encoder_context *encoder_context)
 243 {
 244     struct intel_batchbuffer *batch = encoder_context->base.batch;
 245     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 246     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 247     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 248     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 249     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 250
 251     BEGIN_BCS_BATCH(batch, 13);
 252     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (13 - 2));
 253     OUT_BCS_BATCH(batch,
 254                   ((width_in_mbs * height_in_mbs) & 0xFFFF));
 255     OUT_BCS_BATCH(batch,
 256                   (height_in_mbs << 16) |
 257                   (width_in_mbs << 0));
 258     OUT_BCS_BATCH(batch,
 259                   (0 << 24) |     /*Second Chroma QP Offset*/
 260                   (0 << 16) |     /*Chroma QP Offset*/
 261                   (0 << 14) |   /*Max-bit conformance Intra flag*/
 262                   (0 << 13) |   /*Max Macroblock size conformance Inter flag*/
 263                   (1 << 12) |   /*Should always be written as "1" */
 264                   (0 << 10) |   /*QM Preset FLag */
 265                   (0 << 8)  |   /*Image Structure*/
 266                   (0 << 0) );   /*Current Decoed Image Frame Store ID, reserved in Encode mode*/
 267     OUT_BCS_BATCH(batch,
 268                   (400 << 16) |   /*Mininum Frame size*/
 269                   (0 << 15) |   /*Disable reading of Macroblock Status Buffer*/
 270                   (0 << 14) |   /*Load BitStream Pointer only once, 1 slic 1 frame*/
 271                   (0 << 13) |   /*CABAC 0 word insertion test enable*/
 272                   (1 << 12) |   /*MVUnpackedEnable,compliant to DXVA*/
 273                   (1 << 10) |   /*Chroma Format IDC, 4:2:0*/
 274                   (pPicParameter->pic_fields.bits.entropy_coding_mode_flag << 7)  |   /*0:CAVLC encoding mode,1:CABAC*/
 275                   (0 << 6)  |   /*Only valid for VLD decoding mode*/
 276                   (0 << 5)  |   /*Constrained Intra Predition Flag, from PPS*/
 277                   (pSequenceParameter->seq_fields.bits.direct_8x8_inference_flag << 4)  |   /*Direct 8x8 inference flag*/
 278                   (pPicParameter->pic_fields.bits.transform_8x8_mode_flag << 3)  |   /*8x8 or 4x4 IDCT Transform Mode Flag*/
 279                   (1 << 2)  |   /*Frame MB only flag*/
 280                   (0 << 1)  |   /*MBAFF mode is in active*/
 281                   (0 << 0) );   /*Field picture flag*/
 282     OUT_BCS_BATCH(batch,
 283                   (1<<16)   |   /*Frame Size Rate Control Flag*/
 284                   (1<<12)   |
 285                   (1<<9)    |   /*MB level Rate Control Enabling Flag*/
 286                   (1 << 3)  |   /*FrameBitRateMinReportMask*/
 287                   (1 << 2)  |   /*FrameBitRateMaxReportMask*/
 288                   (1 << 1)  |   /*InterMBMaxSizeReportMask*/
 289                   (1 << 0) );   /*IntraMBMaxSizeReportMask*/
 290     OUT_BCS_BATCH(batch,                        /*Inter and Intra Conformance Max size limit*/
 291                   (0x0600 << 16) |              /*InterMbMaxSz 192 Byte*/
 292                   (0x0800) );                   /*IntraMbMaxSz 256 Byte*/
 293     OUT_BCS_BATCH(batch, 0x00000000);   /*Reserved : MBZReserved*/
 294     OUT_BCS_BATCH(batch, 0x01020304);   /*Slice QP Delta for bitrate control*/
 295     OUT_BCS_BATCH(batch, 0xFEFDFCFB);
 296     OUT_BCS_BATCH(batch, 0x80601004);   /*MAX = 128KB, MIN = 64KB*/
 297     OUT_BCS_BATCH(batch, 0x00800001);
 298     OUT_BCS_BATCH(batch, 0);
 299
 300     ADVANCE_BCS_BATCH(batch);
 301 }
 302
 303 static void
 304 gen6_mfc_avc_directmode_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 305 {
 306     struct intel_batchbuffer *batch = encoder_context->base.batch;
 307     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 308
 309     int i;
 310
 311     BEGIN_BCS_BATCH(batch, 69);
 312
 313     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
 314
 315     /* Reference frames and Current frames */
 316     for(i = 0; i < NUM_MFC_DMV_BUFFERS; i++) {
 317         if ( mfc_context->direct_mv_buffers[i].bo != NULL) {
 318             OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[i].bo,
 319                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 320                           0);
 321         } else {
 322             OUT_BCS_BATCH(batch, 0);
 323         }
 324     }
 325
 326     /* POL list */
 327     for(i = 0; i < 32; i++) {
 328         OUT_BCS_BATCH(batch, i/2);
 329     }
 330     OUT_BCS_BATCH(batch, 0);
 331     OUT_BCS_BATCH(batch, 0);
 332
 333     ADVANCE_BCS_BATCH(batch);
 334 }
 335
 336 static void
 337 gen6_mfc_avc_slice_state(VADriverContextP ctx,
 338                          VAEncPictureParameterBufferH264 *pic_param,
 339                          VAEncSliceParameterBufferH264 *slice_param,
 340                          struct encode_state *encode_state,
 341                          struct intel_encoder_context *encoder_context,
 342                          int rate_control_enable,
 343                          int qp,
 344                          struct intel_batchbuffer *batch)
 345 {
 346     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 347     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 348     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 349     int beginmb = slice_param->macroblock_address;
 350     int endmb = beginmb + slice_param->num_macroblocks;
 351     int beginx = beginmb % width_in_mbs;
 352     int beginy = beginmb / width_in_mbs;
 353     int nextx =  endmb % width_in_mbs;
 354     int nexty = endmb / width_in_mbs;
 355     int slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
 356     int last_slice = (endmb == (width_in_mbs * height_in_mbs));
 357     int maxQpN, maxQpP;
 358     unsigned char correct[6], grow, shrink;
 359     int i;
 360     int weighted_pred_idc = 0;
 361     unsigned int luma_log2_weight_denom = slice_param->luma_log2_weight_denom;
 362     unsigned int chroma_log2_weight_denom = slice_param->chroma_log2_weight_denom;
 363     int bslice = 0;
 364
 365     if (batch == NULL)
 366         batch = encoder_context->base.batch;
 367
 368     if (slice_type == SLICE_TYPE_P) {
 369         weighted_pred_idc = pic_param->pic_fields.bits.weighted_pred_flag;
 370     } else if (slice_type == SLICE_TYPE_B) {
 371         weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc;
 372         bslice = 1;
 373
 374         if (weighted_pred_idc == 2) {
 375             /* 8.4.3 - Derivation process for prediction weights (8-279) */
 376             luma_log2_weight_denom = 5;
 377             chroma_log2_weight_denom = 5;
 378         }
 379     }
 380
 381     maxQpN = mfc_context->bit_rate_control_context[slice_type].MaxQpNegModifier;
 382     maxQpP = mfc_context->bit_rate_control_context[slice_type].MaxQpPosModifier;
 383
 384     for (i = 0; i < 6; i++)
 385         correct[i] = mfc_context->bit_rate_control_context[slice_type].Correct[i];
 386
 387     grow = mfc_context->bit_rate_control_context[slice_type].GrowInit +
 388         (mfc_context->bit_rate_control_context[slice_type].GrowResistance << 4);
 389     shrink = mfc_context->bit_rate_control_context[slice_type].ShrinkInit +
 390         (mfc_context->bit_rate_control_context[slice_type].ShrinkResistance << 4);
 391
 392     BEGIN_BCS_BATCH(batch, 11);;
 393
 394     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) );
 395     OUT_BCS_BATCH(batch, slice_type);                   /*Slice Type: I:P:B Slice*/
 396
 397     if (slice_type == SLICE_TYPE_I) {
 398         OUT_BCS_BATCH(batch, 0);                        /*no reference frames and pred_weight_table*/
 399     } else {
 400         OUT_BCS_BATCH(batch,
 401                       (1 << 16) | (bslice << 24) |     /*1 reference frame*/
 402                       (chroma_log2_weight_denom << 8) |
 403                       (luma_log2_weight_denom << 0));
 404     }
 405
 406     OUT_BCS_BATCH(batch,
 407                   (weighted_pred_idc << 30) |
 408                   (slice_param->direct_spatial_mv_pred_flag<<29) |             /*Direct Prediction Type*/
 409                   (slice_param->disable_deblocking_filter_idc << 27) |
 410                   (slice_param->cabac_init_idc << 24) |
 411                   (qp<<16) |                    /*Slice Quantization Parameter*/
 412                   ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
 413                   ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
 414     OUT_BCS_BATCH(batch,
 415                   (beginy << 24) |                      /*First MB X&Y , the begin postion of current slice*/
 416                   (beginx << 16) |
 417                   slice_param->macroblock_address );
 418     OUT_BCS_BATCH(batch, (nexty << 16) | nextx);                       /*Next slice first MB X&Y*/
 419     OUT_BCS_BATCH(batch,
 420                   (0/*rate_control_enable*/ << 31) |            /*in CBR mode RateControlCounterEnable = enable*/
 421                   (1 << 30) |           /*ResetRateControlCounter*/
 422                   (0 << 28) |           /*RC Triggle Mode = Always Rate Control*/
 423                   (4 << 24) |     /*RC Stable Tolerance, middle level*/
 424                   (0/*rate_control_enable*/ << 23) |     /*RC Panic Enable*/
 425                   (0 << 22) |     /*QP mode, don't modfiy CBP*/
 426                   (0 << 21) |     /*MB Type Direct Conversion Enabled*/
 427                   (0 << 20) |     /*MB Type Skip Conversion Enabled*/
 428                   (last_slice << 19) |     /*IsLastSlice*/
 429                   (0 << 18) |   /*BitstreamOutputFlag Compressed BitStream Output Disable Flag 0:enable 1:disable*/
 430                   (1 << 17) |       /*HeaderPresentFlag*/
 431                   (1 << 16) |       /*SliceData PresentFlag*/
 432                   (1 << 15) |       /*TailPresentFlag*/
 433                   (1 << 13) |       /*RBSP NAL TYPE*/
 434                   (0 << 12) );    /*CabacZeroWordInsertionEnable*/
 435     OUT_BCS_BATCH(batch, mfc_context->mfc_indirect_pak_bse_object.offset);
 436     OUT_BCS_BATCH(batch,
 437                   (maxQpN << 24) |     /*Target QP - 24 is lowest QP*/
 438                   (maxQpP << 16) |     /*Target QP + 20 is highest QP*/
 439                   (shrink << 8)  |
 440                   (grow << 0));
 441     OUT_BCS_BATCH(batch,
 442                   (correct[5] << 20) |
 443                   (correct[4] << 16) |
 444                   (correct[3] << 12) |
 445                   (correct[2] << 8) |
 446                   (correct[1] << 4) |
 447                   (correct[0] << 0));
 448     OUT_BCS_BATCH(batch, 0);
 449
 450     ADVANCE_BCS_BATCH(batch);
 451 }
 452 static void gen6_mfc_avc_qm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 453 {
 454     struct intel_batchbuffer *batch = encoder_context->base.batch;
 455     int i;
 456
 457     BEGIN_BCS_BATCH(batch, 58);
 458
 459     OUT_BCS_BATCH(batch, MFX_AVC_QM_STATE | 56);
 460     OUT_BCS_BATCH(batch, 0xFF ) ;
 461     for( i = 0; i < 56; i++) {
 462         OUT_BCS_BATCH(batch, 0x10101010);
 463     }
 464
 465     ADVANCE_BCS_BATCH(batch);
 466 }
 467
 468 static void gen6_mfc_avc_fqm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 469 {
 470     struct intel_batchbuffer *batch = encoder_context->base.batch;
 471     int i;
 472
 473     BEGIN_BCS_BATCH(batch, 113);
 474     OUT_BCS_BATCH(batch, MFC_AVC_FQM_STATE | (113 - 2));
 475
 476     for(i = 0; i < 112;i++) {
 477         OUT_BCS_BATCH(batch, 0x10001000);
 478     }
 479
 480     ADVANCE_BCS_BATCH(batch);
 481 }
 482
 483 static void
 484 gen6_mfc_avc_ref_idx_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 485 {
 486     struct intel_batchbuffer *batch = encoder_context->base.batch;
 487     int i;
 488
 489     BEGIN_BCS_BATCH(batch, 10);
 490     OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
 491     OUT_BCS_BATCH(batch, 0);                  //Select L0
 492     OUT_BCS_BATCH(batch, 0x80808020);         //Only 1 reference
 493     for(i = 0; i < 7; i++) {
 494         OUT_BCS_BATCH(batch, 0x80808080);
 495     }
 496     ADVANCE_BCS_BATCH(batch);
 497
 498     BEGIN_BCS_BATCH(batch, 10);
 499     OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
 500     OUT_BCS_BATCH(batch, 1);                  //Select L1
 501     OUT_BCS_BATCH(batch, 0x80808022);         //Only 1 reference
 502     for(i = 0; i < 7; i++) {
 503         OUT_BCS_BATCH(batch, 0x80808080);
 504     }
 505     ADVANCE_BCS_BATCH(batch);
 506 }
 507
 508 static void
 509 gen6_mfc_avc_insert_object(VADriverContextP ctx, struct intel_encoder_context *encoder_context,
 510                            unsigned int *insert_data, int lenght_in_dws, int data_bits_in_last_dw,
 511                            int skip_emul_byte_count, int is_last_header, int is_end_of_slice, int emulation_flag,
 512                            struct intel_batchbuffer *batch)
 513 {
 514     if (batch == NULL)
 515         batch = encoder_context->base.batch;
 516
 517     BEGIN_BCS_BATCH(batch, lenght_in_dws + 2);
 518
 519     OUT_BCS_BATCH(batch, MFC_AVC_INSERT_OBJECT | (lenght_in_dws + 2 - 2));
 520
 521     OUT_BCS_BATCH(batch,
 522                   (0 << 16) |   /* always start at offset 0 */
 523                   (data_bits_in_last_dw << 8) |
 524                   (skip_emul_byte_count << 4) |
 525                   (!!emulation_flag << 3) |
 526                   ((!!is_last_header) << 2) |
 527                   ((!!is_end_of_slice) << 1) |
 528                   (0 << 0));    /* FIXME: ??? */
 529
 530     intel_batchbuffer_data(batch, insert_data, lenght_in_dws * 4);
 531     ADVANCE_BCS_BATCH(batch);
 532 }
 533
 534 void
 535 gen6_mfc_init(VADriverContextP ctx,
 536               struct encode_state *encode_state,
 537               struct intel_encoder_context *encoder_context)
 538 {
 539     struct i965_driver_data *i965 = i965_driver_data(ctx);
 540     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 541     dri_bo *bo;
 542     int i;
 543     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 544     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 545     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 546
 547     /*Encode common setup for MFC*/
 548     dri_bo_unreference(mfc_context->post_deblocking_output.bo);
 549     mfc_context->post_deblocking_output.bo = NULL;
 550
 551     dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
 552     mfc_context->pre_deblocking_output.bo = NULL;
 553
 554     dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
 555     mfc_context->uncompressed_picture_source.bo = NULL;
 556
 557     dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
 558     mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
 559
 560     for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
 561         if ( mfc_context->direct_mv_buffers[i].bo != NULL);
 562         dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
 563         mfc_context->direct_mv_buffers[i].bo = NULL;
 564     }
 565
 566     for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
 567         if (mfc_context->reference_surfaces[i].bo != NULL)
 568             dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
 569         mfc_context->reference_surfaces[i].bo = NULL;
 570     }
 571
 572     dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
 573     bo = dri_bo_alloc(i965->intel.bufmgr,
 574                       "Buffer",
 575                       width_in_mbs * 64,
 576                       64);
 577     assert(bo);
 578     mfc_context->intra_row_store_scratch_buffer.bo = bo;
 579
 580     dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
 581     bo = dri_bo_alloc(i965->intel.bufmgr,
 582                       "Buffer",
 583                       width_in_mbs * height_in_mbs * 16,
 584                       64);
 585     assert(bo);
 586     mfc_context->macroblock_status_buffer.bo = bo;
 587
 588     dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
 589     bo = dri_bo_alloc(i965->intel.bufmgr,
 590                       "Buffer",
 591                       4 * width_in_mbs * 64,  /* 4 * width_in_mbs * 64 */
 592                       64);
 593     assert(bo);
 594     mfc_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
 595
 596     dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
 597     bo = dri_bo_alloc(i965->intel.bufmgr,
 598                       "Buffer",
 599                       128 * width_in_mbs, /* 2 * widht_in_mbs * 64 */
 600                       0x1000);
 601     assert(bo);
 602     mfc_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
 603
 604     dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo);
 605     mfc_context->mfc_batchbuffer_surface.bo = NULL;
 606
 607     dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo);
 608     mfc_context->aux_batchbuffer_surface.bo = NULL;
 609
 610     if (mfc_context->aux_batchbuffer)
 611         intel_batchbuffer_free(mfc_context->aux_batchbuffer);
 612
 613     mfc_context->aux_batchbuffer = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD, 0);
 614     mfc_context->aux_batchbuffer_surface.bo = mfc_context->aux_batchbuffer->buffer;
 615     dri_bo_reference(mfc_context->aux_batchbuffer_surface.bo);
 616     mfc_context->aux_batchbuffer_surface.pitch = 16;
 617     mfc_context->aux_batchbuffer_surface.num_blocks = mfc_context->aux_batchbuffer->size / 16;
 618     mfc_context->aux_batchbuffer_surface.size_block = 16;
 619
 620     i965_gpe_context_init(ctx, &mfc_context->gpe_context);
 621 }
 622
 623 static void gen6_mfc_avc_pipeline_picture_programing( VADriverContextP ctx,
 624                                       struct encode_state *encode_state,
 625                                       struct intel_encoder_context *encoder_context)
 626 {
 627     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 628
 629     mfc_context->pipe_mode_select(ctx, MFX_FORMAT_AVC, encoder_context);
 630     mfc_context->set_surface_state(ctx, encoder_context);
 631     mfc_context->ind_obj_base_addr_state(ctx, encoder_context);
 632     gen6_mfc_pipe_buf_addr_state(ctx, encoder_context);
 633     gen6_mfc_bsp_buf_base_addr_state(ctx, encoder_context);
 634     mfc_context->avc_img_state(ctx, encode_state, encoder_context);
 635     mfc_context->avc_qm_state(ctx, encoder_context);
 636     mfc_context->avc_fqm_state(ctx, encoder_context);
 637     gen6_mfc_avc_directmode_state(ctx, encoder_context);
 638     gen6_mfc_avc_ref_idx_state(ctx, encoder_context);
 639 }
 640
 641
 642 VAStatus
 643 gen6_mfc_run(VADriverContextP ctx,
 644              struct encode_state *encode_state,
 645              struct intel_encoder_context *encoder_context)
 646 {
 647     struct intel_batchbuffer *batch = encoder_context->base.batch;
 648
 649     intel_batchbuffer_flush(batch);             //run the pipeline
 650
 651     return VA_STATUS_SUCCESS;
 652 }
 653
 654 VAStatus
 655 gen6_mfc_stop(VADriverContextP ctx,
 656               struct encode_state *encode_state,
 657               struct intel_encoder_context *encoder_context,
 658               int *encoded_bits_size)
 659 {
 660     VAStatus vaStatus = VA_STATUS_ERROR_UNKNOWN;
 661     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 662     VACodedBufferSegment *coded_buffer_segment;
 663
 664     vaStatus = i965_MapBuffer(ctx, pPicParameter->coded_buf, (void **)&coded_buffer_segment);
 665     assert(vaStatus == VA_STATUS_SUCCESS);
 666     *encoded_bits_size = coded_buffer_segment->size * 8;
 667     i965_UnmapBuffer(ctx, pPicParameter->coded_buf);
 668
 669     return VA_STATUS_SUCCESS;
 670 }
 671
 672 #if __SOFTWARE__
 673
 674 static int
 675 gen6_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb, int qp,unsigned int *msg,
 676                               struct intel_encoder_context *encoder_context,
 677                               unsigned char target_mb_size, unsigned char max_mb_size,
 678                               struct intel_batchbuffer *batch)
 679 {
 680     int len_in_dwords = 11;
 681
 682     if (batch == NULL)
 683         batch = encoder_context->base.batch;
 684
 685     BEGIN_BCS_BATCH(batch, len_in_dwords);
 686
 687     OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
 688     OUT_BCS_BATCH(batch, 0);
 689     OUT_BCS_BATCH(batch, 0);
 690     OUT_BCS_BATCH(batch,
 691                   (0 << 24) |           /* PackedMvNum, Debug*/
 692                   (0 << 20) |           /* No motion vector */
 693                   (1 << 19) |           /* CbpDcY */
 694                   (1 << 18) |           /* CbpDcU */
 695                   (1 << 17) |           /* CbpDcV */
 696                   (msg[0] & 0xFFFF) );
 697
 698     OUT_BCS_BATCH(batch, (0xFFFF << 16) | (y << 8) | x);                /* Code Block Pattern for Y*/
 699     OUT_BCS_BATCH(batch, 0x000F000F);                                                   /* Code Block Pattern */
 700     OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp);      /* Last MB */
 701
 702     /*Stuff for Intra MB*/
 703     OUT_BCS_BATCH(batch, msg[1]);                       /* We using Intra16x16 no 4x4 predmode*/
 704     OUT_BCS_BATCH(batch, msg[2]);
 705     OUT_BCS_BATCH(batch, msg[3]&0xFC);
 706
 707     /*MaxSizeInWord and TargetSzieInWord*/
 708     OUT_BCS_BATCH(batch, (max_mb_size << 24) |
 709                   (target_mb_size << 16) );
 710
 711     ADVANCE_BCS_BATCH(batch);
 712
 713     return len_in_dwords;
 714 }
 715
 716 static int
 717 gen6_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, int qp,
 718                               unsigned int *msg, unsigned int offset,
 719                               struct intel_encoder_context *encoder_context,
 720                               unsigned char target_mb_size,unsigned char max_mb_size, int slice_type,
 721                               struct intel_batchbuffer *batch)
 722 {
 723     int len_in_dwords = 11;
 724
 725     if (batch == NULL)
 726         batch = encoder_context->base.batch;
 727
 728     BEGIN_BCS_BATCH(batch, len_in_dwords);
 729
 730     OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
 731
 732     OUT_BCS_BATCH(batch, msg[2]);         /* 32 MV*/
 733     OUT_BCS_BATCH(batch, offset);
 734
 735     OUT_BCS_BATCH(batch, msg[0]);
 736
 737     OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x);        /* Code Block Pattern for Y*/
 738     OUT_BCS_BATCH(batch, 0x000F000F);                         /* Code Block Pattern */
 739 #if 0
 740     if ( slice_type == SLICE_TYPE_B) {
 741         OUT_BCS_BATCH(batch, (0xF<<28) | (end_mb << 26) | qp);  /* Last MB */
 742     } else {
 743         OUT_BCS_BATCH(batch, (end_mb << 26) | qp);      /* Last MB */
 744     }
 745 #else
 746     OUT_BCS_BATCH(batch, (end_mb << 26) | qp);  /* Last MB */
 747 #endif
 748
 749
 750     /*Stuff for Inter MB*/
 751     OUT_BCS_BATCH(batch, msg[1]);
 752     OUT_BCS_BATCH(batch, 0x0);
 753     OUT_BCS_BATCH(batch, 0x0);
 754
 755     /*MaxSizeInWord and TargetSzieInWord*/
 756     OUT_BCS_BATCH(batch, (max_mb_size << 24) |
 757                   (target_mb_size << 16) );
 758
 759     ADVANCE_BCS_BATCH(batch);
 760
 761     return len_in_dwords;
 762 }
 763
 764 static void
 765 gen6_mfc_avc_pipeline_slice_programing(VADriverContextP ctx,
 766                                        struct encode_state *encode_state,
 767                                        struct intel_encoder_context *encoder_context,
 768                                        int slice_index,
 769                                        struct intel_batchbuffer *slice_batch)
 770 {
 771     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 772     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 773     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 774     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 775     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
 776     unsigned int *msg = NULL, offset = 0;
 777     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 778     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 779     int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs);
 780     int i,x,y;
 781     int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta;
 782     unsigned int rate_control_mode = encoder_context->rate_control_mode;
 783     unsigned char *slice_header = NULL;
 784     int slice_header_length_in_bits = 0;
 785     unsigned int tail_data[] = { 0x0, 0x0 };
 786     int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type);
 787     int is_intra = slice_type == SLICE_TYPE_I;
 788
 789     if (rate_control_mode == VA_RC_CBR) {
 790         qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
 791         pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp;
 792     }
 793
 794     /* only support for 8-bit pixel bit-depth */
 795     assert(pSequenceParameter->bit_depth_luma_minus8 == 0);
 796     assert(pSequenceParameter->bit_depth_chroma_minus8 == 0);
 797     assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52);
 798     assert(qp >= 0 && qp < 52);
 799
 800     gen6_mfc_avc_slice_state(ctx,
 801                              pPicParameter,
 802                              pSliceParameter,
 803                              encode_state, encoder_context,
 804                              (rate_control_mode == VA_RC_CBR), qp, slice_batch);
 805
 806     if ( slice_index == 0)
 807         intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch);
 808
 809     slice_header_length_in_bits = build_avc_slice_header(pSequenceParameter, pPicParameter, pSliceParameter, &slice_header);
 810
 811     // slice hander
 812     mfc_context->insert_object(ctx, encoder_context,
 813                                (unsigned int *)slice_header, ALIGN(slice_header_length_in_bits, 32) >> 5, slice_header_length_in_bits & 0x1f,
 814                                5,  /* first 5 bytes are start code + nal unit type */
 815                                1, 0, 1, slice_batch);
 816
 817     dri_bo_map(vme_context->vme_output.bo , 1);
 818     msg = (unsigned int *)vme_context->vme_output.bo->virtual;
 819
 820     if (is_intra) {
 821         msg += pSliceParameter->macroblock_address * INTRA_VME_OUTPUT_IN_DWS;
 822     } else {
 823         msg += pSliceParameter->macroblock_address * INTER_VME_OUTPUT_IN_DWS;
 824         msg += 32; /* the first 32 DWs are MVs */
 825         offset = pSliceParameter->macroblock_address * INTER_VME_OUTPUT_IN_BYTES;
 826     }
 827
 828     for (i = pSliceParameter->macroblock_address;
 829          i < pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks; i++) {
 830         int last_mb = (i == (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks - 1) );
 831         x = i % width_in_mbs;
 832         y = i / width_in_mbs;
 833
 834         if (is_intra) {
 835             assert(msg);
 836             gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch);
 837             msg += INTRA_VME_OUTPUT_IN_DWS;
 838         } else {
 839             if (msg[0] & INTRA_MB_FLAG_MASK) {
 840                 gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch);
 841             } else {
 842                 gen6_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, msg, offset, encoder_context, 0, 0, slice_type, slice_batch);
 843             }
 844
 845             msg += INTER_VME_OUTPUT_IN_DWS;
 846             offset += INTER_VME_OUTPUT_IN_BYTES;
 847         }
 848     }
 849
 850     dri_bo_unmap(vme_context->vme_output.bo);
 851
 852     if ( last_slice ) {
 853         mfc_context->insert_object(ctx, encoder_context,
 854                                    tail_data, 2, 8,
 855                                    2, 1, 1, 0, slice_batch);
 856     } else {
 857         mfc_context->insert_object(ctx, encoder_context,
 858                                    tail_data, 1, 8,
 859                                    1, 1, 1, 0, slice_batch);
 860     }
 861
 862     free(slice_header);
 863
 864 }
 865
 866 static dri_bo *
 867 gen6_mfc_avc_software_batchbuffer(VADriverContextP ctx,
 868                                   struct encode_state *encode_state,
 869                                   struct intel_encoder_context *encoder_context)
 870 {
 871     struct i965_driver_data *i965 = i965_driver_data(ctx);
 872     struct intel_batchbuffer *batch = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD, 0);
 873     dri_bo *batch_bo = batch->buffer;
 874     int i;
 875
 876     for (i = 0; i < encode_state->num_slice_params_ext; i++) {
 877         gen6_mfc_avc_pipeline_slice_programing(ctx, encode_state, encoder_context, i, batch);
 878     }
 879
 880     intel_batchbuffer_align(batch, 8);
 881
 882     BEGIN_BCS_BATCH(batch, 2);
 883     OUT_BCS_BATCH(batch, 0);
 884     OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_END);
 885     ADVANCE_BCS_BATCH(batch);
 886
 887     dri_bo_reference(batch_bo);
 888     intel_batchbuffer_free(batch);
 889
 890     return batch_bo;
 891 }
 892
 893 #else
 894
 895 static void
 896 gen6_mfc_batchbuffer_surfaces_input(VADriverContextP ctx,
 897                                     struct encode_state *encode_state,
 898                                     struct intel_encoder_context *encoder_context)
 899
 900 {
 901     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 902     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 903
 904     assert(vme_context->vme_output.bo);
 905     mfc_context->buffer_suface_setup(ctx,
 906                                      &mfc_context->gpe_context,
 907                                      &vme_context->vme_output,
 908                                      BINDING_TABLE_OFFSET(BIND_IDX_VME_OUTPUT),
 909                                      SURFACE_STATE_OFFSET(BIND_IDX_VME_OUTPUT));
 910     assert(mfc_context->aux_batchbuffer_surface.bo);
 911     mfc_context->buffer_suface_setup(ctx,
 912                                      &mfc_context->gpe_context,
 913                                      &mfc_context->aux_batchbuffer_surface,
 914                                      BINDING_TABLE_OFFSET(BIND_IDX_MFC_SLICE_HEADER),
 915                                      SURFACE_STATE_OFFSET(BIND_IDX_MFC_SLICE_HEADER));
 916 }
 917
 918 static void
 919 gen6_mfc_batchbuffer_surfaces_output(VADriverContextP ctx,
 920                                      struct encode_state *encode_state,
 921                                      struct intel_encoder_context *encoder_context)
 922
 923 {
 924     struct i965_driver_data *i965 = i965_driver_data(ctx);
 925     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 926     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 927     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 928     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 929     mfc_context->mfc_batchbuffer_surface.num_blocks = width_in_mbs * height_in_mbs + encode_state->num_slice_params_ext * 8 + 1;
 930     mfc_context->mfc_batchbuffer_surface.size_block = 16 * CMD_LEN_IN_OWORD; /* 3 OWORDs */
 931     mfc_context->mfc_batchbuffer_surface.pitch = 16;
 932     mfc_context->mfc_batchbuffer_surface.bo = dri_bo_alloc(i965->intel.bufmgr,
 933                                                            "MFC batchbuffer",
 934                                                            mfc_context->mfc_batchbuffer_surface.num_blocks * mfc_context->mfc_batchbuffer_surface.size_block,
 935                                                            0x1000);
 936     mfc_context->buffer_suface_setup(ctx,
 937                                      &mfc_context->gpe_context,
 938                                      &mfc_context->mfc_batchbuffer_surface,
 939                                      BINDING_TABLE_OFFSET(BIND_IDX_MFC_BATCHBUFFER),
 940                                      SURFACE_STATE_OFFSET(BIND_IDX_MFC_BATCHBUFFER));
 941 }
 942
 943 static void
 944 gen6_mfc_batchbuffer_surfaces_setup(VADriverContextP ctx,
 945                                     struct encode_state *encode_state,
 946                                     struct intel_encoder_context *encoder_context)
 947 {
 948     gen6_mfc_batchbuffer_surfaces_input(ctx, encode_state, encoder_context);
 949     gen6_mfc_batchbuffer_surfaces_output(ctx, encode_state, encoder_context);
 950 }
 951
 952 static void
 953 gen6_mfc_batchbuffer_idrt_setup(VADriverContextP ctx,
 954                                 struct encode_state *encode_state,
 955                                 struct intel_encoder_context *encoder_context)
 956 {
 957     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 958     struct gen6_interface_descriptor_data *desc;
 959     int i;
 960     dri_bo *bo;
 961
 962     bo = mfc_context->gpe_context.idrt.bo;
 963     dri_bo_map(bo, 1);
 964     assert(bo->virtual);
 965     desc = bo->virtual;
 966
 967     for (i = 0; i < mfc_context->gpe_context.num_kernels; i++) {
 968         struct i965_kernel *kernel;
 969
 970         kernel = &mfc_context->gpe_context.kernels[i];
 971         assert(sizeof(*desc) == 32);
 972
 973         /*Setup the descritor table*/
 974         memset(desc, 0, sizeof(*desc));
 975         desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6);
 976         desc->desc2.sampler_count = 0;
 977         desc->desc2.sampler_state_pointer = 0;
 978         desc->desc3.binding_table_entry_count = 2;
 979         desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5);
 980         desc->desc4.constant_urb_entry_read_offset = 0;
 981         desc->desc4.constant_urb_entry_read_length = 4;
 982
 983         /*kernel start*/
 984         dri_bo_emit_reloc(bo,
 985                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 986                           0,
 987                           i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0),
 988                           kernel->bo);
 989         desc++;
 990     }
 991
 992     dri_bo_unmap(bo);
 993 }
 994
 995 static void
 996 gen6_mfc_batchbuffer_constant_setup(VADriverContextP ctx,
 997                                     struct encode_state *encode_state,
 998                                     struct intel_encoder_context *encoder_context)
 999 {
1000     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1001
1002     (void)mfc_context;
1003 }
1004
1005 static void
1006 gen6_mfc_batchbuffer_emit_object_command(struct intel_batchbuffer *batch,
1007                                          int index,
1008                                          int head_offset,
1009                                          int batchbuffer_offset,
1010                                          int head_size,
1011                                          int tail_size,
1012                                          int number_mb_cmds,
1013                                          int first_object,
1014                                          int last_object,
1015                                          int last_slice,
1016                                          int mb_x,
1017                                          int mb_y,
1018                                          int width_in_mbs,
1019                                          int qp)
1020 {
1021     BEGIN_BATCH(batch, 12);
1022
1023     OUT_BATCH(batch, CMD_MEDIA_OBJECT | (12 - 2));
1024     OUT_BATCH(batch, index);
1025     OUT_BATCH(batch, 0);
1026     OUT_BATCH(batch, 0);
1027     OUT_BATCH(batch, 0);
1028     OUT_BATCH(batch, 0);
1029
1030     /*inline data */
1031     OUT_BATCH(batch, head_offset);
1032     OUT_BATCH(batch, batchbuffer_offset);
1033     OUT_BATCH(batch,
1034               head_size << 16 |
1035               tail_size);
1036     OUT_BATCH(batch,
1037               number_mb_cmds << 16 |
1038               first_object << 2 |
1039               last_object << 1 |
1040               last_slice);
1041     OUT_BATCH(batch,
1042               mb_y << 8 |
1043               mb_x);
1044     OUT_BATCH(batch,
1045               qp << 16 |
1046               width_in_mbs);
1047
1048     ADVANCE_BATCH(batch);
1049 }
1050
1051 static void
1052 gen6_mfc_avc_batchbuffer_slice_command(VADriverContextP ctx,
1053                                        struct intel_encoder_context *encoder_context,
1054                                        VAEncSliceParameterBufferH264 *slice_param,
1055                                        int head_offset,
1056                                        unsigned short head_size,
1057                                        unsigned short tail_size,
1058                                        int batchbuffer_offset,
1059                                        int qp,
1060                                        int last_slice)
1061 {
1062     struct intel_batchbuffer *batch = encoder_context->base.batch;
1063     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1064     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
1065     int total_mbs = slice_param->num_macroblocks;
1066     int number_mb_cmds = 128;
1067     int starting_mb = 0;
1068     int last_object = 0;
1069     int first_object = 1;
1070     int i;
1071     int mb_x, mb_y;
1072     int index = (slice_param->slice_type == SLICE_TYPE_I) ? MFC_BATCHBUFFER_AVC_INTRA : MFC_BATCHBUFFER_AVC_INTER;
1073
1074     for (i = 0; i < total_mbs / number_mb_cmds; i++) {
1075         last_object = (total_mbs - starting_mb) == number_mb_cmds;
1076         mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs;
1077         mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs;
1078         assert(mb_x <= 255 && mb_y <= 255);
1079
1080         starting_mb += number_mb_cmds;
1081
1082         gen6_mfc_batchbuffer_emit_object_command(batch,
1083                                                  index,
1084                                                  head_offset,
1085                                                  batchbuffer_offset,
1086                                                  head_size,
1087                                                  tail_size,
1088                                                  number_mb_cmds,
1089                                                  first_object,
1090                                                  last_object,
1091                                                  last_slice,
1092                                                  mb_x,
1093                                                  mb_y,
1094                                                  width_in_mbs,
1095                                                  qp);
1096
1097         if (first_object) {
1098             head_offset += head_size;
1099             batchbuffer_offset += head_size;
1100         }
1101
1102         if (last_object) {
1103             head_offset += tail_size;
1104             batchbuffer_offset += tail_size;
1105         }
1106
1107         batchbuffer_offset += number_mb_cmds * CMD_LEN_IN_OWORD;
1108
1109         first_object = 0;
1110     }
1111
1112     if (!last_object) {
1113         last_object = 1;
1114         number_mb_cmds = total_mbs % number_mb_cmds;
1115         mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs;
1116         mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs;
1117         assert(mb_x <= 255 && mb_y <= 255);
1118         starting_mb += number_mb_cmds;
1119
1120         gen6_mfc_batchbuffer_emit_object_command(batch,
1121                                                  index,
1122                                                  head_offset,
1123                                                  batchbuffer_offset,
1124                                                  head_size,
1125                                                  tail_size,
1126                                                  number_mb_cmds,
1127                                                  first_object,
1128                                                  last_object,
1129                                                  last_slice,
1130                                                  mb_x,
1131                                                  mb_y,
1132                                                  width_in_mbs,
1133                                                  qp);
1134     }
1135 }
1136
1137 /*
1138  * return size in Owords (16bytes)
1139  */
1140 static int
1141 gen6_mfc_avc_batchbuffer_slice(VADriverContextP ctx,
1142                                struct encode_state *encode_state,
1143                                struct intel_encoder_context *encoder_context,
1144                                int slice_index,
1145                                int batchbuffer_offset)
1146 {
1147     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1148     struct intel_batchbuffer *slice_batch = mfc_context->aux_batchbuffer;
1149     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
1150     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
1151     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
1152     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
1153     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
1154     int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs);
1155     int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta;
1156     unsigned int rate_control_mode = encoder_context->rate_control_mode;
1157     unsigned char *slice_header = NULL;
1158     int slice_header_length_in_bits = 0;
1159     unsigned int tail_data[] = { 0x0, 0x0 };
1160     long head_offset;
1161     int old_used = intel_batchbuffer_used_size(slice_batch), used;
1162     unsigned short head_size, tail_size;
1163     int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type);
1164
1165     if (rate_control_mode == VA_RC_CBR) {
1166         qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
1167         pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp;
1168     }
1169
1170     /* only support for 8-bit pixel bit-depth */
1171     assert(pSequenceParameter->bit_depth_luma_minus8 == 0);
1172     assert(pSequenceParameter->bit_depth_chroma_minus8 == 0);
1173     assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52);
1174     assert(qp >= 0 && qp < 52);
1175
1176     head_offset = old_used / 16;
1177     gen6_mfc_avc_slice_state(ctx,
1178                              pPicParameter,
1179                              pSliceParameter,
1180                              encode_state,
1181                              encoder_context,
1182                              (rate_control_mode == VA_RC_CBR),
1183                              qp,
1184                              slice_batch);
1185
1186     if (slice_index == 0)
1187         intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch);
1188
1189     slice_header_length_in_bits = build_avc_slice_header(pSequenceParameter, pPicParameter, pSliceParameter, &slice_header);
1190
1191     // slice hander
1192     mfc_context->insert_object(ctx,
1193                                encoder_context,
1194                                (unsigned int *)slice_header,
1195                                ALIGN(slice_header_length_in_bits, 32) >> 5,
1196                                slice_header_length_in_bits & 0x1f,
1197                                5,  /* first 5 bytes are start code + nal unit type */
1198                                1,
1199                                0,
1200                                1,
1201                                slice_batch);
1202     free(slice_header);
1203
1204     intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */
1205     used = intel_batchbuffer_used_size(slice_batch);
1206     head_size = (used - old_used) / 16;
1207     old_used = used;
1208
1209     /* tail */
1210     if (last_slice) {
1211         mfc_context->insert_object(ctx,
1212                                    encoder_context,
1213                                    tail_data,
1214                                    2,
1215                                    8,
1216                                    2,
1217                                    1,
1218                                    1,
1219                                    0,
1220                                    slice_batch);
1221     } else {
1222         mfc_context->insert_object(ctx,
1223                                    encoder_context,
1224                                    tail_data,
1225                                    1,
1226                                    8,
1227                                    1,
1228                                    1,
1229                                    1,
1230                                    0,
1231                                    slice_batch);
1232     }
1233
1234     intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */
1235     used = intel_batchbuffer_used_size(slice_batch);
1236     tail_size = (used - old_used) / 16;
1237
1238
1239     gen6_mfc_avc_batchbuffer_slice_command(ctx,
1240                                            encoder_context,
1241                                            pSliceParameter,
1242                                            head_offset,
1243                                            head_size,
1244                                            tail_size,
1245                                            batchbuffer_offset,
1246                                            qp,
1247                                            last_slice);
1248
1249     return head_size + tail_size + pSliceParameter->num_macroblocks * CMD_LEN_IN_OWORD;
1250 }
1251
1252 static void
1253 gen6_mfc_avc_batchbuffer_pipeline(VADriverContextP ctx,
1254                                   struct encode_state *encode_state,
1255                                   struct intel_encoder_context *encoder_context)
1256 {
1257     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1258     struct intel_batchbuffer *batch = encoder_context->base.batch;
1259     int i, size, offset = 0;
1260     intel_batchbuffer_start_atomic(batch, 0x4000);
1261     gen6_gpe_pipeline_setup(ctx, &mfc_context->gpe_context, batch);
1262
1263     for ( i = 0; i < encode_state->num_slice_params_ext; i++) {
1264         size = gen6_mfc_avc_batchbuffer_slice(ctx, encode_state, encoder_context, i, offset);
1265         offset += size;
1266     }
1267
1268     intel_batchbuffer_end_atomic(batch);
1269     intel_batchbuffer_flush(batch);
1270 }
1271
1272 static void
1273 gen6_mfc_build_avc_batchbuffer(VADriverContextP ctx,
1274                                struct encode_state *encode_state,
1275                                struct intel_encoder_context *encoder_context)
1276 {
1277     gen6_mfc_batchbuffer_surfaces_setup(ctx, encode_state, encoder_context);
1278     gen6_mfc_batchbuffer_idrt_setup(ctx, encode_state, encoder_context);
1279     gen6_mfc_batchbuffer_constant_setup(ctx, encode_state, encoder_context);
1280     gen6_mfc_avc_batchbuffer_pipeline(ctx, encode_state, encoder_context);
1281 }
1282
1283 static dri_bo *
1284 gen6_mfc_avc_hardware_batchbuffer(VADriverContextP ctx,
1285                                   struct encode_state *encode_state,
1286                                   struct intel_encoder_context *encoder_context)
1287 {
1288     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1289
1290     gen6_mfc_build_avc_batchbuffer(ctx, encode_state, encoder_context);
1291     dri_bo_reference(mfc_context->mfc_batchbuffer_surface.bo);
1292
1293     return mfc_context->mfc_batchbuffer_surface.bo;
1294 }
1295
1296 #endif
1297
1298
1299 static void
1300 gen6_mfc_avc_pipeline_programing(VADriverContextP ctx,
1301                                  struct encode_state *encode_state,
1302                                  struct intel_encoder_context *encoder_context)
1303 {
1304     struct intel_batchbuffer *batch = encoder_context->base.batch;
1305     dri_bo *slice_batch_bo;
1306
1307     if ( intel_mfc_interlace_check(ctx, encode_state, encoder_context) ) {
1308         fprintf(stderr, "Current VA driver don't support interlace mode!\n");
1309         assert(0);
1310         return;
1311     }
1312
1313 #if __SOFTWARE__
1314     slice_batch_bo = gen6_mfc_avc_software_batchbuffer(ctx, encode_state, encoder_context);
1315 #else
1316     slice_batch_bo = gen6_mfc_avc_hardware_batchbuffer(ctx, encode_state, encoder_context);
1317 #endif
1318
1319     // begin programing
1320     intel_batchbuffer_start_atomic_bcs(batch, 0x4000);
1321     intel_batchbuffer_emit_mi_flush(batch);
1322
1323     // picture level programing
1324     gen6_mfc_avc_pipeline_picture_programing(ctx, encode_state, encoder_context);
1325
1326     BEGIN_BCS_BATCH(batch, 2);
1327     OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8));
1328     OUT_BCS_RELOC(batch,
1329                   slice_batch_bo,
1330                   I915_GEM_DOMAIN_COMMAND, 0,
1331                   0);
1332     ADVANCE_BCS_BATCH(batch);
1333
1334     // end programing
1335     intel_batchbuffer_end_atomic(batch);
1336
1337     dri_bo_unreference(slice_batch_bo);
1338 }
1339
1340 VAStatus
1341 gen6_mfc_avc_encode_picture(VADriverContextP ctx,
1342                             struct encode_state *encode_state,
1343                             struct intel_encoder_context *encoder_context)
1344 {
1345     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1346     unsigned int rate_control_mode = encoder_context->rate_control_mode;
1347     int current_frame_bits_size;
1348     int sts;
1349
1350     for (;;) {
1351         gen6_mfc_init(ctx, encode_state, encoder_context);
1352         intel_mfc_avc_prepare(ctx, encode_state, encoder_context);
1353         /*Programing bcs pipeline*/
1354         gen6_mfc_avc_pipeline_programing(ctx, encode_state, encoder_context);   //filling the pipeline
1355         gen6_mfc_run(ctx, encode_state, encoder_context);
1356         if (rate_control_mode == VA_RC_CBR /*|| rate_control_mode == VA_RC_VBR*/) {
1357             gen6_mfc_stop(ctx, encode_state, encoder_context, &current_frame_bits_size);
1358             sts = intel_mfc_brc_postpack(encode_state, mfc_context, current_frame_bits_size);
1359             if (sts == BRC_NO_HRD_VIOLATION) {
1360                 intel_mfc_hrd_context_update(encode_state, mfc_context);
1361                 break;
1362             }
1363             else if (sts == BRC_OVERFLOW_WITH_MIN_QP || sts == BRC_UNDERFLOW_WITH_MAX_QP) {
1364                 if (!mfc_context->hrd.violation_noted) {
1365                     fprintf(stderr, "Unrepairable %s!\n", (sts == BRC_OVERFLOW_WITH_MIN_QP)? "overflow": "underflow");
1366                     mfc_context->hrd.violation_noted = 1;
1367                 }
1368                 return VA_STATUS_SUCCESS;
1369             }
1370         } else {
1371             break;
1372         }
1373     }
1374
1375     return VA_STATUS_SUCCESS;
1376 }
1377
1378 VAStatus
1379 gen6_mfc_pipeline(VADriverContextP ctx,
1380                   VAProfile profile,
1381                   struct encode_state *encode_state,
1382                   struct intel_encoder_context *encoder_context)
1383 {
1384     VAStatus vaStatus;
1385
1386     switch (profile) {
1387     case VAProfileH264Baseline:
1388     case VAProfileH264Main:
1389     case VAProfileH264High:
1390         vaStatus = gen6_mfc_avc_encode_picture(ctx, encode_state, encoder_context);
1391         break;
1392
1393         /* FIXME: add for other profile */
1394     default:
1395         vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
1396         break;
1397     }
1398
1399     return vaStatus;
1400 }
1401
1402 void
1403 gen6_mfc_context_destroy(void *context)
1404 {
1405     struct gen6_mfc_context *mfc_context = context;
1406     int i;
1407
1408     dri_bo_unreference(mfc_context->post_deblocking_output.bo);
1409     mfc_context->post_deblocking_output.bo = NULL;
1410
1411     dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
1412     mfc_context->pre_deblocking_output.bo = NULL;
1413
1414     dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
1415     mfc_context->uncompressed_picture_source.bo = NULL;
1416
1417     dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
1418     mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
1419
1420     for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
1421         dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
1422         mfc_context->direct_mv_buffers[i].bo = NULL;
1423     }
1424
1425     dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
1426     mfc_context->intra_row_store_scratch_buffer.bo = NULL;
1427
1428     dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
1429     mfc_context->macroblock_status_buffer.bo = NULL;
1430
1431     dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
1432     mfc_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
1433
1434     dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
1435     mfc_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
1436
1437
1438     for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
1439         dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
1440         mfc_context->reference_surfaces[i].bo = NULL;
1441     }
1442
1443     i965_gpe_context_destroy(&mfc_context->gpe_context);
1444
1445     dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo);
1446     mfc_context->mfc_batchbuffer_surface.bo = NULL;
1447
1448     dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo);
1449     mfc_context->aux_batchbuffer_surface.bo = NULL;
1450
1451     if (mfc_context->aux_batchbuffer)
1452         intel_batchbuffer_free(mfc_context->aux_batchbuffer);
1453
1454     mfc_context->aux_batchbuffer = NULL;
1455
1456     free(mfc_context);
1457 }
1458
1459 Bool gen6_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
1460 {
1461     struct gen6_mfc_context *mfc_context = calloc(1, sizeof(struct gen6_mfc_context));
1462
1463     mfc_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6;
1464
1465     mfc_context->gpe_context.idrt.max_entries = MAX_GPE_KERNELS;
1466     mfc_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data);
1467
1468     mfc_context->gpe_context.curbe.length = 32 * 4;
1469
1470     mfc_context->gpe_context.vfe_state.max_num_threads = 60 - 1;
1471     mfc_context->gpe_context.vfe_state.num_urb_entries = 16;
1472     mfc_context->gpe_context.vfe_state.gpgpu_mode = 0;
1473     mfc_context->gpe_context.vfe_state.urb_entry_size = 59 - 1;
1474     mfc_context->gpe_context.vfe_state.curbe_allocation_size = 37 - 1;
1475
1476     i965_gpe_load_kernels(ctx,
1477                           &mfc_context->gpe_context,
1478                           gen6_mfc_kernels,
1479                           NUM_MFC_KERNEL);
1480
1481     mfc_context->pipe_mode_select = gen6_mfc_pipe_mode_select;
1482     mfc_context->set_surface_state = gen6_mfc_surface_state;
1483     mfc_context->ind_obj_base_addr_state = gen6_mfc_ind_obj_base_addr_state;
1484     mfc_context->avc_img_state = gen6_mfc_avc_img_state;
1485     mfc_context->avc_qm_state = gen6_mfc_avc_qm_state;
1486     mfc_context->avc_fqm_state = gen6_mfc_avc_fqm_state;
1487     mfc_context->insert_object = gen6_mfc_avc_insert_object;
1488     mfc_context->buffer_suface_setup = i965_gpe_buffer_suface_setup;
1489
1490     encoder_context->mfc_context = mfc_context;
1491     encoder_context->mfc_context_destroy = gen6_mfc_context_destroy;
1492     encoder_context->mfc_pipeline = gen6_mfc_pipeline;
1493     encoder_context->mfc_brc_prepare = intel_mfc_brc_prepare;
1494
1495     return True;
1496 }