2 * Copyright © 2010-2011 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 * Zhou Chang <chang.zhou@intel.com>
35 #include "intel_batchbuffer.h"
36 #include "i965_defines.h"
37 #include "i965_structs.h"
38 #include "i965_drv_video.h"
39 #include "i965_encoder.h"
40 #include "i965_encoder_utils.h"
43 #include "intel_media.h"
45 static const uint32_t gen6_mfc_batchbuffer_avc_intra[][4] = {
46 #include "shaders/utils/mfc_batchbuffer_avc_intra.g6b"
49 static const uint32_t gen6_mfc_batchbuffer_avc_inter[][4] = {
50 #include "shaders/utils/mfc_batchbuffer_avc_inter.g6b"
53 static struct i965_kernel gen6_mfc_kernels[] = {
55 "MFC AVC INTRA BATCHBUFFER ",
56 MFC_BATCHBUFFER_AVC_INTRA,
57 gen6_mfc_batchbuffer_avc_intra,
58 sizeof(gen6_mfc_batchbuffer_avc_intra),
63 "MFC AVC INTER BATCHBUFFER ",
64 MFC_BATCHBUFFER_AVC_INTER,
65 gen6_mfc_batchbuffer_avc_inter,
66 sizeof(gen6_mfc_batchbuffer_avc_inter),
72 gen6_mfc_pipe_mode_select(VADriverContextP ctx,
74 struct intel_encoder_context *encoder_context)
76 struct intel_batchbuffer *batch = encoder_context->base.batch;
77 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
79 assert(standard_select == MFX_FORMAT_AVC);
81 BEGIN_BCS_BATCH(batch, 4);
83 OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (4 - 2));
85 (1 << 10) | /* disable Stream-Out , advanced QP/bitrate control need enable it*/
86 ((!!mfc_context->post_deblocking_output.bo) << 9) | /* Post Deblocking Output */
87 ((!!mfc_context->pre_deblocking_output.bo) << 8) | /* Pre Deblocking Output */
88 (0 << 7) | /* disable TLB prefectch */
89 (0 << 5) | /* not in stitch mode */
90 (1 << 4) | /* encoding mode */
91 (2 << 0)); /* Standard Select: AVC */
93 (0 << 20) | /* round flag in PB slice */
94 (0 << 19) | /* round flag in Intra8x8 */
95 (0 << 7) | /* expand NOA bus flag */
96 (1 << 6) | /* must be 1 */
97 (0 << 5) | /* disable clock gating for NOA */
98 (0 << 4) | /* terminate if AVC motion and POC table error occurs */
99 (0 << 3) | /* terminate if AVC mbdata error occurs */
100 (0 << 2) | /* terminate if AVC CABAC/CAVLC decode error occurs */
101 (0 << 1) | /* AVC long field motion vector */
102 (0 << 0)); /* always calculate AVC ILDB boundary strength */
103 OUT_BCS_BATCH(batch, 0);
105 ADVANCE_BCS_BATCH(batch);
109 gen6_mfc_surface_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
111 struct intel_batchbuffer *batch = encoder_context->base.batch;
112 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
114 BEGIN_BCS_BATCH(batch, 6);
116 OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
117 OUT_BCS_BATCH(batch, 0);
119 ((mfc_context->surface_state.height - 1) << 19) |
120 ((mfc_context->surface_state.width - 1) << 6));
122 (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
123 (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
124 (0 << 22) | /* surface object control state, FIXME??? */
125 ((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */
126 (0 << 2) | /* must be 0 for interleave U/V */
127 (1 << 1) | /* must be y-tiled */
128 (I965_TILEWALK_YMAJOR << 0)); /* tile walk, TILEWALK_YMAJOR */
130 (0 << 16) | /* must be 0 for interleave U/V */
131 (mfc_context->surface_state.h_pitch)); /* y offset for U(cb) */
132 OUT_BCS_BATCH(batch, 0);
133 ADVANCE_BCS_BATCH(batch);
137 gen6_mfc_pipe_buf_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
139 struct intel_batchbuffer *batch = encoder_context->base.batch;
140 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
143 BEGIN_BCS_BATCH(batch, 24);
145 OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
147 if (mfc_context->pre_deblocking_output.bo)
148 OUT_BCS_RELOC(batch, mfc_context->pre_deblocking_output.bo,
149 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
152 OUT_BCS_BATCH(batch, 0); /* pre output addr */
154 if (mfc_context->post_deblocking_output.bo)
155 OUT_BCS_RELOC(batch, mfc_context->post_deblocking_output.bo,
156 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
157 0); /* post output addr */
159 OUT_BCS_BATCH(batch, 0);
161 OUT_BCS_RELOC(batch, mfc_context->uncompressed_picture_source.bo,
162 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
163 0); /* uncompressed data */
164 OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
165 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
166 0); /* StreamOut data*/
167 OUT_BCS_RELOC(batch, mfc_context->intra_row_store_scratch_buffer.bo,
168 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
170 OUT_BCS_RELOC(batch, mfc_context->deblocking_filter_row_store_scratch_buffer.bo,
171 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
173 /* 7..22 Reference pictures*/
174 for (i = 0; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) {
175 if ( mfc_context->reference_surfaces[i].bo != NULL) {
176 OUT_BCS_RELOC(batch, mfc_context->reference_surfaces[i].bo,
177 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
180 OUT_BCS_BATCH(batch, 0);
183 OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
184 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
185 0); /* Macroblock status buffer*/
187 ADVANCE_BCS_BATCH(batch);
191 gen6_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
193 struct intel_batchbuffer *batch = encoder_context->base.batch;
194 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
195 struct gen6_vme_context *vme_context = encoder_context->vme_context;
197 BEGIN_BCS_BATCH(batch, 11);
199 OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
200 OUT_BCS_BATCH(batch, 0);
201 OUT_BCS_BATCH(batch, 0);
202 /* MFX Indirect MV Object Base Address */
203 OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
204 OUT_BCS_BATCH(batch, 0);
205 OUT_BCS_BATCH(batch, 0);
206 OUT_BCS_BATCH(batch, 0);
207 OUT_BCS_BATCH(batch, 0);
208 OUT_BCS_BATCH(batch, 0);
209 /*MFC Indirect PAK-BSE Object Base Address for Encoder*/
211 mfc_context->mfc_indirect_pak_bse_object.bo,
212 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
215 mfc_context->mfc_indirect_pak_bse_object.bo,
216 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
217 mfc_context->mfc_indirect_pak_bse_object.end_offset);
219 ADVANCE_BCS_BATCH(batch);
223 gen6_mfc_bsp_buf_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
225 struct intel_batchbuffer *batch = encoder_context->base.batch;
226 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
228 BEGIN_BCS_BATCH(batch, 4);
230 OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
231 OUT_BCS_RELOC(batch, mfc_context->bsd_mpc_row_store_scratch_buffer.bo,
232 I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
234 OUT_BCS_BATCH(batch, 0);
235 OUT_BCS_BATCH(batch, 0);
237 ADVANCE_BCS_BATCH(batch);
241 gen6_mfc_avc_img_state(VADriverContextP ctx,struct encode_state *encode_state,
242 struct intel_encoder_context *encoder_context)
244 struct intel_batchbuffer *batch = encoder_context->base.batch;
245 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
246 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
247 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
248 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
249 int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
251 BEGIN_BCS_BATCH(batch, 13);
252 OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (13 - 2));
254 ((width_in_mbs * height_in_mbs) & 0xFFFF));
256 (height_in_mbs << 16) |
257 (width_in_mbs << 0));
259 (0 << 24) | /*Second Chroma QP Offset*/
260 (0 << 16) | /*Chroma QP Offset*/
261 (0 << 14) | /*Max-bit conformance Intra flag*/
262 (0 << 13) | /*Max Macroblock size conformance Inter flag*/
263 (1 << 12) | /*Should always be written as "1" */
264 (0 << 10) | /*QM Preset FLag */
265 (0 << 8) | /*Image Structure*/
266 (0 << 0) ); /*Current Decoed Image Frame Store ID, reserved in Encode mode*/
268 (400 << 16) | /*Mininum Frame size*/
269 (0 << 15) | /*Disable reading of Macroblock Status Buffer*/
270 (0 << 14) | /*Load BitStream Pointer only once, 1 slic 1 frame*/
271 (0 << 13) | /*CABAC 0 word insertion test enable*/
272 (1 << 12) | /*MVUnpackedEnable,compliant to DXVA*/
273 (1 << 10) | /*Chroma Format IDC, 4:2:0*/
274 (pPicParameter->pic_fields.bits.entropy_coding_mode_flag << 7) | /*0:CAVLC encoding mode,1:CABAC*/
275 (0 << 6) | /*Only valid for VLD decoding mode*/
276 (0 << 5) | /*Constrained Intra Predition Flag, from PPS*/
277 (pSequenceParameter->seq_fields.bits.direct_8x8_inference_flag << 4) | /*Direct 8x8 inference flag*/
278 (pPicParameter->pic_fields.bits.transform_8x8_mode_flag << 3) | /*8x8 or 4x4 IDCT Transform Mode Flag*/
279 (1 << 2) | /*Frame MB only flag*/
280 (0 << 1) | /*MBAFF mode is in active*/
281 (0 << 0) ); /*Field picture flag*/
283 (1<<16) | /*Frame Size Rate Control Flag*/
285 (1<<9) | /*MB level Rate Control Enabling Flag*/
286 (1 << 3) | /*FrameBitRateMinReportMask*/
287 (1 << 2) | /*FrameBitRateMaxReportMask*/
288 (1 << 1) | /*InterMBMaxSizeReportMask*/
289 (1 << 0) ); /*IntraMBMaxSizeReportMask*/
290 OUT_BCS_BATCH(batch, /*Inter and Intra Conformance Max size limit*/
291 (0x0600 << 16) | /*InterMbMaxSz 192 Byte*/
292 (0x0800) ); /*IntraMbMaxSz 256 Byte*/
293 OUT_BCS_BATCH(batch, 0x00000000); /*Reserved : MBZReserved*/
294 OUT_BCS_BATCH(batch, 0x01020304); /*Slice QP Delta for bitrate control*/
295 OUT_BCS_BATCH(batch, 0xFEFDFCFB);
296 OUT_BCS_BATCH(batch, 0x80601004); /*MAX = 128KB, MIN = 64KB*/
297 OUT_BCS_BATCH(batch, 0x00800001);
298 OUT_BCS_BATCH(batch, 0);
300 ADVANCE_BCS_BATCH(batch);
304 gen6_mfc_avc_directmode_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
306 struct intel_batchbuffer *batch = encoder_context->base.batch;
307 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
311 BEGIN_BCS_BATCH(batch, 69);
313 OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
315 /* Reference frames and Current frames */
316 for(i = 0; i < NUM_MFC_DMV_BUFFERS; i++) {
317 if ( mfc_context->direct_mv_buffers[i].bo != NULL) {
318 OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[i].bo,
319 I915_GEM_DOMAIN_INSTRUCTION, 0,
322 OUT_BCS_BATCH(batch, 0);
327 for(i = 0; i < 32; i++) {
328 OUT_BCS_BATCH(batch, i/2);
330 OUT_BCS_BATCH(batch, 0);
331 OUT_BCS_BATCH(batch, 0);
333 ADVANCE_BCS_BATCH(batch);
337 gen6_mfc_avc_slice_state(VADriverContextP ctx,
338 VAEncPictureParameterBufferH264 *pic_param,
339 VAEncSliceParameterBufferH264 *slice_param,
340 struct encode_state *encode_state,
341 struct intel_encoder_context *encoder_context,
342 int rate_control_enable,
344 struct intel_batchbuffer *batch)
346 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
347 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
348 int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
349 int beginmb = slice_param->macroblock_address;
350 int endmb = beginmb + slice_param->num_macroblocks;
351 int beginx = beginmb % width_in_mbs;
352 int beginy = beginmb / width_in_mbs;
353 int nextx = endmb % width_in_mbs;
354 int nexty = endmb / width_in_mbs;
355 int slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
356 int last_slice = (endmb == (width_in_mbs * height_in_mbs));
358 unsigned char correct[6], grow, shrink;
360 int weighted_pred_idc = 0;
361 unsigned int luma_log2_weight_denom = slice_param->luma_log2_weight_denom;
362 unsigned int chroma_log2_weight_denom = slice_param->chroma_log2_weight_denom;
366 batch = encoder_context->base.batch;
368 if (slice_type == SLICE_TYPE_P) {
369 weighted_pred_idc = pic_param->pic_fields.bits.weighted_pred_flag;
370 } else if (slice_type == SLICE_TYPE_B) {
371 weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc;
374 if (weighted_pred_idc == 2) {
375 /* 8.4.3 - Derivation process for prediction weights (8-279) */
376 luma_log2_weight_denom = 5;
377 chroma_log2_weight_denom = 5;
381 maxQpN = mfc_context->bit_rate_control_context[slice_type].MaxQpNegModifier;
382 maxQpP = mfc_context->bit_rate_control_context[slice_type].MaxQpPosModifier;
384 for (i = 0; i < 6; i++)
385 correct[i] = mfc_context->bit_rate_control_context[slice_type].Correct[i];
387 grow = mfc_context->bit_rate_control_context[slice_type].GrowInit +
388 (mfc_context->bit_rate_control_context[slice_type].GrowResistance << 4);
389 shrink = mfc_context->bit_rate_control_context[slice_type].ShrinkInit +
390 (mfc_context->bit_rate_control_context[slice_type].ShrinkResistance << 4);
392 BEGIN_BCS_BATCH(batch, 11);;
394 OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) );
395 OUT_BCS_BATCH(batch, slice_type); /*Slice Type: I:P:B Slice*/
397 if (slice_type == SLICE_TYPE_I) {
398 OUT_BCS_BATCH(batch, 0); /*no reference frames and pred_weight_table*/
401 (1 << 16) | (bslice << 24) | /*1 reference frame*/
402 (chroma_log2_weight_denom << 8) |
403 (luma_log2_weight_denom << 0));
407 (weighted_pred_idc << 30) |
408 (slice_param->direct_spatial_mv_pred_flag<<29) | /*Direct Prediction Type*/
409 (slice_param->disable_deblocking_filter_idc << 27) |
410 (slice_param->cabac_init_idc << 24) |
411 (qp<<16) | /*Slice Quantization Parameter*/
412 ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
413 ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
415 (beginy << 24) | /*First MB X&Y , the begin postion of current slice*/
417 slice_param->macroblock_address );
418 OUT_BCS_BATCH(batch, (nexty << 16) | nextx); /*Next slice first MB X&Y*/
420 (0/*rate_control_enable*/ << 31) | /*in CBR mode RateControlCounterEnable = enable*/
421 (1 << 30) | /*ResetRateControlCounter*/
422 (0 << 28) | /*RC Triggle Mode = Always Rate Control*/
423 (4 << 24) | /*RC Stable Tolerance, middle level*/
424 (0/*rate_control_enable*/ << 23) | /*RC Panic Enable*/
425 (0 << 22) | /*QP mode, don't modfiy CBP*/
426 (0 << 21) | /*MB Type Direct Conversion Enabled*/
427 (0 << 20) | /*MB Type Skip Conversion Enabled*/
428 (last_slice << 19) | /*IsLastSlice*/
429 (0 << 18) | /*BitstreamOutputFlag Compressed BitStream Output Disable Flag 0:enable 1:disable*/
430 (1 << 17) | /*HeaderPresentFlag*/
431 (1 << 16) | /*SliceData PresentFlag*/
432 (1 << 15) | /*TailPresentFlag*/
433 (1 << 13) | /*RBSP NAL TYPE*/
434 (0 << 12) ); /*CabacZeroWordInsertionEnable*/
435 OUT_BCS_BATCH(batch, mfc_context->mfc_indirect_pak_bse_object.offset);
437 (maxQpN << 24) | /*Target QP - 24 is lowest QP*/
438 (maxQpP << 16) | /*Target QP + 20 is highest QP*/
448 OUT_BCS_BATCH(batch, 0);
450 ADVANCE_BCS_BATCH(batch);
452 static void gen6_mfc_avc_qm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
454 struct intel_batchbuffer *batch = encoder_context->base.batch;
457 BEGIN_BCS_BATCH(batch, 58);
459 OUT_BCS_BATCH(batch, MFX_AVC_QM_STATE | 56);
460 OUT_BCS_BATCH(batch, 0xFF ) ;
461 for( i = 0; i < 56; i++) {
462 OUT_BCS_BATCH(batch, 0x10101010);
465 ADVANCE_BCS_BATCH(batch);
468 static void gen6_mfc_avc_fqm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
470 struct intel_batchbuffer *batch = encoder_context->base.batch;
473 BEGIN_BCS_BATCH(batch, 113);
474 OUT_BCS_BATCH(batch, MFC_AVC_FQM_STATE | (113 - 2));
476 for(i = 0; i < 112;i++) {
477 OUT_BCS_BATCH(batch, 0x10001000);
480 ADVANCE_BCS_BATCH(batch);
484 gen6_mfc_avc_ref_idx_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
486 struct intel_batchbuffer *batch = encoder_context->base.batch;
489 BEGIN_BCS_BATCH(batch, 10);
490 OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
491 OUT_BCS_BATCH(batch, 0); //Select L0
492 OUT_BCS_BATCH(batch, 0x80808020); //Only 1 reference
493 for(i = 0; i < 7; i++) {
494 OUT_BCS_BATCH(batch, 0x80808080);
496 ADVANCE_BCS_BATCH(batch);
498 BEGIN_BCS_BATCH(batch, 10);
499 OUT_BCS_BATCH(batch, MFX_AVC_REF_IDX_STATE | 8);
500 OUT_BCS_BATCH(batch, 1); //Select L1
501 OUT_BCS_BATCH(batch, 0x80808022); //Only 1 reference
502 for(i = 0; i < 7; i++) {
503 OUT_BCS_BATCH(batch, 0x80808080);
505 ADVANCE_BCS_BATCH(batch);
509 gen6_mfc_avc_insert_object(VADriverContextP ctx, struct intel_encoder_context *encoder_context,
510 unsigned int *insert_data, int lenght_in_dws, int data_bits_in_last_dw,
511 int skip_emul_byte_count, int is_last_header, int is_end_of_slice, int emulation_flag,
512 struct intel_batchbuffer *batch)
515 batch = encoder_context->base.batch;
517 BEGIN_BCS_BATCH(batch, lenght_in_dws + 2);
519 OUT_BCS_BATCH(batch, MFC_AVC_INSERT_OBJECT | (lenght_in_dws + 2 - 2));
522 (0 << 16) | /* always start at offset 0 */
523 (data_bits_in_last_dw << 8) |
524 (skip_emul_byte_count << 4) |
525 (!!emulation_flag << 3) |
526 ((!!is_last_header) << 2) |
527 ((!!is_end_of_slice) << 1) |
528 (0 << 0)); /* FIXME: ??? */
530 intel_batchbuffer_data(batch, insert_data, lenght_in_dws * 4);
531 ADVANCE_BCS_BATCH(batch);
535 gen6_mfc_init(VADriverContextP ctx,
536 struct encode_state *encode_state,
537 struct intel_encoder_context *encoder_context)
539 struct i965_driver_data *i965 = i965_driver_data(ctx);
540 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
543 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
544 int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
545 int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
547 /*Encode common setup for MFC*/
548 dri_bo_unreference(mfc_context->post_deblocking_output.bo);
549 mfc_context->post_deblocking_output.bo = NULL;
551 dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
552 mfc_context->pre_deblocking_output.bo = NULL;
554 dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
555 mfc_context->uncompressed_picture_source.bo = NULL;
557 dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
558 mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
560 for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
561 if ( mfc_context->direct_mv_buffers[i].bo != NULL);
562 dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
563 mfc_context->direct_mv_buffers[i].bo = NULL;
566 for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
567 if (mfc_context->reference_surfaces[i].bo != NULL)
568 dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
569 mfc_context->reference_surfaces[i].bo = NULL;
572 dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
573 bo = dri_bo_alloc(i965->intel.bufmgr,
578 mfc_context->intra_row_store_scratch_buffer.bo = bo;
580 dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
581 bo = dri_bo_alloc(i965->intel.bufmgr,
583 width_in_mbs * height_in_mbs * 16,
586 mfc_context->macroblock_status_buffer.bo = bo;
588 dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
589 bo = dri_bo_alloc(i965->intel.bufmgr,
591 4 * width_in_mbs * 64, /* 4 * width_in_mbs * 64 */
594 mfc_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
596 dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
597 bo = dri_bo_alloc(i965->intel.bufmgr,
599 128 * width_in_mbs, /* 2 * widht_in_mbs * 64 */
602 mfc_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
604 dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo);
605 mfc_context->mfc_batchbuffer_surface.bo = NULL;
607 dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo);
608 mfc_context->aux_batchbuffer_surface.bo = NULL;
610 if (mfc_context->aux_batchbuffer)
611 intel_batchbuffer_free(mfc_context->aux_batchbuffer);
613 mfc_context->aux_batchbuffer = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD, 0);
614 mfc_context->aux_batchbuffer_surface.bo = mfc_context->aux_batchbuffer->buffer;
615 dri_bo_reference(mfc_context->aux_batchbuffer_surface.bo);
616 mfc_context->aux_batchbuffer_surface.pitch = 16;
617 mfc_context->aux_batchbuffer_surface.num_blocks = mfc_context->aux_batchbuffer->size / 16;
618 mfc_context->aux_batchbuffer_surface.size_block = 16;
620 i965_gpe_context_init(ctx, &mfc_context->gpe_context);
623 static void gen6_mfc_avc_pipeline_picture_programing( VADriverContextP ctx,
624 struct encode_state *encode_state,
625 struct intel_encoder_context *encoder_context)
627 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
629 mfc_context->pipe_mode_select(ctx, MFX_FORMAT_AVC, encoder_context);
630 mfc_context->set_surface_state(ctx, encoder_context);
631 mfc_context->ind_obj_base_addr_state(ctx, encoder_context);
632 gen6_mfc_pipe_buf_addr_state(ctx, encoder_context);
633 gen6_mfc_bsp_buf_base_addr_state(ctx, encoder_context);
634 mfc_context->avc_img_state(ctx, encode_state, encoder_context);
635 mfc_context->avc_qm_state(ctx, encoder_context);
636 mfc_context->avc_fqm_state(ctx, encoder_context);
637 gen6_mfc_avc_directmode_state(ctx, encoder_context);
638 gen6_mfc_avc_ref_idx_state(ctx, encoder_context);
643 gen6_mfc_run(VADriverContextP ctx,
644 struct encode_state *encode_state,
645 struct intel_encoder_context *encoder_context)
647 struct intel_batchbuffer *batch = encoder_context->base.batch;
649 intel_batchbuffer_flush(batch); //run the pipeline
651 return VA_STATUS_SUCCESS;
655 gen6_mfc_stop(VADriverContextP ctx,
656 struct encode_state *encode_state,
657 struct intel_encoder_context *encoder_context,
658 int *encoded_bits_size)
660 VAStatus vaStatus = VA_STATUS_ERROR_UNKNOWN;
661 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
662 VACodedBufferSegment *coded_buffer_segment;
664 vaStatus = i965_MapBuffer(ctx, pPicParameter->coded_buf, (void **)&coded_buffer_segment);
665 assert(vaStatus == VA_STATUS_SUCCESS);
666 *encoded_bits_size = coded_buffer_segment->size * 8;
667 i965_UnmapBuffer(ctx, pPicParameter->coded_buf);
669 return VA_STATUS_SUCCESS;
675 gen6_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb, int qp,unsigned int *msg,
676 struct intel_encoder_context *encoder_context,
677 unsigned char target_mb_size, unsigned char max_mb_size,
678 struct intel_batchbuffer *batch)
680 int len_in_dwords = 11;
683 batch = encoder_context->base.batch;
685 BEGIN_BCS_BATCH(batch, len_in_dwords);
687 OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
688 OUT_BCS_BATCH(batch, 0);
689 OUT_BCS_BATCH(batch, 0);
691 (0 << 24) | /* PackedMvNum, Debug*/
692 (0 << 20) | /* No motion vector */
693 (1 << 19) | /* CbpDcY */
694 (1 << 18) | /* CbpDcU */
695 (1 << 17) | /* CbpDcV */
698 OUT_BCS_BATCH(batch, (0xFFFF << 16) | (y << 8) | x); /* Code Block Pattern for Y*/
699 OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */
700 OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp); /* Last MB */
702 /*Stuff for Intra MB*/
703 OUT_BCS_BATCH(batch, msg[1]); /* We using Intra16x16 no 4x4 predmode*/
704 OUT_BCS_BATCH(batch, msg[2]);
705 OUT_BCS_BATCH(batch, msg[3]&0xFC);
707 /*MaxSizeInWord and TargetSzieInWord*/
708 OUT_BCS_BATCH(batch, (max_mb_size << 24) |
709 (target_mb_size << 16) );
711 ADVANCE_BCS_BATCH(batch);
713 return len_in_dwords;
717 gen6_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, int qp,
718 unsigned int *msg, unsigned int offset,
719 struct intel_encoder_context *encoder_context,
720 unsigned char target_mb_size,unsigned char max_mb_size, int slice_type,
721 struct intel_batchbuffer *batch)
723 int len_in_dwords = 11;
726 batch = encoder_context->base.batch;
728 BEGIN_BCS_BATCH(batch, len_in_dwords);
730 OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
732 OUT_BCS_BATCH(batch, msg[2]); /* 32 MV*/
733 OUT_BCS_BATCH(batch, offset);
735 OUT_BCS_BATCH(batch, msg[0]);
737 OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x); /* Code Block Pattern for Y*/
738 OUT_BCS_BATCH(batch, 0x000F000F); /* Code Block Pattern */
740 if ( slice_type == SLICE_TYPE_B) {
741 OUT_BCS_BATCH(batch, (0xF<<28) | (end_mb << 26) | qp); /* Last MB */
743 OUT_BCS_BATCH(batch, (end_mb << 26) | qp); /* Last MB */
746 OUT_BCS_BATCH(batch, (end_mb << 26) | qp); /* Last MB */
750 /*Stuff for Inter MB*/
751 OUT_BCS_BATCH(batch, msg[1]);
752 OUT_BCS_BATCH(batch, 0x0);
753 OUT_BCS_BATCH(batch, 0x0);
755 /*MaxSizeInWord and TargetSzieInWord*/
756 OUT_BCS_BATCH(batch, (max_mb_size << 24) |
757 (target_mb_size << 16) );
759 ADVANCE_BCS_BATCH(batch);
761 return len_in_dwords;
765 gen6_mfc_avc_pipeline_slice_programing(VADriverContextP ctx,
766 struct encode_state *encode_state,
767 struct intel_encoder_context *encoder_context,
769 struct intel_batchbuffer *slice_batch)
771 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
772 struct gen6_vme_context *vme_context = encoder_context->vme_context;
773 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
774 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
775 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
776 unsigned int *msg = NULL, offset = 0;
777 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
778 int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
779 int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs);
781 int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta;
782 unsigned int rate_control_mode = encoder_context->rate_control_mode;
783 unsigned char *slice_header = NULL;
784 int slice_header_length_in_bits = 0;
785 unsigned int tail_data[] = { 0x0, 0x0 };
786 int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type);
787 int is_intra = slice_type == SLICE_TYPE_I;
789 if (rate_control_mode == VA_RC_CBR) {
790 qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
791 pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp;
794 /* only support for 8-bit pixel bit-depth */
795 assert(pSequenceParameter->bit_depth_luma_minus8 == 0);
796 assert(pSequenceParameter->bit_depth_chroma_minus8 == 0);
797 assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52);
798 assert(qp >= 0 && qp < 52);
800 gen6_mfc_avc_slice_state(ctx,
803 encode_state, encoder_context,
804 (rate_control_mode == VA_RC_CBR), qp, slice_batch);
806 if ( slice_index == 0)
807 intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch);
809 slice_header_length_in_bits = build_avc_slice_header(pSequenceParameter, pPicParameter, pSliceParameter, &slice_header);
812 mfc_context->insert_object(ctx, encoder_context,
813 (unsigned int *)slice_header, ALIGN(slice_header_length_in_bits, 32) >> 5, slice_header_length_in_bits & 0x1f,
814 5, /* first 5 bytes are start code + nal unit type */
815 1, 0, 1, slice_batch);
817 dri_bo_map(vme_context->vme_output.bo , 1);
818 msg = (unsigned int *)vme_context->vme_output.bo->virtual;
821 msg += pSliceParameter->macroblock_address * INTRA_VME_OUTPUT_IN_DWS;
823 msg += pSliceParameter->macroblock_address * INTER_VME_OUTPUT_IN_DWS;
824 msg += 32; /* the first 32 DWs are MVs */
825 offset = pSliceParameter->macroblock_address * INTER_VME_OUTPUT_IN_BYTES;
828 for (i = pSliceParameter->macroblock_address;
829 i < pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks; i++) {
830 int last_mb = (i == (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks - 1) );
831 x = i % width_in_mbs;
832 y = i / width_in_mbs;
836 gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch);
837 msg += INTRA_VME_OUTPUT_IN_DWS;
839 if (msg[0] & INTRA_MB_FLAG_MASK) {
840 gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch);
842 gen6_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, msg, offset, encoder_context, 0, 0, slice_type, slice_batch);
845 msg += INTER_VME_OUTPUT_IN_DWS;
846 offset += INTER_VME_OUTPUT_IN_BYTES;
850 dri_bo_unmap(vme_context->vme_output.bo);
853 mfc_context->insert_object(ctx, encoder_context,
855 2, 1, 1, 0, slice_batch);
857 mfc_context->insert_object(ctx, encoder_context,
859 1, 1, 1, 0, slice_batch);
867 gen6_mfc_avc_software_batchbuffer(VADriverContextP ctx,
868 struct encode_state *encode_state,
869 struct intel_encoder_context *encoder_context)
871 struct i965_driver_data *i965 = i965_driver_data(ctx);
872 struct intel_batchbuffer *batch = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD, 0);
873 dri_bo *batch_bo = batch->buffer;
876 for (i = 0; i < encode_state->num_slice_params_ext; i++) {
877 gen6_mfc_avc_pipeline_slice_programing(ctx, encode_state, encoder_context, i, batch);
880 intel_batchbuffer_align(batch, 8);
882 BEGIN_BCS_BATCH(batch, 2);
883 OUT_BCS_BATCH(batch, 0);
884 OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_END);
885 ADVANCE_BCS_BATCH(batch);
887 dri_bo_reference(batch_bo);
888 intel_batchbuffer_free(batch);
896 gen6_mfc_batchbuffer_surfaces_input(VADriverContextP ctx,
897 struct encode_state *encode_state,
898 struct intel_encoder_context *encoder_context)
901 struct gen6_vme_context *vme_context = encoder_context->vme_context;
902 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
904 assert(vme_context->vme_output.bo);
905 mfc_context->buffer_suface_setup(ctx,
906 &mfc_context->gpe_context,
907 &vme_context->vme_output,
908 BINDING_TABLE_OFFSET(BIND_IDX_VME_OUTPUT),
909 SURFACE_STATE_OFFSET(BIND_IDX_VME_OUTPUT));
910 assert(mfc_context->aux_batchbuffer_surface.bo);
911 mfc_context->buffer_suface_setup(ctx,
912 &mfc_context->gpe_context,
913 &mfc_context->aux_batchbuffer_surface,
914 BINDING_TABLE_OFFSET(BIND_IDX_MFC_SLICE_HEADER),
915 SURFACE_STATE_OFFSET(BIND_IDX_MFC_SLICE_HEADER));
919 gen6_mfc_batchbuffer_surfaces_output(VADriverContextP ctx,
920 struct encode_state *encode_state,
921 struct intel_encoder_context *encoder_context)
924 struct i965_driver_data *i965 = i965_driver_data(ctx);
925 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
926 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
927 int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
928 int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
929 mfc_context->mfc_batchbuffer_surface.num_blocks = width_in_mbs * height_in_mbs + encode_state->num_slice_params_ext * 8 + 1;
930 mfc_context->mfc_batchbuffer_surface.size_block = 16 * CMD_LEN_IN_OWORD; /* 3 OWORDs */
931 mfc_context->mfc_batchbuffer_surface.pitch = 16;
932 mfc_context->mfc_batchbuffer_surface.bo = dri_bo_alloc(i965->intel.bufmgr,
934 mfc_context->mfc_batchbuffer_surface.num_blocks * mfc_context->mfc_batchbuffer_surface.size_block,
936 mfc_context->buffer_suface_setup(ctx,
937 &mfc_context->gpe_context,
938 &mfc_context->mfc_batchbuffer_surface,
939 BINDING_TABLE_OFFSET(BIND_IDX_MFC_BATCHBUFFER),
940 SURFACE_STATE_OFFSET(BIND_IDX_MFC_BATCHBUFFER));
944 gen6_mfc_batchbuffer_surfaces_setup(VADriverContextP ctx,
945 struct encode_state *encode_state,
946 struct intel_encoder_context *encoder_context)
948 gen6_mfc_batchbuffer_surfaces_input(ctx, encode_state, encoder_context);
949 gen6_mfc_batchbuffer_surfaces_output(ctx, encode_state, encoder_context);
953 gen6_mfc_batchbuffer_idrt_setup(VADriverContextP ctx,
954 struct encode_state *encode_state,
955 struct intel_encoder_context *encoder_context)
957 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
958 struct gen6_interface_descriptor_data *desc;
962 bo = mfc_context->gpe_context.idrt.bo;
967 for (i = 0; i < mfc_context->gpe_context.num_kernels; i++) {
968 struct i965_kernel *kernel;
970 kernel = &mfc_context->gpe_context.kernels[i];
971 assert(sizeof(*desc) == 32);
973 /*Setup the descritor table*/
974 memset(desc, 0, sizeof(*desc));
975 desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6);
976 desc->desc2.sampler_count = 0;
977 desc->desc2.sampler_state_pointer = 0;
978 desc->desc3.binding_table_entry_count = 2;
979 desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5);
980 desc->desc4.constant_urb_entry_read_offset = 0;
981 desc->desc4.constant_urb_entry_read_length = 4;
984 dri_bo_emit_reloc(bo,
985 I915_GEM_DOMAIN_INSTRUCTION, 0,
987 i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0),
996 gen6_mfc_batchbuffer_constant_setup(VADriverContextP ctx,
997 struct encode_state *encode_state,
998 struct intel_encoder_context *encoder_context)
1000 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1006 gen6_mfc_batchbuffer_emit_object_command(struct intel_batchbuffer *batch,
1009 int batchbuffer_offset,
1021 BEGIN_BATCH(batch, 12);
1023 OUT_BATCH(batch, CMD_MEDIA_OBJECT | (12 - 2));
1024 OUT_BATCH(batch, index);
1025 OUT_BATCH(batch, 0);
1026 OUT_BATCH(batch, 0);
1027 OUT_BATCH(batch, 0);
1028 OUT_BATCH(batch, 0);
1031 OUT_BATCH(batch, head_offset);
1032 OUT_BATCH(batch, batchbuffer_offset);
1037 number_mb_cmds << 16 |
1048 ADVANCE_BATCH(batch);
1052 gen6_mfc_avc_batchbuffer_slice_command(VADriverContextP ctx,
1053 struct intel_encoder_context *encoder_context,
1054 VAEncSliceParameterBufferH264 *slice_param,
1056 unsigned short head_size,
1057 unsigned short tail_size,
1058 int batchbuffer_offset,
1062 struct intel_batchbuffer *batch = encoder_context->base.batch;
1063 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1064 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
1065 int total_mbs = slice_param->num_macroblocks;
1066 int number_mb_cmds = 128;
1067 int starting_mb = 0;
1068 int last_object = 0;
1069 int first_object = 1;
1072 int index = (slice_param->slice_type == SLICE_TYPE_I) ? MFC_BATCHBUFFER_AVC_INTRA : MFC_BATCHBUFFER_AVC_INTER;
1074 for (i = 0; i < total_mbs / number_mb_cmds; i++) {
1075 last_object = (total_mbs - starting_mb) == number_mb_cmds;
1076 mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs;
1077 mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs;
1078 assert(mb_x <= 255 && mb_y <= 255);
1080 starting_mb += number_mb_cmds;
1082 gen6_mfc_batchbuffer_emit_object_command(batch,
1098 head_offset += head_size;
1099 batchbuffer_offset += head_size;
1103 head_offset += tail_size;
1104 batchbuffer_offset += tail_size;
1107 batchbuffer_offset += number_mb_cmds * CMD_LEN_IN_OWORD;
1114 number_mb_cmds = total_mbs % number_mb_cmds;
1115 mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs;
1116 mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs;
1117 assert(mb_x <= 255 && mb_y <= 255);
1118 starting_mb += number_mb_cmds;
1120 gen6_mfc_batchbuffer_emit_object_command(batch,
1138 * return size in Owords (16bytes)
1141 gen6_mfc_avc_batchbuffer_slice(VADriverContextP ctx,
1142 struct encode_state *encode_state,
1143 struct intel_encoder_context *encoder_context,
1145 int batchbuffer_offset)
1147 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1148 struct intel_batchbuffer *slice_batch = mfc_context->aux_batchbuffer;
1149 VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
1150 VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
1151 VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
1152 int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
1153 int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
1154 int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs);
1155 int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta;
1156 unsigned int rate_control_mode = encoder_context->rate_control_mode;
1157 unsigned char *slice_header = NULL;
1158 int slice_header_length_in_bits = 0;
1159 unsigned int tail_data[] = { 0x0, 0x0 };
1161 int old_used = intel_batchbuffer_used_size(slice_batch), used;
1162 unsigned short head_size, tail_size;
1163 int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type);
1165 if (rate_control_mode == VA_RC_CBR) {
1166 qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
1167 pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp;
1170 /* only support for 8-bit pixel bit-depth */
1171 assert(pSequenceParameter->bit_depth_luma_minus8 == 0);
1172 assert(pSequenceParameter->bit_depth_chroma_minus8 == 0);
1173 assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52);
1174 assert(qp >= 0 && qp < 52);
1176 head_offset = old_used / 16;
1177 gen6_mfc_avc_slice_state(ctx,
1182 (rate_control_mode == VA_RC_CBR),
1186 if (slice_index == 0)
1187 intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch);
1189 slice_header_length_in_bits = build_avc_slice_header(pSequenceParameter, pPicParameter, pSliceParameter, &slice_header);
1192 mfc_context->insert_object(ctx,
1194 (unsigned int *)slice_header,
1195 ALIGN(slice_header_length_in_bits, 32) >> 5,
1196 slice_header_length_in_bits & 0x1f,
1197 5, /* first 5 bytes are start code + nal unit type */
1204 intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */
1205 used = intel_batchbuffer_used_size(slice_batch);
1206 head_size = (used - old_used) / 16;
1211 mfc_context->insert_object(ctx,
1222 mfc_context->insert_object(ctx,
1234 intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */
1235 used = intel_batchbuffer_used_size(slice_batch);
1236 tail_size = (used - old_used) / 16;
1239 gen6_mfc_avc_batchbuffer_slice_command(ctx,
1249 return head_size + tail_size + pSliceParameter->num_macroblocks * CMD_LEN_IN_OWORD;
1253 gen6_mfc_avc_batchbuffer_pipeline(VADriverContextP ctx,
1254 struct encode_state *encode_state,
1255 struct intel_encoder_context *encoder_context)
1257 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1258 struct intel_batchbuffer *batch = encoder_context->base.batch;
1259 int i, size, offset = 0;
1260 intel_batchbuffer_start_atomic(batch, 0x4000);
1261 gen6_gpe_pipeline_setup(ctx, &mfc_context->gpe_context, batch);
1263 for ( i = 0; i < encode_state->num_slice_params_ext; i++) {
1264 size = gen6_mfc_avc_batchbuffer_slice(ctx, encode_state, encoder_context, i, offset);
1268 intel_batchbuffer_end_atomic(batch);
1269 intel_batchbuffer_flush(batch);
1273 gen6_mfc_build_avc_batchbuffer(VADriverContextP ctx,
1274 struct encode_state *encode_state,
1275 struct intel_encoder_context *encoder_context)
1277 gen6_mfc_batchbuffer_surfaces_setup(ctx, encode_state, encoder_context);
1278 gen6_mfc_batchbuffer_idrt_setup(ctx, encode_state, encoder_context);
1279 gen6_mfc_batchbuffer_constant_setup(ctx, encode_state, encoder_context);
1280 gen6_mfc_avc_batchbuffer_pipeline(ctx, encode_state, encoder_context);
1284 gen6_mfc_avc_hardware_batchbuffer(VADriverContextP ctx,
1285 struct encode_state *encode_state,
1286 struct intel_encoder_context *encoder_context)
1288 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1290 gen6_mfc_build_avc_batchbuffer(ctx, encode_state, encoder_context);
1291 dri_bo_reference(mfc_context->mfc_batchbuffer_surface.bo);
1293 return mfc_context->mfc_batchbuffer_surface.bo;
1300 gen6_mfc_avc_pipeline_programing(VADriverContextP ctx,
1301 struct encode_state *encode_state,
1302 struct intel_encoder_context *encoder_context)
1304 struct intel_batchbuffer *batch = encoder_context->base.batch;
1305 dri_bo *slice_batch_bo;
1307 if ( intel_mfc_interlace_check(ctx, encode_state, encoder_context) ) {
1308 fprintf(stderr, "Current VA driver don't support interlace mode!\n");
1314 slice_batch_bo = gen6_mfc_avc_software_batchbuffer(ctx, encode_state, encoder_context);
1316 slice_batch_bo = gen6_mfc_avc_hardware_batchbuffer(ctx, encode_state, encoder_context);
1320 intel_batchbuffer_start_atomic_bcs(batch, 0x4000);
1321 intel_batchbuffer_emit_mi_flush(batch);
1323 // picture level programing
1324 gen6_mfc_avc_pipeline_picture_programing(ctx, encode_state, encoder_context);
1326 BEGIN_BCS_BATCH(batch, 2);
1327 OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8));
1328 OUT_BCS_RELOC(batch,
1330 I915_GEM_DOMAIN_COMMAND, 0,
1332 ADVANCE_BCS_BATCH(batch);
1335 intel_batchbuffer_end_atomic(batch);
1337 dri_bo_unreference(slice_batch_bo);
1341 gen6_mfc_avc_encode_picture(VADriverContextP ctx,
1342 struct encode_state *encode_state,
1343 struct intel_encoder_context *encoder_context)
1345 struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1346 unsigned int rate_control_mode = encoder_context->rate_control_mode;
1347 int current_frame_bits_size;
1351 gen6_mfc_init(ctx, encode_state, encoder_context);
1352 intel_mfc_avc_prepare(ctx, encode_state, encoder_context);
1353 /*Programing bcs pipeline*/
1354 gen6_mfc_avc_pipeline_programing(ctx, encode_state, encoder_context); //filling the pipeline
1355 gen6_mfc_run(ctx, encode_state, encoder_context);
1356 if (rate_control_mode == VA_RC_CBR /*|| rate_control_mode == VA_RC_VBR*/) {
1357 gen6_mfc_stop(ctx, encode_state, encoder_context, ¤t_frame_bits_size);
1358 sts = intel_mfc_brc_postpack(encode_state, mfc_context, current_frame_bits_size);
1359 if (sts == BRC_NO_HRD_VIOLATION) {
1360 intel_mfc_hrd_context_update(encode_state, mfc_context);
1363 else if (sts == BRC_OVERFLOW_WITH_MIN_QP || sts == BRC_UNDERFLOW_WITH_MAX_QP) {
1364 if (!mfc_context->hrd.violation_noted) {
1365 fprintf(stderr, "Unrepairable %s!\n", (sts == BRC_OVERFLOW_WITH_MIN_QP)? "overflow": "underflow");
1366 mfc_context->hrd.violation_noted = 1;
1368 return VA_STATUS_SUCCESS;
1375 return VA_STATUS_SUCCESS;
1379 gen6_mfc_qm_state(VADriverContextP ctx,
1383 struct intel_encoder_context *encoder_context)
1385 struct intel_batchbuffer *batch = encoder_context->base.batch;
1386 unsigned int qm_buffer[16];
1388 assert(qm_length <= 16);
1389 assert(sizeof(*qm) == 4);
1390 memcpy(qm_buffer, qm, qm_length * 4);
1392 BEGIN_BCS_BATCH(batch, 18);
1393 OUT_BCS_BATCH(batch, MFX_QM_STATE | (18 - 2));
1394 OUT_BCS_BATCH(batch, qm_type << 0);
1395 intel_batchbuffer_data(batch, qm_buffer, 16 * 4);
1396 ADVANCE_BCS_BATCH(batch);
1400 gen6_mfc_fqm_state(VADriverContextP ctx,
1404 struct intel_encoder_context *encoder_context)
1406 struct intel_batchbuffer *batch = encoder_context->base.batch;
1407 unsigned int fqm_buffer[32];
1409 assert(fqm_length <= 32);
1410 assert(sizeof(*fqm) == 4);
1411 memcpy(fqm_buffer, fqm, fqm_length * 4);
1413 BEGIN_BCS_BATCH(batch, 34);
1414 OUT_BCS_BATCH(batch, MFX_FQM_STATE | (34 - 2));
1415 OUT_BCS_BATCH(batch, fqm_type << 0);
1416 intel_batchbuffer_data(batch, fqm_buffer, 32 * 4);
1417 ADVANCE_BCS_BATCH(batch);
1421 gen6_mfc_pipeline(VADriverContextP ctx,
1423 struct encode_state *encode_state,
1424 struct intel_encoder_context *encoder_context)
1429 case VAProfileH264Baseline:
1430 case VAProfileH264Main:
1431 case VAProfileH264High:
1432 vaStatus = gen6_mfc_avc_encode_picture(ctx, encode_state, encoder_context);
1435 /* FIXME: add for other profile */
1437 vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
1445 gen6_mfc_context_destroy(void *context)
1447 struct gen6_mfc_context *mfc_context = context;
1450 dri_bo_unreference(mfc_context->post_deblocking_output.bo);
1451 mfc_context->post_deblocking_output.bo = NULL;
1453 dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
1454 mfc_context->pre_deblocking_output.bo = NULL;
1456 dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
1457 mfc_context->uncompressed_picture_source.bo = NULL;
1459 dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
1460 mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
1462 for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
1463 dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
1464 mfc_context->direct_mv_buffers[i].bo = NULL;
1467 dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
1468 mfc_context->intra_row_store_scratch_buffer.bo = NULL;
1470 dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
1471 mfc_context->macroblock_status_buffer.bo = NULL;
1473 dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
1474 mfc_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
1476 dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
1477 mfc_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
1480 for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
1481 dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
1482 mfc_context->reference_surfaces[i].bo = NULL;
1485 i965_gpe_context_destroy(&mfc_context->gpe_context);
1487 dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo);
1488 mfc_context->mfc_batchbuffer_surface.bo = NULL;
1490 dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo);
1491 mfc_context->aux_batchbuffer_surface.bo = NULL;
1493 if (mfc_context->aux_batchbuffer)
1494 intel_batchbuffer_free(mfc_context->aux_batchbuffer);
1496 mfc_context->aux_batchbuffer = NULL;
1501 Bool gen6_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
1503 struct gen6_mfc_context *mfc_context = calloc(1, sizeof(struct gen6_mfc_context));
1505 mfc_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6;
1507 mfc_context->gpe_context.idrt.max_entries = MAX_GPE_KERNELS;
1508 mfc_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data);
1510 mfc_context->gpe_context.curbe.length = 32 * 4;
1512 mfc_context->gpe_context.vfe_state.max_num_threads = 60 - 1;
1513 mfc_context->gpe_context.vfe_state.num_urb_entries = 16;
1514 mfc_context->gpe_context.vfe_state.gpgpu_mode = 0;
1515 mfc_context->gpe_context.vfe_state.urb_entry_size = 59 - 1;
1516 mfc_context->gpe_context.vfe_state.curbe_allocation_size = 37 - 1;
1518 i965_gpe_load_kernels(ctx,
1519 &mfc_context->gpe_context,
1523 mfc_context->pipe_mode_select = gen6_mfc_pipe_mode_select;
1524 mfc_context->set_surface_state = gen6_mfc_surface_state;
1525 mfc_context->ind_obj_base_addr_state = gen6_mfc_ind_obj_base_addr_state;
1526 mfc_context->avc_img_state = gen6_mfc_avc_img_state;
1527 mfc_context->avc_qm_state = gen6_mfc_avc_qm_state;
1528 mfc_context->avc_fqm_state = gen6_mfc_avc_fqm_state;
1529 mfc_context->insert_object = gen6_mfc_avc_insert_object;
1530 mfc_context->buffer_suface_setup = i965_gpe_buffer_suface_setup;
1532 encoder_context->mfc_context = mfc_context;
1533 encoder_context->mfc_context_destroy = gen6_mfc_context_destroy;
1534 encoder_context->mfc_pipeline = gen6_mfc_pipeline;
1535 encoder_context->mfc_brc_prepare = intel_mfc_brc_prepare;