src/gen6_mfc.c

   1 /*
   2  * Copyright © 2010-2011 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the
   6  * "Software"), to deal in the Software without restriction, including
   7  * without limitation the rights to use, copy, modify, merge, publish,
   8  * distribute, sub license, and/or sell copies of the Software, and to
   9  * permit persons to whom the Software is furnished to do so, subject to
  10  * the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the
  13  * next paragraph) shall be included in all copies or substantial portions
  14  * of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
  20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Zhou Chang <chang.zhou@intel.com>
  26  *
  27  */
  28
  29 #include <stdio.h>
  30 #include <stdlib.h>
  31 #include <string.h>
  32 #include <assert.h>
  33 #include <math.h>
  34
  35 #include "intel_batchbuffer.h"
  36 #include "i965_defines.h"
  37 #include "i965_structs.h"
  38 #include "i965_drv_video.h"
  39 #include "i965_encoder.h"
  40 #include "i965_encoder_utils.h"
  41 #include "gen6_mfc.h"
  42 #include "gen6_vme.h"
  43 #include "intel_media.h"
  44
  45 #define SURFACE_STATE_PADDED_SIZE               MAX(SURFACE_STATE_PADDED_SIZE_GEN6, SURFACE_STATE_PADDED_SIZE_GEN7)
  46 #define SURFACE_STATE_OFFSET(index)             (SURFACE_STATE_PADDED_SIZE * index)
  47 #define BINDING_TABLE_OFFSET(index)             (SURFACE_STATE_OFFSET(MAX_MEDIA_SURFACES_GEN6) + sizeof(unsigned int) * index)
  48
  49 static const uint32_t gen6_mfc_batchbuffer_avc_intra[][4] = {
  50 #include "shaders/utils/mfc_batchbuffer_avc_intra.g6b"
  51 };
  52
  53 static const uint32_t gen6_mfc_batchbuffer_avc_inter[][4] = {
  54 #include "shaders/utils/mfc_batchbuffer_avc_inter.g6b"
  55 };
  56
  57 static struct i965_kernel gen6_mfc_kernels[] = {
  58     {
  59         "MFC AVC INTRA BATCHBUFFER ",
  60         MFC_BATCHBUFFER_AVC_INTRA,
  61         gen6_mfc_batchbuffer_avc_intra,
  62         sizeof(gen6_mfc_batchbuffer_avc_intra),
  63         NULL
  64     },
  65
  66     {
  67         "MFC AVC INTER BATCHBUFFER ",
  68         MFC_BATCHBUFFER_AVC_INTER,
  69         gen6_mfc_batchbuffer_avc_inter,
  70         sizeof(gen6_mfc_batchbuffer_avc_inter),
  71         NULL
  72     },
  73 };
  74
  75 static void
  76 gen6_mfc_pipe_mode_select(VADriverContextP ctx,
  77                           int standard_select,
  78                           struct intel_encoder_context *encoder_context)
  79 {
  80     struct intel_batchbuffer *batch = encoder_context->base.batch;
  81     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
  82
  83     assert(standard_select == MFX_FORMAT_AVC);
  84
  85     BEGIN_BCS_BATCH(batch, 4);
  86
  87     OUT_BCS_BATCH(batch, MFX_PIPE_MODE_SELECT | (4 - 2));
  88     OUT_BCS_BATCH(batch,
  89                   (1 << 10) | /* disable Stream-Out , advanced QP/bitrate control need enable it*/
  90                   ((!!mfc_context->post_deblocking_output.bo) << 9)  | /* Post Deblocking Output */
  91                   ((!!mfc_context->pre_deblocking_output.bo) << 8)  | /* Pre Deblocking Output */
  92                   (0 << 7)  | /* disable TLB prefectch */
  93                   (0 << 5)  | /* not in stitch mode */
  94                   (1 << 4)  | /* encoding mode */
  95                   (2 << 0));  /* Standard Select: AVC */
  96     OUT_BCS_BATCH(batch,
  97                   (0 << 20) | /* round flag in PB slice */
  98                   (0 << 19) | /* round flag in Intra8x8 */
  99                   (0 << 7)  | /* expand NOA bus flag */
 100                   (1 << 6)  | /* must be 1 */
 101                   (0 << 5)  | /* disable clock gating for NOA */
 102                   (0 << 4)  | /* terminate if AVC motion and POC table error occurs */
 103                   (0 << 3)  | /* terminate if AVC mbdata error occurs */
 104                   (0 << 2)  | /* terminate if AVC CABAC/CAVLC decode error occurs */
 105                   (0 << 1)  | /* AVC long field motion vector */
 106                   (0 << 0));  /* always calculate AVC ILDB boundary strength */
 107     OUT_BCS_BATCH(batch, 0);
 108
 109     ADVANCE_BCS_BATCH(batch);
 110 }
 111
 112 static void
 113 gen6_mfc_surface_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 114 {
 115     struct intel_batchbuffer *batch = encoder_context->base.batch;
 116     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 117
 118     BEGIN_BCS_BATCH(batch, 6);
 119
 120     OUT_BCS_BATCH(batch, MFX_SURFACE_STATE | (6 - 2));
 121     OUT_BCS_BATCH(batch, 0);
 122     OUT_BCS_BATCH(batch,
 123                   ((mfc_context->surface_state.height - 1) << 19) |
 124                   ((mfc_context->surface_state.width - 1) << 6));
 125     OUT_BCS_BATCH(batch,
 126                   (MFX_SURFACE_PLANAR_420_8 << 28) | /* 420 planar YUV surface */
 127                   (1 << 27) | /* must be 1 for interleave U/V, hardware requirement */
 128                   (0 << 22) | /* surface object control state, FIXME??? */
 129                   ((mfc_context->surface_state.w_pitch - 1) << 3) | /* pitch */
 130                   (0 << 2)  | /* must be 0 for interleave U/V */
 131                   (1 << 1)  | /* must be y-tiled */
 132                   (I965_TILEWALK_YMAJOR << 0));                         /* tile walk, TILEWALK_YMAJOR */
 133     OUT_BCS_BATCH(batch,
 134                   (0 << 16) |                                                           /* must be 0 for interleave U/V */
 135                   (mfc_context->surface_state.h_pitch));                /* y offset for U(cb) */
 136     OUT_BCS_BATCH(batch, 0);
 137     ADVANCE_BCS_BATCH(batch);
 138 }
 139
 140 void
 141 gen6_mfc_pipe_buf_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 142 {
 143     struct intel_batchbuffer *batch = encoder_context->base.batch;
 144     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 145     int i;
 146
 147     BEGIN_BCS_BATCH(batch, 24);
 148
 149     OUT_BCS_BATCH(batch, MFX_PIPE_BUF_ADDR_STATE | (24 - 2));
 150
 151     if (mfc_context->pre_deblocking_output.bo)
 152         OUT_BCS_RELOC(batch, mfc_context->pre_deblocking_output.bo,
 153                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 154                       0);
 155     else
 156         OUT_BCS_BATCH(batch, 0);                                                                                        /* pre output addr   */
 157
 158     if (mfc_context->post_deblocking_output.bo)
 159         OUT_BCS_RELOC(batch, mfc_context->post_deblocking_output.bo,
 160                       I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 161                       0);                                                                                       /* post output addr  */
 162     else
 163         OUT_BCS_BATCH(batch, 0);
 164
 165     OUT_BCS_RELOC(batch, mfc_context->uncompressed_picture_source.bo,
 166                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 167                   0);                                                                                   /* uncompressed data */
 168     OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
 169                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 170                   0);                                                                                   /* StreamOut data*/
 171     OUT_BCS_RELOC(batch, mfc_context->intra_row_store_scratch_buffer.bo,
 172                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 173                   0);
 174     OUT_BCS_RELOC(batch, mfc_context->deblocking_filter_row_store_scratch_buffer.bo,
 175                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 176                   0);
 177     /* 7..22 Reference pictures*/
 178     for (i = 0; i < ARRAY_ELEMS(mfc_context->reference_surfaces); i++) {
 179         if ( mfc_context->reference_surfaces[i].bo != NULL) {
 180             OUT_BCS_RELOC(batch, mfc_context->reference_surfaces[i].bo,
 181                           I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 182                           0);
 183         } else {
 184             OUT_BCS_BATCH(batch, 0);
 185         }
 186     }
 187     OUT_BCS_RELOC(batch, mfc_context->macroblock_status_buffer.bo,
 188                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 189                   0);                                                                                   /* Macroblock status buffer*/
 190
 191     ADVANCE_BCS_BATCH(batch);
 192 }
 193
 194 static void
 195 gen6_mfc_ind_obj_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 196 {
 197     struct intel_batchbuffer *batch = encoder_context->base.batch;
 198     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 199     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 200
 201     BEGIN_BCS_BATCH(batch, 11);
 202
 203     OUT_BCS_BATCH(batch, MFX_IND_OBJ_BASE_ADDR_STATE | (11 - 2));
 204     OUT_BCS_BATCH(batch, 0);
 205     OUT_BCS_BATCH(batch, 0);
 206     /* MFX Indirect MV Object Base Address */
 207     OUT_BCS_RELOC(batch, vme_context->vme_output.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
 208     OUT_BCS_BATCH(batch, 0);
 209     OUT_BCS_BATCH(batch, 0);
 210     OUT_BCS_BATCH(batch, 0);
 211     OUT_BCS_BATCH(batch, 0);
 212     OUT_BCS_BATCH(batch, 0);
 213     /*MFC Indirect PAK-BSE Object Base Address for Encoder*/
 214     OUT_BCS_RELOC(batch,
 215                   mfc_context->mfc_indirect_pak_bse_object.bo,
 216                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 217                   0);
 218     OUT_BCS_RELOC(batch,
 219                   mfc_context->mfc_indirect_pak_bse_object.bo,
 220                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 221                   mfc_context->mfc_indirect_pak_bse_object.end_offset);
 222
 223     ADVANCE_BCS_BATCH(batch);
 224 }
 225
 226 void
 227 gen6_mfc_bsp_buf_base_addr_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 228 {
 229     struct intel_batchbuffer *batch = encoder_context->base.batch;
 230     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 231
 232     BEGIN_BCS_BATCH(batch, 4);
 233
 234     OUT_BCS_BATCH(batch, MFX_BSP_BUF_BASE_ADDR_STATE | (4 - 2));
 235     OUT_BCS_RELOC(batch, mfc_context->bsd_mpc_row_store_scratch_buffer.bo,
 236                   I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
 237                   0);
 238     OUT_BCS_BATCH(batch, 0);
 239     OUT_BCS_BATCH(batch, 0);
 240
 241     ADVANCE_BCS_BATCH(batch);
 242 }
 243
 244 static void
 245 gen6_mfc_avc_img_state(VADriverContextP ctx,struct encode_state *encode_state,
 246                        struct intel_encoder_context *encoder_context)
 247 {
 248     struct intel_batchbuffer *batch = encoder_context->base.batch;
 249     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 250     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 251     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 252     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 253     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 254
 255     BEGIN_BCS_BATCH(batch, 13);
 256     OUT_BCS_BATCH(batch, MFX_AVC_IMG_STATE | (13 - 2));
 257     OUT_BCS_BATCH(batch,
 258                   ((width_in_mbs * height_in_mbs) & 0xFFFF));
 259     OUT_BCS_BATCH(batch,
 260                   (height_in_mbs << 16) |
 261                   (width_in_mbs << 0));
 262     OUT_BCS_BATCH(batch,
 263                   (0 << 24) |     /*Second Chroma QP Offset*/
 264                   (0 << 16) |     /*Chroma QP Offset*/
 265                   (0 << 14) |   /*Max-bit conformance Intra flag*/
 266                   (0 << 13) |   /*Max Macroblock size conformance Inter flag*/
 267                   (1 << 12) |   /*Should always be written as "1" */
 268                   (0 << 10) |   /*QM Preset FLag */
 269                   (0 << 8)  |   /*Image Structure*/
 270                   (0 << 0) );   /*Current Decoed Image Frame Store ID, reserved in Encode mode*/
 271     OUT_BCS_BATCH(batch,
 272                   (400 << 16) |   /*Mininum Frame size*/
 273                   (0 << 15) |   /*Disable reading of Macroblock Status Buffer*/
 274                   (0 << 14) |   /*Load BitStream Pointer only once, 1 slic 1 frame*/
 275                   (0 << 13) |   /*CABAC 0 word insertion test enable*/
 276                   (1 << 12) |   /*MVUnpackedEnable,compliant to DXVA*/
 277                   (1 << 10) |   /*Chroma Format IDC, 4:2:0*/
 278                   (pPicParameter->pic_fields.bits.entropy_coding_mode_flag << 7)  |   /*0:CAVLC encoding mode,1:CABAC*/
 279                   (0 << 6)  |   /*Only valid for VLD decoding mode*/
 280                   (0 << 5)  |   /*Constrained Intra Predition Flag, from PPS*/
 281                   (pSequenceParameter->seq_fields.bits.direct_8x8_inference_flag << 4)  |   /*Direct 8x8 inference flag*/
 282                   (pPicParameter->pic_fields.bits.transform_8x8_mode_flag << 3)  |   /*8x8 or 4x4 IDCT Transform Mode Flag*/
 283                   (1 << 2)  |   /*Frame MB only flag*/
 284                   (0 << 1)  |   /*MBAFF mode is in active*/
 285                   (0 << 0) );   /*Field picture flag*/
 286     OUT_BCS_BATCH(batch,
 287                   (1<<16)   |   /*Frame Size Rate Control Flag*/
 288                   (1<<12)   |
 289                   (1<<9)    |   /*MB level Rate Control Enabling Flag*/
 290                   (1 << 3)  |   /*FrameBitRateMinReportMask*/
 291                   (1 << 2)  |   /*FrameBitRateMaxReportMask*/
 292                   (1 << 1)  |   /*InterMBMaxSizeReportMask*/
 293                   (1 << 0) );   /*IntraMBMaxSizeReportMask*/
 294     OUT_BCS_BATCH(batch,                        /*Inter and Intra Conformance Max size limit*/
 295                   (0x0600 << 16) |              /*InterMbMaxSz 192 Byte*/
 296                   (0x0800) );                   /*IntraMbMaxSz 256 Byte*/
 297     OUT_BCS_BATCH(batch, 0x00000000);   /*Reserved : MBZReserved*/
 298     OUT_BCS_BATCH(batch, 0x01020304);   /*Slice QP Delta for bitrate control*/
 299     OUT_BCS_BATCH(batch, 0xFEFDFCFB);
 300     OUT_BCS_BATCH(batch, 0x80601004);   /*MAX = 128KB, MIN = 64KB*/
 301     OUT_BCS_BATCH(batch, 0x00800001);
 302     OUT_BCS_BATCH(batch, 0);
 303
 304     ADVANCE_BCS_BATCH(batch);
 305 }
 306
 307 static void
 308 gen6_mfc_avc_directmode_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 309 {
 310     struct intel_batchbuffer *batch = encoder_context->base.batch;
 311     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 312
 313     int i;
 314
 315     BEGIN_BCS_BATCH(batch, 69);
 316
 317     OUT_BCS_BATCH(batch, MFX_AVC_DIRECTMODE_STATE | (69 - 2));
 318
 319     /* Reference frames and Current frames */
 320     for(i = 0; i < NUM_MFC_DMV_BUFFERS; i++) {
 321         if ( mfc_context->direct_mv_buffers[i].bo != NULL) {
 322             OUT_BCS_RELOC(batch, mfc_context->direct_mv_buffers[i].bo,
 323                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 324                           0);
 325         } else {
 326             OUT_BCS_BATCH(batch, 0);
 327         }
 328     }
 329
 330     /* POL list */
 331     for(i = 0; i < 32; i++) {
 332         OUT_BCS_BATCH(batch, i/2);
 333     }
 334     OUT_BCS_BATCH(batch, 0);
 335     OUT_BCS_BATCH(batch, 0);
 336
 337     ADVANCE_BCS_BATCH(batch);
 338 }
 339
 340 static void
 341 gen6_mfc_avc_slice_state(VADriverContextP ctx,
 342                          VAEncPictureParameterBufferH264 *pic_param,
 343                          VAEncSliceParameterBufferH264 *slice_param,
 344                          struct encode_state *encode_state,
 345                          struct intel_encoder_context *encoder_context,
 346                          int rate_control_enable,
 347                          int qp,
 348                          struct intel_batchbuffer *batch)
 349 {
 350     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 351     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 352     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 353     int beginmb = slice_param->macroblock_address;
 354     int endmb = beginmb + slice_param->num_macroblocks;
 355     int beginx = beginmb % width_in_mbs;
 356     int beginy = beginmb / width_in_mbs;
 357     int nextx =  endmb % width_in_mbs;
 358     int nexty = endmb / width_in_mbs;
 359     int slice_type = intel_avc_enc_slice_type_fixup(slice_param->slice_type);
 360     int last_slice = (endmb == (width_in_mbs * height_in_mbs));
 361     int maxQpN, maxQpP;
 362     unsigned char correct[6], grow, shrink;
 363     int i;
 364     int weighted_pred_idc = 0;
 365     unsigned int luma_log2_weight_denom = slice_param->luma_log2_weight_denom;
 366     unsigned int chroma_log2_weight_denom = slice_param->chroma_log2_weight_denom;
 367     int num_ref_l0 = 0, num_ref_l1 = 0;
 368
 369     if (batch == NULL)
 370         batch = encoder_context->base.batch;
 371
 372     if (slice_type == SLICE_TYPE_I) {
 373         luma_log2_weight_denom = 0;
 374         chroma_log2_weight_denom = 0;
 375     } else if (slice_type == SLICE_TYPE_P) {
 376         weighted_pred_idc = pic_param->pic_fields.bits.weighted_pred_flag;
 377         num_ref_l0 = pic_param->num_ref_idx_l0_active_minus1 + 1;
 378
 379         if (slice_param->num_ref_idx_active_override_flag)
 380             num_ref_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
 381     } else if (slice_type == SLICE_TYPE_B) {
 382         weighted_pred_idc = pic_param->pic_fields.bits.weighted_bipred_idc;
 383         num_ref_l0 = pic_param->num_ref_idx_l0_active_minus1 + 1;
 384         num_ref_l1 = pic_param->num_ref_idx_l1_active_minus1 + 1;
 385
 386         if (slice_param->num_ref_idx_active_override_flag) {
 387             num_ref_l0 = slice_param->num_ref_idx_l0_active_minus1 + 1;
 388             num_ref_l1 = slice_param->num_ref_idx_l1_active_minus1 + 1;
 389         }
 390
 391         if (weighted_pred_idc == 2) {
 392             /* 8.4.3 - Derivation process for prediction weights (8-279) */
 393             luma_log2_weight_denom = 5;
 394             chroma_log2_weight_denom = 5;
 395         }
 396     }
 397
 398     maxQpN = mfc_context->bit_rate_control_context[slice_type].MaxQpNegModifier;
 399     maxQpP = mfc_context->bit_rate_control_context[slice_type].MaxQpPosModifier;
 400
 401     for (i = 0; i < 6; i++)
 402         correct[i] = mfc_context->bit_rate_control_context[slice_type].Correct[i];
 403
 404     grow = mfc_context->bit_rate_control_context[slice_type].GrowInit +
 405         (mfc_context->bit_rate_control_context[slice_type].GrowResistance << 4);
 406     shrink = mfc_context->bit_rate_control_context[slice_type].ShrinkInit +
 407         (mfc_context->bit_rate_control_context[slice_type].ShrinkResistance << 4);
 408
 409     BEGIN_BCS_BATCH(batch, 11);;
 410
 411     OUT_BCS_BATCH(batch, MFX_AVC_SLICE_STATE | (11 - 2) );
 412     OUT_BCS_BATCH(batch, slice_type);                   /*Slice Type: I:P:B Slice*/
 413
 414     OUT_BCS_BATCH(batch,
 415                   (num_ref_l0 << 16) |
 416                   (num_ref_l1 << 24) |
 417                   (chroma_log2_weight_denom << 8) |
 418                   (luma_log2_weight_denom << 0));
 419
 420     OUT_BCS_BATCH(batch,
 421                   (weighted_pred_idc << 30) |
 422                   (slice_param->direct_spatial_mv_pred_flag<<29) |             /*Direct Prediction Type*/
 423                   (slice_param->disable_deblocking_filter_idc << 27) |
 424                   (slice_param->cabac_init_idc << 24) |
 425                   (qp<<16) |                    /*Slice Quantization Parameter*/
 426                   ((slice_param->slice_beta_offset_div2 & 0xf) << 8) |
 427                   ((slice_param->slice_alpha_c0_offset_div2 & 0xf) << 0));
 428     OUT_BCS_BATCH(batch,
 429                   (beginy << 24) |                      /*First MB X&Y , the begin postion of current slice*/
 430                   (beginx << 16) |
 431                   slice_param->macroblock_address );
 432     OUT_BCS_BATCH(batch, (nexty << 16) | nextx);                       /*Next slice first MB X&Y*/
 433     OUT_BCS_BATCH(batch,
 434                   (0/*rate_control_enable*/ << 31) |            /*in CBR mode RateControlCounterEnable = enable*/
 435                   (1 << 30) |           /*ResetRateControlCounter*/
 436                   (0 << 28) |           /*RC Triggle Mode = Always Rate Control*/
 437                   (4 << 24) |     /*RC Stable Tolerance, middle level*/
 438                   (0/*rate_control_enable*/ << 23) |     /*RC Panic Enable*/
 439                   (0 << 22) |     /*QP mode, don't modfiy CBP*/
 440                   (0 << 21) |     /*MB Type Direct Conversion Enabled*/
 441                   (0 << 20) |     /*MB Type Skip Conversion Enabled*/
 442                   (last_slice << 19) |     /*IsLastSlice*/
 443                   (0 << 18) |   /*BitstreamOutputFlag Compressed BitStream Output Disable Flag 0:enable 1:disable*/
 444                   (1 << 17) |       /*HeaderPresentFlag*/
 445                   (1 << 16) |       /*SliceData PresentFlag*/
 446                   (1 << 15) |       /*TailPresentFlag*/
 447                   (1 << 13) |       /*RBSP NAL TYPE*/
 448                   (0 << 12) );    /*CabacZeroWordInsertionEnable*/
 449     OUT_BCS_BATCH(batch, mfc_context->mfc_indirect_pak_bse_object.offset);
 450     OUT_BCS_BATCH(batch,
 451                   (maxQpN << 24) |     /*Target QP - 24 is lowest QP*/
 452                   (maxQpP << 16) |     /*Target QP + 20 is highest QP*/
 453                   (shrink << 8)  |
 454                   (grow << 0));
 455     OUT_BCS_BATCH(batch,
 456                   (correct[5] << 20) |
 457                   (correct[4] << 16) |
 458                   (correct[3] << 12) |
 459                   (correct[2] << 8) |
 460                   (correct[1] << 4) |
 461                   (correct[0] << 0));
 462     OUT_BCS_BATCH(batch, 0);
 463
 464     ADVANCE_BCS_BATCH(batch);
 465 }
 466
 467 static void gen6_mfc_avc_qm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 468 {
 469     struct intel_batchbuffer *batch = encoder_context->base.batch;
 470     int i;
 471
 472     BEGIN_BCS_BATCH(batch, 58);
 473
 474     OUT_BCS_BATCH(batch, MFX_AVC_QM_STATE | 56);
 475     OUT_BCS_BATCH(batch, 0xFF ) ;
 476     for( i = 0; i < 56; i++) {
 477         OUT_BCS_BATCH(batch, 0x10101010);
 478     }
 479
 480     ADVANCE_BCS_BATCH(batch);
 481 }
 482
 483 static void gen6_mfc_avc_fqm_state(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
 484 {
 485     struct intel_batchbuffer *batch = encoder_context->base.batch;
 486     int i;
 487
 488     BEGIN_BCS_BATCH(batch, 113);
 489     OUT_BCS_BATCH(batch, MFC_AVC_FQM_STATE | (113 - 2));
 490
 491     for(i = 0; i < 112;i++) {
 492         OUT_BCS_BATCH(batch, 0x10001000);
 493     }
 494
 495     ADVANCE_BCS_BATCH(batch);
 496 }
 497
 498 static void
 499 gen6_mfc_avc_insert_object(VADriverContextP ctx, struct intel_encoder_context *encoder_context,
 500                            unsigned int *insert_data, int lenght_in_dws, int data_bits_in_last_dw,
 501                            int skip_emul_byte_count, int is_last_header, int is_end_of_slice, int emulation_flag,
 502                            struct intel_batchbuffer *batch)
 503 {
 504     if (batch == NULL)
 505         batch = encoder_context->base.batch;
 506
 507     BEGIN_BCS_BATCH(batch, lenght_in_dws + 2);
 508
 509     OUT_BCS_BATCH(batch, MFC_AVC_INSERT_OBJECT | (lenght_in_dws + 2 - 2));
 510
 511     OUT_BCS_BATCH(batch,
 512                   (0 << 16) |   /* always start at offset 0 */
 513                   (data_bits_in_last_dw << 8) |
 514                   (skip_emul_byte_count << 4) |
 515                   (!!emulation_flag << 3) |
 516                   ((!!is_last_header) << 2) |
 517                   ((!!is_end_of_slice) << 1) |
 518                   (0 << 0));    /* FIXME: ??? */
 519
 520     intel_batchbuffer_data(batch, insert_data, lenght_in_dws * 4);
 521     ADVANCE_BCS_BATCH(batch);
 522 }
 523
 524 void
 525 gen6_mfc_init(VADriverContextP ctx,
 526               struct encode_state *encode_state,
 527               struct intel_encoder_context *encoder_context)
 528 {
 529     struct i965_driver_data *i965 = i965_driver_data(ctx);
 530     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 531     dri_bo *bo;
 532     int i;
 533     int width_in_mbs = 0;
 534     int height_in_mbs = 0;
 535     int slice_batchbuffer_size;
 536
 537     if (encoder_context->codec == CODEC_H264) {
 538         VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 539         width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 540         height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 541     } else {
 542         VAEncSequenceParameterBufferMPEG2 *pSequenceParameter = (VAEncSequenceParameterBufferMPEG2 *)encode_state->seq_param_ext->buffer;
 543
 544         assert(encoder_context->codec == CODEC_MPEG2);
 545
 546         width_in_mbs = ALIGN(pSequenceParameter->picture_width, 16) / 16;
 547         height_in_mbs = ALIGN(pSequenceParameter->picture_height, 16) / 16;
 548     }
 549
 550     slice_batchbuffer_size = 64 * width_in_mbs * height_in_mbs + 4096 +
 551                 (SLICE_HEADER + SLICE_TAIL) * encode_state->num_slice_params_ext;
 552
 553     /*Encode common setup for MFC*/
 554     dri_bo_unreference(mfc_context->post_deblocking_output.bo);
 555     mfc_context->post_deblocking_output.bo = NULL;
 556
 557     dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
 558     mfc_context->pre_deblocking_output.bo = NULL;
 559
 560     dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
 561     mfc_context->uncompressed_picture_source.bo = NULL;
 562
 563     dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
 564     mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
 565
 566     for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
 567         if ( mfc_context->direct_mv_buffers[i].bo != NULL);
 568         dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
 569         mfc_context->direct_mv_buffers[i].bo = NULL;
 570     }
 571
 572     for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
 573         if (mfc_context->reference_surfaces[i].bo != NULL)
 574             dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
 575         mfc_context->reference_surfaces[i].bo = NULL;
 576     }
 577
 578     dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
 579     bo = dri_bo_alloc(i965->intel.bufmgr,
 580                       "Buffer",
 581                       width_in_mbs * 64,
 582                       64);
 583     assert(bo);
 584     mfc_context->intra_row_store_scratch_buffer.bo = bo;
 585
 586     dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
 587     bo = dri_bo_alloc(i965->intel.bufmgr,
 588                       "Buffer",
 589                       width_in_mbs * height_in_mbs * 16,
 590                       64);
 591     assert(bo);
 592     mfc_context->macroblock_status_buffer.bo = bo;
 593
 594     dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
 595     bo = dri_bo_alloc(i965->intel.bufmgr,
 596                       "Buffer",
 597                       4 * width_in_mbs * 64,  /* 4 * width_in_mbs * 64 */
 598                       64);
 599     assert(bo);
 600     mfc_context->deblocking_filter_row_store_scratch_buffer.bo = bo;
 601
 602     dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
 603     bo = dri_bo_alloc(i965->intel.bufmgr,
 604                       "Buffer",
 605                       128 * width_in_mbs, /* 2 * widht_in_mbs * 64 */
 606                       0x1000);
 607     assert(bo);
 608     mfc_context->bsd_mpc_row_store_scratch_buffer.bo = bo;
 609
 610     dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo);
 611     mfc_context->mfc_batchbuffer_surface.bo = NULL;
 612
 613     dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo);
 614     mfc_context->aux_batchbuffer_surface.bo = NULL;
 615
 616     if (mfc_context->aux_batchbuffer)
 617         intel_batchbuffer_free(mfc_context->aux_batchbuffer);
 618
 619     mfc_context->aux_batchbuffer = intel_batchbuffer_new(&i965->intel, I915_EXEC_BSD,
 620                                                          slice_batchbuffer_size);
 621     mfc_context->aux_batchbuffer_surface.bo = mfc_context->aux_batchbuffer->buffer;
 622     dri_bo_reference(mfc_context->aux_batchbuffer_surface.bo);
 623     mfc_context->aux_batchbuffer_surface.pitch = 16;
 624     mfc_context->aux_batchbuffer_surface.num_blocks = mfc_context->aux_batchbuffer->size / 16;
 625     mfc_context->aux_batchbuffer_surface.size_block = 16;
 626
 627     i965_gpe_context_init(ctx, &mfc_context->gpe_context);
 628 }
 629
 630 static void gen6_mfc_avc_pipeline_picture_programing( VADriverContextP ctx,
 631                                                       struct encode_state *encode_state,
 632                                                       struct intel_encoder_context *encoder_context)
 633 {
 634     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 635
 636     mfc_context->pipe_mode_select(ctx, MFX_FORMAT_AVC, encoder_context);
 637     mfc_context->set_surface_state(ctx, encoder_context);
 638     mfc_context->ind_obj_base_addr_state(ctx, encoder_context);
 639     gen6_mfc_pipe_buf_addr_state(ctx, encoder_context);
 640     gen6_mfc_bsp_buf_base_addr_state(ctx, encoder_context);
 641     mfc_context->avc_img_state(ctx, encode_state, encoder_context);
 642     mfc_context->avc_qm_state(ctx, encoder_context);
 643     mfc_context->avc_fqm_state(ctx, encoder_context);
 644     gen6_mfc_avc_directmode_state(ctx, encoder_context);
 645     intel_mfc_avc_ref_idx_state(ctx, encode_state, encoder_context);
 646 }
 647
 648
 649 VAStatus
 650 gen6_mfc_run(VADriverContextP ctx,
 651              struct encode_state *encode_state,
 652              struct intel_encoder_context *encoder_context)
 653 {
 654     struct intel_batchbuffer *batch = encoder_context->base.batch;
 655
 656     intel_batchbuffer_flush(batch);             //run the pipeline
 657
 658     return VA_STATUS_SUCCESS;
 659 }
 660
 661 VAStatus
 662 gen6_mfc_stop(VADriverContextP ctx,
 663               struct encode_state *encode_state,
 664               struct intel_encoder_context *encoder_context,
 665               int *encoded_bits_size)
 666 {
 667     VAStatus vaStatus = VA_STATUS_ERROR_UNKNOWN;
 668     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 669     VACodedBufferSegment *coded_buffer_segment;
 670
 671     vaStatus = i965_MapBuffer(ctx, pPicParameter->coded_buf, (void **)&coded_buffer_segment);
 672     assert(vaStatus == VA_STATUS_SUCCESS);
 673     *encoded_bits_size = coded_buffer_segment->size * 8;
 674     i965_UnmapBuffer(ctx, pPicParameter->coded_buf);
 675
 676     return VA_STATUS_SUCCESS;
 677 }
 678
 679 #if __SOFTWARE__
 680
 681 static int
 682 gen6_mfc_avc_pak_object_intra(VADriverContextP ctx, int x, int y, int end_mb, int qp,unsigned int *msg,
 683                               struct intel_encoder_context *encoder_context,
 684                               unsigned char target_mb_size, unsigned char max_mb_size,
 685                               struct intel_batchbuffer *batch)
 686 {
 687     int len_in_dwords = 11;
 688
 689     if (batch == NULL)
 690         batch = encoder_context->base.batch;
 691
 692     BEGIN_BCS_BATCH(batch, len_in_dwords);
 693
 694     OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
 695     OUT_BCS_BATCH(batch, 0);
 696     OUT_BCS_BATCH(batch, 0);
 697     OUT_BCS_BATCH(batch,
 698                   (0 << 24) |           /* PackedMvNum, Debug*/
 699                   (0 << 20) |           /* No motion vector */
 700                   (1 << 19) |           /* CbpDcY */
 701                   (1 << 18) |           /* CbpDcU */
 702                   (1 << 17) |           /* CbpDcV */
 703                   (msg[0] & 0xFFFF) );
 704
 705     OUT_BCS_BATCH(batch, (0xFFFF << 16) | (y << 8) | x);                /* Code Block Pattern for Y*/
 706     OUT_BCS_BATCH(batch, 0x000F000F);                                                   /* Code Block Pattern */
 707     OUT_BCS_BATCH(batch, (0 << 27) | (end_mb << 26) | qp);      /* Last MB */
 708
 709     /*Stuff for Intra MB*/
 710     OUT_BCS_BATCH(batch, msg[1]);                       /* We using Intra16x16 no 4x4 predmode*/
 711     OUT_BCS_BATCH(batch, msg[2]);
 712     OUT_BCS_BATCH(batch, msg[3]&0xFC);
 713
 714     /*MaxSizeInWord and TargetSzieInWord*/
 715     OUT_BCS_BATCH(batch, (max_mb_size << 24) |
 716                   (target_mb_size << 16) );
 717
 718     ADVANCE_BCS_BATCH(batch);
 719
 720     return len_in_dwords;
 721 }
 722
 723 static int
 724 gen6_mfc_avc_pak_object_inter(VADriverContextP ctx, int x, int y, int end_mb, int qp,
 725                               unsigned int *msg, unsigned int offset,
 726                               struct intel_encoder_context *encoder_context,
 727                               unsigned char target_mb_size,unsigned char max_mb_size, int slice_type,
 728                               struct intel_batchbuffer *batch)
 729 {
 730     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 731     int len_in_dwords = 11;
 732
 733     if (batch == NULL)
 734         batch = encoder_context->base.batch;
 735
 736     BEGIN_BCS_BATCH(batch, len_in_dwords);
 737
 738     OUT_BCS_BATCH(batch, MFC_AVC_PAK_OBJECT | (len_in_dwords - 2));
 739
 740     OUT_BCS_BATCH(batch, msg[2]);         /* 32 MV*/
 741     OUT_BCS_BATCH(batch, offset);
 742
 743     OUT_BCS_BATCH(batch, msg[0]);
 744
 745     OUT_BCS_BATCH(batch, (0xFFFF<<16) | (y << 8) | x);        /* Code Block Pattern for Y*/
 746     OUT_BCS_BATCH(batch, 0x000F000F);                         /* Code Block Pattern */
 747 #if 0
 748     if ( slice_type == SLICE_TYPE_B) {
 749         OUT_BCS_BATCH(batch, (0xF<<28) | (end_mb << 26) | qp);  /* Last MB */
 750     } else {
 751         OUT_BCS_BATCH(batch, (end_mb << 26) | qp);      /* Last MB */
 752     }
 753 #else
 754     OUT_BCS_BATCH(batch, (end_mb << 26) | qp);  /* Last MB */
 755 #endif
 756
 757
 758     /*Stuff for Inter MB*/
 759     OUT_BCS_BATCH(batch, msg[1]);
 760     OUT_BCS_BATCH(batch, vme_context->ref_index_in_mb[0]);
 761     OUT_BCS_BATCH(batch, vme_context->ref_index_in_mb[1]);
 762
 763     /*MaxSizeInWord and TargetSzieInWord*/
 764     OUT_BCS_BATCH(batch, (max_mb_size << 24) |
 765                   (target_mb_size << 16) );
 766
 767     ADVANCE_BCS_BATCH(batch);
 768
 769     return len_in_dwords;
 770 }
 771
 772 static void
 773 gen6_mfc_avc_pipeline_slice_programing(VADriverContextP ctx,
 774                                        struct encode_state *encode_state,
 775                                        struct intel_encoder_context *encoder_context,
 776                                        int slice_index,
 777                                        struct intel_batchbuffer *slice_batch)
 778 {
 779     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 780     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 781     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 782     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
 783     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
 784     unsigned int *msg = NULL, offset = 0;
 785     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
 786     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
 787     int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs);
 788     int i,x,y;
 789     int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta;
 790     unsigned int rate_control_mode = encoder_context->rate_control_mode;
 791     unsigned int tail_data[] = { 0x0, 0x0 };
 792     int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type);
 793     int is_intra = slice_type == SLICE_TYPE_I;
 794     int qp_slice;
 795
 796     qp_slice = qp;
 797     if (rate_control_mode == VA_RC_CBR) {
 798         qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
 799         if (encode_state->slice_header_index[slice_index] == 0) {
 800             pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp;
 801             qp_slice = qp;
 802         }
 803     }
 804
 805     /* only support for 8-bit pixel bit-depth */
 806     assert(pSequenceParameter->bit_depth_luma_minus8 == 0);
 807     assert(pSequenceParameter->bit_depth_chroma_minus8 == 0);
 808     assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52);
 809     assert(qp >= 0 && qp < 52);
 810
 811     gen6_mfc_avc_slice_state(ctx,
 812                              pPicParameter,
 813                              pSliceParameter,
 814                              encode_state, encoder_context,
 815                              (rate_control_mode == VA_RC_CBR), qp_slice, slice_batch);
 816
 817     if ( slice_index == 0)
 818         intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch);
 819
 820     intel_avc_slice_insert_packed_data(ctx, encode_state, encoder_context, slice_index, slice_batch);
 821
 822     dri_bo_map(vme_context->vme_output.bo , 1);
 823     msg = (unsigned int *)vme_context->vme_output.bo->virtual;
 824
 825     if (is_intra) {
 826         msg += pSliceParameter->macroblock_address * INTRA_VME_OUTPUT_IN_DWS;
 827     } else {
 828         msg += pSliceParameter->macroblock_address * INTER_VME_OUTPUT_IN_DWS;
 829         msg += 32; /* the first 32 DWs are MVs */
 830         offset = pSliceParameter->macroblock_address * INTER_VME_OUTPUT_IN_BYTES;
 831     }
 832
 833     for (i = pSliceParameter->macroblock_address;
 834          i < pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks; i++) {
 835         int last_mb = (i == (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks - 1) );
 836         x = i % width_in_mbs;
 837         y = i / width_in_mbs;
 838
 839         if (is_intra) {
 840             assert(msg);
 841             gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch);
 842             msg += INTRA_VME_OUTPUT_IN_DWS;
 843         } else {
 844             if (msg[0] & INTRA_MB_FLAG_MASK) {
 845                 gen6_mfc_avc_pak_object_intra(ctx, x, y, last_mb, qp, msg, encoder_context, 0, 0, slice_batch);
 846             } else {
 847                 gen6_mfc_avc_pak_object_inter(ctx, x, y, last_mb, qp, msg, offset, encoder_context, 0, 0, slice_type, slice_batch);
 848             }
 849
 850             msg += INTER_VME_OUTPUT_IN_DWS;
 851             offset += INTER_VME_OUTPUT_IN_BYTES;
 852         }
 853     }
 854
 855     dri_bo_unmap(vme_context->vme_output.bo);
 856
 857     if ( last_slice ) {
 858         mfc_context->insert_object(ctx, encoder_context,
 859                                    tail_data, 2, 8,
 860                                    2, 1, 1, 0, slice_batch);
 861     } else {
 862         mfc_context->insert_object(ctx, encoder_context,
 863                                    tail_data, 1, 8,
 864                                    1, 1, 1, 0, slice_batch);
 865     }
 866
 867
 868 }
 869
 870 static dri_bo *
 871 gen6_mfc_avc_software_batchbuffer(VADriverContextP ctx,
 872                                   struct encode_state *encode_state,
 873                                   struct intel_encoder_context *encoder_context)
 874 {
 875     struct i965_driver_data *i965 = i965_driver_data(ctx);
 876     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 877     struct intel_batchbuffer *batch;;
 878     dri_bo *batch_bo;
 879     int i;
 880
 881     batch = mfc_context->aux_batchbuffer;
 882     batch_bo = batch->buffer;
 883
 884     for (i = 0; i < encode_state->num_slice_params_ext; i++) {
 885         gen6_mfc_avc_pipeline_slice_programing(ctx, encode_state, encoder_context, i, batch);
 886     }
 887
 888     intel_batchbuffer_align(batch, 8);
 889
 890     BEGIN_BCS_BATCH(batch, 2);
 891     OUT_BCS_BATCH(batch, 0);
 892     OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_END);
 893     ADVANCE_BCS_BATCH(batch);
 894
 895     dri_bo_reference(batch_bo);
 896
 897     intel_batchbuffer_free(batch);
 898     mfc_context->aux_batchbuffer = NULL;
 899
 900     return batch_bo;
 901 }
 902
 903 #else
 904
 905 static void
 906 gen6_mfc_batchbuffer_surfaces_input(VADriverContextP ctx,
 907                                     struct encode_state *encode_state,
 908                                     struct intel_encoder_context *encoder_context)
 909
 910 {
 911     struct gen6_vme_context *vme_context = encoder_context->vme_context;
 912     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 913
 914     assert(vme_context->vme_output.bo);
 915     mfc_context->buffer_suface_setup(ctx,
 916                                      &mfc_context->gpe_context,
 917                                      &vme_context->vme_output,
 918                                      BINDING_TABLE_OFFSET(BIND_IDX_VME_OUTPUT),
 919                                      SURFACE_STATE_OFFSET(BIND_IDX_VME_OUTPUT));
 920     assert(mfc_context->aux_batchbuffer_surface.bo);
 921     mfc_context->buffer_suface_setup(ctx,
 922                                      &mfc_context->gpe_context,
 923                                      &mfc_context->aux_batchbuffer_surface,
 924                                      BINDING_TABLE_OFFSET(BIND_IDX_MFC_SLICE_HEADER),
 925                                      SURFACE_STATE_OFFSET(BIND_IDX_MFC_SLICE_HEADER));
 926 }
 927
 928 static void
 929 gen6_mfc_batchbuffer_surfaces_output(VADriverContextP ctx,
 930                                      struct encode_state *encode_state,
 931                                      struct intel_encoder_context *encoder_context)
 932
 933 {
 934     struct i965_driver_data *i965 = i965_driver_data(ctx);
 935     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 936     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
 937     int width_in_mbs = pSequenceParameter->picture_width_in_mbs;
 938     int height_in_mbs = pSequenceParameter->picture_height_in_mbs;
 939     mfc_context->mfc_batchbuffer_surface.num_blocks = width_in_mbs * height_in_mbs + encode_state->num_slice_params_ext * 8 + 1;
 940     mfc_context->mfc_batchbuffer_surface.size_block = 16 * CMD_LEN_IN_OWORD; /* 3 OWORDs */
 941     mfc_context->mfc_batchbuffer_surface.pitch = 16;
 942     mfc_context->mfc_batchbuffer_surface.bo = dri_bo_alloc(i965->intel.bufmgr,
 943                                                            "MFC batchbuffer",
 944                                                            mfc_context->mfc_batchbuffer_surface.num_blocks * mfc_context->mfc_batchbuffer_surface.size_block,
 945                                                            0x1000);
 946     mfc_context->buffer_suface_setup(ctx,
 947                                      &mfc_context->gpe_context,
 948                                      &mfc_context->mfc_batchbuffer_surface,
 949                                      BINDING_TABLE_OFFSET(BIND_IDX_MFC_BATCHBUFFER),
 950                                      SURFACE_STATE_OFFSET(BIND_IDX_MFC_BATCHBUFFER));
 951 }
 952
 953 static void
 954 gen6_mfc_batchbuffer_surfaces_setup(VADriverContextP ctx,
 955                                     struct encode_state *encode_state,
 956                                     struct intel_encoder_context *encoder_context)
 957 {
 958     gen6_mfc_batchbuffer_surfaces_input(ctx, encode_state, encoder_context);
 959     gen6_mfc_batchbuffer_surfaces_output(ctx, encode_state, encoder_context);
 960 }
 961
 962 static void
 963 gen6_mfc_batchbuffer_idrt_setup(VADriverContextP ctx,
 964                                 struct encode_state *encode_state,
 965                                 struct intel_encoder_context *encoder_context)
 966 {
 967     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
 968     struct gen6_interface_descriptor_data *desc;
 969     int i;
 970     dri_bo *bo;
 971
 972     bo = mfc_context->gpe_context.idrt.bo;
 973     dri_bo_map(bo, 1);
 974     assert(bo->virtual);
 975     desc = bo->virtual;
 976
 977     for (i = 0; i < mfc_context->gpe_context.num_kernels; i++) {
 978         struct i965_kernel *kernel;
 979
 980         kernel = &mfc_context->gpe_context.kernels[i];
 981         assert(sizeof(*desc) == 32);
 982
 983         /*Setup the descritor table*/
 984         memset(desc, 0, sizeof(*desc));
 985         desc->desc0.kernel_start_pointer = (kernel->bo->offset >> 6);
 986         desc->desc2.sampler_count = 0;
 987         desc->desc2.sampler_state_pointer = 0;
 988         desc->desc3.binding_table_entry_count = 2;
 989         desc->desc3.binding_table_pointer = (BINDING_TABLE_OFFSET(0) >> 5);
 990         desc->desc4.constant_urb_entry_read_offset = 0;
 991         desc->desc4.constant_urb_entry_read_length = 4;
 992
 993         /*kernel start*/
 994         dri_bo_emit_reloc(bo,
 995                           I915_GEM_DOMAIN_INSTRUCTION, 0,
 996                           0,
 997                           i * sizeof(*desc) + offsetof(struct gen6_interface_descriptor_data, desc0),
 998                           kernel->bo);
 999         desc++;
1000     }
1001
1002     dri_bo_unmap(bo);
1003 }
1004
1005 static void
1006 gen6_mfc_batchbuffer_constant_setup(VADriverContextP ctx,
1007                                     struct encode_state *encode_state,
1008                                     struct intel_encoder_context *encoder_context)
1009 {
1010     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1011
1012     (void)mfc_context;
1013 }
1014
1015 static void
1016 gen6_mfc_batchbuffer_emit_object_command(struct intel_batchbuffer *batch,
1017                                          int index,
1018                                          int head_offset,
1019                                          int batchbuffer_offset,
1020                                          int head_size,
1021                                          int tail_size,
1022                                          int number_mb_cmds,
1023                                          int first_object,
1024                                          int last_object,
1025                                          int last_slice,
1026                                          int mb_x,
1027                                          int mb_y,
1028                                          int width_in_mbs,
1029                                          int qp,
1030                                          unsigned int ref_index[2])
1031 {
1032     BEGIN_BATCH(batch, 14);
1033
1034     OUT_BATCH(batch, CMD_MEDIA_OBJECT | (14 - 2));
1035     OUT_BATCH(batch, index);
1036     OUT_BATCH(batch, 0);
1037     OUT_BATCH(batch, 0);
1038     OUT_BATCH(batch, 0);
1039     OUT_BATCH(batch, 0);
1040
1041     /*inline data */
1042     OUT_BATCH(batch, head_offset);
1043     OUT_BATCH(batch, batchbuffer_offset);
1044     OUT_BATCH(batch,
1045               head_size << 16 |
1046               tail_size);
1047     OUT_BATCH(batch,
1048               number_mb_cmds << 16 |
1049               first_object << 2 |
1050               last_object << 1 |
1051               last_slice);
1052     OUT_BATCH(batch,
1053               mb_y << 8 |
1054               mb_x);
1055     OUT_BATCH(batch,
1056               qp << 16 |
1057               width_in_mbs);
1058     OUT_BATCH(batch, ref_index[0]);
1059     OUT_BATCH(batch, ref_index[1]);
1060
1061     ADVANCE_BATCH(batch);
1062 }
1063
1064 static void
1065 gen6_mfc_avc_batchbuffer_slice_command(VADriverContextP ctx,
1066                                        struct intel_encoder_context *encoder_context,
1067                                        VAEncSliceParameterBufferH264 *slice_param,
1068                                        int head_offset,
1069                                        unsigned short head_size,
1070                                        unsigned short tail_size,
1071                                        int batchbuffer_offset,
1072                                        int qp,
1073                                        int last_slice)
1074 {
1075     struct intel_batchbuffer *batch = encoder_context->base.batch;
1076     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1077     struct gen6_vme_context *vme_context = encoder_context->vme_context;
1078     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
1079     int total_mbs = slice_param->num_macroblocks;
1080     int number_mb_cmds = 128;
1081     int starting_mb = 0;
1082     int last_object = 0;
1083     int first_object = 1;
1084     int i;
1085     int mb_x, mb_y;
1086     int index = (slice_param->slice_type == SLICE_TYPE_I) ? MFC_BATCHBUFFER_AVC_INTRA : MFC_BATCHBUFFER_AVC_INTER;
1087
1088     for (i = 0; i < total_mbs / number_mb_cmds; i++) {
1089         last_object = (total_mbs - starting_mb) == number_mb_cmds;
1090         mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs;
1091         mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs;
1092         assert(mb_x <= 255 && mb_y <= 255);
1093
1094         starting_mb += number_mb_cmds;
1095
1096         gen6_mfc_batchbuffer_emit_object_command(batch,
1097                                                  index,
1098                                                  head_offset,
1099                                                  batchbuffer_offset,
1100                                                  head_size,
1101                                                  tail_size,
1102                                                  number_mb_cmds,
1103                                                  first_object,
1104                                                  last_object,
1105                                                  last_slice,
1106                                                  mb_x,
1107                                                  mb_y,
1108                                                  width_in_mbs,
1109                                                  qp,
1110                                                  vme_context->ref_index_in_mb);
1111
1112         if (first_object) {
1113             head_offset += head_size;
1114             batchbuffer_offset += head_size;
1115         }
1116
1117         if (last_object) {
1118             head_offset += tail_size;
1119             batchbuffer_offset += tail_size;
1120         }
1121
1122         batchbuffer_offset += number_mb_cmds * CMD_LEN_IN_OWORD;
1123
1124         first_object = 0;
1125     }
1126
1127     if (!last_object) {
1128         last_object = 1;
1129         number_mb_cmds = total_mbs % number_mb_cmds;
1130         mb_x = (slice_param->macroblock_address + starting_mb) % width_in_mbs;
1131         mb_y = (slice_param->macroblock_address + starting_mb) / width_in_mbs;
1132         assert(mb_x <= 255 && mb_y <= 255);
1133         starting_mb += number_mb_cmds;
1134
1135         gen6_mfc_batchbuffer_emit_object_command(batch,
1136                                                  index,
1137                                                  head_offset,
1138                                                  batchbuffer_offset,
1139                                                  head_size,
1140                                                  tail_size,
1141                                                  number_mb_cmds,
1142                                                  first_object,
1143                                                  last_object,
1144                                                  last_slice,
1145                                                  mb_x,
1146                                                  mb_y,
1147                                                  width_in_mbs,
1148                                                  qp,
1149                                                  vme_context->ref_index_in_mb);
1150     }
1151 }
1152
1153 /*
1154  * return size in Owords (16bytes)
1155  */
1156 static int
1157 gen6_mfc_avc_batchbuffer_slice(VADriverContextP ctx,
1158                                struct encode_state *encode_state,
1159                                struct intel_encoder_context *encoder_context,
1160                                int slice_index,
1161                                int batchbuffer_offset)
1162 {
1163     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1164     struct intel_batchbuffer *slice_batch = mfc_context->aux_batchbuffer;
1165     VAEncSequenceParameterBufferH264 *pSequenceParameter = (VAEncSequenceParameterBufferH264 *)encode_state->seq_param_ext->buffer;
1166     VAEncPictureParameterBufferH264 *pPicParameter = (VAEncPictureParameterBufferH264 *)encode_state->pic_param_ext->buffer;
1167     VAEncSliceParameterBufferH264 *pSliceParameter = (VAEncSliceParameterBufferH264 *)encode_state->slice_params_ext[slice_index]->buffer;
1168     int width_in_mbs = (mfc_context->surface_state.width + 15) / 16;
1169     int height_in_mbs = (mfc_context->surface_state.height + 15) / 16;
1170     int last_slice = (pSliceParameter->macroblock_address + pSliceParameter->num_macroblocks) == (width_in_mbs * height_in_mbs);
1171     int qp = pPicParameter->pic_init_qp + pSliceParameter->slice_qp_delta;
1172     unsigned int rate_control_mode = encoder_context->rate_control_mode;
1173     unsigned int tail_data[] = { 0x0, 0x0 };
1174     long head_offset;
1175     int old_used = intel_batchbuffer_used_size(slice_batch), used;
1176     unsigned short head_size, tail_size;
1177     int slice_type = intel_avc_enc_slice_type_fixup(pSliceParameter->slice_type);
1178     int qp_slice;
1179
1180     qp_slice = qp;
1181     if (rate_control_mode == VA_RC_CBR) {
1182         qp = mfc_context->bit_rate_control_context[slice_type].QpPrimeY;
1183         if (encode_state->slice_header_index[slice_index] == 0) {
1184             pSliceParameter->slice_qp_delta = qp - pPicParameter->pic_init_qp;
1185             /* Use the adjusted qp when slice_header is generated by driver */
1186             qp_slice = qp;
1187         }
1188     }
1189
1190     /* only support for 8-bit pixel bit-depth */
1191     assert(pSequenceParameter->bit_depth_luma_minus8 == 0);
1192     assert(pSequenceParameter->bit_depth_chroma_minus8 == 0);
1193     assert(pPicParameter->pic_init_qp >= 0 && pPicParameter->pic_init_qp < 52);
1194     assert(qp >= 0 && qp < 52);
1195
1196     head_offset = old_used / 16;
1197     gen6_mfc_avc_slice_state(ctx,
1198                              pPicParameter,
1199                              pSliceParameter,
1200                              encode_state,
1201                              encoder_context,
1202                              (rate_control_mode == VA_RC_CBR),
1203                              qp_slice,
1204                              slice_batch);
1205
1206     if (slice_index == 0)
1207         intel_mfc_avc_pipeline_header_programing(ctx, encode_state, encoder_context, slice_batch);
1208
1209     intel_avc_slice_insert_packed_data(ctx, encode_state, encoder_context, slice_index, slice_batch);
1210
1211     intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */
1212     used = intel_batchbuffer_used_size(slice_batch);
1213     head_size = (used - old_used) / 16;
1214     old_used = used;
1215
1216     /* tail */
1217     if (last_slice) {
1218         mfc_context->insert_object(ctx,
1219                                    encoder_context,
1220                                    tail_data,
1221                                    2,
1222                                    8,
1223                                    2,
1224                                    1,
1225                                    1,
1226                                    0,
1227                                    slice_batch);
1228     } else {
1229         mfc_context->insert_object(ctx,
1230                                    encoder_context,
1231                                    tail_data,
1232                                    1,
1233                                    8,
1234                                    1,
1235                                    1,
1236                                    1,
1237                                    0,
1238                                    slice_batch);
1239     }
1240
1241     intel_batchbuffer_align(slice_batch, 16); /* aligned by an Oword */
1242     used = intel_batchbuffer_used_size(slice_batch);
1243     tail_size = (used - old_used) / 16;
1244
1245
1246     gen6_mfc_avc_batchbuffer_slice_command(ctx,
1247                                            encoder_context,
1248                                            pSliceParameter,
1249                                            head_offset,
1250                                            head_size,
1251                                            tail_size,
1252                                            batchbuffer_offset,
1253                                            qp,
1254                                            last_slice);
1255
1256     return head_size + tail_size + pSliceParameter->num_macroblocks * CMD_LEN_IN_OWORD;
1257 }
1258
1259 static void
1260 gen6_mfc_avc_batchbuffer_pipeline(VADriverContextP ctx,
1261                                   struct encode_state *encode_state,
1262                                   struct intel_encoder_context *encoder_context)
1263 {
1264     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1265     struct intel_batchbuffer *batch = encoder_context->base.batch;
1266     int i, size, offset = 0;
1267     intel_batchbuffer_start_atomic(batch, 0x4000);
1268     gen6_gpe_pipeline_setup(ctx, &mfc_context->gpe_context, batch);
1269
1270     for ( i = 0; i < encode_state->num_slice_params_ext; i++) {
1271         size = gen6_mfc_avc_batchbuffer_slice(ctx, encode_state, encoder_context, i, offset);
1272         offset += size;
1273     }
1274
1275     intel_batchbuffer_end_atomic(batch);
1276     intel_batchbuffer_flush(batch);
1277 }
1278
1279 static void
1280 gen6_mfc_build_avc_batchbuffer(VADriverContextP ctx,
1281                                struct encode_state *encode_state,
1282                                struct intel_encoder_context *encoder_context)
1283 {
1284     gen6_mfc_batchbuffer_surfaces_setup(ctx, encode_state, encoder_context);
1285     gen6_mfc_batchbuffer_idrt_setup(ctx, encode_state, encoder_context);
1286     gen6_mfc_batchbuffer_constant_setup(ctx, encode_state, encoder_context);
1287     gen6_mfc_avc_batchbuffer_pipeline(ctx, encode_state, encoder_context);
1288 }
1289
1290 static dri_bo *
1291 gen6_mfc_avc_hardware_batchbuffer(VADriverContextP ctx,
1292                                   struct encode_state *encode_state,
1293                                   struct intel_encoder_context *encoder_context)
1294 {
1295     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1296
1297     gen6_mfc_build_avc_batchbuffer(ctx, encode_state, encoder_context);
1298     dri_bo_reference(mfc_context->mfc_batchbuffer_surface.bo);
1299
1300     return mfc_context->mfc_batchbuffer_surface.bo;
1301 }
1302
1303 #endif
1304
1305
1306 static void
1307 gen6_mfc_avc_pipeline_programing(VADriverContextP ctx,
1308                                  struct encode_state *encode_state,
1309                                  struct intel_encoder_context *encoder_context)
1310 {
1311     struct intel_batchbuffer *batch = encoder_context->base.batch;
1312     dri_bo *slice_batch_bo;
1313
1314     if ( intel_mfc_interlace_check(ctx, encode_state, encoder_context) ) {
1315         fprintf(stderr, "Current VA driver don't support interlace mode!\n");
1316         assert(0);
1317         return;
1318     }
1319
1320 #if __SOFTWARE__
1321     slice_batch_bo = gen6_mfc_avc_software_batchbuffer(ctx, encode_state, encoder_context);
1322 #else
1323     slice_batch_bo = gen6_mfc_avc_hardware_batchbuffer(ctx, encode_state, encoder_context);
1324 #endif
1325
1326     // begin programing
1327     intel_batchbuffer_start_atomic_bcs(batch, 0x4000);
1328     intel_batchbuffer_emit_mi_flush(batch);
1329
1330     // picture level programing
1331     gen6_mfc_avc_pipeline_picture_programing(ctx, encode_state, encoder_context);
1332
1333     BEGIN_BCS_BATCH(batch, 2);
1334     OUT_BCS_BATCH(batch, MI_BATCH_BUFFER_START | (1 << 8));
1335     OUT_BCS_RELOC(batch,
1336                   slice_batch_bo,
1337                   I915_GEM_DOMAIN_COMMAND, 0,
1338                   0);
1339     ADVANCE_BCS_BATCH(batch);
1340
1341     // end programing
1342     intel_batchbuffer_end_atomic(batch);
1343
1344     dri_bo_unreference(slice_batch_bo);
1345 }
1346
1347 VAStatus
1348 gen6_mfc_avc_encode_picture(VADriverContextP ctx,
1349                             struct encode_state *encode_state,
1350                             struct intel_encoder_context *encoder_context)
1351 {
1352     struct gen6_mfc_context *mfc_context = encoder_context->mfc_context;
1353     unsigned int rate_control_mode = encoder_context->rate_control_mode;
1354     int current_frame_bits_size;
1355     int sts;
1356
1357     for (;;) {
1358         gen6_mfc_init(ctx, encode_state, encoder_context);
1359         intel_mfc_avc_prepare(ctx, encode_state, encoder_context);
1360         /*Programing bcs pipeline*/
1361         gen6_mfc_avc_pipeline_programing(ctx, encode_state, encoder_context);   //filling the pipeline
1362         gen6_mfc_run(ctx, encode_state, encoder_context);
1363         if (rate_control_mode == VA_RC_CBR /*|| rate_control_mode == VA_RC_VBR*/) {
1364             gen6_mfc_stop(ctx, encode_state, encoder_context, &current_frame_bits_size);
1365             sts = intel_mfc_brc_postpack(encode_state, mfc_context, current_frame_bits_size);
1366             if (sts == BRC_NO_HRD_VIOLATION) {
1367                 intel_mfc_hrd_context_update(encode_state, mfc_context);
1368                 break;
1369             }
1370             else if (sts == BRC_OVERFLOW_WITH_MIN_QP || sts == BRC_UNDERFLOW_WITH_MAX_QP) {
1371                 if (!mfc_context->hrd.violation_noted) {
1372                     fprintf(stderr, "Unrepairable %s!\n", (sts == BRC_OVERFLOW_WITH_MIN_QP)? "overflow": "underflow");
1373                     mfc_context->hrd.violation_noted = 1;
1374                 }
1375                 return VA_STATUS_SUCCESS;
1376             }
1377         } else {
1378             break;
1379         }
1380     }
1381
1382     return VA_STATUS_SUCCESS;
1383 }
1384
1385 VAStatus
1386 gen6_mfc_pipeline(VADriverContextP ctx,
1387                   VAProfile profile,
1388                   struct encode_state *encode_state,
1389                   struct intel_encoder_context *encoder_context)
1390 {
1391     VAStatus vaStatus;
1392
1393     switch (profile) {
1394     case VAProfileH264ConstrainedBaseline:
1395     case VAProfileH264Main:
1396     case VAProfileH264High:
1397         vaStatus = gen6_mfc_avc_encode_picture(ctx, encode_state, encoder_context);
1398         break;
1399
1400         /* FIXME: add for other profile */
1401     default:
1402         vaStatus = VA_STATUS_ERROR_UNSUPPORTED_PROFILE;
1403         break;
1404     }
1405
1406     return vaStatus;
1407 }
1408
1409 void
1410 gen6_mfc_context_destroy(void *context)
1411 {
1412     struct gen6_mfc_context *mfc_context = context;
1413     int i;
1414
1415     dri_bo_unreference(mfc_context->post_deblocking_output.bo);
1416     mfc_context->post_deblocking_output.bo = NULL;
1417
1418     dri_bo_unreference(mfc_context->pre_deblocking_output.bo);
1419     mfc_context->pre_deblocking_output.bo = NULL;
1420
1421     dri_bo_unreference(mfc_context->uncompressed_picture_source.bo);
1422     mfc_context->uncompressed_picture_source.bo = NULL;
1423
1424     dri_bo_unreference(mfc_context->mfc_indirect_pak_bse_object.bo);
1425     mfc_context->mfc_indirect_pak_bse_object.bo = NULL;
1426
1427     for (i = 0; i < NUM_MFC_DMV_BUFFERS; i++){
1428         dri_bo_unreference(mfc_context->direct_mv_buffers[i].bo);
1429         mfc_context->direct_mv_buffers[i].bo = NULL;
1430     }
1431
1432     dri_bo_unreference(mfc_context->intra_row_store_scratch_buffer.bo);
1433     mfc_context->intra_row_store_scratch_buffer.bo = NULL;
1434
1435     dri_bo_unreference(mfc_context->macroblock_status_buffer.bo);
1436     mfc_context->macroblock_status_buffer.bo = NULL;
1437
1438     dri_bo_unreference(mfc_context->deblocking_filter_row_store_scratch_buffer.bo);
1439     mfc_context->deblocking_filter_row_store_scratch_buffer.bo = NULL;
1440
1441     dri_bo_unreference(mfc_context->bsd_mpc_row_store_scratch_buffer.bo);
1442     mfc_context->bsd_mpc_row_store_scratch_buffer.bo = NULL;
1443
1444
1445     for (i = 0; i < MAX_MFC_REFERENCE_SURFACES; i++){
1446         dri_bo_unreference(mfc_context->reference_surfaces[i].bo);
1447         mfc_context->reference_surfaces[i].bo = NULL;
1448     }
1449
1450     i965_gpe_context_destroy(&mfc_context->gpe_context);
1451
1452     dri_bo_unreference(mfc_context->mfc_batchbuffer_surface.bo);
1453     mfc_context->mfc_batchbuffer_surface.bo = NULL;
1454
1455     dri_bo_unreference(mfc_context->aux_batchbuffer_surface.bo);
1456     mfc_context->aux_batchbuffer_surface.bo = NULL;
1457
1458     if (mfc_context->aux_batchbuffer)
1459         intel_batchbuffer_free(mfc_context->aux_batchbuffer);
1460
1461     mfc_context->aux_batchbuffer = NULL;
1462
1463     free(mfc_context);
1464 }
1465
1466 Bool gen6_mfc_context_init(VADriverContextP ctx, struct intel_encoder_context *encoder_context)
1467 {
1468     struct gen6_mfc_context *mfc_context = calloc(1, sizeof(struct gen6_mfc_context));
1469
1470     if (!mfc_context)
1471         return False;
1472
1473     mfc_context->gpe_context.surface_state_binding_table.length = (SURFACE_STATE_PADDED_SIZE + sizeof(unsigned int)) * MAX_MEDIA_SURFACES_GEN6;
1474
1475     mfc_context->gpe_context.idrt.max_entries = MAX_GPE_KERNELS;
1476     mfc_context->gpe_context.idrt.entry_size = sizeof(struct gen6_interface_descriptor_data);
1477
1478     mfc_context->gpe_context.curbe.length = 32 * 4;
1479
1480     mfc_context->gpe_context.vfe_state.max_num_threads = 60 - 1;
1481     mfc_context->gpe_context.vfe_state.num_urb_entries = 16;
1482     mfc_context->gpe_context.vfe_state.gpgpu_mode = 0;
1483     mfc_context->gpe_context.vfe_state.urb_entry_size = 59 - 1;
1484     mfc_context->gpe_context.vfe_state.curbe_allocation_size = 37 - 1;
1485
1486     i965_gpe_load_kernels(ctx,
1487                           &mfc_context->gpe_context,
1488                           gen6_mfc_kernels,
1489                           NUM_MFC_KERNEL);
1490
1491     mfc_context->pipe_mode_select = gen6_mfc_pipe_mode_select;
1492     mfc_context->set_surface_state = gen6_mfc_surface_state;
1493     mfc_context->ind_obj_base_addr_state = gen6_mfc_ind_obj_base_addr_state;
1494     mfc_context->avc_img_state = gen6_mfc_avc_img_state;
1495     mfc_context->avc_qm_state = gen6_mfc_avc_qm_state;
1496     mfc_context->avc_fqm_state = gen6_mfc_avc_fqm_state;
1497     mfc_context->insert_object = gen6_mfc_avc_insert_object;
1498     mfc_context->buffer_suface_setup = i965_gpe_buffer_suface_setup;
1499
1500     encoder_context->mfc_context = mfc_context;
1501     encoder_context->mfc_context_destroy = gen6_mfc_context_destroy;
1502     encoder_context->mfc_pipeline = gen6_mfc_pipeline;
1503     encoder_context->mfc_brc_prepare = intel_mfc_brc_prepare;
1504
1505     return True;
1506 }