2 * Copyright © 2011 Marek Olšák <maraeo@gmail.com>
5 * Permission is hereby granted, free of charge, to any person obtaining
6 * a copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
14 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
15 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
16 * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
17 * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
27 #define _FILE_OFFSET_BITS 64
28 #include "radeon_drm_cs.h"
30 #include "util/u_hash_table.h"
31 #include "util/u_memory.h"
32 #include "util/u_simple_list.h"
33 #include "os/os_thread.h"
35 #include "state_tracker/drm_driver.h"
37 #include <sys/ioctl.h>
42 #define RADEON_BO_FLAGS_MACRO_TILE 1
43 #define RADEON_BO_FLAGS_MICRO_TILE 2
44 #define RADEON_BO_FLAGS_MICRO_TILE_SQUARE 0x20
46 extern const struct pb_vtbl radeon_bo_vtbl;
49 static INLINE struct radeon_bo *radeon_bo(struct pb_buffer *bo)
51 assert(bo->vtbl == &radeon_bo_vtbl);
52 return (struct radeon_bo *)bo;
57 struct pb_manager base;
60 struct radeon_drm_winsys *rws;
62 /* List of buffer handles and its mutex. */
63 struct util_hash_table *bo_handles;
64 pipe_mutex bo_handles_mutex;
67 static INLINE struct radeon_bomgr *radeon_bomgr(struct pb_manager *mgr)
69 return (struct radeon_bomgr *)mgr;
72 static struct radeon_bo *get_radeon_bo(struct pb_buffer *_buf)
74 struct radeon_bo *bo = NULL;
76 if (_buf->vtbl == &radeon_bo_vtbl) {
79 struct pb_buffer *base_buf;
81 pb_get_base_buffer(_buf, &base_buf, &offset);
83 if (base_buf->vtbl == &radeon_bo_vtbl)
84 bo = radeon_bo(base_buf);
90 static void radeon_bo_wait(struct pb_buffer *_buf)
92 struct radeon_bo *bo = get_radeon_bo(pb_buffer(_buf));
93 struct drm_radeon_gem_wait_idle args = {};
95 while (p_atomic_read(&bo->num_active_ioctls)) {
99 args.handle = bo->handle;
100 while (drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_WAIT_IDLE,
101 &args, sizeof(args)) == -EBUSY);
103 bo->busy_for_write = FALSE;
106 static boolean radeon_bo_is_busy(struct pb_buffer *_buf)
108 struct radeon_bo *bo = get_radeon_bo(pb_buffer(_buf));
109 struct drm_radeon_gem_busy args = {};
112 if (p_atomic_read(&bo->num_active_ioctls)) {
116 args.handle = bo->handle;
117 busy = drmCommandWriteRead(bo->rws->fd, DRM_RADEON_GEM_BUSY,
118 &args, sizeof(args)) != 0;
121 bo->busy_for_write = FALSE;
125 static void radeon_bo_destroy(struct pb_buffer *_buf)
127 struct radeon_bo *bo = radeon_bo(_buf);
128 struct drm_gem_close args = {};
131 pipe_mutex_lock(bo->mgr->bo_handles_mutex);
132 util_hash_table_remove(bo->mgr->bo_handles,
133 (void*)(uintptr_t)bo->name);
134 pipe_mutex_unlock(bo->mgr->bo_handles_mutex);
138 munmap(bo->ptr, bo->size);
141 args.handle = bo->handle;
142 drmIoctl(bo->rws->fd, DRM_IOCTL_GEM_CLOSE, &args);
143 pipe_mutex_destroy(bo->map_mutex);
147 static unsigned get_pb_usage_from_transfer_flags(enum pipe_transfer_usage usage)
151 if (usage & PIPE_TRANSFER_WRITE)
152 res |= PB_USAGE_CPU_WRITE;
154 if (usage & PIPE_TRANSFER_DONTBLOCK)
155 res |= PB_USAGE_DONTBLOCK;
157 if (usage & PIPE_TRANSFER_UNSYNCHRONIZED)
158 res |= PB_USAGE_UNSYNCHRONIZED;
163 static void *radeon_bo_map_internal(struct pb_buffer *_buf,
164 unsigned flags, void *flush_ctx)
166 struct radeon_bo *bo = radeon_bo(_buf);
167 struct radeon_drm_cs *cs = flush_ctx;
168 struct drm_radeon_gem_mmap args = {};
171 /* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
172 if (!(flags & PB_USAGE_UNSYNCHRONIZED)) {
173 /* DONTBLOCK doesn't make sense with UNSYNCHRONIZED. */
174 if (flags & PB_USAGE_DONTBLOCK) {
175 if (radeon_bo_is_referenced_by_cs(cs, bo)) {
176 cs->flush_cs(cs->flush_data, RADEON_FLUSH_ASYNC);
180 if (radeon_bo_is_busy((struct pb_buffer*)bo)) {
184 if (!(flags & PB_USAGE_CPU_WRITE)) {
187 * Since we are mapping for read, we don't need to wait
188 * if the GPU is using the buffer for read too
189 * (neither one is changing it).
191 * Only check whether the buffer is being used for write. */
192 if (radeon_bo_is_referenced_by_cs_for_write(cs, bo)) {
193 cs->flush_cs(cs->flush_data, 0);
194 radeon_bo_wait((struct pb_buffer*)bo);
195 } else if (bo->busy_for_write) {
196 /* Update the busy_for_write field (done by radeon_bo_is_busy)
197 * and wait if needed. */
198 if (radeon_bo_is_busy((struct pb_buffer*)bo)) {
199 radeon_bo_wait((struct pb_buffer*)bo);
203 /* Mapping for write. */
204 if (radeon_bo_is_referenced_by_cs(cs, bo)) {
205 cs->flush_cs(cs->flush_data, 0);
207 /* Try to avoid busy-waiting in radeon_bo_wait. */
208 if (p_atomic_read(&bo->num_active_ioctls))
209 radeon_drm_cs_sync_flush(cs);
212 radeon_bo_wait((struct pb_buffer*)bo);
217 /* Return the pointer if it's already mapped. */
221 /* Map the buffer. */
222 pipe_mutex_lock(bo->map_mutex);
223 /* Return the pointer if it's already mapped (in case of a race). */
225 pipe_mutex_unlock(bo->map_mutex);
228 args.handle = bo->handle;
230 args.size = (uint64_t)bo->size;
231 if (drmCommandWriteRead(bo->rws->fd,
235 pipe_mutex_unlock(bo->map_mutex);
236 fprintf(stderr, "radeon: gem_mmap failed: %p 0x%08X\n",
241 ptr = mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED,
242 bo->rws->fd, args.addr_ptr);
243 if (ptr == MAP_FAILED) {
244 pipe_mutex_unlock(bo->map_mutex);
245 fprintf(stderr, "radeon: mmap failed, errno: %i\n", errno);
249 pipe_mutex_unlock(bo->map_mutex);
254 static void radeon_bo_unmap_internal(struct pb_buffer *_buf)
259 static void radeon_bo_get_base_buffer(struct pb_buffer *buf,
260 struct pb_buffer **base_buf,
267 static enum pipe_error radeon_bo_validate(struct pb_buffer *_buf,
268 struct pb_validate *vl,
275 static void radeon_bo_fence(struct pb_buffer *buf,
276 struct pipe_fence_handle *fence)
280 const struct pb_vtbl radeon_bo_vtbl = {
282 radeon_bo_map_internal,
283 radeon_bo_unmap_internal,
286 radeon_bo_get_base_buffer,
289 static struct pb_buffer *radeon_bomgr_create_bo(struct pb_manager *_mgr,
291 const struct pb_desc *desc)
293 struct radeon_bomgr *mgr = radeon_bomgr(_mgr);
294 struct radeon_drm_winsys *rws = mgr->rws;
295 struct radeon_bo *bo;
296 struct drm_radeon_gem_create args = {};
299 args.alignment = desc->alignment;
300 args.initial_domain =
301 (desc->usage & RADEON_PB_USAGE_DOMAIN_GTT ?
302 RADEON_GEM_DOMAIN_GTT : 0) |
303 (desc->usage & RADEON_PB_USAGE_DOMAIN_VRAM ?
304 RADEON_GEM_DOMAIN_VRAM : 0);
306 if (drmCommandWriteRead(rws->fd, DRM_RADEON_GEM_CREATE,
307 &args, sizeof(args))) {
308 fprintf(stderr, "radeon: Failed to allocate a buffer:\n");
309 fprintf(stderr, "radeon: size : %d bytes\n", size);
310 fprintf(stderr, "radeon: alignment : %d bytes\n", desc->alignment);
311 fprintf(stderr, "radeon: domains : %d\n", args.initial_domain);
315 bo = CALLOC_STRUCT(radeon_bo);
319 pipe_reference_init(&bo->base.base.reference, 1);
320 bo->base.base.alignment = desc->alignment;
321 bo->base.base.usage = desc->usage;
322 bo->base.base.size = size;
323 bo->base.vtbl = &radeon_bo_vtbl;
326 bo->handle = args.handle;
328 pipe_mutex_init(bo->map_mutex);
333 static void radeon_bomgr_flush(struct pb_manager *mgr)
338 /* This is for the cache bufmgr. */
339 static boolean radeon_bomgr_is_buffer_busy(struct pb_manager *_mgr,
340 struct pb_buffer *_buf)
342 struct radeon_bo *bo = radeon_bo(_buf);
344 if (radeon_bo_is_referenced_by_any_cs(bo)) {
348 if (radeon_bo_is_busy((struct pb_buffer*)bo)) {
355 static void radeon_bomgr_destroy(struct pb_manager *_mgr)
357 struct radeon_bomgr *mgr = radeon_bomgr(_mgr);
358 util_hash_table_destroy(mgr->bo_handles);
359 pipe_mutex_destroy(mgr->bo_handles_mutex);
363 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
365 static unsigned handle_hash(void *key)
367 return PTR_TO_UINT(key);
370 static int handle_compare(void *key1, void *key2)
372 return PTR_TO_UINT(key1) != PTR_TO_UINT(key2);
375 struct pb_manager *radeon_bomgr_create(struct radeon_drm_winsys *rws)
377 struct radeon_bomgr *mgr;
379 mgr = CALLOC_STRUCT(radeon_bomgr);
383 mgr->base.destroy = radeon_bomgr_destroy;
384 mgr->base.create_buffer = radeon_bomgr_create_bo;
385 mgr->base.flush = radeon_bomgr_flush;
386 mgr->base.is_buffer_busy = radeon_bomgr_is_buffer_busy;
389 mgr->bo_handles = util_hash_table_create(handle_hash, handle_compare);
390 pipe_mutex_init(mgr->bo_handles_mutex);
394 static void *radeon_bo_map(struct pb_buffer *buf,
395 struct radeon_winsys_cs *cs,
396 enum pipe_transfer_usage usage)
398 struct pb_buffer *_buf = pb_buffer(buf);
400 return pb_map(_buf, get_pb_usage_from_transfer_flags(usage), cs);
403 static void radeon_bo_get_tiling(struct pb_buffer *_buf,
404 enum radeon_bo_layout *microtiled,
405 enum radeon_bo_layout *macrotiled)
407 struct radeon_bo *bo = get_radeon_bo(pb_buffer(_buf));
408 struct drm_radeon_gem_set_tiling args = {};
410 args.handle = bo->handle;
412 drmCommandWriteRead(bo->rws->fd,
413 DRM_RADEON_GEM_GET_TILING,
417 *microtiled = RADEON_LAYOUT_LINEAR;
418 *macrotiled = RADEON_LAYOUT_LINEAR;
419 if (args.tiling_flags & RADEON_BO_FLAGS_MICRO_TILE)
420 *microtiled = RADEON_LAYOUT_TILED;
422 if (args.tiling_flags & RADEON_BO_FLAGS_MACRO_TILE)
423 *macrotiled = RADEON_LAYOUT_TILED;
426 static void radeon_bo_set_tiling(struct pb_buffer *_buf,
427 struct radeon_winsys_cs *rcs,
428 enum radeon_bo_layout microtiled,
429 enum radeon_bo_layout macrotiled,
432 struct radeon_bo *bo = get_radeon_bo(pb_buffer(_buf));
433 struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
434 struct drm_radeon_gem_set_tiling args = {};
436 /* Tiling determines how DRM treats the buffer data.
437 * We must flush CS when changing it if the buffer is referenced. */
438 if (cs && radeon_bo_is_referenced_by_cs(cs, bo)) {
439 cs->flush_cs(cs->flush_data, 0);
442 while (p_atomic_read(&bo->num_active_ioctls)) {
446 if (microtiled == RADEON_LAYOUT_TILED)
447 args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE;
448 else if (microtiled == RADEON_LAYOUT_SQUARETILED)
449 args.tiling_flags |= RADEON_BO_FLAGS_MICRO_TILE_SQUARE;
451 if (macrotiled == RADEON_LAYOUT_TILED)
452 args.tiling_flags |= RADEON_BO_FLAGS_MACRO_TILE;
454 args.handle = bo->handle;
457 drmCommandWriteRead(bo->rws->fd,
458 DRM_RADEON_GEM_SET_TILING,
463 static struct radeon_winsys_cs_handle *radeon_drm_get_cs_handle(
464 struct pb_buffer *_buf)
466 /* return radeon_bo. */
467 return (struct radeon_winsys_cs_handle*)
468 get_radeon_bo(pb_buffer(_buf));
471 static unsigned get_pb_usage_from_create_flags(unsigned bind, unsigned usage,
472 enum radeon_bo_domain domain)
476 if (domain & RADEON_DOMAIN_GTT)
477 res |= RADEON_PB_USAGE_DOMAIN_GTT;
479 if (domain & RADEON_DOMAIN_VRAM)
480 res |= RADEON_PB_USAGE_DOMAIN_VRAM;
485 static struct pb_buffer *
486 radeon_winsys_bo_create(struct radeon_winsys *rws,
491 enum radeon_bo_domain domain)
493 struct radeon_drm_winsys *ws = radeon_drm_winsys(rws);
495 struct pb_manager *provider;
496 struct pb_buffer *buffer;
498 memset(&desc, 0, sizeof(desc));
499 desc.alignment = alignment;
500 desc.usage = get_pb_usage_from_create_flags(bind, usage, domain);
502 /* Assign a buffer manager. */
503 if (bind & (PIPE_BIND_VERTEX_BUFFER | PIPE_BIND_INDEX_BUFFER))
508 buffer = provider->create_buffer(provider, size, &desc);
512 return (struct pb_buffer*)buffer;
515 static struct pb_buffer *radeon_winsys_bo_from_handle(struct radeon_winsys *rws,
516 struct winsys_handle *whandle,
520 struct radeon_drm_winsys *ws = radeon_drm_winsys(rws);
521 struct radeon_bo *bo;
522 struct radeon_bomgr *mgr = radeon_bomgr(ws->kman);
523 struct drm_gem_open open_arg = {};
525 /* We must maintain a list of pairs <handle, bo>, so that we always return
526 * the same BO for one particular handle. If we didn't do that and created
527 * more than one BO for the same handle and then relocated them in a CS,
528 * we would hit a deadlock in the kernel.
530 * The list of pairs is guarded by a mutex, of course. */
531 pipe_mutex_lock(mgr->bo_handles_mutex);
533 /* First check if there already is an existing bo for the handle. */
534 bo = util_hash_table_get(mgr->bo_handles, (void*)(uintptr_t)whandle->handle);
536 /* Increase the refcount. */
537 struct pb_buffer *b = NULL;
538 pb_reference(&b, &bo->base);
542 /* There isn't, create a new one. */
543 bo = CALLOC_STRUCT(radeon_bo);
549 open_arg.name = whandle->handle;
550 if (drmIoctl(ws->fd, DRM_IOCTL_GEM_OPEN, &open_arg)) {
554 bo->handle = open_arg.handle;
555 bo->size = open_arg.size;
556 bo->name = whandle->handle;
559 pipe_reference_init(&bo->base.base.reference, 1);
560 bo->base.base.alignment = 0;
561 bo->base.base.usage = PB_USAGE_GPU_WRITE | PB_USAGE_GPU_READ;
562 bo->base.base.size = bo->size;
563 bo->base.vtbl = &radeon_bo_vtbl;
566 pipe_mutex_init(bo->map_mutex);
568 util_hash_table_set(mgr->bo_handles, (void*)(uintptr_t)whandle->handle, bo);
571 pipe_mutex_unlock(mgr->bo_handles_mutex);
574 *stride = whandle->stride;
576 *size = bo->base.base.size;
578 return (struct pb_buffer*)bo;
581 pipe_mutex_unlock(mgr->bo_handles_mutex);
585 static boolean radeon_winsys_bo_get_handle(struct pb_buffer *buffer,
587 struct winsys_handle *whandle)
589 struct drm_gem_flink flink = {};
590 struct radeon_bo *bo = get_radeon_bo(pb_buffer(buffer));
592 if (whandle->type == DRM_API_HANDLE_TYPE_SHARED) {
594 flink.handle = bo->handle;
596 if (ioctl(bo->rws->fd, DRM_IOCTL_GEM_FLINK, &flink)) {
601 bo->flink = flink.name;
603 whandle->handle = bo->flink;
604 } else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
605 whandle->handle = bo->handle;
608 whandle->stride = stride;
612 void radeon_bomgr_init_functions(struct radeon_drm_winsys *ws)
614 ws->base.buffer_get_cs_handle = radeon_drm_get_cs_handle;
615 ws->base.buffer_set_tiling = radeon_bo_set_tiling;
616 ws->base.buffer_get_tiling = radeon_bo_get_tiling;
617 ws->base.buffer_map = radeon_bo_map;
618 ws->base.buffer_unmap = pb_unmap;
619 ws->base.buffer_wait = radeon_bo_wait;
620 ws->base.buffer_is_busy = radeon_bo_is_busy;
621 ws->base.buffer_create = radeon_winsys_bo_create;
622 ws->base.buffer_from_handle = radeon_winsys_bo_from_handle;
623 ws->base.buffer_get_handle = radeon_winsys_bo_get_handle;