1 /**************************************************************************
3 * Copyright 2007 VMware, Inc.
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26 **************************************************************************/
32 * Abstract graphics pipe state objects.
35 * 1. Want compact representations, so we use bitfields.
36 * 2. Put bitfields before other (GLfloat) fields.
37 * 3. enum bitfields need to be at least one bit extra in size so the most
38 * significant bit is zero. MSVC treats enums as signed so if the high
39 * bit is set, the value will be interpreted as a negative number.
40 * That causes trouble in various places.
47 #include "util/u_memory.h"
49 #include "p_compiler.h"
50 #include "p_defines.h"
51 #include "util/format/u_formats.h"
58 struct gl_buffer_object;
61 * Implementation limits
63 #define PIPE_MAX_ATTRIBS 32
64 #define PIPE_MAX_CLIP_PLANES 8
65 #define PIPE_MAX_COLOR_BUFS 8
66 #define PIPE_MAX_CONSTANT_BUFFERS 32
67 #define PIPE_MAX_SAMPLERS 32
68 #define PIPE_MAX_SHADER_INPUTS 80 /* 32 GENERIC + 32 PATCH + 16 others */
69 #define PIPE_MAX_SHADER_OUTPUTS 80 /* 32 GENERIC + 32 PATCH + 16 others */
70 #define PIPE_MAX_SHADER_SAMPLER_VIEWS 128
71 #define PIPE_MAX_SHADER_BUFFERS 32
72 #define PIPE_MAX_SHADER_IMAGES 64
73 #define PIPE_MAX_TEXTURE_LEVELS 16
74 #define PIPE_MAX_SO_BUFFERS 4
75 #define PIPE_MAX_SO_OUTPUTS 64
76 #define PIPE_MAX_VIEWPORTS 16
77 #define PIPE_MAX_CLIP_OR_CULL_DISTANCE_COUNT 8
78 #define PIPE_MAX_CLIP_OR_CULL_DISTANCE_ELEMENT_COUNT 2
79 #define PIPE_MAX_WINDOW_RECTANGLES 8
80 #define PIPE_MAX_SAMPLE_LOCATION_GRID_SIZE 4
82 #define PIPE_MAX_HW_ATOMIC_BUFFERS 32
83 #define PIPE_MAX_VERTEX_STREAMS 4
87 int32_t count; /* atomic */
93 * Primitive (point/line/tri) rasterization info
95 struct pipe_rasterizer_state
98 unsigned light_twoside:1;
99 unsigned clamp_vertex_color:1;
100 unsigned clamp_fragment_color:1;
101 unsigned front_ccw:1;
102 unsigned cull_face:2; /**< PIPE_FACE_x */
103 unsigned fill_front:2; /**< PIPE_POLYGON_MODE_x */
104 unsigned fill_back:2; /**< PIPE_POLYGON_MODE_x */
105 unsigned offset_point:1;
106 unsigned offset_line:1;
107 unsigned offset_tri:1;
109 unsigned poly_smooth:1;
110 unsigned poly_stipple_enable:1;
111 unsigned point_smooth:1;
112 unsigned sprite_coord_mode:1; /**< PIPE_SPRITE_COORD_ */
113 unsigned point_quad_rasterization:1; /** points rasterized as quads or points */
114 unsigned point_tri_clip:1; /** large points clipped as tris or points */
115 unsigned point_size_per_vertex:1; /**< size computed in vertex shader */
116 unsigned multisample:1; /* XXX maybe more ms state in future */
117 unsigned no_ms_sample_mask_out:1;
118 unsigned force_persample_interp:1;
119 unsigned line_smooth:1;
120 unsigned line_stipple_enable:1;
121 unsigned line_last_pixel:1;
122 unsigned line_rectangular:1; /** lines rasterized as rectangles or parallelograms */
123 unsigned conservative_raster_mode:2; /**< PIPE_CONSERVATIVE_RASTER_x */
126 * Use the first vertex of a primitive as the provoking vertex for
129 unsigned flatshade_first:1;
131 unsigned half_pixel_center:1;
132 unsigned bottom_edge_rule:1;
135 * Conservative rasterization subpixel precision bias in bits
137 unsigned subpixel_precision_x:4;
138 unsigned subpixel_precision_y:4;
141 * When true, rasterization is disabled and no pixels are written.
142 * This only makes sense with the Stream Out functionality.
144 unsigned rasterizer_discard:1;
147 * Exposed by PIPE_CAP_TILE_RASTER_ORDER. When true,
148 * tile_raster_order_increasing_* indicate the order that the rasterizer
149 * should render tiles, to meet the requirements of
150 * GL_MESA_tile_raster_order.
152 unsigned tile_raster_order_fixed:1;
153 unsigned tile_raster_order_increasing_x:1;
154 unsigned tile_raster_order_increasing_y:1;
157 * When false, depth clipping is disabled and the depth value will be
158 * clamped later at the per-pixel level before depth testing.
159 * This depends on PIPE_CAP_DEPTH_CLIP_DISABLE.
161 * If PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE is unsupported, depth_clip_near
162 * is equal to depth_clip_far.
164 unsigned depth_clip_near:1;
165 unsigned depth_clip_far:1;
168 * When true, depth clamp is enabled.
169 * If PIPE_CAP_DEPTH_CLAMP_ENABLE is unsupported, this is always the inverse
172 unsigned depth_clamp:1;
175 * When true clip space in the z axis goes from [0..1] (D3D). When false
178 * NOTE: D3D will always use depth clamping.
180 unsigned clip_halfz:1;
183 * When true do not scale offset_units and use same rules for unorm and
184 * float depth buffers (D3D9). When false use GL/D3D1X behaviour.
185 * This depends on PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED.
187 unsigned offset_units_unscaled:1;
190 * Depth values output from fragment shader may be outside 0..1.
191 * These have to be clamped for use with UNORM buffers.
192 * Vulkan can allow this with an extension,
193 * GL could with NV_depth_buffer_float, but GLES doesn't.
195 unsigned unclamped_fragment_depth_values:1;
198 * Enable bits for clipping half-spaces.
199 * This applies to both user clip planes and shader clip distances.
200 * Note that if the bound shader exports any clip distances, these
201 * replace all user clip planes, and clip half-spaces enabled here
202 * but not written by the shader count as disabled.
204 unsigned clip_plane_enable:PIPE_MAX_CLIP_PLANES;
206 unsigned line_stipple_factor:8; /**< [1..256] actually */
207 unsigned line_stipple_pattern:16;
210 * Replace the given TEXCOORD inputs with point coordinates, max. 8 inputs.
211 * If TEXCOORD (including PCOORD) are unsupported, replace GENERIC inputs
212 * instead. Max. 9 inputs: 8x GENERIC to emulate TEXCOORD, and 1x GENERIC
215 uint16_t sprite_coord_enable; /* 0-7: TEXCOORD/GENERIC, 8: PCOORD */
218 float point_size; /**< used when no per-vertex size */
222 float conservative_raster_dilate;
226 struct pipe_poly_stipple
228 unsigned stipple[32];
232 struct pipe_viewport_state
236 enum pipe_viewport_swizzle swizzle_x:8;
237 enum pipe_viewport_swizzle swizzle_y:8;
238 enum pipe_viewport_swizzle swizzle_z:8;
239 enum pipe_viewport_swizzle swizzle_w:8;
243 struct pipe_scissor_state
252 struct pipe_clip_state
254 float ucp[PIPE_MAX_CLIP_PLANES][4];
258 * A single output for vertex transform feedback.
260 struct pipe_stream_output
262 unsigned register_index:6; /**< 0 to 63 (OUT index) */
263 unsigned start_component:2; /** 0 to 3 */
264 unsigned num_components:3; /** 1 to 4 */
265 unsigned output_buffer:3; /**< 0 to PIPE_MAX_SO_BUFFERS */
266 unsigned dst_offset:16; /**< offset into the buffer in dwords */
267 unsigned stream:2; /**< 0 to 3 */
271 * Stream output for vertex transform feedback.
273 struct pipe_stream_output_info
275 unsigned num_outputs;
276 /** stride for an entire vertex for each buffer in dwords */
277 uint16_t stride[PIPE_MAX_SO_BUFFERS];
280 * Array of stream outputs, in the order they are to be written in.
281 * Selected components are tightly packed into the output buffer.
283 struct pipe_stream_output output[PIPE_MAX_SO_OUTPUTS];
287 * The 'type' parameter identifies whether the shader state contains TGSI
288 * tokens, etc. If the driver returns 'PIPE_SHADER_IR_TGSI' for the
289 * 'PIPE_SHADER_CAP_PREFERRED_IR' shader param, the ir will *always* be
290 * 'PIPE_SHADER_IR_TGSI' and the tokens ptr will be valid. If the driver
291 * requests a different 'pipe_shader_ir' type, then it must check the 'type'
292 * enum to see if it is getting TGSI tokens or its preferred IR.
294 * TODO pipe_compute_state should probably get similar treatment to handle
295 * multiple IR's in a cleaner way..
297 * NOTE: since it is expected that the consumer will want to perform
298 * additional passes on the nir_shader, the driver takes ownership of
299 * the nir_shader. If gallium frontends need to hang on to the IR (for
300 * example, variant management), it should use nir_shader_clone().
302 struct pipe_shader_state
304 enum pipe_shader_ir type;
305 /* TODO move tokens into union. */
306 const struct tgsi_token *tokens;
311 struct pipe_stream_output_info stream_output;
315 pipe_shader_state_from_tgsi(struct pipe_shader_state *state,
316 const struct tgsi_token *tokens)
318 state->type = PIPE_SHADER_IR_TGSI;
319 state->tokens = tokens;
320 memset(&state->stream_output, 0, sizeof(state->stream_output));
324 struct pipe_stencil_state
326 unsigned enabled:1; /**< stencil[0]: stencil enabled, stencil[1]: two-side enabled */
327 unsigned func:3; /**< PIPE_FUNC_x */
328 unsigned fail_op:3; /**< PIPE_STENCIL_OP_x */
329 unsigned zpass_op:3; /**< PIPE_STENCIL_OP_x */
330 unsigned zfail_op:3; /**< PIPE_STENCIL_OP_x */
331 unsigned valuemask:8;
332 unsigned writemask:8;
336 struct pipe_depth_stencil_alpha_state
338 struct pipe_stencil_state stencil[2]; /**< [0] = front, [1] = back */
340 unsigned alpha_enabled:1; /**< alpha test enabled? */
341 unsigned alpha_func:3; /**< PIPE_FUNC_x */
343 unsigned depth_enabled:1; /**< depth test enabled? */
344 unsigned depth_writemask:1; /**< allow depth buffer writes? */
345 unsigned depth_func:3; /**< depth test func (PIPE_FUNC_x) */
346 unsigned depth_bounds_test:1; /**< depth bounds test enabled? */
348 float alpha_ref_value; /**< reference value */
349 double depth_bounds_min; /**< minimum depth bound */
350 double depth_bounds_max; /**< maximum depth bound */
354 struct pipe_rt_blend_state
356 unsigned blend_enable:1;
358 unsigned rgb_func:3; /**< PIPE_BLEND_x */
359 unsigned rgb_src_factor:5; /**< PIPE_BLENDFACTOR_x */
360 unsigned rgb_dst_factor:5; /**< PIPE_BLENDFACTOR_x */
362 unsigned alpha_func:3; /**< PIPE_BLEND_x */
363 unsigned alpha_src_factor:5; /**< PIPE_BLENDFACTOR_x */
364 unsigned alpha_dst_factor:5; /**< PIPE_BLENDFACTOR_x */
366 unsigned colormask:4; /**< bitmask of PIPE_MASK_R/G/B/A */
370 struct pipe_blend_state
372 unsigned independent_blend_enable:1;
373 unsigned logicop_enable:1;
374 unsigned logicop_func:4; /**< PIPE_LOGICOP_x */
376 unsigned alpha_to_coverage:1;
377 unsigned alpha_to_coverage_dither:1;
378 unsigned alpha_to_one:1;
379 unsigned max_rt:3; /* index of max rt, Ie. # of cbufs minus 1 */
380 unsigned advanced_blend_func:4;
381 struct pipe_rt_blend_state rt[PIPE_MAX_COLOR_BUFS];
385 struct pipe_blend_color
391 struct pipe_stencil_ref
398 * Note that pipe_surfaces are "texture views for rendering"
399 * and so in the case of ARB_framebuffer_no_attachment there
400 * is no pipe_surface state available such that we may
401 * extract the number of samples and layers.
403 struct pipe_framebuffer_state
405 uint16_t width, height;
406 uint16_t layers; /**< Number of layers in a no-attachment framebuffer */
407 ubyte samples; /**< Number of samples in a no-attachment framebuffer */
409 /** multiple color buffers for multiple render targets */
411 struct pipe_surface *cbufs[PIPE_MAX_COLOR_BUFS];
413 struct pipe_surface *zsbuf; /**< Z/stencil buffer */
418 * Texture sampler state.
420 struct pipe_sampler_state
422 unsigned wrap_s:3; /**< PIPE_TEX_WRAP_x */
423 unsigned wrap_t:3; /**< PIPE_TEX_WRAP_x */
424 unsigned wrap_r:3; /**< PIPE_TEX_WRAP_x */
425 unsigned min_img_filter:1; /**< PIPE_TEX_FILTER_x */
426 unsigned min_mip_filter:2; /**< PIPE_TEX_MIPFILTER_x */
427 unsigned mag_img_filter:1; /**< PIPE_TEX_FILTER_x */
428 unsigned compare_mode:1; /**< PIPE_TEX_COMPARE_x */
429 unsigned compare_func:3; /**< PIPE_FUNC_x */
430 unsigned unnormalized_coords:1; /**< Are coords normalized to [0,1]? */
431 unsigned max_anisotropy:5;
432 unsigned seamless_cube_map:1;
433 unsigned border_color_is_integer:1;
434 unsigned reduction_mode:2; /**< PIPE_TEX_REDUCTION_x */
435 unsigned pad:5; /**< take bits from this for new members */
436 float lod_bias; /**< LOD/lambda bias */
437 float min_lod, max_lod; /**< LOD clamp range, after bias */
438 union pipe_color_union border_color;
439 enum pipe_format border_color_format; /**< only with PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_FREEDRENO, must be last */
442 union pipe_surface_desc {
445 unsigned first_layer:16;
446 unsigned last_layer:16;
449 unsigned first_element;
450 unsigned last_element;
455 * A view into a texture that can be bound to a color render target /
456 * depth stencil attachment point.
460 struct pipe_reference reference;
461 enum pipe_format format:16;
462 unsigned writable:1; /**< writable shader resource */
463 struct pipe_resource *texture; /**< resource into which this is a view */
464 struct pipe_context *context; /**< context this surface belongs to */
466 /* XXX width/height should be removed */
467 uint16_t width; /**< logical width in pixels */
468 uint16_t height; /**< logical height in pixels */
471 * Number of samples for the surface. This will be 0 if rendering
472 * should use the resource's nr_samples, or another value if the resource
473 * is bound using FramebufferTexture2DMultisampleEXT.
475 unsigned nr_samples:8;
477 union pipe_surface_desc u;
482 * A view into a texture that can be bound to a shader stage.
484 struct pipe_sampler_view
486 /* Put the refcount on its own cache line to prevent "False sharing". */
487 EXCLUSIVE_CACHELINE(struct pipe_reference reference);
489 enum pipe_format format:15; /**< typed PIPE_FORMAT_x */
490 enum pipe_texture_target target:5; /**< PIPE_TEXTURE_x */
491 unsigned swizzle_r:3; /**< PIPE_SWIZZLE_x for red component */
492 unsigned swizzle_g:3; /**< PIPE_SWIZZLE_x for green component */
493 unsigned swizzle_b:3; /**< PIPE_SWIZZLE_x for blue component */
494 unsigned swizzle_a:3; /**< PIPE_SWIZZLE_x for alpha component */
495 struct pipe_resource *texture; /**< texture into which this is a view */
496 struct pipe_context *context; /**< context this view belongs to */
499 unsigned first_layer:16; /**< first layer to use for array textures */
500 unsigned last_layer:16; /**< last layer to use for array textures */
501 unsigned first_level:8; /**< first mipmap level to use */
502 unsigned last_level:8; /**< last mipmap level to use */
505 unsigned offset; /**< offset in bytes */
506 unsigned size; /**< size of the readable sub-range in bytes */
513 * A description of a buffer or texture image that can be bound to a shader
516 struct pipe_image_view
518 struct pipe_resource *resource; /**< resource into which this is a view */
519 enum pipe_format format; /**< typed PIPE_FORMAT_x */
520 uint16_t access; /**< PIPE_IMAGE_ACCESS_x */
521 uint16_t shader_access; /**< PIPE_IMAGE_ACCESS_x */
525 unsigned first_layer:16; /**< first layer to use for array textures */
526 unsigned last_layer:16; /**< last layer to use for array textures */
527 unsigned level:8; /**< mipmap level to use */
530 unsigned offset; /**< offset in bytes */
531 unsigned size; /**< size of the accessible sub-range in bytes */
538 * Subregion of 1D/2D/3D image resource.
542 /* Fields only used by textures use int16_t instead of int.
543 * x and width are used by buffers, so they need the full 32-bit range.
555 * A memory object/resource such as a vertex buffer or texture.
559 /* Put the refcount on its own cache line to prevent "False sharing". */
560 EXCLUSIVE_CACHELINE(struct pipe_reference reference);
562 unsigned width0; /**< Used by both buffers and textures. */
563 uint16_t height0; /* Textures: The maximum height/depth/array_size is 16k. */
567 enum pipe_format format:16; /**< PIPE_FORMAT_x */
568 enum pipe_texture_target target:8; /**< PIPE_TEXTURE_x */
569 unsigned last_level:8; /**< Index of last mipmap level present/defined */
571 /** Number of samples determining quality, driving rasterizer, shading,
574 unsigned nr_samples:8;
576 /** Multiple samples within a pixel can have the same value.
577 * nr_storage_samples determines how many slots for different values
578 * there are per pixel. Only color buffers can set this lower than
581 unsigned nr_storage_samples:8;
583 unsigned nr_sparse_levels:8; /**< Mipmap levels support partial resident */
585 unsigned usage:8; /**< PIPE_USAGE_x (not a bitmask) */
586 unsigned bind; /**< bitmask of PIPE_BIND_x */
587 unsigned flags; /**< bitmask of PIPE_RESOURCE_FLAG_x */
590 * For planar images, ie. YUV EGLImage external, etc, pointer to the
593 struct pipe_resource *next;
594 /* The screen pointer should be last for optimal structure packing. */
595 struct pipe_screen *screen; /**< screen that this texture belongs to */
599 * Opaque object used for separate resource/memory allocations.
601 struct pipe_memory_allocation;
604 * Transfer object. For data transfer to/from a resource.
608 struct pipe_resource *resource; /**< resource to transfer to/from */
609 enum pipe_map_flags usage:24;
610 unsigned level:8; /**< texture mipmap level */
611 struct pipe_box box; /**< region of the resource to access */
612 unsigned stride; /**< row stride in bytes */
613 unsigned layer_stride; /**< image/layer stride in bytes */
615 /* Offset into a driver-internal staging buffer to make use of unused
616 * padding in this structure.
623 * A vertex buffer. Typically, all the vertex data/attributes for
624 * drawing something will be in one buffer. But it's also possible, for
625 * example, to put colors in one buffer and texcoords in another.
627 struct pipe_vertex_buffer
629 uint16_t stride; /**< stride to same attrib in next vertex, in bytes */
631 unsigned buffer_offset; /**< offset to start of data in buffer, in bytes */
634 struct pipe_resource *resource; /**< the actual buffer */
635 const void *user; /**< pointer to a user buffer */
641 * A constant buffer. A subrange of an existing buffer can be set
642 * as a constant buffer.
644 struct pipe_constant_buffer
646 struct pipe_resource *buffer; /**< the actual buffer */
647 unsigned buffer_offset; /**< offset to start of data in buffer, in bytes */
648 unsigned buffer_size; /**< how much data can be read in shader */
649 const void *user_buffer; /**< pointer to a user buffer if buffer == NULL */
654 * An untyped shader buffer supporting loads, stores, and atomics.
656 struct pipe_shader_buffer {
657 struct pipe_resource *buffer; /**< the actual buffer */
658 unsigned buffer_offset; /**< offset to start of data in buffer, in bytes */
659 unsigned buffer_size; /**< how much data can be read in shader */
664 * A stream output target. The structure specifies the range vertices can
667 * In addition to that, the structure should internally maintain the offset
668 * into the buffer, which should be incremented everytime something is written
669 * (appended) to it. The internal offset is buffer_offset + how many bytes
670 * have been written. The internal offset can be stored on the device
671 * and the CPU actually doesn't have to query it.
673 * Note that the buffer_size variable is actually specifying the available
674 * space in the buffer, not the size of the attached buffer.
675 * In other words in majority of cases buffer_size would simply be
676 * 'buffer->width0 - buffer_offset', so buffer_size refers to the size
677 * of the buffer left, after accounting for buffer offset, for stream output
680 * Use PIPE_QUERY_SO_STATISTICS to know how many primitives have
681 * actually been written.
683 struct pipe_stream_output_target
685 struct pipe_reference reference;
686 struct pipe_resource *buffer; /**< the output buffer */
687 struct pipe_context *context; /**< context this SO target belongs to */
689 unsigned buffer_offset; /**< offset where data should be written, in bytes */
690 unsigned buffer_size; /**< how much data is allowed to be written */
695 * Information to describe a vertex attribute (position, color, etc)
697 struct pipe_vertex_element
699 /** Offset of this attribute, in bytes, from the start of the vertex */
702 /** Which vertex_buffer (as given to pipe->set_vertex_buffer()) does
703 * this attribute live in?
705 uint8_t vertex_buffer_index:7;
708 * Whether this element refers to a dual-slot vertex shader input.
709 * The purpose of this field is to do dual-slot lowering when the CSO is
710 * created instead of during every state change.
712 * It's lowered by util_lower_uint64_vertex_elements.
717 * This has only 8 bits because all vertex formats should be <= 255.
719 uint8_t src_format; /* low 8 bits of enum pipe_format. */
721 /** Instance data rate divisor. 0 means this is per-vertex data,
722 * n means per-instance data used for n consecutive instances (n > 0).
724 unsigned instance_divisor;
728 * Opaque refcounted constant state object encapsulating a vertex buffer,
729 * index buffer, and vertex elements. Used by display lists to bind those
730 * states and pass buffer references quickly.
732 * The state contains 1 index buffer, 0 or 1 vertex buffer, and 0 or more
735 * Constraints on the buffers to get the fastest codepath:
736 * - All buffer contents are considered immutable and read-only after
737 * initialization. This implies the following things.
738 * - No place is required to track whether these buffers are busy.
739 * - All CPU mappings of these buffers can be forced to UNSYNCHRONIZED by
740 * both drivers and common code unconditionally.
741 * - Buffer invalidation can be skipped by both drivers and common code
744 struct pipe_vertex_state {
745 struct pipe_reference reference;
746 struct pipe_screen *screen;
748 /* The following structure is used as a key for util_vertex_state_cache
749 * to deduplicate identical state objects and thus enable more
750 * opportunities for draw merging.
753 struct pipe_resource *indexbuf;
754 struct pipe_vertex_buffer vbuffer;
755 unsigned num_elements;
756 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS];
757 uint32_t full_velem_mask;
761 struct pipe_draw_indirect_info
763 unsigned offset; /**< must be 4 byte aligned */
764 unsigned stride; /**< must be 4 byte aligned */
765 unsigned draw_count; /**< number of indirect draws */
766 unsigned indirect_draw_count_offset; /**< must be 4 byte aligned */
768 /* Indirect draw parameters resource is laid out as follows:
770 * if using indexed drawing:
773 * uint32_t instance_count;
775 * int32_t index_bias;
776 * uint32_t start_instance;
781 * uint32_t instance_count;
783 * uint32_t start_instance;
786 * If NULL, count_from_stream_output != NULL.
788 struct pipe_resource *buffer;
790 /* Indirect draw count resource: If not NULL, contains a 32-bit value which
791 * is to be used as the real draw_count.
793 struct pipe_resource *indirect_draw_count;
796 * Stream output target. If not NULL, it's used to provide the 'count'
797 * parameter based on the number vertices captured by the stream output
798 * stage. (or generally, based on the number of bytes captured)
800 * Only 'mode', 'start_instance', and 'instance_count' are taken into
801 * account, all the other variables from pipe_draw_info are ignored.
803 * 'start' is implicitly 0 and 'count' is set as discussed above.
804 * The draw command is non-indexed.
806 * Note that this only provides the count. The vertex buffers must
807 * be set via set_vertex_buffers manually.
809 struct pipe_stream_output_target *count_from_stream_output;
812 struct pipe_draw_start_count_bias {
815 int index_bias; /**< a bias to be added to each index */
819 * Draw vertex state description. It's translated to pipe_draw_info as follows:
820 * - mode comes from this structure
822 * - instance_count is 1
823 * - index.resource comes from pipe_vertex_state
824 * - everything else is 0
826 struct pipe_draw_vertex_state_info {
827 #if defined(__GNUC__)
828 /* sizeof(mode) == 1 because it's a packed enum. */
829 enum pipe_prim_type mode; /**< the mode of the primitive */
831 /* sizeof(mode) == 1 is required by draw merging in u_threaded_context. */
832 uint8_t mode; /**< the mode of the primitive */
834 bool take_vertex_state_ownership; /**< for skipping reference counting */
838 * Information to describe a draw_vbo call.
840 struct pipe_draw_info
842 #if defined(__GNUC__)
843 /* sizeof(mode) == 1 because it's a packed enum. */
844 enum pipe_prim_type mode; /**< the mode of the primitive */
846 /* sizeof(mode) == 1 is required by draw merging in u_threaded_context. */
847 uint8_t mode; /**< the mode of the primitive */
849 uint8_t index_size; /**< if 0, the draw is not indexed. */
850 uint8_t view_mask; /**< mask of multiviews for this draw */
851 bool primitive_restart:1;
852 bool has_user_indices:1; /**< if true, use index.user_buffer */
853 bool index_bounds_valid:1; /**< whether min_index and max_index are valid;
854 they're always invalid if index_size == 0 */
855 bool increment_draw_id:1; /**< whether drawid increments for direct draws */
856 bool take_index_buffer_ownership:1; /**< callee inherits caller's refcount
857 (no need to reference indexbuf, but still needs to unreference it) */
858 bool index_bias_varies:1; /**< true if index_bias varies between draws */
859 bool was_line_loop:1; /**< true if pipe_prim_type was LINE_LOOP before translation */
862 unsigned start_instance; /**< first instance id */
863 unsigned instance_count; /**< number of instances */
866 * Primitive restart enable/index (only applies to indexed drawing)
868 unsigned restart_index;
870 /* Pointers must be placed appropriately for optimal structure packing on
875 * An index buffer. When an index buffer is bound, all indices to vertices
876 * will be looked up from the buffer.
878 * If has_user_indices, use index.user, else use index.resource.
881 struct pipe_resource *resource; /**< real buffer */
882 struct gl_buffer_object *gl_bo; /**< for the GL frontend, not passed to drivers */
883 const void *user; /**< pointer to a user buffer */
886 /* These must be last for better packing in u_threaded_context. */
887 unsigned min_index; /**< the min index */
888 unsigned max_index; /**< the max index */
893 * Information to describe a blit call.
895 struct pipe_blit_info
898 struct pipe_resource *resource;
900 struct pipe_box box; /**< negative width, height only legal for src */
901 /* For pipe_surface-like format casting: */
902 enum pipe_format format; /**< must be supported for sampling (src)
903 or rendering (dst), ZS is always supported */
906 unsigned mask; /**< bitmask of PIPE_MASK_R/G/B/A/Z/S */
907 unsigned filter; /**< PIPE_TEX_FILTER_* */
908 uint8_t dst_sample; /**< if non-zero, set sample_mask to (1 << (dst_sample - 1)) */
911 struct pipe_scissor_state scissor;
913 /* Window rectangles can either be inclusive or exclusive. */
914 bool window_rectangle_include;
915 unsigned num_window_rectangles;
916 struct pipe_scissor_state window_rectangles[PIPE_MAX_WINDOW_RECTANGLES];
918 bool render_condition_enable; /**< whether the blit should honor the
919 current render condition */
920 bool alpha_blend; /* dst.rgb = src.rgb * src.a + dst.rgb * (1 - src.a) */
924 * Information to describe a launch_grid call.
926 struct pipe_grid_info
929 * For drivers that use PIPE_SHADER_IR_NATIVE as their prefered IR, this
930 * value will be the index of the kernel in the opencl.kernels metadata
936 * Will be used to initialize the INPUT resource, and it should point to a
937 * buffer of at least pipe_compute_state::req_input_mem bytes.
942 * Variable shared memory used by this invocation.
944 * This comes on top of shader declared shared memory.
946 uint32_t variable_shared_mem;
949 * Grid number of dimensions, 1-3, e.g. the work_dim parameter passed to
950 * clEnqueueNDRangeKernel. Note block[] and grid[] must be padded with
951 * 1 for non-used dimensions.
956 * Determine the layout of the working block (in thread units) to be used.
961 * last_block allows disabling threads at the farthermost grid boundary.
962 * Full blocks as specified by "block" are launched, but the threads
963 * outside of "last_block" dimensions are disabled.
965 * If a block touches the grid boundary in the i-th axis, threads with
966 * THREAD_ID[i] >= last_block[i] are disabled.
968 * If last_block[i] is 0, it has the same behavior as last_block[i] = block[i],
971 * It's equivalent to doing this at the beginning of the compute shader:
973 * for (i = 0; i < 3; i++) {
974 * if (block_id[i] == grid[i] - 1 &&
975 * last_block[i] && thread_id[i] >= last_block[i])
982 * Determine the layout of the grid (in block units) to be used.
987 * Base offsets to launch grids from
991 /* Indirect compute parameters resource: If not NULL, block sizes are taken
992 * from this buffer instead, which is laid out as follows:
995 * uint32_t num_blocks_x;
996 * uint32_t num_blocks_y;
997 * uint32_t num_blocks_z;
1000 struct pipe_resource *indirect;
1001 unsigned indirect_offset; /**< must be 4 byte aligned */
1005 * Structure used as a header for serialized compute programs.
1007 struct pipe_binary_program_header
1009 uint32_t num_bytes; /**< Number of bytes in the LLVM bytecode program. */
1013 struct pipe_compute_state
1015 enum pipe_shader_ir ir_type; /**< IR type contained in prog. */
1016 const void *prog; /**< Compute program to be executed. */
1017 unsigned static_shared_mem; /**< equal to info.shared_size, used for shaders passed as TGSI */
1018 unsigned req_input_mem; /**< Required size of the INPUT resource. */
1022 * Structure that contains a callback for device reset messages from the driver
1023 * back to the gallium frontend.
1025 * The callback must not be called from driver-created threads.
1027 struct pipe_device_reset_callback
1030 * Callback for the driver to report when a device reset is detected.
1032 * \param data user-supplied data pointer
1033 * \param status PIPE_*_RESET
1035 void (*reset)(void *data, enum pipe_reset_status status);
1041 * Information about memory usage. All sizes are in kilobytes.
1043 struct pipe_memory_info
1045 unsigned total_device_memory; /**< size of device memory, e.g. VRAM */
1046 unsigned avail_device_memory; /**< free device memory at the moment */
1047 unsigned total_staging_memory; /**< size of staging memory, e.g. GART */
1048 unsigned avail_staging_memory; /**< free staging memory at the moment */
1049 unsigned device_memory_evicted; /**< size of memory evicted (monotonic counter) */
1050 unsigned nr_device_memory_evictions; /**< # of evictions (monotonic counter) */
1054 * Structure that contains information about external memory
1056 struct pipe_memory_object