src/gallium/drivers/r600/r700_asm.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include <stdio.h>
  24 #include "util/u_memory.h"
  25 #include "r600_pipe.h"
  26 #include "r600_asm.h"
  27 #include "r700_sq.h"
  28
  29 void r700_bc_cf_vtx_build(uint32_t *bytecode, const struct r600_bc_cf *cf)
  30 {
  31         unsigned count = (cf->ndw / 4) - 1;
  32         *bytecode++ = S_SQ_CF_WORD0_ADDR(cf->addr >> 1);
  33         *bytecode++ = S_SQ_CF_WORD1_CF_INST(cf->inst) |
  34                         S_SQ_CF_WORD1_BARRIER(1) |
  35                         S_SQ_CF_WORD1_COUNT(count) |
  36                         S_SQ_CF_WORD1_COUNT_3(count >> 3);
  37 }
  38
  39 int r700_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned id)
  40 {
  41         bc->bytecode[id++] = S_SQ_ALU_WORD0_SRC0_SEL(alu->src[0].sel) |
  42                 S_SQ_ALU_WORD0_SRC0_REL(alu->src[0].rel) |
  43                 S_SQ_ALU_WORD0_SRC0_CHAN(alu->src[0].chan) |
  44                 S_SQ_ALU_WORD0_SRC0_NEG(alu->src[0].neg) |
  45                 S_SQ_ALU_WORD0_SRC1_SEL(alu->src[1].sel) |
  46                 S_SQ_ALU_WORD0_SRC1_REL(alu->src[1].rel) |
  47                 S_SQ_ALU_WORD0_SRC1_CHAN(alu->src[1].chan) |
  48                 S_SQ_ALU_WORD0_SRC1_NEG(alu->src[1].neg) |
  49                 S_SQ_ALU_WORD0_LAST(alu->last);
  50
  51         /* don't replace gpr by pv or ps for destination register */
  52         if (alu->is_op3) {
  53                 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
  54                                         S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
  55                                         S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
  56                                         S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
  57                                         S_SQ_ALU_WORD1_OP3_SRC2_SEL(alu->src[2].sel) |
  58                                         S_SQ_ALU_WORD1_OP3_SRC2_REL(alu->src[2].rel) |
  59                                         S_SQ_ALU_WORD1_OP3_SRC2_CHAN(alu->src[2].chan) |
  60                                         S_SQ_ALU_WORD1_OP3_SRC2_NEG(alu->src[2].neg) |
  61                                         S_SQ_ALU_WORD1_OP3_ALU_INST(alu->inst) |
  62                                         S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle);
  63         } else {
  64                 bc->bytecode[id++] = S_SQ_ALU_WORD1_DST_GPR(alu->dst.sel) |
  65                                         S_SQ_ALU_WORD1_DST_CHAN(alu->dst.chan) |
  66                                         S_SQ_ALU_WORD1_DST_REL(alu->dst.rel) |
  67                                         S_SQ_ALU_WORD1_CLAMP(alu->dst.clamp) |
  68                                         S_SQ_ALU_WORD1_OP2_SRC0_ABS(alu->src[0].abs) |
  69                                         S_SQ_ALU_WORD1_OP2_SRC1_ABS(alu->src[1].abs) |
  70                                         S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu->dst.write) |
  71                                         S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) |
  72                                         S_SQ_ALU_WORD1_OP2_ALU_INST(alu->inst) |
  73                                         S_SQ_ALU_WORD1_BANK_SWIZZLE(alu->bank_swizzle) |
  74                                         S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu->predicate) |
  75                                         S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu->predicate);
  76         }
  77         return 0;
  78 }