2 * Copyright 2010 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie <airlied@redhat.com>
25 * Jerome Glisse <jglisse@redhat.com>
27 #include <util/u_memory.h>
28 #include <util/u_format.h>
29 #include <pipebuffer/pb_buffer.h>
30 #include "pipe/p_shader_tokens.h"
31 #include "tgsi/tgsi_parse.h"
32 #include "r600_formats.h"
33 #include "r600_pipe.h"
36 static void r600_spi_update(struct r600_pipe_context *rctx);
38 static int r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
40 static const int prim_conv[] = {
41 V_008958_DI_PT_POINTLIST,
42 V_008958_DI_PT_LINELIST,
43 V_008958_DI_PT_LINELOOP,
44 V_008958_DI_PT_LINESTRIP,
45 V_008958_DI_PT_TRILIST,
46 V_008958_DI_PT_TRISTRIP,
47 V_008958_DI_PT_TRIFAN,
48 V_008958_DI_PT_QUADLIST,
49 V_008958_DI_PT_QUADSTRIP,
50 V_008958_DI_PT_POLYGON,
57 *prim = prim_conv[pprim];
59 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim);
65 /* common state between evergreen and r600 */
66 void r600_bind_blend_state(struct pipe_context *ctx, void *state)
68 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
69 struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
70 struct r600_pipe_state *rstate;
74 rstate = &blend->rstate;
75 rctx->states[rstate->id] = rstate;
76 rctx->cb_target_mask = blend->cb_target_mask;
77 r600_context_pipe_state_set(&rctx->ctx, rstate);
80 void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
82 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
83 struct r600_pipe_dsa *dsa = state;
84 struct r600_pipe_state *rstate;
88 rstate = &dsa->rstate;
89 rctx->states[rstate->id] = rstate;
90 rctx->alpha_ref = dsa->alpha_ref;
91 rctx->alpha_ref_dirty = true;
92 r600_context_pipe_state_set(&rctx->ctx, rstate);
95 void r600_bind_rs_state(struct pipe_context *ctx, void *state)
97 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
98 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
103 rctx->clamp_vertex_color = rs->clamp_vertex_color;
104 rctx->clamp_fragment_color = rs->clamp_fragment_color;
105 rctx->flatshade = rs->flatshade;
106 rctx->sprite_coord_enable = rs->sprite_coord_enable;
107 rctx->rasterizer = rs;
109 rctx->states[rs->rstate.id] = &rs->rstate;
110 r600_context_pipe_state_set(&rctx->ctx, &rs->rstate);
112 if (rctx->family >= CHIP_CEDAR) {
113 evergreen_polygon_offset_update(rctx);
115 r600_polygon_offset_update(rctx);
117 if (rctx->ps_shader && rctx->vs_shader)
118 rctx->spi_dirty = true;
121 void r600_delete_rs_state(struct pipe_context *ctx, void *state)
123 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
124 struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
126 if (rctx->rasterizer == rs) {
127 rctx->rasterizer = NULL;
129 if (rctx->states[rs->rstate.id] == &rs->rstate) {
130 rctx->states[rs->rstate.id] = NULL;
135 void r600_sampler_view_destroy(struct pipe_context *ctx,
136 struct pipe_sampler_view *state)
138 struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
140 pipe_resource_reference(&state->texture, NULL);
144 void r600_delete_state(struct pipe_context *ctx, void *state)
146 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
147 struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
149 if (rctx->states[rstate->id] == rstate) {
150 rctx->states[rstate->id] = NULL;
152 for (int i = 0; i < rstate->nregs; i++) {
153 r600_bo_reference(rctx->radeon, &rstate->regs[i].bo, NULL);
158 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
160 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
161 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
163 rctx->vertex_elements = v;
165 u_vbuf_mgr_bind_vertex_elements(rctx->vbuf_mgr, state,
168 rctx->states[v->rstate.id] = &v->rstate;
169 r600_context_pipe_state_set(&rctx->ctx, &v->rstate);
173 void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
175 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
176 struct r600_vertex_element *v = (struct r600_vertex_element*)state;
178 if (rctx->states[v->rstate.id] == &v->rstate) {
179 rctx->states[v->rstate.id] = NULL;
181 if (rctx->vertex_elements == state)
182 rctx->vertex_elements = NULL;
184 r600_bo_reference(rctx->radeon, &v->fetch_shader, NULL);
185 u_vbuf_mgr_destroy_vertex_elements(rctx->vbuf_mgr, v->vmgr_elements);
190 void r600_set_index_buffer(struct pipe_context *ctx,
191 const struct pipe_index_buffer *ib)
193 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
196 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
197 memcpy(&rctx->index_buffer, ib, sizeof(rctx->index_buffer));
199 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
200 memset(&rctx->index_buffer, 0, sizeof(rctx->index_buffer));
203 /* TODO make this more like a state */
206 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
207 const struct pipe_vertex_buffer *buffers)
209 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
213 for (i = 0; i < count; i++) {
214 if (!buffers[i].buffer) {
215 if (rctx->family >= CHIP_CEDAR) {
216 evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
218 r600_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
222 for (; i < rctx->vbuf_mgr->nr_real_vertex_buffers; i++) {
223 if (rctx->family >= CHIP_CEDAR) {
224 evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
226 r600_context_pipe_state_set_fs_resource(&rctx->ctx, NULL, i);
230 u_vbuf_mgr_set_vertex_buffers(rctx->vbuf_mgr, count, buffers);
233 void *r600_create_vertex_elements(struct pipe_context *ctx,
235 const struct pipe_vertex_element *elements)
237 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
238 struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
246 u_vbuf_mgr_create_vertex_elements(rctx->vbuf_mgr, count,
247 elements, v->elements);
249 if (r600_vertex_elements_build_fetch_shader(rctx, v)) {
257 void *r600_create_shader_state(struct pipe_context *ctx,
258 const struct pipe_shader_state *state)
260 struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
263 shader->tokens = tgsi_dup_tokens(state->tokens);
265 r = r600_pipe_shader_create(ctx, shader);
272 void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
274 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
276 /* TODO delete old shader */
277 rctx->ps_shader = (struct r600_pipe_shader *)state;
279 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_shader->rstate);
281 if (rctx->ps_shader && rctx->vs_shader) {
282 rctx->spi_dirty = true;
283 r600_adjust_gprs(rctx);
287 void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
289 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
291 /* TODO delete old shader */
292 rctx->vs_shader = (struct r600_pipe_shader *)state;
294 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_shader->rstate);
296 if (rctx->ps_shader && rctx->vs_shader) {
297 rctx->spi_dirty = true;
298 r600_adjust_gprs(rctx);
302 void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
304 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
305 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
307 if (rctx->ps_shader == shader) {
308 rctx->ps_shader = NULL;
311 free(shader->tokens);
312 r600_pipe_shader_destroy(ctx, shader);
316 void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
318 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
319 struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
321 if (rctx->vs_shader == shader) {
322 rctx->vs_shader = NULL;
325 free(shader->tokens);
326 r600_pipe_shader_destroy(ctx, shader);
330 static void r600_update_alpha_ref(struct r600_pipe_context *rctx)
333 struct r600_pipe_state rstate;
335 alpha_ref = rctx->alpha_ref;
337 if (rctx->export_16bpc)
338 alpha_ref &= ~0x1FFF;
339 r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref, 0xFFFFFFFF, NULL);
341 r600_context_pipe_state_set(&rctx->ctx, &rstate);
342 rctx->alpha_ref_dirty = false;
345 /* FIXME optimize away spi update when it's not needed */
346 static void r600_spi_block_init(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate)
350 rstate->id = R600_PIPE_STATE_SPI;
351 for (i = 0; i < 32; i++) {
352 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4, 0, 0xFFFFFFFF, NULL);
356 static void r600_spi_update(struct r600_pipe_context *rctx)
358 struct r600_pipe_shader *shader = rctx->ps_shader;
359 struct r600_pipe_state *rstate = &rctx->spi;
360 struct r600_shader *rshader = &shader->shader;
361 unsigned i, tmp, sid;
363 if (rctx->spi.id == 0)
364 r600_spi_block_init(rctx, &rctx->spi);
367 for (i = 0; i < rshader->ninput; i++) {
368 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
369 rshader->input[i].name == TGSI_SEMANTIC_FACE)
370 if (rctx->family >= CHIP_CEDAR)
375 sid=r600_find_vs_semantic_index(&rctx->vs_shader->shader, rshader, i);
377 tmp = S_028644_SEMANTIC(sid);
379 if (rshader->input[i].name == TGSI_SEMANTIC_COLOR ||
380 rshader->input[i].name == TGSI_SEMANTIC_BCOLOR ||
381 rshader->input[i].name == TGSI_SEMANTIC_POSITION) {
382 tmp |= S_028644_FLAT_SHADE(rctx->flatshade);
385 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
386 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
387 tmp |= S_028644_PT_SPRITE_TEX(1);
390 if (rctx->family < CHIP_CEDAR) {
391 if (rshader->input[i].centroid)
392 tmp |= S_028644_SEL_CENTROID(1);
394 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR)
395 tmp |= S_028644_SEL_LINEAR(1);
398 r600_pipe_state_mod_reg(rstate, tmp);
401 rctx->spi_dirty = false;
402 r600_context_pipe_state_set(&rctx->ctx, rstate);
405 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
406 struct pipe_resource *buffer)
408 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
409 struct r600_resource_buffer *rbuffer = r600_buffer(buffer);
410 struct r600_pipe_resource_state *rstate;
413 /* Note that the state tracker can unbind constant buffers by
416 if (buffer == NULL) {
420 r600_upload_const_buffer(rctx, &rbuffer, &offset);
421 offset += r600_bo_offset(rbuffer->r.bo);
424 case PIPE_SHADER_VERTEX:
425 rctx->vs_const_buffer.nregs = 0;
426 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
427 R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
428 ALIGN_DIVUP(buffer->width0 >> 4, 16),
430 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
431 R_028980_ALU_CONST_CACHE_VS_0,
432 offset >> 8, 0xFFFFFFFF, rbuffer->r.bo);
433 r600_context_pipe_state_set(&rctx->ctx, &rctx->vs_const_buffer);
435 rstate = &rctx->vs_const_buffer_resource[index];
437 if (rctx->family >= CHIP_CEDAR) {
438 evergreen_pipe_init_buffer_resource(rctx, rstate);
440 r600_pipe_init_buffer_resource(rctx, rstate);
444 if (rctx->family >= CHIP_CEDAR) {
445 evergreen_pipe_mod_buffer_resource(rstate, &rbuffer->r, offset, 16);
446 evergreen_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, index);
448 r600_pipe_mod_buffer_resource(rstate, &rbuffer->r, offset, 16);
449 r600_context_pipe_state_set_vs_resource(&rctx->ctx, rstate, index);
452 case PIPE_SHADER_FRAGMENT:
453 rctx->ps_const_buffer.nregs = 0;
454 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
455 R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
456 ALIGN_DIVUP(buffer->width0 >> 4, 16),
458 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
459 R_028940_ALU_CONST_CACHE_PS_0,
460 offset >> 8, 0xFFFFFFFF, rbuffer->r.bo);
461 r600_context_pipe_state_set(&rctx->ctx, &rctx->ps_const_buffer);
463 rstate = &rctx->ps_const_buffer_resource[index];
465 if (rctx->family >= CHIP_CEDAR) {
466 evergreen_pipe_init_buffer_resource(rctx, rstate);
468 r600_pipe_init_buffer_resource(rctx, rstate);
471 if (rctx->family >= CHIP_CEDAR) {
472 evergreen_pipe_mod_buffer_resource(rstate, &rbuffer->r, offset, 16);
473 evergreen_context_pipe_state_set_ps_resource(&rctx->ctx, rstate, index);
475 r600_pipe_mod_buffer_resource(rstate, &rbuffer->r, offset, 16);
476 r600_context_pipe_state_set_ps_resource(&rctx->ctx, rstate, index);
480 R600_ERR("unsupported %d\n", shader);
484 if (buffer != &rbuffer->r.b.b.b)
485 pipe_resource_reference((struct pipe_resource**)&rbuffer, NULL);
488 static void r600_vertex_buffer_update(struct r600_pipe_context *rctx)
490 struct r600_pipe_resource_state *rstate;
491 struct r600_resource *rbuffer;
492 struct pipe_vertex_buffer *vertex_buffer;
493 unsigned i, count, offset;
495 if (rctx->vertex_elements->vbuffer_need_offset) {
496 /* one resource per vertex elements */
497 count = rctx->vertex_elements->count;
499 /* bind vertex buffer once */
500 count = rctx->vbuf_mgr->nr_real_vertex_buffers;
503 for (i = 0 ; i < count; i++) {
504 rstate = &rctx->fs_resource[i];
506 if (rctx->vertex_elements->vbuffer_need_offset) {
507 /* one resource per vertex elements */
508 unsigned vbuffer_index;
509 vbuffer_index = rctx->vertex_elements->elements[i].vertex_buffer_index;
510 vertex_buffer = &rctx->vbuf_mgr->vertex_buffer[vbuffer_index];
511 rbuffer = (struct r600_resource*)rctx->vbuf_mgr->real_vertex_buffer[vbuffer_index];
512 offset = rctx->vertex_elements->vbuffer_offset[i];
514 /* bind vertex buffer once */
515 vertex_buffer = &rctx->vbuf_mgr->vertex_buffer[i];
516 rbuffer = (struct r600_resource*)rctx->vbuf_mgr->real_vertex_buffer[i];
519 if (vertex_buffer == NULL || rbuffer == NULL)
521 offset += vertex_buffer->buffer_offset + r600_bo_offset(rbuffer->bo);
524 if (rctx->family >= CHIP_CEDAR) {
525 evergreen_pipe_init_buffer_resource(rctx, rstate);
527 r600_pipe_init_buffer_resource(rctx, rstate);
531 if (rctx->family >= CHIP_CEDAR) {
532 evergreen_pipe_mod_buffer_resource(rstate, rbuffer, offset, vertex_buffer->stride);
533 evergreen_context_pipe_state_set_fs_resource(&rctx->ctx, rstate, i);
535 r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, vertex_buffer->stride);
536 r600_context_pipe_state_set_fs_resource(&rctx->ctx, rstate, i);
541 static int r600_shader_rebuild(struct pipe_context * ctx, struct r600_pipe_shader * shader)
543 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
546 r600_pipe_shader_destroy(ctx, shader);
547 r = r600_pipe_shader_create(ctx, shader);
551 r600_context_pipe_state_set(&rctx->ctx, &shader->rstate);
556 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
558 struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
559 struct r600_resource *rbuffer;
560 struct r600_draw rdraw;
561 struct r600_drawl draw;
565 if (rctx->have_depth_fb || rctx->have_depth_texture)
566 r600_flush_depth_textures(rctx);
568 u_vbuf_mgr_draw_begin(rctx->vbuf_mgr, info);
569 r600_vertex_buffer_update(rctx);
573 draw.index_buffer = NULL;
574 if (info->indexed && rctx->index_buffer.buffer) {
575 draw.info.start += rctx->index_buffer.offset / rctx->index_buffer.index_size;
576 pipe_resource_reference(&draw.index_buffer, rctx->index_buffer.buffer);
578 r600_translate_index_buffer(rctx, &draw.index_buffer,
579 &rctx->index_buffer.index_size,
583 draw.index_size = rctx->index_buffer.index_size;
584 draw.index_buffer_offset = draw.info.start * draw.index_size;
587 if (u_vbuf_resource(draw.index_buffer)->user_ptr) {
588 r600_upload_index_buffer(rctx, &draw);
592 draw.index_buffer_offset = 0;
593 draw.info.index_bias = info->start;
596 if (r600_conv_pipe_prim(draw.info.mode, &prim))
599 if (rctx->vs_shader->shader.clamp_color != rctx->clamp_vertex_color)
600 r600_shader_rebuild(ctx, rctx->vs_shader);
602 if ((rctx->ps_shader->shader.clamp_color != rctx->clamp_fragment_color) ||
603 (rctx->ps_shader->shader.fs_write_all &&
604 (rctx->ps_shader->shader.nr_cbufs != rctx->nr_cbufs)))
605 r600_shader_rebuild(ctx, rctx->ps_shader);
608 r600_spi_update(rctx);
610 if (rctx->alpha_ref_dirty)
611 r600_update_alpha_ref(rctx);
613 mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
615 if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
616 rctx->vgt.id = R600_PIPE_STATE_VGT;
618 r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, 0xFFFFFFFF, NULL);
619 r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, 0xFFFFFFFF, NULL);
620 r600_pipe_state_add_reg(&rctx->vgt, R_028400_VGT_MAX_VTX_INDX, draw.info.max_index, 0xFFFFFFFF, NULL);
621 r600_pipe_state_add_reg(&rctx->vgt, R_028404_VGT_MIN_VTX_INDX, draw.info.min_index, 0xFFFFFFFF, NULL);
622 r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, draw.info.index_bias, 0xFFFFFFFF, NULL);
623 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0xFFFFFFFF, NULL);
624 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, draw.info.start_instance, 0xFFFFFFFF, NULL);
625 r600_pipe_state_add_reg(&rctx->vgt, R_028814_PA_SU_SC_MODE_CNTL,
627 S_028814_PROVOKING_VTX_LAST(1), NULL);
632 r600_pipe_state_mod_reg(&rctx->vgt, prim);
633 r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_target_mask & mask);
634 r600_pipe_state_mod_reg(&rctx->vgt, draw.info.max_index);
635 r600_pipe_state_mod_reg(&rctx->vgt, draw.info.min_index);
636 r600_pipe_state_mod_reg(&rctx->vgt, draw.info.index_bias);
637 r600_pipe_state_mod_reg(&rctx->vgt, 0);
638 r600_pipe_state_mod_reg(&rctx->vgt, draw.info.start_instance);
639 if (draw.info.mode == PIPE_PRIM_QUADS || draw.info.mode == PIPE_PRIM_QUAD_STRIP || draw.info.mode == PIPE_PRIM_POLYGON) {
640 r600_pipe_state_mod_reg(&rctx->vgt, S_028814_PROVOKING_VTX_LAST(1));
643 r600_context_pipe_state_set(&rctx->ctx, &rctx->vgt);
645 rdraw.vgt_num_indices = draw.info.count;
646 rdraw.vgt_num_instances = draw.info.instance_count;
647 rdraw.vgt_index_type = ((draw.index_size == 4) ? 1 : 0);
649 rdraw.vgt_index_type |= (draw.index_size >> 1) << 2;
650 rdraw.vgt_draw_initiator = draw.index_size ? 0 : 2;
651 rdraw.indices = NULL;
652 if (draw.index_buffer) {
653 rbuffer = (struct r600_resource*)draw.index_buffer;
654 rdraw.indices = rbuffer->bo;
655 rdraw.indices_bo_offset = draw.index_buffer_offset;
658 if (rctx->family >= CHIP_CEDAR) {
659 evergreen_context_draw(&rctx->ctx, &rdraw);
661 r600_context_draw(&rctx->ctx, &rdraw);
664 if (rctx->framebuffer.zsbuf)
666 struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture;
667 ((struct r600_resource_texture *)tex)->dirty_db = TRUE;
670 pipe_resource_reference(&draw.index_buffer, NULL);
672 u_vbuf_mgr_draw_end(rctx->vbuf_mgr);
675 void _r600_pipe_state_add_reg(struct r600_context *ctx,
676 struct r600_pipe_state *state,
677 u32 offset, u32 value, u32 mask,
678 u32 range_id, u32 block_id,
681 struct r600_range *range;
682 struct r600_block *block;
684 range = &ctx->range[range_id];
685 block = range->blocks[block_id];
686 state->regs[state->nregs].block = block;
687 state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
689 state->regs[state->nregs].value = value;
690 state->regs[state->nregs].mask = mask;
691 state->regs[state->nregs].bo = bo;
694 assert(state->nregs < R600_BLOCK_MAX_REG);
697 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
698 u32 offset, u32 value, u32 mask,
701 state->regs[state->nregs].id = offset;
702 state->regs[state->nregs].block = NULL;
703 state->regs[state->nregs].value = value;
704 state->regs[state->nregs].mask = mask;
705 state->regs[state->nregs].bo = bo;
708 assert(state->nregs < R600_BLOCK_MAX_REG);