src/gallium/drivers/r600/r600_state_common.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *           2010 Jerome Glisse
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie <airlied@redhat.com>
  25  *          Jerome Glisse <jglisse@redhat.com>
  26  */
  27 #include "r600_formats.h"
  28 #include "r600d.h"
  29
  30 #include "util/u_blitter.h"
  31 #include "util/u_upload_mgr.h"
  32 #include "tgsi/tgsi_parse.h"
  33 #include <byteswap.h>
  34
  35 static void r600_emit_command_buffer(struct r600_context *rctx, struct r600_atom *atom)
  36 {
  37         struct radeon_winsys_cs *cs = rctx->cs;
  38         struct r600_command_buffer *cb = (struct r600_command_buffer*)atom;
  39
  40         assert(cs->cdw + cb->atom.num_dw <= RADEON_MAX_CMDBUF_DWORDS);
  41         memcpy(cs->buf + cs->cdw, cb->buf, 4 * cb->atom.num_dw);
  42         cs->cdw += cb->atom.num_dw;
  43 }
  44
  45 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags)
  46 {
  47         cb->atom.emit = r600_emit_command_buffer;
  48         cb->atom.num_dw = 0;
  49         cb->atom.flags = flags;
  50         cb->buf = CALLOC(1, 4 * num_dw);
  51         cb->max_num_dw = num_dw;
  52 }
  53
  54 void r600_release_command_buffer(struct r600_command_buffer *cb)
  55 {
  56         FREE(cb->buf);
  57 }
  58
  59 static void r600_emit_surface_sync(struct r600_context *rctx, struct r600_atom *atom)
  60 {
  61         struct radeon_winsys_cs *cs = rctx->cs;
  62         struct r600_surface_sync_cmd *a = (struct r600_surface_sync_cmd*)atom;
  63
  64         cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
  65         cs->buf[cs->cdw++] = a->flush_flags;  /* CP_COHER_CNTL */
  66         cs->buf[cs->cdw++] = 0xffffffff;      /* CP_COHER_SIZE */
  67         cs->buf[cs->cdw++] = 0;               /* CP_COHER_BASE */
  68         cs->buf[cs->cdw++] = 0x0000000A;      /* POLL_INTERVAL */
  69
  70         a->flush_flags = 0;
  71 }
  72
  73 static void r600_emit_r6xx_flush_and_inv(struct r600_context *rctx, struct r600_atom *atom)
  74 {
  75         struct radeon_winsys_cs *cs = rctx->cs;
  76         cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
  77         cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
  78 }
  79
  80 void r600_init_atom(struct r600_atom *atom,
  81                     void (*emit)(struct r600_context *ctx, struct r600_atom *state),
  82                     unsigned num_dw, enum r600_atom_flags flags)
  83 {
  84         atom->emit = emit;
  85         atom->num_dw = num_dw;
  86         atom->flags = flags;
  87 }
  88
  89 void r600_init_common_atoms(struct r600_context *rctx)
  90 {
  91         r600_init_atom(&rctx->surface_sync_cmd.atom,    r600_emit_surface_sync,         5, EMIT_EARLY);
  92         r600_init_atom(&rctx->r6xx_flush_and_inv_cmd,   r600_emit_r6xx_flush_and_inv,   2, EMIT_EARLY);
  93 }
  94
  95 unsigned r600_get_cb_flush_flags(struct r600_context *rctx)
  96 {
  97         unsigned flags = 0;
  98
  99         if (rctx->framebuffer.nr_cbufs) {
 100                 flags |= S_0085F0_CB_ACTION_ENA(1) |
 101                          (((1 << rctx->framebuffer.nr_cbufs) - 1) << S_0085F0_CB0_DEST_BASE_ENA_SHIFT);
 102         }
 103
 104         /* Workaround for broken flushing on some R6xx chipsets. */
 105         if (rctx->family == CHIP_RV670 ||
 106             rctx->family == CHIP_RS780 ||
 107             rctx->family == CHIP_RS880) {
 108                 flags |=  S_0085F0_CB1_DEST_BASE_ENA(1) |
 109                           S_0085F0_DEST_BASE_0_ENA(1);
 110         }
 111         return flags;
 112 }
 113
 114 void r600_texture_barrier(struct pipe_context *ctx)
 115 {
 116         struct r600_context *rctx = (struct r600_context *)ctx;
 117
 118         rctx->surface_sync_cmd.flush_flags |= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx);
 119         r600_atom_dirty(rctx, &rctx->surface_sync_cmd.atom);
 120 }
 121
 122 static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
 123 {
 124         static const int prim_conv[] = {
 125                 V_008958_DI_PT_POINTLIST,
 126                 V_008958_DI_PT_LINELIST,
 127                 V_008958_DI_PT_LINELOOP,
 128                 V_008958_DI_PT_LINESTRIP,
 129                 V_008958_DI_PT_TRILIST,
 130                 V_008958_DI_PT_TRISTRIP,
 131                 V_008958_DI_PT_TRIFAN,
 132                 V_008958_DI_PT_QUADLIST,
 133                 V_008958_DI_PT_QUADSTRIP,
 134                 V_008958_DI_PT_POLYGON,
 135                 -1,
 136                 -1,
 137                 -1,
 138                 -1
 139         };
 140
 141         *prim = prim_conv[pprim];
 142         if (*prim == -1) {
 143                 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim);
 144                 return false;
 145         }
 146         return true;
 147 }
 148
 149 /* common state between evergreen and r600 */
 150 void r600_bind_blend_state(struct pipe_context *ctx, void *state)
 151 {
 152         struct r600_context *rctx = (struct r600_context *)ctx;
 153         struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
 154         struct r600_pipe_state *rstate;
 155         bool update_cb = false;
 156
 157         if (state == NULL)
 158                 return;
 159         rstate = &blend->rstate;
 160         rctx->states[rstate->id] = rstate;
 161         rctx->dual_src_blend = blend->dual_src_blend;
 162         r600_context_pipe_state_set(rctx, rstate);
 163
 164         if (rctx->cb_misc_state.blend_colormask != blend->cb_target_mask) {
 165                 rctx->cb_misc_state.blend_colormask = blend->cb_target_mask;
 166                 update_cb = true;
 167         }
 168         if (rctx->chip_class <= R700 &&
 169             rctx->cb_misc_state.cb_color_control != blend->cb_color_control) {
 170                 rctx->cb_misc_state.cb_color_control = blend->cb_color_control;
 171                 update_cb = true;
 172         }
 173         if (rctx->cb_misc_state.dual_src_blend != blend->dual_src_blend) {
 174                 rctx->cb_misc_state.dual_src_blend = blend->dual_src_blend;
 175                 update_cb = true;
 176         }
 177         if (update_cb) {
 178                 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
 179         }
 180 }
 181
 182 void r600_set_blend_color(struct pipe_context *ctx,
 183                           const struct pipe_blend_color *state)
 184 {
 185         struct r600_context *rctx = (struct r600_context *)ctx;
 186         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 187
 188         if (rstate == NULL)
 189                 return;
 190
 191         rstate->id = R600_PIPE_STATE_BLEND_COLOR;
 192         r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]));
 193         r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]));
 194         r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]));
 195         r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]));
 196
 197         free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
 198         rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
 199         r600_context_pipe_state_set(rctx, rstate);
 200 }
 201
 202 static void r600_set_stencil_ref(struct pipe_context *ctx,
 203                                  const struct r600_stencil_ref *state)
 204 {
 205         struct r600_context *rctx = (struct r600_context *)ctx;
 206         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 207
 208         if (rstate == NULL)
 209                 return;
 210
 211         rstate->id = R600_PIPE_STATE_STENCIL_REF;
 212         r600_pipe_state_add_reg(rstate,
 213                                 R_028430_DB_STENCILREFMASK,
 214                                 S_028430_STENCILREF(state->ref_value[0]) |
 215                                 S_028430_STENCILMASK(state->valuemask[0]) |
 216                                 S_028430_STENCILWRITEMASK(state->writemask[0]));
 217         r600_pipe_state_add_reg(rstate,
 218                                 R_028434_DB_STENCILREFMASK_BF,
 219                                 S_028434_STENCILREF_BF(state->ref_value[1]) |
 220                                 S_028434_STENCILMASK_BF(state->valuemask[1]) |
 221                                 S_028434_STENCILWRITEMASK_BF(state->writemask[1]));
 222
 223         free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
 224         rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
 225         r600_context_pipe_state_set(rctx, rstate);
 226 }
 227
 228 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
 229                                const struct pipe_stencil_ref *state)
 230 {
 231         struct r600_context *rctx = (struct r600_context *)ctx;
 232         struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
 233         struct r600_stencil_ref ref;
 234
 235         rctx->stencil_ref = *state;
 236
 237         if (!dsa)
 238                 return;
 239
 240         ref.ref_value[0] = state->ref_value[0];
 241         ref.ref_value[1] = state->ref_value[1];
 242         ref.valuemask[0] = dsa->valuemask[0];
 243         ref.valuemask[1] = dsa->valuemask[1];
 244         ref.writemask[0] = dsa->writemask[0];
 245         ref.writemask[1] = dsa->writemask[1];
 246
 247         r600_set_stencil_ref(ctx, &ref);
 248 }
 249
 250 void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
 251 {
 252         struct r600_context *rctx = (struct r600_context *)ctx;
 253         struct r600_pipe_dsa *dsa = state;
 254         struct r600_pipe_state *rstate;
 255         struct r600_stencil_ref ref;
 256
 257         if (state == NULL)
 258                 return;
 259         rstate = &dsa->rstate;
 260         rctx->states[rstate->id] = rstate;
 261         rctx->sx_alpha_test_control &= ~0xff;
 262         rctx->sx_alpha_test_control |= dsa->sx_alpha_test_control;
 263         rctx->alpha_ref = dsa->alpha_ref;
 264         rctx->alpha_ref_dirty = true;
 265         r600_context_pipe_state_set(rctx, rstate);
 266
 267         ref.ref_value[0] = rctx->stencil_ref.ref_value[0];
 268         ref.ref_value[1] = rctx->stencil_ref.ref_value[1];
 269         ref.valuemask[0] = dsa->valuemask[0];
 270         ref.valuemask[1] = dsa->valuemask[1];
 271         ref.writemask[0] = dsa->writemask[0];
 272         ref.writemask[1] = dsa->writemask[1];
 273
 274         r600_set_stencil_ref(ctx, &ref);
 275 }
 276
 277 void r600_set_max_scissor(struct r600_context *rctx)
 278 {
 279         /* Set a scissor state such that it doesn't do anything. */
 280         struct pipe_scissor_state scissor;
 281         scissor.minx = 0;
 282         scissor.miny = 0;
 283         scissor.maxx = 8192;
 284         scissor.maxy = 8192;
 285
 286         r600_set_scissor_state(rctx, &scissor);
 287 }
 288
 289 void r600_bind_rs_state(struct pipe_context *ctx, void *state)
 290 {
 291         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
 292         struct r600_context *rctx = (struct r600_context *)ctx;
 293
 294         if (state == NULL)
 295                 return;
 296
 297         rctx->sprite_coord_enable = rs->sprite_coord_enable;
 298         rctx->two_side = rs->two_side;
 299         rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
 300         rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
 301
 302         rctx->rasterizer = rs;
 303
 304         rctx->states[rs->rstate.id] = &rs->rstate;
 305         r600_context_pipe_state_set(rctx, &rs->rstate);
 306
 307         if (rctx->chip_class >= EVERGREEN) {
 308                 evergreen_polygon_offset_update(rctx);
 309         } else {
 310                 r600_polygon_offset_update(rctx);
 311         }
 312
 313         /* Workaround for a missing scissor enable on r600. */
 314         if (rctx->chip_class == R600) {
 315                 if (rs->scissor_enable != rctx->scissor_enable) {
 316                         rctx->scissor_enable = rs->scissor_enable;
 317
 318                         if (rs->scissor_enable) {
 319                                 r600_set_scissor_state(rctx, &rctx->scissor_state);
 320                         } else {
 321                                 r600_set_max_scissor(rctx);
 322                         }
 323                 }
 324         }
 325 }
 326
 327 void r600_delete_rs_state(struct pipe_context *ctx, void *state)
 328 {
 329         struct r600_context *rctx = (struct r600_context *)ctx;
 330         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
 331
 332         if (rctx->rasterizer == rs) {
 333                 rctx->rasterizer = NULL;
 334         }
 335         if (rctx->states[rs->rstate.id] == &rs->rstate) {
 336                 rctx->states[rs->rstate.id] = NULL;
 337         }
 338         free(rs);
 339 }
 340
 341 void r600_sampler_view_destroy(struct pipe_context *ctx,
 342                                struct pipe_sampler_view *state)
 343 {
 344         struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
 345
 346         pipe_resource_reference(&state->texture, NULL);
 347         FREE(resource);
 348 }
 349
 350 void r600_delete_state(struct pipe_context *ctx, void *state)
 351 {
 352         struct r600_context *rctx = (struct r600_context *)ctx;
 353         struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
 354
 355         if (rctx->states[rstate->id] == rstate) {
 356                 rctx->states[rstate->id] = NULL;
 357         }
 358         for (int i = 0; i < rstate->nregs; i++) {
 359                 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL);
 360         }
 361         free(rstate);
 362 }
 363
 364 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
 365 {
 366         struct r600_context *rctx = (struct r600_context *)ctx;
 367         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 368
 369         rctx->vertex_elements = v;
 370         if (v) {
 371                 r600_inval_shader_cache(rctx);
 372
 373                 rctx->states[v->rstate.id] = &v->rstate;
 374                 r600_context_pipe_state_set(rctx, &v->rstate);
 375         }
 376 }
 377
 378 void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
 379 {
 380         struct r600_context *rctx = (struct r600_context *)ctx;
 381         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 382
 383         if (rctx->states[v->rstate.id] == &v->rstate) {
 384                 rctx->states[v->rstate.id] = NULL;
 385         }
 386         if (rctx->vertex_elements == state)
 387                 rctx->vertex_elements = NULL;
 388
 389         pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL);
 390         FREE(state);
 391 }
 392
 393 void r600_set_index_buffer(struct pipe_context *ctx,
 394                            const struct pipe_index_buffer *ib)
 395 {
 396         struct r600_context *rctx = (struct r600_context *)ctx;
 397
 398         if (ib) {
 399                 pipe_resource_reference(&rctx->index_buffer.buffer, ib->buffer);
 400                 memcpy(&rctx->index_buffer, ib, sizeof(*ib));
 401         } else {
 402                 pipe_resource_reference(&rctx->index_buffer.buffer, NULL);
 403         }
 404 }
 405
 406 void r600_vertex_buffers_dirty(struct r600_context *rctx)
 407 {
 408         if (rctx->vertex_buffer_state.dirty_mask) {
 409                 r600_inval_vertex_cache(rctx);
 410                 rctx->vertex_buffer_state.atom.num_dw = (rctx->chip_class >= EVERGREEN ? 12 : 11) *
 411                                                util_bitcount(rctx->vertex_buffer_state.dirty_mask);
 412                 r600_atom_dirty(rctx, &rctx->vertex_buffer_state.atom);
 413         }
 414 }
 415
 416 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 417                              const struct pipe_vertex_buffer *input)
 418 {
 419         struct r600_context *rctx = (struct r600_context *)ctx;
 420         struct r600_vertexbuf_state *state = &rctx->vertex_buffer_state;
 421         struct pipe_vertex_buffer *vb = state->vb;
 422         unsigned i;
 423         /* This sets 1-bit for buffers with index >= count. */
 424         uint32_t disable_mask = ~((1ull << count) - 1);
 425         /* These are the new buffers set by this function. */
 426         uint32_t new_buffer_mask = 0;
 427
 428         /* Set buffers with index >= count to NULL. */
 429         uint32_t remaining_buffers_mask =
 430                 rctx->vertex_buffer_state.enabled_mask & disable_mask;
 431
 432         while (remaining_buffers_mask) {
 433                 i = u_bit_scan(&remaining_buffers_mask);
 434                 pipe_resource_reference(&vb[i].buffer, NULL);
 435         }
 436
 437         /* Set vertex buffers. */
 438         for (i = 0; i < count; i++) {
 439                 if (memcmp(&input[i], &vb[i], sizeof(struct pipe_vertex_buffer))) {
 440                         if (input[i].buffer) {
 441                                 vb[i].stride = input[i].stride;
 442                                 vb[i].buffer_offset = input[i].buffer_offset;
 443                                 pipe_resource_reference(&vb[i].buffer, input[i].buffer);
 444                                 new_buffer_mask |= 1 << i;
 445                         } else {
 446                                 pipe_resource_reference(&vb[i].buffer, NULL);
 447                                 disable_mask |= 1 << i;
 448                         }
 449                 }
 450         }
 451
 452         rctx->vertex_buffer_state.enabled_mask &= ~disable_mask;
 453         rctx->vertex_buffer_state.dirty_mask &= rctx->vertex_buffer_state.enabled_mask;
 454         rctx->vertex_buffer_state.enabled_mask |= new_buffer_mask;
 455         rctx->vertex_buffer_state.dirty_mask |= new_buffer_mask;
 456
 457         r600_vertex_buffers_dirty(rctx);
 458 }
 459
 460 void r600_sampler_views_dirty(struct r600_context *rctx,
 461                               struct r600_samplerview_state *state)
 462 {
 463         if (state->dirty_mask) {
 464                 r600_inval_texture_cache(rctx);
 465                 state->atom.num_dw = (rctx->chip_class >= EVERGREEN ? 14 : 13) *
 466                                      util_bitcount(state->dirty_mask);
 467                 r600_atom_dirty(rctx, &state->atom);
 468         }
 469 }
 470
 471 void r600_set_sampler_views(struct r600_context *rctx,
 472                             struct r600_textures_info *dst,
 473                             unsigned count,
 474                             struct pipe_sampler_view **views)
 475 {
 476         struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
 477         unsigned i;
 478         /* This sets 1-bit for textures with index >= count. */
 479         uint32_t disable_mask = ~((1ull << count) - 1);
 480         /* These are the new textures set by this function. */
 481         uint32_t new_mask = 0;
 482
 483         /* Set textures with index >= count to NULL. */
 484         uint32_t remaining_mask = dst->views.enabled_mask & disable_mask;
 485
 486         while (remaining_mask) {
 487                 i = u_bit_scan(&remaining_mask);
 488                 assert(dst->views.views[i]);
 489
 490                 pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
 491         }
 492
 493         for (i = 0; i < count; i++) {
 494                 if (rviews[i] == dst->views.views[i]) {
 495                         continue;
 496                 }
 497
 498                 if (rviews[i]) {
 499                         struct r600_resource_texture *rtex =
 500                                 (struct r600_resource_texture*)rviews[i]->base.texture;
 501
 502                         if (rtex->is_depth && !rtex->is_flushing_texture) {
 503                                 dst->views.depth_texture_mask |= 1 << i;
 504                         } else {
 505                                 dst->views.depth_texture_mask &= ~(1 << i);
 506                         }
 507
 508                         /* Changing from array to non-arrays textures and vice
 509                          * versa requires updating TEX_ARRAY_OVERRIDE on R6xx-R7xx. */
 510                         if (rctx->chip_class <= R700 &&
 511                             (rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
 512                              rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i]) {
 513                                 dst->samplers_dirty = true;
 514                         }
 515
 516                         pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], views[i]);
 517                         new_mask |= 1 << i;
 518                 } else {
 519                         pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views.views[i], NULL);
 520                         disable_mask |= 1 << i;
 521                 }
 522         }
 523
 524         dst->views.enabled_mask &= ~disable_mask;
 525         dst->views.dirty_mask &= dst->views.enabled_mask;
 526         dst->views.enabled_mask |= new_mask;
 527         dst->views.dirty_mask |= new_mask;
 528         dst->views.depth_texture_mask &= dst->views.enabled_mask;
 529
 530         r600_sampler_views_dirty(rctx, &dst->views);
 531 }
 532
 533 void *r600_create_vertex_elements(struct pipe_context *ctx,
 534                                   unsigned count,
 535                                   const struct pipe_vertex_element *elements)
 536 {
 537         struct r600_context *rctx = (struct r600_context *)ctx;
 538         struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
 539
 540         assert(count < 32);
 541         if (!v)
 542                 return NULL;
 543
 544         v->count = count;
 545         memcpy(v->elements, elements, sizeof(struct pipe_vertex_element) * count);
 546
 547         if (r600_vertex_elements_build_fetch_shader(rctx, v)) {
 548                 FREE(v);
 549                 return NULL;
 550         }
 551
 552         return v;
 553 }
 554
 555 /* Compute the key for the hw shader variant */
 556 static INLINE unsigned r600_shader_selector_key(struct pipe_context * ctx,
 557                 struct r600_pipe_shader_selector * sel)
 558 {
 559         struct r600_context *rctx = (struct r600_context *)ctx;
 560         unsigned key;
 561
 562         if (sel->type == PIPE_SHADER_FRAGMENT) {
 563                 key = rctx->two_side |
 564                                 MIN2(sel->nr_ps_max_color_exports, rctx->nr_cbufs + rctx->dual_src_blend) << 1;
 565         } else
 566                 key = 0;
 567
 568         return key;
 569 }
 570
 571 /* Select the hw shader variant depending on the current state.
 572  * (*dirty) is set to 1 if current variant was changed */
 573 static int r600_shader_select(struct pipe_context *ctx,
 574         struct r600_pipe_shader_selector* sel,
 575         unsigned *dirty)
 576 {
 577         unsigned key;
 578         struct r600_context *rctx = (struct r600_context *)ctx;
 579         struct r600_pipe_shader * shader = NULL;
 580         int r;
 581
 582         key = r600_shader_selector_key(ctx, sel);
 583
 584         /* Check if we don't need to change anything.
 585          * This path is also used for most shaders that don't need multiple
 586          * variants, it will cost just a computation of the key and this
 587          * test. */
 588         if (likely(sel->current && sel->current->key == key)) {
 589                 return 0;
 590         }
 591
 592         /* lookup if we have other variants in the list */
 593         if (sel->num_shaders > 1) {
 594                 struct r600_pipe_shader *p = sel->current, *c = p->next_variant;
 595
 596                 while (c && c->key != key) {
 597                         p = c;
 598                         c = c->next_variant;
 599                 }
 600
 601                 if (c) {
 602                         p->next_variant = c->next_variant;
 603                         shader = c;
 604                 }
 605         }
 606
 607         if (unlikely(!shader)) {
 608                 shader = CALLOC(1, sizeof(struct r600_pipe_shader));
 609                 shader->selector = sel;
 610
 611                 r = r600_pipe_shader_create(ctx, shader);
 612                 if (unlikely(r)) {
 613                         R600_ERR("Failed to build shader variant (type=%u, key=%u) %d\n",
 614                                         sel->type, key, r);
 615                         sel->current = NULL;
 616                         return r;
 617                 }
 618
 619                 /* We don't know the value of nr_ps_max_color_exports until we built
 620                  * at least one variant, so we may need to recompute the key after
 621                  * building first variant. */
 622                 if (sel->type == PIPE_SHADER_FRAGMENT &&
 623                                 sel->num_shaders == 0) {
 624                         sel->nr_ps_max_color_exports = shader->shader.nr_ps_max_color_exports;
 625                         key = r600_shader_selector_key(ctx, sel);
 626                 }
 627
 628                 shader->key = key;
 629                 sel->num_shaders++;
 630         }
 631
 632         if (dirty)
 633                 *dirty = 1;
 634
 635         shader->next_variant = sel->current;
 636         sel->current = shader;
 637
 638         if (rctx->chip_class < EVERGREEN && rctx->ps_shader && rctx->vs_shader) {
 639                 r600_adjust_gprs(rctx);
 640         }
 641
 642         if (rctx->ps_shader &&
 643             rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
 644                 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
 645                 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
 646         }
 647         return 0;
 648 }
 649
 650 static void *r600_create_shader_state(struct pipe_context *ctx,
 651                                const struct pipe_shader_state *state,
 652                                unsigned pipe_shader_type)
 653 {
 654         struct r600_pipe_shader_selector *sel = CALLOC_STRUCT(r600_pipe_shader_selector);
 655         int r;
 656
 657         sel->type = pipe_shader_type;
 658         sel->tokens = tgsi_dup_tokens(state->tokens);
 659         sel->so = state->stream_output;
 660
 661         r = r600_shader_select(ctx, sel, NULL);
 662         if (r)
 663             return NULL;
 664
 665         return sel;
 666 }
 667
 668 void *r600_create_shader_state_ps(struct pipe_context *ctx,
 669                 const struct pipe_shader_state *state)
 670 {
 671         return r600_create_shader_state(ctx, state, PIPE_SHADER_FRAGMENT);
 672 }
 673
 674 void *r600_create_shader_state_vs(struct pipe_context *ctx,
 675                 const struct pipe_shader_state *state)
 676 {
 677         return r600_create_shader_state(ctx, state, PIPE_SHADER_VERTEX);
 678 }
 679
 680 void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
 681 {
 682         struct r600_context *rctx = (struct r600_context *)ctx;
 683
 684         if (!state)
 685                 state = rctx->dummy_pixel_shader;
 686
 687         rctx->ps_shader = (struct r600_pipe_shader_selector *)state;
 688         r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
 689
 690         if (rctx->chip_class <= R700) {
 691                 bool multiwrite = rctx->ps_shader->current->shader.fs_write_all;
 692
 693                 if (rctx->cb_misc_state.multiwrite != multiwrite) {
 694                         rctx->cb_misc_state.multiwrite = multiwrite;
 695                         r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
 696                 }
 697
 698                 if (rctx->vs_shader)
 699                         r600_adjust_gprs(rctx);
 700         }
 701
 702         if (rctx->cb_misc_state.nr_ps_color_outputs != rctx->ps_shader->current->nr_ps_color_outputs) {
 703                 rctx->cb_misc_state.nr_ps_color_outputs = rctx->ps_shader->current->nr_ps_color_outputs;
 704                 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
 705         }
 706 }
 707
 708 void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
 709 {
 710         struct r600_context *rctx = (struct r600_context *)ctx;
 711
 712         rctx->vs_shader = (struct r600_pipe_shader_selector *)state;
 713         if (state) {
 714                 r600_context_pipe_state_set(rctx, &rctx->vs_shader->current->rstate);
 715
 716                 if (rctx->chip_class < EVERGREEN && rctx->ps_shader)
 717                         r600_adjust_gprs(rctx);
 718         }
 719 }
 720
 721 static void r600_delete_shader_selector(struct pipe_context *ctx,
 722                 struct r600_pipe_shader_selector *sel)
 723 {
 724         struct r600_pipe_shader *p = sel->current, *c;
 725         while (p) {
 726                 c = p->next_variant;
 727                 r600_pipe_shader_destroy(ctx, p);
 728                 free(p);
 729                 p = c;
 730         }
 731
 732         free(sel->tokens);
 733         free(sel);
 734 }
 735
 736
 737 void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
 738 {
 739         struct r600_context *rctx = (struct r600_context *)ctx;
 740         struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
 741
 742         if (rctx->ps_shader == sel) {
 743                 rctx->ps_shader = NULL;
 744         }
 745
 746         r600_delete_shader_selector(ctx, sel);
 747 }
 748
 749 void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
 750 {
 751         struct r600_context *rctx = (struct r600_context *)ctx;
 752         struct r600_pipe_shader_selector *sel = (struct r600_pipe_shader_selector *)state;
 753
 754         if (rctx->vs_shader == sel) {
 755                 rctx->vs_shader = NULL;
 756         }
 757
 758         r600_delete_shader_selector(ctx, sel);
 759 }
 760
 761 static void r600_update_alpha_ref(struct r600_context *rctx)
 762 {
 763         unsigned alpha_ref;
 764         struct r600_pipe_state rstate;
 765
 766         alpha_ref = rctx->alpha_ref;
 767         rstate.nregs = 0;
 768         if (rctx->export_16bpc && rctx->chip_class >= EVERGREEN) {
 769                 alpha_ref &= ~0x1FFF;
 770         }
 771         r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref);
 772
 773         r600_context_pipe_state_set(rctx, &rstate);
 774         rctx->alpha_ref_dirty = false;
 775 }
 776
 777 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state)
 778 {
 779         if (state->dirty_mask) {
 780                 r600_inval_shader_cache(rctx);
 781                 state->atom.num_dw = rctx->chip_class >= EVERGREEN ? util_bitcount(state->dirty_mask)*20
 782                                                                    : util_bitcount(state->dirty_mask)*19;
 783                 r600_atom_dirty(rctx, &state->atom);
 784         }
 785 }
 786
 787 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 788                               struct pipe_constant_buffer *input)
 789 {
 790         struct r600_context *rctx = (struct r600_context *)ctx;
 791         struct r600_constbuf_state *state;
 792         struct pipe_constant_buffer *cb;
 793         const uint8_t *ptr;
 794
 795         switch (shader) {
 796         case PIPE_SHADER_VERTEX:
 797                 state = &rctx->vs_constbuf_state;
 798                 break;
 799         case PIPE_SHADER_FRAGMENT:
 800                 state = &rctx->ps_constbuf_state;
 801                 break;
 802         default:
 803                 return;
 804         }
 805
 806         /* Note that the state tracker can unbind constant buffers by
 807          * passing NULL here.
 808          */
 809         if (unlikely(!input)) {
 810                 state->enabled_mask &= ~(1 << index);
 811                 state->dirty_mask &= ~(1 << index);
 812                 pipe_resource_reference(&state->cb[index].buffer, NULL);
 813                 return;
 814         }
 815
 816         cb = &state->cb[index];
 817         cb->buffer_size = input->buffer_size;
 818
 819         ptr = input->user_buffer;
 820
 821         if (ptr) {
 822                 /* Upload the user buffer. */
 823                 if (R600_BIG_ENDIAN) {
 824                         uint32_t *tmpPtr;
 825                         unsigned i, size = input->buffer_size;
 826
 827                         if (!(tmpPtr = malloc(size))) {
 828                                 R600_ERR("Failed to allocate BE swap buffer.\n");
 829                                 return;
 830                         }
 831
 832                         for (i = 0; i < size / 4; ++i) {
 833                                 tmpPtr[i] = bswap_32(((uint32_t *)ptr)[i]);
 834                         }
 835
 836                         u_upload_data(rctx->uploader, 0, size, tmpPtr, &cb->buffer_offset, &cb->buffer);
 837                         free(tmpPtr);
 838                 } else {
 839                         u_upload_data(rctx->uploader, 0, input->buffer_size, ptr, &cb->buffer_offset, &cb->buffer);
 840                 }
 841         } else {
 842                 /* Setup the hw buffer. */
 843                 cb->buffer_offset = input->buffer_offset;
 844                 pipe_resource_reference(&cb->buffer, input->buffer);
 845         }
 846
 847         state->enabled_mask |= 1 << index;
 848         state->dirty_mask |= 1 << index;
 849         r600_constant_buffers_dirty(rctx, state);
 850 }
 851
 852 struct pipe_stream_output_target *
 853 r600_create_so_target(struct pipe_context *ctx,
 854                       struct pipe_resource *buffer,
 855                       unsigned buffer_offset,
 856                       unsigned buffer_size)
 857 {
 858         struct r600_context *rctx = (struct r600_context *)ctx;
 859         struct r600_so_target *t;
 860         void *ptr;
 861
 862         t = CALLOC_STRUCT(r600_so_target);
 863         if (!t) {
 864                 return NULL;
 865         }
 866
 867         t->b.reference.count = 1;
 868         t->b.context = ctx;
 869         pipe_resource_reference(&t->b.buffer, buffer);
 870         t->b.buffer_offset = buffer_offset;
 871         t->b.buffer_size = buffer_size;
 872
 873         t->filled_size = (struct r600_resource*)
 874                 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
 875         ptr = rctx->ws->buffer_map(t->filled_size->cs_buf, rctx->cs, PIPE_TRANSFER_WRITE);
 876         memset(ptr, 0, t->filled_size->buf->size);
 877         rctx->ws->buffer_unmap(t->filled_size->cs_buf);
 878
 879         return &t->b;
 880 }
 881
 882 void r600_so_target_destroy(struct pipe_context *ctx,
 883                             struct pipe_stream_output_target *target)
 884 {
 885         struct r600_so_target *t = (struct r600_so_target*)target;
 886         pipe_resource_reference(&t->b.buffer, NULL);
 887         pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL);
 888         FREE(t);
 889 }
 890
 891 void r600_set_so_targets(struct pipe_context *ctx,
 892                          unsigned num_targets,
 893                          struct pipe_stream_output_target **targets,
 894                          unsigned append_bitmask)
 895 {
 896         struct r600_context *rctx = (struct r600_context *)ctx;
 897         unsigned i;
 898
 899         /* Stop streamout. */
 900         if (rctx->num_so_targets && !rctx->streamout_start) {
 901                 r600_context_streamout_end(rctx);
 902         }
 903
 904         /* Set the new targets. */
 905         for (i = 0; i < num_targets; i++) {
 906                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
 907         }
 908         for (; i < rctx->num_so_targets; i++) {
 909                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
 910         }
 911
 912         rctx->num_so_targets = num_targets;
 913         rctx->streamout_start = num_targets != 0;
 914         rctx->streamout_append_bitmask = append_bitmask;
 915 }
 916
 917 static void r600_update_derived_state(struct r600_context *rctx)
 918 {
 919         struct pipe_context * ctx = (struct pipe_context*)rctx;
 920         unsigned ps_dirty = 0;
 921
 922         if (!rctx->blitter->running) {
 923                 /* Flush depth textures which need to be flushed. */
 924                 if (rctx->vs_samplers.views.depth_texture_mask) {
 925                         r600_flush_depth_textures(rctx, &rctx->vs_samplers.views);
 926                 }
 927                 if (rctx->ps_samplers.views.depth_texture_mask) {
 928                         r600_flush_depth_textures(rctx, &rctx->ps_samplers.views);
 929                 }
 930         }
 931
 932         if (rctx->chip_class < EVERGREEN) {
 933                 r600_update_sampler_states(rctx);
 934         }
 935
 936         r600_shader_select(ctx, rctx->ps_shader, &ps_dirty);
 937
 938         if (rctx->alpha_ref_dirty) {
 939                 r600_update_alpha_ref(rctx);
 940         }
 941
 942         if (rctx->ps_shader && ((rctx->sprite_coord_enable &&
 943                 (rctx->ps_shader->current->sprite_coord_enable != rctx->sprite_coord_enable)) ||
 944                 (rctx->rasterizer && rctx->rasterizer->flatshade != rctx->ps_shader->current->flatshade))) {
 945
 946                 if (rctx->chip_class >= EVERGREEN)
 947                         evergreen_pipe_shader_ps(ctx, rctx->ps_shader->current);
 948                 else
 949                         r600_pipe_shader_ps(ctx, rctx->ps_shader->current);
 950
 951                 ps_dirty = 1;
 952         }
 953
 954         if (ps_dirty)
 955                 r600_context_pipe_state_set(rctx, &rctx->ps_shader->current->rstate);
 956
 957         if (rctx->chip_class >= EVERGREEN) {
 958                 evergreen_update_dual_export_state(rctx);
 959         } else {
 960                 r600_update_dual_export_state(rctx);
 961         }
 962 }
 963
 964 static unsigned r600_conv_prim_to_gs_out(unsigned mode)
 965 {
 966         static const int prim_conv[] = {
 967                 V_028A6C_OUTPRIM_TYPE_POINTLIST,
 968                 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
 969                 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
 970                 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
 971                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
 972                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
 973                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
 974                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
 975                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
 976                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
 977                 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
 978                 V_028A6C_OUTPRIM_TYPE_LINESTRIP,
 979                 V_028A6C_OUTPRIM_TYPE_TRISTRIP,
 980                 V_028A6C_OUTPRIM_TYPE_TRISTRIP
 981         };
 982         assert(mode < Elements(prim_conv));
 983
 984         return prim_conv[mode];
 985 }
 986
 987 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
 988 {
 989         struct r600_context *rctx = (struct r600_context *)ctx;
 990         struct pipe_draw_info info = *dinfo;
 991         struct pipe_index_buffer ib = {};
 992         unsigned prim, ls_mask = 0;
 993         struct r600_block *dirty_block = NULL, *next_block = NULL;
 994         struct r600_atom *state = NULL, *next_state = NULL;
 995         struct radeon_winsys_cs *cs = rctx->cs;
 996         uint64_t va;
 997         uint8_t *ptr;
 998
 999         if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
1000             !r600_conv_pipe_prim(info.mode, &prim)) {
1001                 assert(0);
1002                 return;
1003         }
1004
1005         if (!rctx->vs_shader) {
1006                 assert(0);
1007                 return;
1008         }
1009
1010         r600_update_derived_state(rctx);
1011
1012         if (info.indexed) {
1013                 /* Initialize the index buffer struct. */
1014                 pipe_resource_reference(&ib.buffer, rctx->index_buffer.buffer);
1015                 ib.user_buffer = rctx->index_buffer.user_buffer;
1016                 ib.index_size = rctx->index_buffer.index_size;
1017                 ib.offset = rctx->index_buffer.offset + info.start * ib.index_size;
1018
1019                 /* Translate or upload, if needed. */
1020                 r600_translate_index_buffer(rctx, &ib, info.count);
1021
1022                 ptr = (uint8_t*)ib.user_buffer;
1023                 if (!ib.buffer && ptr) {
1024                         u_upload_data(rctx->uploader, 0, info.count * ib.index_size,
1025                                       ptr, &ib.offset, &ib.buffer);
1026                 }
1027         } else {
1028                 info.index_bias = info.start;
1029                 if (info.count_from_stream_output) {
1030                         r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info.count_from_stream_output);
1031                 }
1032         }
1033
1034         if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
1035                 rctx->vgt.id = R600_PIPE_STATE_VGT;
1036                 rctx->vgt.nregs = 0;
1037                 r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim);
1038                 r600_pipe_state_add_reg(&rctx->vgt, R_028A6C_VGT_GS_OUT_PRIM_TYPE, 0);
1039                 r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias);
1040                 r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index);
1041                 r600_pipe_state_add_reg(&rctx->vgt, R_028410_SX_ALPHA_TEST_CONTROL, 0);
1042                 r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart);
1043                 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance);
1044                 r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0);
1045                 r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0);
1046                 r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0);
1047         }
1048
1049         rctx->vgt.nregs = 0;
1050         r600_pipe_state_mod_reg(&rctx->vgt, prim);
1051         r600_pipe_state_mod_reg(&rctx->vgt, r600_conv_prim_to_gs_out(info.mode));
1052         r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
1053         r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
1054         r600_pipe_state_mod_reg(&rctx->vgt, rctx->sx_alpha_test_control);
1055         r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
1056         r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
1057
1058         if (prim == V_008958_DI_PT_LINELIST)
1059                 ls_mask = 1;
1060         else if (prim == V_008958_DI_PT_LINESTRIP)
1061                 ls_mask = 2;
1062         r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple);
1063         r600_pipe_state_mod_reg(&rctx->vgt,
1064                                 rctx->vs_shader->current->pa_cl_vs_out_cntl |
1065                                 (rctx->rasterizer->clip_plane_enable & rctx->vs_shader->current->shader.clip_dist_write));
1066         r600_pipe_state_mod_reg(&rctx->vgt,
1067                                 rctx->pa_cl_clip_cntl |
1068                                 (rctx->vs_shader->current->shader.clip_dist_write ||
1069                                  rctx->vs_shader->current->shader.vs_prohibit_ucps ?
1070                                  0 : rctx->rasterizer->clip_plane_enable & 0x3F));
1071
1072         r600_context_pipe_state_set(rctx, &rctx->vgt);
1073
1074         /* Emit states (the function expects that we emit at most 17 dwords here). */
1075         r600_need_cs_space(rctx, 0, TRUE);
1076
1077         LIST_FOR_EACH_ENTRY_SAFE(state, next_state, &rctx->dirty_states, head) {
1078                 r600_emit_atom(rctx, state);
1079         }
1080         LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
1081                 r600_context_block_emit_dirty(rctx, dirty_block, 0 /* pkt_flags */);
1082         }
1083         rctx->pm4_dirty_cdwords = 0;
1084
1085         /* Enable stream out if needed. */
1086         if (rctx->streamout_start) {
1087                 r600_context_streamout_begin(rctx);
1088                 rctx->streamout_start = FALSE;
1089         }
1090
1091         /* draw packet */
1092         cs->buf[cs->cdw++] = PKT3(PKT3_INDEX_TYPE, 0, rctx->predicate_drawing);
1093         cs->buf[cs->cdw++] = ib.index_size == 4 ?
1094                                 (VGT_INDEX_32 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0)) :
1095                                 (VGT_INDEX_16 | (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0));
1096         cs->buf[cs->cdw++] = PKT3(PKT3_NUM_INSTANCES, 0, rctx->predicate_drawing);
1097         cs->buf[cs->cdw++] = info.instance_count;
1098         if (info.indexed) {
1099                 va = r600_resource_va(ctx->screen, ib.buffer);
1100                 va += ib.offset;
1101                 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX, 3, rctx->predicate_drawing);
1102                 cs->buf[cs->cdw++] = va;
1103                 cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF;
1104                 cs->buf[cs->cdw++] = info.count;
1105                 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_DMA;
1106                 cs->buf[cs->cdw++] = PKT3(PKT3_NOP, 0, rctx->predicate_drawing);
1107                 cs->buf[cs->cdw++] = r600_context_bo_reloc(rctx, (struct r600_resource*)ib.buffer, RADEON_USAGE_READ);
1108         } else {
1109                 cs->buf[cs->cdw++] = PKT3(PKT3_DRAW_INDEX_AUTO, 1, rctx->predicate_drawing);
1110                 cs->buf[cs->cdw++] = info.count;
1111                 cs->buf[cs->cdw++] = V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1112                                         (info.count_from_stream_output ? S_0287F0_USE_OPAQUE(1) : 0);
1113         }
1114
1115         rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING;
1116
1117         /* Set the depth buffer as dirty. */
1118         if (rctx->framebuffer.zsbuf) {
1119                 struct pipe_surface *surf = rctx->framebuffer.zsbuf;
1120                 struct r600_resource_texture *rtex = (struct r600_resource_texture *)surf->texture;
1121
1122                 rtex->dirty_db_mask |= 1 << surf->u.tex.level;
1123         }
1124
1125         pipe_resource_reference(&ib.buffer, NULL);
1126 }
1127
1128 void _r600_pipe_state_add_reg_bo(struct r600_context *ctx,
1129                                  struct r600_pipe_state *state,
1130                                  uint32_t offset, uint32_t value,
1131                                  uint32_t range_id, uint32_t block_id,
1132                                  struct r600_resource *bo,
1133                                  enum radeon_bo_usage usage)
1134
1135 {
1136         struct r600_range *range;
1137         struct r600_block *block;
1138
1139         if (bo) assert(usage);
1140
1141         range = &ctx->range[range_id];
1142         block = range->blocks[block_id];
1143         state->regs[state->nregs].block = block;
1144         state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
1145
1146         state->regs[state->nregs].value = value;
1147         state->regs[state->nregs].bo = bo;
1148         state->regs[state->nregs].bo_usage = usage;
1149
1150         state->nregs++;
1151         assert(state->nregs < R600_BLOCK_MAX_REG);
1152 }
1153
1154 void _r600_pipe_state_add_reg(struct r600_context *ctx,
1155                               struct r600_pipe_state *state,
1156                               uint32_t offset, uint32_t value,
1157                               uint32_t range_id, uint32_t block_id)
1158 {
1159         _r600_pipe_state_add_reg_bo(ctx, state, offset, value,
1160                                     range_id, block_id, NULL, 0);
1161 }
1162
1163 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
1164                                      uint32_t offset, uint32_t value,
1165                                      struct r600_resource *bo,
1166                                      enum radeon_bo_usage usage)
1167 {
1168         if (bo) assert(usage);
1169
1170         state->regs[state->nregs].id = offset;
1171         state->regs[state->nregs].block = NULL;
1172         state->regs[state->nregs].value = value;
1173         state->regs[state->nregs].bo = bo;
1174         state->regs[state->nregs].bo_usage = usage;
1175
1176         state->nregs++;
1177         assert(state->nregs < R600_BLOCK_MAX_REG);
1178 }
1179
1180 uint32_t r600_translate_stencil_op(int s_op)
1181 {
1182         switch (s_op) {
1183         case PIPE_STENCIL_OP_KEEP:
1184                 return V_028800_STENCIL_KEEP;
1185         case PIPE_STENCIL_OP_ZERO:
1186                 return V_028800_STENCIL_ZERO;
1187         case PIPE_STENCIL_OP_REPLACE:
1188                 return V_028800_STENCIL_REPLACE;
1189         case PIPE_STENCIL_OP_INCR:
1190                 return V_028800_STENCIL_INCR;
1191         case PIPE_STENCIL_OP_DECR:
1192                 return V_028800_STENCIL_DECR;
1193         case PIPE_STENCIL_OP_INCR_WRAP:
1194                 return V_028800_STENCIL_INCR_WRAP;
1195         case PIPE_STENCIL_OP_DECR_WRAP:
1196                 return V_028800_STENCIL_DECR_WRAP;
1197         case PIPE_STENCIL_OP_INVERT:
1198                 return V_028800_STENCIL_INVERT;
1199         default:
1200                 R600_ERR("Unknown stencil op %d", s_op);
1201                 assert(0);
1202                 break;
1203         }
1204         return 0;
1205 }
1206
1207 uint32_t r600_translate_fill(uint32_t func)
1208 {
1209         switch(func) {
1210         case PIPE_POLYGON_MODE_FILL:
1211                 return 2;
1212         case PIPE_POLYGON_MODE_LINE:
1213                 return 1;
1214         case PIPE_POLYGON_MODE_POINT:
1215                 return 0;
1216         default:
1217                 assert(0);
1218                 return 0;
1219         }
1220 }
1221
1222 unsigned r600_tex_wrap(unsigned wrap)
1223 {
1224         switch (wrap) {
1225         default:
1226         case PIPE_TEX_WRAP_REPEAT:
1227                 return V_03C000_SQ_TEX_WRAP;
1228         case PIPE_TEX_WRAP_CLAMP:
1229                 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
1230         case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
1231                 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
1232         case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
1233                 return V_03C000_SQ_TEX_CLAMP_BORDER;
1234         case PIPE_TEX_WRAP_MIRROR_REPEAT:
1235                 return V_03C000_SQ_TEX_MIRROR;
1236         case PIPE_TEX_WRAP_MIRROR_CLAMP:
1237                 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
1238         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
1239                 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1240         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1241                 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1242         }
1243 }
1244
1245 unsigned r600_tex_filter(unsigned filter)
1246 {
1247         switch (filter) {
1248         default:
1249         case PIPE_TEX_FILTER_NEAREST:
1250                 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1251         case PIPE_TEX_FILTER_LINEAR:
1252                 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1253         }
1254 }
1255
1256 unsigned r600_tex_mipfilter(unsigned filter)
1257 {
1258         switch (filter) {
1259         case PIPE_TEX_MIPFILTER_NEAREST:
1260                 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1261         case PIPE_TEX_MIPFILTER_LINEAR:
1262                 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1263         default:
1264         case PIPE_TEX_MIPFILTER_NONE:
1265                 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1266         }
1267 }
1268
1269 unsigned r600_tex_compare(unsigned compare)
1270 {
1271         switch (compare) {
1272         default:
1273         case PIPE_FUNC_NEVER:
1274                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1275         case PIPE_FUNC_LESS:
1276                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1277         case PIPE_FUNC_EQUAL:
1278                 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1279         case PIPE_FUNC_LEQUAL:
1280                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1281         case PIPE_FUNC_GREATER:
1282                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1283         case PIPE_FUNC_NOTEQUAL:
1284                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1285         case PIPE_FUNC_GEQUAL:
1286                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1287         case PIPE_FUNC_ALWAYS:
1288                 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1289         }
1290 }