src/gallium/drivers/r600/r600_state_common.c

   1 /*
   2  * Copyright 2010 Red Hat Inc.
   3  *           2010 Jerome Glisse
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * on the rights to use, copy, modify, merge, publish, distribute, sub
   9  * license, and/or sell copies of the Software, and to permit persons to whom
  10  * the Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  20  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  21  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  22  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie <airlied@redhat.com>
  25  *          Jerome Glisse <jglisse@redhat.com>
  26  */
  27 #include "util/u_blitter.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_format.h"
  30 #include "pipebuffer/pb_buffer.h"
  31 #include "pipe/p_shader_tokens.h"
  32 #include "tgsi/tgsi_parse.h"
  33 #include "r600_formats.h"
  34 #include "r600_pipe.h"
  35 #include "r600d.h"
  36
  37 static void r600_emit_surface_sync(struct r600_context *rctx, struct r600_atom *atom)
  38 {
  39         struct radeon_winsys_cs *cs = rctx->cs;
  40         struct r600_atom_surface_sync *a = (struct r600_atom_surface_sync*)atom;
  41
  42         cs->buf[cs->cdw++] = PKT3(PKT3_SURFACE_SYNC, 3, 0);
  43         cs->buf[cs->cdw++] = a->flush_flags;  /* CP_COHER_CNTL */
  44         cs->buf[cs->cdw++] = 0xffffffff;      /* CP_COHER_SIZE */
  45         cs->buf[cs->cdw++] = 0;               /* CP_COHER_BASE */
  46         cs->buf[cs->cdw++] = 0x0000000A;      /* POLL_INTERVAL */
  47
  48         a->flush_flags = 0;
  49 }
  50
  51 static void r600_emit_r6xx_flush_and_inv(struct r600_context *rctx, struct r600_atom *atom)
  52 {
  53         struct radeon_winsys_cs *cs = rctx->cs;
  54         cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
  55         cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
  56 }
  57
  58 static void r600_init_atom(struct r600_atom *atom,
  59                            void (*emit)(struct r600_context *ctx, struct r600_atom *state),
  60                            unsigned num_dw,
  61                            enum r600_atom_flags flags)
  62 {
  63         atom->emit = emit;
  64         atom->num_dw = num_dw;
  65         atom->flags = flags;
  66 }
  67
  68 void r600_init_common_atoms(struct r600_context *rctx)
  69 {
  70         r600_init_atom(&rctx->atom_surface_sync.atom,   r600_emit_surface_sync,         5, EMIT_EARLY);
  71         r600_init_atom(&rctx->atom_r6xx_flush_and_inv,  r600_emit_r6xx_flush_and_inv,   2, EMIT_EARLY);
  72 }
  73
  74 unsigned r600_get_cb_flush_flags(struct r600_context *rctx)
  75 {
  76         unsigned flags = 0;
  77
  78         if (rctx->framebuffer.nr_cbufs) {
  79                 flags |= S_0085F0_CB_ACTION_ENA(1) |
  80                          (((1 << rctx->framebuffer.nr_cbufs) - 1) << S_0085F0_CB0_DEST_BASE_ENA_SHIFT);
  81         }
  82
  83         /* Workaround for broken flushing on some R6xx chipsets. */
  84         if (rctx->family == CHIP_RV670 ||
  85             rctx->family == CHIP_RS780 ||
  86             rctx->family == CHIP_RS880) {
  87                 flags |=  S_0085F0_CB1_DEST_BASE_ENA(1) |
  88                           S_0085F0_DEST_BASE_0_ENA(1);
  89         }
  90         return flags;
  91 }
  92
  93 void r600_texture_barrier(struct pipe_context *ctx)
  94 {
  95         struct r600_context *rctx = (struct r600_context *)ctx;
  96
  97         rctx->atom_surface_sync.flush_flags |= S_0085F0_TC_ACTION_ENA(1) | r600_get_cb_flush_flags(rctx);
  98         r600_atom_dirty(rctx, &rctx->atom_surface_sync.atom);
  99 }
 100
 101 static bool r600_conv_pipe_prim(unsigned pprim, unsigned *prim)
 102 {
 103         static const int prim_conv[] = {
 104                 V_008958_DI_PT_POINTLIST,
 105                 V_008958_DI_PT_LINELIST,
 106                 V_008958_DI_PT_LINELOOP,
 107                 V_008958_DI_PT_LINESTRIP,
 108                 V_008958_DI_PT_TRILIST,
 109                 V_008958_DI_PT_TRISTRIP,
 110                 V_008958_DI_PT_TRIFAN,
 111                 V_008958_DI_PT_QUADLIST,
 112                 V_008958_DI_PT_QUADSTRIP,
 113                 V_008958_DI_PT_POLYGON,
 114                 -1,
 115                 -1,
 116                 -1,
 117                 -1
 118         };
 119
 120         *prim = prim_conv[pprim];
 121         if (*prim == -1) {
 122                 fprintf(stderr, "%s:%d unsupported %d\n", __func__, __LINE__, pprim);
 123                 return false;
 124         }
 125         return true;
 126 }
 127
 128 /* common state between evergreen and r600 */
 129 void r600_bind_blend_state(struct pipe_context *ctx, void *state)
 130 {
 131         struct r600_context *rctx = (struct r600_context *)ctx;
 132         struct r600_pipe_blend *blend = (struct r600_pipe_blend *)state;
 133         struct r600_pipe_state *rstate;
 134
 135         if (state == NULL)
 136                 return;
 137         rstate = &blend->rstate;
 138         rctx->states[rstate->id] = rstate;
 139         rctx->cb_target_mask = blend->cb_target_mask;
 140
 141         /* Replace every bit except MULTIWRITE_ENABLE. */
 142         rctx->cb_color_control &= ~C_028808_MULTIWRITE_ENABLE;
 143         rctx->cb_color_control |= blend->cb_color_control & C_028808_MULTIWRITE_ENABLE;
 144
 145         r600_context_pipe_state_set(rctx, rstate);
 146 }
 147
 148 static void r600_set_stencil_ref(struct pipe_context *ctx,
 149                                  const struct r600_stencil_ref *state)
 150 {
 151         struct r600_context *rctx = (struct r600_context *)ctx;
 152         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 153
 154         if (rstate == NULL)
 155                 return;
 156
 157         rstate->id = R600_PIPE_STATE_STENCIL_REF;
 158         r600_pipe_state_add_reg(rstate,
 159                                 R_028430_DB_STENCILREFMASK,
 160                                 S_028430_STENCILREF(state->ref_value[0]) |
 161                                 S_028430_STENCILMASK(state->valuemask[0]) |
 162                                 S_028430_STENCILWRITEMASK(state->writemask[0]),
 163                                 NULL, 0);
 164         r600_pipe_state_add_reg(rstate,
 165                                 R_028434_DB_STENCILREFMASK_BF,
 166                                 S_028434_STENCILREF_BF(state->ref_value[1]) |
 167                                 S_028434_STENCILMASK_BF(state->valuemask[1]) |
 168                                 S_028434_STENCILWRITEMASK_BF(state->writemask[1]),
 169                                 NULL, 0);
 170
 171         free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
 172         rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
 173         r600_context_pipe_state_set(rctx, rstate);
 174 }
 175
 176 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
 177                                const struct pipe_stencil_ref *state)
 178 {
 179         struct r600_context *rctx = (struct r600_context *)ctx;
 180         struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
 181         struct r600_stencil_ref ref;
 182
 183         rctx->stencil_ref = *state;
 184
 185         if (!dsa)
 186                 return;
 187
 188         ref.ref_value[0] = state->ref_value[0];
 189         ref.ref_value[1] = state->ref_value[1];
 190         ref.valuemask[0] = dsa->valuemask[0];
 191         ref.valuemask[1] = dsa->valuemask[1];
 192         ref.writemask[0] = dsa->writemask[0];
 193         ref.writemask[1] = dsa->writemask[1];
 194
 195         r600_set_stencil_ref(ctx, &ref);
 196 }
 197
 198 void r600_bind_dsa_state(struct pipe_context *ctx, void *state)
 199 {
 200         struct r600_context *rctx = (struct r600_context *)ctx;
 201         struct r600_pipe_dsa *dsa = state;
 202         struct r600_pipe_state *rstate;
 203         struct r600_stencil_ref ref;
 204
 205         if (state == NULL)
 206                 return;
 207         rstate = &dsa->rstate;
 208         rctx->states[rstate->id] = rstate;
 209         rctx->alpha_ref = dsa->alpha_ref;
 210         rctx->alpha_ref_dirty = true;
 211         r600_context_pipe_state_set(rctx, rstate);
 212
 213         ref.ref_value[0] = rctx->stencil_ref.ref_value[0];
 214         ref.ref_value[1] = rctx->stencil_ref.ref_value[1];
 215         ref.valuemask[0] = dsa->valuemask[0];
 216         ref.valuemask[1] = dsa->valuemask[1];
 217         ref.writemask[0] = dsa->writemask[0];
 218         ref.writemask[1] = dsa->writemask[1];
 219
 220         r600_set_stencil_ref(ctx, &ref);
 221 }
 222
 223 void r600_bind_rs_state(struct pipe_context *ctx, void *state)
 224 {
 225         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
 226         struct r600_context *rctx = (struct r600_context *)ctx;
 227
 228         if (state == NULL)
 229                 return;
 230
 231         rctx->sprite_coord_enable = rs->sprite_coord_enable;
 232         rctx->two_side = rs->two_side;
 233         rctx->pa_sc_line_stipple = rs->pa_sc_line_stipple;
 234         rctx->pa_su_sc_mode_cntl = rs->pa_su_sc_mode_cntl;
 235         rctx->pa_cl_clip_cntl = rs->pa_cl_clip_cntl;
 236
 237         rctx->rasterizer = rs;
 238
 239         rctx->states[rs->rstate.id] = &rs->rstate;
 240         r600_context_pipe_state_set(rctx, &rs->rstate);
 241
 242         if (rctx->chip_class >= EVERGREEN) {
 243                 evergreen_polygon_offset_update(rctx);
 244         } else {
 245                 r600_polygon_offset_update(rctx);
 246         }
 247 }
 248
 249 void r600_delete_rs_state(struct pipe_context *ctx, void *state)
 250 {
 251         struct r600_context *rctx = (struct r600_context *)ctx;
 252         struct r600_pipe_rasterizer *rs = (struct r600_pipe_rasterizer *)state;
 253
 254         if (rctx->rasterizer == rs) {
 255                 rctx->rasterizer = NULL;
 256         }
 257         if (rctx->states[rs->rstate.id] == &rs->rstate) {
 258                 rctx->states[rs->rstate.id] = NULL;
 259         }
 260         free(rs);
 261 }
 262
 263 void r600_sampler_view_destroy(struct pipe_context *ctx,
 264                                struct pipe_sampler_view *state)
 265 {
 266         struct r600_pipe_sampler_view *resource = (struct r600_pipe_sampler_view *)state;
 267
 268         pipe_resource_reference(&state->texture, NULL);
 269         FREE(resource);
 270 }
 271
 272 void r600_delete_state(struct pipe_context *ctx, void *state)
 273 {
 274         struct r600_context *rctx = (struct r600_context *)ctx;
 275         struct r600_pipe_state *rstate = (struct r600_pipe_state *)state;
 276
 277         if (rctx->states[rstate->id] == rstate) {
 278                 rctx->states[rstate->id] = NULL;
 279         }
 280         for (int i = 0; i < rstate->nregs; i++) {
 281                 pipe_resource_reference((struct pipe_resource**)&rstate->regs[i].bo, NULL);
 282         }
 283         free(rstate);
 284 }
 285
 286 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state)
 287 {
 288         struct r600_context *rctx = (struct r600_context *)ctx;
 289         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 290
 291         rctx->vertex_elements = v;
 292         if (v) {
 293                 r600_inval_shader_cache(rctx);
 294                 u_vbuf_bind_vertex_elements(rctx->vbuf_mgr, state,
 295                                                 v->vmgr_elements);
 296
 297                 rctx->states[v->rstate.id] = &v->rstate;
 298                 r600_context_pipe_state_set(rctx, &v->rstate);
 299         }
 300 }
 301
 302 void r600_delete_vertex_element(struct pipe_context *ctx, void *state)
 303 {
 304         struct r600_context *rctx = (struct r600_context *)ctx;
 305         struct r600_vertex_element *v = (struct r600_vertex_element*)state;
 306
 307         if (rctx->states[v->rstate.id] == &v->rstate) {
 308                 rctx->states[v->rstate.id] = NULL;
 309         }
 310         if (rctx->vertex_elements == state)
 311                 rctx->vertex_elements = NULL;
 312
 313         pipe_resource_reference((struct pipe_resource**)&v->fetch_shader, NULL);
 314         u_vbuf_destroy_vertex_elements(rctx->vbuf_mgr, v->vmgr_elements);
 315         FREE(state);
 316 }
 317
 318
 319 void r600_set_index_buffer(struct pipe_context *ctx,
 320                            const struct pipe_index_buffer *ib)
 321 {
 322         struct r600_context *rctx = (struct r600_context *)ctx;
 323
 324         u_vbuf_set_index_buffer(rctx->vbuf_mgr, ib);
 325 }
 326
 327 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 328                              const struct pipe_vertex_buffer *buffers)
 329 {
 330         struct r600_context *rctx = (struct r600_context *)ctx;
 331         int i;
 332
 333         /* Zero states. */
 334         for (i = 0; i < count; i++) {
 335                 if (!buffers[i].buffer) {
 336                         if (rctx->chip_class >= EVERGREEN) {
 337                                 evergreen_context_pipe_state_set_fs_resource(rctx, NULL, i);
 338                         } else {
 339                                 r600_context_pipe_state_set_fs_resource(rctx, NULL, i);
 340                         }
 341                 }
 342         }
 343         for (; i < rctx->vbuf_mgr->nr_real_vertex_buffers; i++) {
 344                 if (rctx->chip_class >= EVERGREEN) {
 345                         evergreen_context_pipe_state_set_fs_resource(rctx, NULL, i);
 346                 } else {
 347                         r600_context_pipe_state_set_fs_resource(rctx, NULL, i);
 348                 }
 349         }
 350
 351         u_vbuf_set_vertex_buffers(rctx->vbuf_mgr, count, buffers);
 352 }
 353
 354 void *r600_create_vertex_elements(struct pipe_context *ctx,
 355                                   unsigned count,
 356                                   const struct pipe_vertex_element *elements)
 357 {
 358         struct r600_context *rctx = (struct r600_context *)ctx;
 359         struct r600_vertex_element *v = CALLOC_STRUCT(r600_vertex_element);
 360
 361         assert(count < 32);
 362         if (!v)
 363                 return NULL;
 364
 365         v->count = count;
 366         v->vmgr_elements =
 367                 u_vbuf_create_vertex_elements(rctx->vbuf_mgr, count,
 368                                                   elements, v->elements);
 369
 370         if (r600_vertex_elements_build_fetch_shader(rctx, v)) {
 371                 FREE(v);
 372                 return NULL;
 373         }
 374
 375         return v;
 376 }
 377
 378 void *r600_create_shader_state(struct pipe_context *ctx,
 379                                const struct pipe_shader_state *state)
 380 {
 381         struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
 382         int r;
 383
 384         shader->tokens = tgsi_dup_tokens(state->tokens);
 385         shader->so = state->stream_output;
 386
 387         r =  r600_pipe_shader_create(ctx, shader);
 388         if (r) {
 389                 return NULL;
 390         }
 391         return shader;
 392 }
 393
 394 void r600_bind_ps_shader(struct pipe_context *ctx, void *state)
 395 {
 396         struct r600_context *rctx = (struct r600_context *)ctx;
 397
 398         /* TODO delete old shader */
 399         rctx->ps_shader = (struct r600_pipe_shader *)state;
 400         if (state) {
 401                 r600_inval_shader_cache(rctx);
 402                 r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
 403
 404                 rctx->cb_color_control &= C_028808_MULTIWRITE_ENABLE;
 405                 rctx->cb_color_control |= S_028808_MULTIWRITE_ENABLE(!!rctx->ps_shader->shader.fs_write_all);
 406         }
 407         if (rctx->ps_shader && rctx->vs_shader) {
 408                 r600_adjust_gprs(rctx);
 409         }
 410 }
 411
 412 void r600_bind_vs_shader(struct pipe_context *ctx, void *state)
 413 {
 414         struct r600_context *rctx = (struct r600_context *)ctx;
 415
 416         /* TODO delete old shader */
 417         rctx->vs_shader = (struct r600_pipe_shader *)state;
 418         if (state) {
 419                 r600_inval_shader_cache(rctx);
 420                 r600_context_pipe_state_set(rctx, &rctx->vs_shader->rstate);
 421         }
 422         if (rctx->ps_shader && rctx->vs_shader) {
 423                 r600_adjust_gprs(rctx);
 424         }
 425 }
 426
 427 void r600_delete_ps_shader(struct pipe_context *ctx, void *state)
 428 {
 429         struct r600_context *rctx = (struct r600_context *)ctx;
 430         struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
 431
 432         if (rctx->ps_shader == shader) {
 433                 rctx->ps_shader = NULL;
 434         }
 435
 436         free(shader->tokens);
 437         r600_pipe_shader_destroy(ctx, shader);
 438         free(shader);
 439 }
 440
 441 void r600_delete_vs_shader(struct pipe_context *ctx, void *state)
 442 {
 443         struct r600_context *rctx = (struct r600_context *)ctx;
 444         struct r600_pipe_shader *shader = (struct r600_pipe_shader *)state;
 445
 446         if (rctx->vs_shader == shader) {
 447                 rctx->vs_shader = NULL;
 448         }
 449
 450         free(shader->tokens);
 451         r600_pipe_shader_destroy(ctx, shader);
 452         free(shader);
 453 }
 454
 455 static void r600_update_alpha_ref(struct r600_context *rctx)
 456 {
 457         unsigned alpha_ref;
 458         struct r600_pipe_state rstate;
 459
 460         alpha_ref = rctx->alpha_ref;
 461         rstate.nregs = 0;
 462         if (rctx->export_16bpc)
 463                 alpha_ref &= ~0x1FFF;
 464         r600_pipe_state_add_reg(&rstate, R_028438_SX_ALPHA_REF, alpha_ref, NULL, 0);
 465
 466         r600_context_pipe_state_set(rctx, &rstate);
 467         rctx->alpha_ref_dirty = false;
 468 }
 469
 470 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 471                               struct pipe_resource *buffer)
 472 {
 473         struct r600_context *rctx = (struct r600_context *)ctx;
 474         struct r600_resource *rbuffer = r600_resource(buffer);
 475         struct r600_pipe_resource_state *rstate;
 476         uint64_t va_offset;
 477         uint32_t offset;
 478
 479         /* Note that the state tracker can unbind constant buffers by
 480          * passing NULL here.
 481          */
 482         if (buffer == NULL) {
 483                 return;
 484         }
 485
 486         r600_inval_shader_cache(rctx);
 487
 488         r600_upload_const_buffer(rctx, &rbuffer, &offset);
 489         va_offset = r600_resource_va(ctx->screen, (void*)rbuffer);
 490         va_offset += offset;
 491         va_offset >>= 8;
 492
 493         switch (shader) {
 494         case PIPE_SHADER_VERTEX:
 495                 rctx->vs_const_buffer.nregs = 0;
 496                 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
 497                                         R_028180_ALU_CONST_BUFFER_SIZE_VS_0 + index * 4,
 498                                         ALIGN_DIVUP(buffer->width0 >> 4, 16),
 499                                         NULL, 0);
 500                 r600_pipe_state_add_reg(&rctx->vs_const_buffer,
 501                                         R_028980_ALU_CONST_CACHE_VS_0 + index * 4,
 502                                         va_offset, rbuffer, RADEON_USAGE_READ);
 503                 r600_context_pipe_state_set(rctx, &rctx->vs_const_buffer);
 504
 505                 rstate = &rctx->vs_const_buffer_resource[index];
 506                 if (!rstate->id) {
 507                         if (rctx->chip_class >= EVERGREEN) {
 508                                 evergreen_pipe_init_buffer_resource(rctx, rstate);
 509                         } else {
 510                                 r600_pipe_init_buffer_resource(rctx, rstate);
 511                         }
 512                 }
 513
 514                 if (rctx->chip_class >= EVERGREEN) {
 515                         evergreen_pipe_mod_buffer_resource(ctx, rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 516                         evergreen_context_pipe_state_set_vs_resource(rctx, rstate, index);
 517                 } else {
 518                         r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 519                         r600_context_pipe_state_set_vs_resource(rctx, rstate, index);
 520                 }
 521                 break;
 522         case PIPE_SHADER_FRAGMENT:
 523                 rctx->ps_const_buffer.nregs = 0;
 524                 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
 525                                         R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
 526                                         ALIGN_DIVUP(buffer->width0 >> 4, 16),
 527                                         NULL, 0);
 528                 r600_pipe_state_add_reg(&rctx->ps_const_buffer,
 529                                         R_028940_ALU_CONST_CACHE_PS_0,
 530                                         va_offset, rbuffer, RADEON_USAGE_READ);
 531                 r600_context_pipe_state_set(rctx, &rctx->ps_const_buffer);
 532
 533                 rstate = &rctx->ps_const_buffer_resource[index];
 534                 if (!rstate->id) {
 535                         if (rctx->chip_class >= EVERGREEN) {
 536                                 evergreen_pipe_init_buffer_resource(rctx, rstate);
 537                         } else {
 538                                 r600_pipe_init_buffer_resource(rctx, rstate);
 539                         }
 540                 }
 541                 if (rctx->chip_class >= EVERGREEN) {
 542                         evergreen_pipe_mod_buffer_resource(ctx, rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 543                         evergreen_context_pipe_state_set_ps_resource(rctx, rstate, index);
 544                 } else {
 545                         r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, 16, RADEON_USAGE_READ);
 546                         r600_context_pipe_state_set_ps_resource(rctx, rstate, index);
 547                 }
 548                 break;
 549         default:
 550                 R600_ERR("unsupported %d\n", shader);
 551                 return;
 552         }
 553
 554         if (buffer != &rbuffer->b.b.b)
 555                 pipe_resource_reference((struct pipe_resource**)&rbuffer, NULL);
 556 }
 557
 558 struct pipe_stream_output_target *
 559 r600_create_so_target(struct pipe_context *ctx,
 560                       struct pipe_resource *buffer,
 561                       unsigned buffer_offset,
 562                       unsigned buffer_size)
 563 {
 564         struct r600_context *rctx = (struct r600_context *)ctx;
 565         struct r600_so_target *t;
 566         void *ptr;
 567
 568         t = CALLOC_STRUCT(r600_so_target);
 569         if (!t) {
 570                 return NULL;
 571         }
 572
 573         t->b.reference.count = 1;
 574         t->b.context = ctx;
 575         pipe_resource_reference(&t->b.buffer, buffer);
 576         t->b.buffer_offset = buffer_offset;
 577         t->b.buffer_size = buffer_size;
 578
 579         t->filled_size = (struct r600_resource*)
 580                 pipe_buffer_create(ctx->screen, PIPE_BIND_CUSTOM, PIPE_USAGE_STATIC, 4);
 581         ptr = rctx->ws->buffer_map(t->filled_size->buf, rctx->cs, PIPE_TRANSFER_WRITE);
 582         memset(ptr, 0, t->filled_size->buf->size);
 583         rctx->ws->buffer_unmap(t->filled_size->buf);
 584
 585         return &t->b;
 586 }
 587
 588 void r600_so_target_destroy(struct pipe_context *ctx,
 589                             struct pipe_stream_output_target *target)
 590 {
 591         struct r600_so_target *t = (struct r600_so_target*)target;
 592         pipe_resource_reference(&t->b.buffer, NULL);
 593         pipe_resource_reference((struct pipe_resource**)&t->filled_size, NULL);
 594         FREE(t);
 595 }
 596
 597 void r600_set_so_targets(struct pipe_context *ctx,
 598                          unsigned num_targets,
 599                          struct pipe_stream_output_target **targets,
 600                          unsigned append_bitmask)
 601 {
 602         struct r600_context *rctx = (struct r600_context *)ctx;
 603         unsigned i;
 604
 605         /* Stop streamout. */
 606         if (rctx->num_so_targets) {
 607                 r600_context_streamout_end(rctx);
 608         }
 609
 610         /* Set the new targets. */
 611         for (i = 0; i < num_targets; i++) {
 612                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], targets[i]);
 613         }
 614         for (; i < rctx->num_so_targets; i++) {
 615                 pipe_so_target_reference((struct pipe_stream_output_target**)&rctx->so_targets[i], NULL);
 616         }
 617
 618         rctx->num_so_targets = num_targets;
 619         rctx->streamout_start = num_targets != 0;
 620         rctx->streamout_append_bitmask = append_bitmask;
 621 }
 622
 623 static void r600_vertex_buffer_update(struct r600_context *rctx)
 624 {
 625         struct r600_pipe_resource_state *rstate;
 626         struct r600_resource *rbuffer;
 627         struct pipe_vertex_buffer *vertex_buffer;
 628         unsigned i, count, offset;
 629
 630         r600_inval_vertex_cache(rctx);
 631
 632         if (rctx->vertex_elements->vbuffer_need_offset) {
 633                 /* one resource per vertex elements */
 634                 count = rctx->vertex_elements->count;
 635         } else {
 636                 /* bind vertex buffer once */
 637                 count = rctx->vbuf_mgr->nr_real_vertex_buffers;
 638         }
 639
 640         for (i = 0 ; i < count; i++) {
 641                 rstate = &rctx->fs_resource[i];
 642
 643                 if (rctx->vertex_elements->vbuffer_need_offset) {
 644                         /* one resource per vertex elements */
 645                         unsigned vbuffer_index;
 646                         vbuffer_index = rctx->vertex_elements->elements[i].vertex_buffer_index;
 647                         vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[vbuffer_index];
 648                         rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 649                         offset = rctx->vertex_elements->vbuffer_offset[i];
 650                 } else {
 651                         /* bind vertex buffer once */
 652                         vertex_buffer = &rctx->vbuf_mgr->real_vertex_buffer[i];
 653                         rbuffer = (struct r600_resource*)vertex_buffer->buffer;
 654                         offset = 0;
 655                 }
 656                 if (vertex_buffer == NULL || rbuffer == NULL)
 657                         continue;
 658                 offset += vertex_buffer->buffer_offset;
 659
 660                 if (!rstate->id) {
 661                         if (rctx->chip_class >= EVERGREEN) {
 662                                 evergreen_pipe_init_buffer_resource(rctx, rstate);
 663                         } else {
 664                                 r600_pipe_init_buffer_resource(rctx, rstate);
 665                         }
 666                 }
 667
 668                 if (rctx->chip_class >= EVERGREEN) {
 669                         evergreen_pipe_mod_buffer_resource(&rctx->context, rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
 670                         evergreen_context_pipe_state_set_fs_resource(rctx, rstate, i);
 671                 } else {
 672                         r600_pipe_mod_buffer_resource(rstate, rbuffer, offset, vertex_buffer->stride, RADEON_USAGE_READ);
 673                         r600_context_pipe_state_set_fs_resource(rctx, rstate, i);
 674                 }
 675         }
 676 }
 677
 678 static int r600_shader_rebuild(struct pipe_context * ctx, struct r600_pipe_shader * shader)
 679 {
 680         struct r600_context *rctx = (struct r600_context *)ctx;
 681         int r;
 682
 683         r600_pipe_shader_destroy(ctx, shader);
 684         r = r600_pipe_shader_create(ctx, shader);
 685         if (r) {
 686                 return r;
 687         }
 688         r600_context_pipe_state_set(rctx, &shader->rstate);
 689
 690         return 0;
 691 }
 692
 693 static void r600_update_derived_state(struct r600_context *rctx)
 694 {
 695         struct pipe_context * ctx = (struct pipe_context*)rctx;
 696         struct r600_pipe_state rstate;
 697
 698         rstate.nregs = 0;
 699
 700         if (rstate.nregs)
 701                 r600_context_pipe_state_set(rctx, &rstate);
 702
 703         if (!rctx->blitter->running) {
 704                 if (rctx->have_depth_fb || rctx->have_depth_texture)
 705                         r600_flush_depth_textures(rctx);
 706         }
 707
 708         if (rctx->chip_class < EVERGREEN) {
 709                 r600_update_sampler_states(rctx);
 710         }
 711
 712         if ((rctx->ps_shader->shader.two_side != rctx->two_side) ||
 713             ((rctx->chip_class >= EVERGREEN) && rctx->ps_shader->shader.fs_write_all &&
 714              (rctx->ps_shader->shader.nr_cbufs != rctx->nr_cbufs))) {
 715                 r600_shader_rebuild(&rctx->context, rctx->ps_shader);
 716         }
 717
 718         if (rctx->alpha_ref_dirty) {
 719                 r600_update_alpha_ref(rctx);
 720         }
 721
 722         if (rctx->ps_shader && ((rctx->sprite_coord_enable &&
 723                 (rctx->ps_shader->sprite_coord_enable != rctx->sprite_coord_enable)) ||
 724                 (rctx->rasterizer && rctx->rasterizer->flatshade != rctx->ps_shader->flatshade))) {
 725
 726                 if (rctx->chip_class >= EVERGREEN)
 727                         evergreen_pipe_shader_ps(ctx, rctx->ps_shader);
 728                 else
 729                         r600_pipe_shader_ps(ctx, rctx->ps_shader);
 730
 731                 r600_context_pipe_state_set(rctx, &rctx->ps_shader->rstate);
 732         }
 733
 734 }
 735
 736 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo)
 737 {
 738         struct r600_context *rctx = (struct r600_context *)ctx;
 739         struct r600_pipe_dsa *dsa = (struct r600_pipe_dsa*)rctx->states[R600_PIPE_STATE_DSA];
 740         struct pipe_draw_info info = *dinfo;
 741         struct r600_draw rdraw = {};
 742         struct pipe_index_buffer ib = {};
 743         unsigned prim, mask, ls_mask = 0;
 744         struct r600_block *dirty_block = NULL, *next_block = NULL;
 745         struct r600_atom *state = NULL, *next_state = NULL;
 746
 747         if ((!info.count && (info.indexed || !info.count_from_stream_output)) ||
 748             (info.indexed && !rctx->vbuf_mgr->index_buffer.buffer) ||
 749             !r600_conv_pipe_prim(info.mode, &prim)) {
 750                 return;
 751         }
 752
 753         if (!rctx->ps_shader || !rctx->vs_shader)
 754                 return;
 755
 756         r600_update_derived_state(rctx);
 757
 758         u_vbuf_draw_begin(rctx->vbuf_mgr, &info);
 759         r600_vertex_buffer_update(rctx);
 760
 761         rdraw.vgt_num_indices = info.count;
 762         rdraw.vgt_num_instances = info.instance_count;
 763
 764         if (info.indexed) {
 765                 /* Initialize the index buffer struct. */
 766                 pipe_resource_reference(&ib.buffer, rctx->vbuf_mgr->index_buffer.buffer);
 767                 ib.index_size = rctx->vbuf_mgr->index_buffer.index_size;
 768                 ib.offset = rctx->vbuf_mgr->index_buffer.offset + info.start * ib.index_size;
 769
 770                 /* Translate or upload, if needed. */
 771                 r600_translate_index_buffer(rctx, &ib, info.count);
 772
 773                 if (u_vbuf_resource(ib.buffer)->user_ptr) {
 774                         r600_upload_index_buffer(rctx, &ib, info.count);
 775                 }
 776
 777                 /* Initialize the r600_draw struct with index buffer info. */
 778                 if (ib.index_size == 4) {
 779                         rdraw.vgt_index_type = VGT_INDEX_32 |
 780                                 (R600_BIG_ENDIAN ? VGT_DMA_SWAP_32_BIT : 0);
 781                 } else {
 782                         rdraw.vgt_index_type = VGT_INDEX_16 |
 783                                 (R600_BIG_ENDIAN ? VGT_DMA_SWAP_16_BIT : 0);
 784                 }
 785                 rdraw.indices = (struct r600_resource*)ib.buffer;
 786                 rdraw.indices_bo_offset = ib.offset;
 787                 rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_DMA;
 788         } else {
 789                 info.index_bias = info.start;
 790                 rdraw.vgt_draw_initiator = V_0287F0_DI_SRC_SEL_AUTO_INDEX;
 791                 if (info.count_from_stream_output) {
 792                         rdraw.vgt_draw_initiator |= S_0287F0_USE_OPAQUE(1);
 793
 794                         r600_context_draw_opaque_count(rctx, (struct r600_so_target*)info.count_from_stream_output);
 795                 }
 796         }
 797
 798         rctx->vs_so_stride_in_dw = rctx->vs_shader->so.stride;
 799
 800         mask = (1ULL << ((unsigned)rctx->framebuffer.nr_cbufs * 4)) - 1;
 801
 802         if (rctx->vgt.id != R600_PIPE_STATE_VGT) {
 803                 rctx->vgt.id = R600_PIPE_STATE_VGT;
 804                 rctx->vgt.nregs = 0;
 805                 r600_pipe_state_add_reg(&rctx->vgt, R_008958_VGT_PRIMITIVE_TYPE, prim, NULL, 0);
 806                 r600_pipe_state_add_reg(&rctx->vgt, R_028238_CB_TARGET_MASK, rctx->cb_target_mask & mask, NULL, 0);
 807                 r600_pipe_state_add_reg(&rctx->vgt, R_028400_VGT_MAX_VTX_INDX, ~0, NULL, 0);
 808                 r600_pipe_state_add_reg(&rctx->vgt, R_028404_VGT_MIN_VTX_INDX, 0, NULL, 0);
 809                 r600_pipe_state_add_reg(&rctx->vgt, R_028408_VGT_INDX_OFFSET, info.index_bias, NULL, 0);
 810                 r600_pipe_state_add_reg(&rctx->vgt, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, info.restart_index, NULL, 0);
 811                 r600_pipe_state_add_reg(&rctx->vgt, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info.primitive_restart, NULL, 0);
 812                 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, NULL, 0);
 813                 r600_pipe_state_add_reg(&rctx->vgt, R_03CFF4_SQ_VTX_START_INST_LOC, info.start_instance, NULL, 0);
 814                 r600_pipe_state_add_reg(&rctx->vgt, R_028A0C_PA_SC_LINE_STIPPLE, 0, NULL, 0);
 815                 r600_pipe_state_add_reg(&rctx->vgt, R_028814_PA_SU_SC_MODE_CNTL, 0, NULL, 0);
 816                 if (rctx->chip_class <= R700)
 817                         r600_pipe_state_add_reg(&rctx->vgt, R_028808_CB_COLOR_CONTROL, rctx->cb_color_control, NULL, 0);
 818                 r600_pipe_state_add_reg(&rctx->vgt, R_02881C_PA_CL_VS_OUT_CNTL, 0, NULL, 0);
 819                 r600_pipe_state_add_reg(&rctx->vgt, R_028810_PA_CL_CLIP_CNTL, 0, NULL, 0);
 820         }
 821
 822         rctx->vgt.nregs = 0;
 823         r600_pipe_state_mod_reg(&rctx->vgt, prim);
 824         r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_target_mask & mask);
 825         r600_pipe_state_mod_reg(&rctx->vgt, ~0);
 826         r600_pipe_state_mod_reg(&rctx->vgt, 0);
 827         r600_pipe_state_mod_reg(&rctx->vgt, info.index_bias);
 828         r600_pipe_state_mod_reg(&rctx->vgt, info.restart_index);
 829         r600_pipe_state_mod_reg(&rctx->vgt, info.primitive_restart);
 830         r600_pipe_state_mod_reg(&rctx->vgt, 0);
 831         r600_pipe_state_mod_reg(&rctx->vgt, info.start_instance);
 832
 833         if (prim == V_008958_DI_PT_LINELIST)
 834                 ls_mask = 1;
 835         else if (prim == V_008958_DI_PT_LINESTRIP)
 836                 ls_mask = 2;
 837         r600_pipe_state_mod_reg(&rctx->vgt, S_028A0C_AUTO_RESET_CNTL(ls_mask) | rctx->pa_sc_line_stipple);
 838
 839         if (info.mode == PIPE_PRIM_QUADS || info.mode == PIPE_PRIM_QUAD_STRIP || info.mode == PIPE_PRIM_POLYGON) {
 840                 r600_pipe_state_mod_reg(&rctx->vgt, S_028814_PROVOKING_VTX_LAST(1) | rctx->pa_su_sc_mode_cntl);
 841         } else {
 842                 r600_pipe_state_mod_reg(&rctx->vgt, rctx->pa_su_sc_mode_cntl);
 843         }
 844         if (rctx->chip_class <= R700)
 845                 r600_pipe_state_mod_reg(&rctx->vgt, rctx->cb_color_control);
 846         r600_pipe_state_mod_reg(&rctx->vgt,
 847                                 rctx->vs_shader->pa_cl_vs_out_cntl |
 848                                 (rctx->rasterizer->clip_plane_enable & rctx->vs_shader->shader.clip_dist_write));
 849         r600_pipe_state_mod_reg(&rctx->vgt,
 850                                 rctx->pa_cl_clip_cntl |
 851                                 (rctx->vs_shader->shader.clip_dist_write ||
 852                                  rctx->vs_shader->shader.vs_prohibit_ucps ?
 853                                  0 : rctx->rasterizer->clip_plane_enable & 0x3F));
 854
 855         r600_context_pipe_state_set(rctx, &rctx->vgt);
 856
 857         rdraw.db_render_override = dsa->db_render_override;
 858         rdraw.db_render_control = dsa->db_render_control;
 859
 860         /* Emit states. */
 861         r600_need_cs_space(rctx, 0, TRUE);
 862
 863         LIST_FOR_EACH_ENTRY_SAFE(state, next_state, &rctx->dirty_states, head) {
 864                 r600_emit_atom(rctx, state);
 865         }
 866         LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->dirty,list) {
 867                 r600_context_block_emit_dirty(rctx, dirty_block);
 868         }
 869         LIST_FOR_EACH_ENTRY_SAFE(dirty_block, next_block, &rctx->resource_dirty,list) {
 870                 r600_context_block_resource_emit_dirty(rctx, dirty_block);
 871         }
 872         rctx->pm4_dirty_cdwords = 0;
 873
 874         /* Enable stream out if needed. */
 875         if (rctx->streamout_start) {
 876                 r600_context_streamout_begin(rctx);
 877                 rctx->streamout_start = FALSE;
 878         }
 879
 880         if (rctx->chip_class >= EVERGREEN) {
 881                 evergreen_context_draw(rctx, &rdraw);
 882         } else {
 883                 r600_context_draw(rctx, &rdraw);
 884         }
 885
 886         rctx->flags |= R600_CONTEXT_DST_CACHES_DIRTY | R600_CONTEXT_DRAW_PENDING;
 887
 888         if (rctx->framebuffer.zsbuf)
 889         {
 890                 struct pipe_resource *tex = rctx->framebuffer.zsbuf->texture;
 891                 ((struct r600_resource_texture *)tex)->dirty_db = TRUE;
 892         }
 893
 894         pipe_resource_reference(&ib.buffer, NULL);
 895         u_vbuf_draw_end(rctx->vbuf_mgr);
 896 }
 897
 898 void _r600_pipe_state_add_reg(struct r600_context *ctx,
 899                               struct r600_pipe_state *state,
 900                               uint32_t offset, uint32_t value,
 901                               uint32_t range_id, uint32_t block_id,
 902                               struct r600_resource *bo,
 903                               enum radeon_bo_usage usage)
 904 {
 905         struct r600_range *range;
 906         struct r600_block *block;
 907
 908         if (bo) assert(usage);
 909
 910         range = &ctx->range[range_id];
 911         block = range->blocks[block_id];
 912         state->regs[state->nregs].block = block;
 913         state->regs[state->nregs].id = (offset - block->start_offset) >> 2;
 914
 915         state->regs[state->nregs].value = value;
 916         state->regs[state->nregs].bo = bo;
 917         state->regs[state->nregs].bo_usage = usage;
 918
 919         state->nregs++;
 920         assert(state->nregs < R600_BLOCK_MAX_REG);
 921 }
 922
 923 void r600_pipe_state_add_reg_noblock(struct r600_pipe_state *state,
 924                                      uint32_t offset, uint32_t value,
 925                                      struct r600_resource *bo,
 926                                      enum radeon_bo_usage usage)
 927 {
 928         if (bo) assert(usage);
 929
 930         state->regs[state->nregs].id = offset;
 931         state->regs[state->nregs].block = NULL;
 932         state->regs[state->nregs].value = value;
 933         state->regs[state->nregs].bo = bo;
 934         state->regs[state->nregs].bo_usage = usage;
 935
 936         state->nregs++;
 937         assert(state->nregs < R600_BLOCK_MAX_REG);
 938 }
 939
 940 uint32_t r600_translate_stencil_op(int s_op)
 941 {
 942         switch (s_op) {
 943         case PIPE_STENCIL_OP_KEEP:
 944                 return V_028800_STENCIL_KEEP;
 945         case PIPE_STENCIL_OP_ZERO:
 946                 return V_028800_STENCIL_ZERO;
 947         case PIPE_STENCIL_OP_REPLACE:
 948                 return V_028800_STENCIL_REPLACE;
 949         case PIPE_STENCIL_OP_INCR:
 950                 return V_028800_STENCIL_INCR;
 951         case PIPE_STENCIL_OP_DECR:
 952                 return V_028800_STENCIL_DECR;
 953         case PIPE_STENCIL_OP_INCR_WRAP:
 954                 return V_028800_STENCIL_INCR_WRAP;
 955         case PIPE_STENCIL_OP_DECR_WRAP:
 956                 return V_028800_STENCIL_DECR_WRAP;
 957         case PIPE_STENCIL_OP_INVERT:
 958                 return V_028800_STENCIL_INVERT;
 959         default:
 960                 R600_ERR("Unknown stencil op %d", s_op);
 961                 assert(0);
 962                 break;
 963         }
 964         return 0;
 965 }
 966
 967 uint32_t r600_translate_fill(uint32_t func)
 968 {
 969         switch(func) {
 970         case PIPE_POLYGON_MODE_FILL:
 971                 return 2;
 972         case PIPE_POLYGON_MODE_LINE:
 973                 return 1;
 974         case PIPE_POLYGON_MODE_POINT:
 975                 return 0;
 976         default:
 977                 assert(0);
 978                 return 0;
 979         }
 980 }
 981
 982 unsigned r600_tex_wrap(unsigned wrap)
 983 {
 984         switch (wrap) {
 985         default:
 986         case PIPE_TEX_WRAP_REPEAT:
 987                 return V_03C000_SQ_TEX_WRAP;
 988         case PIPE_TEX_WRAP_CLAMP:
 989                 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
 990         case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
 991                 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
 992         case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
 993                 return V_03C000_SQ_TEX_CLAMP_BORDER;
 994         case PIPE_TEX_WRAP_MIRROR_REPEAT:
 995                 return V_03C000_SQ_TEX_MIRROR;
 996         case PIPE_TEX_WRAP_MIRROR_CLAMP:
 997                 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
 998         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
 999                 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1000         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
1001                 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
1002         }
1003 }
1004
1005 unsigned r600_tex_filter(unsigned filter)
1006 {
1007         switch (filter) {
1008         default:
1009         case PIPE_TEX_FILTER_NEAREST:
1010                 return V_03C000_SQ_TEX_XY_FILTER_POINT;
1011         case PIPE_TEX_FILTER_LINEAR:
1012                 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
1013         }
1014 }
1015
1016 unsigned r600_tex_mipfilter(unsigned filter)
1017 {
1018         switch (filter) {
1019         case PIPE_TEX_MIPFILTER_NEAREST:
1020                 return V_03C000_SQ_TEX_Z_FILTER_POINT;
1021         case PIPE_TEX_MIPFILTER_LINEAR:
1022                 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
1023         default:
1024         case PIPE_TEX_MIPFILTER_NONE:
1025                 return V_03C000_SQ_TEX_Z_FILTER_NONE;
1026         }
1027 }
1028
1029 unsigned r600_tex_compare(unsigned compare)
1030 {
1031         switch (compare) {
1032         default:
1033         case PIPE_FUNC_NEVER:
1034                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
1035         case PIPE_FUNC_LESS:
1036                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
1037         case PIPE_FUNC_EQUAL:
1038                 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
1039         case PIPE_FUNC_LEQUAL:
1040                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1041         case PIPE_FUNC_GREATER:
1042                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
1043         case PIPE_FUNC_NOTEQUAL:
1044                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1045         case PIPE_FUNC_GEQUAL:
1046                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1047         case PIPE_FUNC_ALWAYS:
1048                 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1049         }
1050 }