src/gallium/drivers/r600/r600_state.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "r600_formats.h"
  24 #include "r600d.h"
  25
  26 #include "pipe/p_shader_tokens.h"
  27 #include "util/u_pack_color.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_framebuffer.h"
  30 #include "util/u_dual_blend.h"
  31
  32 static uint32_t r600_translate_blend_function(int blend_func)
  33 {
  34         switch (blend_func) {
  35         case PIPE_BLEND_ADD:
  36                 return V_028804_COMB_DST_PLUS_SRC;
  37         case PIPE_BLEND_SUBTRACT:
  38                 return V_028804_COMB_SRC_MINUS_DST;
  39         case PIPE_BLEND_REVERSE_SUBTRACT:
  40                 return V_028804_COMB_DST_MINUS_SRC;
  41         case PIPE_BLEND_MIN:
  42                 return V_028804_COMB_MIN_DST_SRC;
  43         case PIPE_BLEND_MAX:
  44                 return V_028804_COMB_MAX_DST_SRC;
  45         default:
  46                 R600_ERR("Unknown blend function %d\n", blend_func);
  47                 assert(0);
  48                 break;
  49         }
  50         return 0;
  51 }
  52
  53 static uint32_t r600_translate_blend_factor(int blend_fact)
  54 {
  55         switch (blend_fact) {
  56         case PIPE_BLENDFACTOR_ONE:
  57                 return V_028804_BLEND_ONE;
  58         case PIPE_BLENDFACTOR_SRC_COLOR:
  59                 return V_028804_BLEND_SRC_COLOR;
  60         case PIPE_BLENDFACTOR_SRC_ALPHA:
  61                 return V_028804_BLEND_SRC_ALPHA;
  62         case PIPE_BLENDFACTOR_DST_ALPHA:
  63                 return V_028804_BLEND_DST_ALPHA;
  64         case PIPE_BLENDFACTOR_DST_COLOR:
  65                 return V_028804_BLEND_DST_COLOR;
  66         case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
  67                 return V_028804_BLEND_SRC_ALPHA_SATURATE;
  68         case PIPE_BLENDFACTOR_CONST_COLOR:
  69                 return V_028804_BLEND_CONST_COLOR;
  70         case PIPE_BLENDFACTOR_CONST_ALPHA:
  71                 return V_028804_BLEND_CONST_ALPHA;
  72         case PIPE_BLENDFACTOR_ZERO:
  73                 return V_028804_BLEND_ZERO;
  74         case PIPE_BLENDFACTOR_INV_SRC_COLOR:
  75                 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
  76         case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
  77                 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
  78         case PIPE_BLENDFACTOR_INV_DST_ALPHA:
  79                 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
  80         case PIPE_BLENDFACTOR_INV_DST_COLOR:
  81                 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
  82         case PIPE_BLENDFACTOR_INV_CONST_COLOR:
  83                 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
  84         case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
  85                 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
  86         case PIPE_BLENDFACTOR_SRC1_COLOR:
  87                 return V_028804_BLEND_SRC1_COLOR;
  88         case PIPE_BLENDFACTOR_SRC1_ALPHA:
  89                 return V_028804_BLEND_SRC1_ALPHA;
  90         case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
  91                 return V_028804_BLEND_INV_SRC1_COLOR;
  92         case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
  93                 return V_028804_BLEND_INV_SRC1_ALPHA;
  94         default:
  95                 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
  96                 assert(0);
  97                 break;
  98         }
  99         return 0;
 100 }
 101
 102 static unsigned r600_tex_dim(unsigned dim)
 103 {
 104         switch (dim) {
 105         default:
 106         case PIPE_TEXTURE_1D:
 107                 return V_038000_SQ_TEX_DIM_1D;
 108         case PIPE_TEXTURE_1D_ARRAY:
 109                 return V_038000_SQ_TEX_DIM_1D_ARRAY;
 110         case PIPE_TEXTURE_2D:
 111         case PIPE_TEXTURE_RECT:
 112                 return V_038000_SQ_TEX_DIM_2D;
 113         case PIPE_TEXTURE_2D_ARRAY:
 114                 return V_038000_SQ_TEX_DIM_2D_ARRAY;
 115         case PIPE_TEXTURE_3D:
 116                 return V_038000_SQ_TEX_DIM_3D;
 117         case PIPE_TEXTURE_CUBE:
 118                 return V_038000_SQ_TEX_DIM_CUBEMAP;
 119         }
 120 }
 121
 122 static uint32_t r600_translate_dbformat(enum pipe_format format)
 123 {
 124         switch (format) {
 125         case PIPE_FORMAT_Z16_UNORM:
 126                 return V_028010_DEPTH_16;
 127         case PIPE_FORMAT_Z24X8_UNORM:
 128                 return V_028010_DEPTH_X8_24;
 129         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 130                 return V_028010_DEPTH_8_24;
 131         case PIPE_FORMAT_Z32_FLOAT:
 132                 return V_028010_DEPTH_32_FLOAT;
 133         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 134                 return V_028010_DEPTH_X24_8_32_FLOAT;
 135         default:
 136                 return ~0U;
 137         }
 138 }
 139
 140 static uint32_t r600_translate_colorswap(enum pipe_format format)
 141 {
 142         switch (format) {
 143         /* 8-bit buffers. */
 144         case PIPE_FORMAT_A8_UNORM:
 145         case PIPE_FORMAT_A8_SNORM:
 146         case PIPE_FORMAT_A8_UINT:
 147         case PIPE_FORMAT_A8_SINT:
 148         case PIPE_FORMAT_A16_UNORM:
 149         case PIPE_FORMAT_A16_SNORM:
 150         case PIPE_FORMAT_A16_UINT:
 151         case PIPE_FORMAT_A16_SINT:
 152         case PIPE_FORMAT_A16_FLOAT:
 153         case PIPE_FORMAT_A32_UINT:
 154         case PIPE_FORMAT_A32_SINT:
 155         case PIPE_FORMAT_A32_FLOAT:
 156         case PIPE_FORMAT_R4A4_UNORM:
 157                 return V_0280A0_SWAP_ALT_REV;
 158         case PIPE_FORMAT_I8_UNORM:
 159         case PIPE_FORMAT_I8_SNORM:
 160         case PIPE_FORMAT_I8_UINT:
 161         case PIPE_FORMAT_I8_SINT:
 162         case PIPE_FORMAT_L8_UNORM:
 163         case PIPE_FORMAT_L8_SNORM:
 164         case PIPE_FORMAT_L8_UINT:
 165         case PIPE_FORMAT_L8_SINT:
 166         case PIPE_FORMAT_L8_SRGB:
 167         case PIPE_FORMAT_L16_UNORM:
 168         case PIPE_FORMAT_L16_SNORM:
 169         case PIPE_FORMAT_L16_UINT:
 170         case PIPE_FORMAT_L16_SINT:
 171         case PIPE_FORMAT_L16_FLOAT:
 172         case PIPE_FORMAT_L32_UINT:
 173         case PIPE_FORMAT_L32_SINT:
 174         case PIPE_FORMAT_L32_FLOAT:
 175         case PIPE_FORMAT_I16_UNORM:
 176         case PIPE_FORMAT_I16_SNORM:
 177         case PIPE_FORMAT_I16_UINT:
 178         case PIPE_FORMAT_I16_SINT:
 179         case PIPE_FORMAT_I16_FLOAT:
 180         case PIPE_FORMAT_I32_UINT:
 181         case PIPE_FORMAT_I32_SINT:
 182         case PIPE_FORMAT_I32_FLOAT:
 183         case PIPE_FORMAT_R8_UNORM:
 184         case PIPE_FORMAT_R8_SNORM:
 185         case PIPE_FORMAT_R8_UINT:
 186         case PIPE_FORMAT_R8_SINT:
 187                 return V_0280A0_SWAP_STD;
 188
 189         case PIPE_FORMAT_L4A4_UNORM:
 190         case PIPE_FORMAT_A4R4_UNORM:
 191                 return V_0280A0_SWAP_ALT;
 192
 193         /* 16-bit buffers. */
 194         case PIPE_FORMAT_B5G6R5_UNORM:
 195                 return V_0280A0_SWAP_STD_REV;
 196
 197         case PIPE_FORMAT_B5G5R5A1_UNORM:
 198         case PIPE_FORMAT_B5G5R5X1_UNORM:
 199                 return V_0280A0_SWAP_ALT;
 200
 201         case PIPE_FORMAT_B4G4R4A4_UNORM:
 202         case PIPE_FORMAT_B4G4R4X4_UNORM:
 203                 return V_0280A0_SWAP_ALT;
 204
 205         case PIPE_FORMAT_Z16_UNORM:
 206                 return V_0280A0_SWAP_STD;
 207
 208         case PIPE_FORMAT_L8A8_UNORM:
 209         case PIPE_FORMAT_L8A8_SNORM:
 210         case PIPE_FORMAT_L8A8_UINT:
 211         case PIPE_FORMAT_L8A8_SINT:
 212         case PIPE_FORMAT_L8A8_SRGB:
 213         case PIPE_FORMAT_L16A16_UNORM:
 214         case PIPE_FORMAT_L16A16_SNORM:
 215         case PIPE_FORMAT_L16A16_UINT:
 216         case PIPE_FORMAT_L16A16_SINT:
 217         case PIPE_FORMAT_L16A16_FLOAT:
 218         case PIPE_FORMAT_L32A32_UINT:
 219         case PIPE_FORMAT_L32A32_SINT:
 220         case PIPE_FORMAT_L32A32_FLOAT:
 221                 return V_0280A0_SWAP_ALT;
 222         case PIPE_FORMAT_R8G8_UNORM:
 223         case PIPE_FORMAT_R8G8_SNORM:
 224         case PIPE_FORMAT_R8G8_UINT:
 225         case PIPE_FORMAT_R8G8_SINT:
 226                 return V_0280A0_SWAP_STD;
 227
 228         case PIPE_FORMAT_R16_UNORM:
 229         case PIPE_FORMAT_R16_SNORM:
 230         case PIPE_FORMAT_R16_UINT:
 231         case PIPE_FORMAT_R16_SINT:
 232         case PIPE_FORMAT_R16_FLOAT:
 233                 return V_0280A0_SWAP_STD;
 234
 235         /* 32-bit buffers. */
 236
 237         case PIPE_FORMAT_A8B8G8R8_SRGB:
 238                 return V_0280A0_SWAP_STD_REV;
 239         case PIPE_FORMAT_B8G8R8A8_SRGB:
 240                 return V_0280A0_SWAP_ALT;
 241
 242         case PIPE_FORMAT_B8G8R8A8_UNORM:
 243         case PIPE_FORMAT_B8G8R8X8_UNORM:
 244                 return V_0280A0_SWAP_ALT;
 245
 246         case PIPE_FORMAT_A8R8G8B8_UNORM:
 247         case PIPE_FORMAT_X8R8G8B8_UNORM:
 248                 return V_0280A0_SWAP_ALT_REV;
 249         case PIPE_FORMAT_R8G8B8A8_SNORM:
 250         case PIPE_FORMAT_R8G8B8A8_UNORM:
 251         case PIPE_FORMAT_R8G8B8X8_UNORM:
 252         case PIPE_FORMAT_R8G8B8A8_SINT:
 253         case PIPE_FORMAT_R8G8B8A8_UINT:
 254                 return V_0280A0_SWAP_STD;
 255
 256         case PIPE_FORMAT_A8B8G8R8_UNORM:
 257         case PIPE_FORMAT_X8B8G8R8_UNORM:
 258         /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
 259                 return V_0280A0_SWAP_STD_REV;
 260
 261         case PIPE_FORMAT_Z24X8_UNORM:
 262         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 263                 return V_0280A0_SWAP_STD;
 264
 265         case PIPE_FORMAT_X8Z24_UNORM:
 266         case PIPE_FORMAT_S8_UINT_Z24_UNORM:
 267                 return V_0280A0_SWAP_STD;
 268
 269         case PIPE_FORMAT_R10G10B10A2_UNORM:
 270         case PIPE_FORMAT_R10G10B10X2_SNORM:
 271         case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
 272                 return V_0280A0_SWAP_STD;
 273
 274         case PIPE_FORMAT_B10G10R10A2_UNORM:
 275         case PIPE_FORMAT_B10G10R10A2_UINT:
 276                 return V_0280A0_SWAP_ALT;
 277
 278         case PIPE_FORMAT_R11G11B10_FLOAT:
 279         case PIPE_FORMAT_R16G16_UNORM:
 280         case PIPE_FORMAT_R16G16_SNORM:
 281         case PIPE_FORMAT_R16G16_FLOAT:
 282         case PIPE_FORMAT_R16G16_UINT:
 283         case PIPE_FORMAT_R16G16_SINT:
 284         case PIPE_FORMAT_R16G16B16_FLOAT:
 285         case PIPE_FORMAT_R32G32B32_FLOAT:
 286         case PIPE_FORMAT_R32_UINT:
 287         case PIPE_FORMAT_R32_SINT:
 288         case PIPE_FORMAT_R32_FLOAT:
 289         case PIPE_FORMAT_Z32_FLOAT:
 290                 return V_0280A0_SWAP_STD;
 291
 292         /* 64-bit buffers. */
 293         case PIPE_FORMAT_R32G32_FLOAT:
 294         case PIPE_FORMAT_R32G32_UINT:
 295         case PIPE_FORMAT_R32G32_SINT:
 296         case PIPE_FORMAT_R16G16B16A16_UNORM:
 297         case PIPE_FORMAT_R16G16B16A16_SNORM:
 298         case PIPE_FORMAT_R16G16B16A16_UINT:
 299         case PIPE_FORMAT_R16G16B16A16_SINT:
 300         case PIPE_FORMAT_R16G16B16A16_FLOAT:
 301         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 302
 303         /* 128-bit buffers. */
 304         case PIPE_FORMAT_R32G32B32A32_FLOAT:
 305         case PIPE_FORMAT_R32G32B32A32_SNORM:
 306         case PIPE_FORMAT_R32G32B32A32_UNORM:
 307         case PIPE_FORMAT_R32G32B32A32_SINT:
 308         case PIPE_FORMAT_R32G32B32A32_UINT:
 309                 return V_0280A0_SWAP_STD;
 310         default:
 311                 R600_ERR("unsupported colorswap format %d\n", format);
 312                 return ~0U;
 313         }
 314         return ~0U;
 315 }
 316
 317 static uint32_t r600_translate_colorformat(enum pipe_format format)
 318 {
 319         switch (format) {
 320         case PIPE_FORMAT_L4A4_UNORM:
 321         case PIPE_FORMAT_R4A4_UNORM:
 322         case PIPE_FORMAT_A4R4_UNORM:
 323                 return V_0280A0_COLOR_4_4;
 324
 325         /* 8-bit buffers. */
 326         case PIPE_FORMAT_A8_UNORM:
 327         case PIPE_FORMAT_A8_SNORM:
 328         case PIPE_FORMAT_A8_UINT:
 329         case PIPE_FORMAT_A8_SINT:
 330         case PIPE_FORMAT_I8_UNORM:
 331         case PIPE_FORMAT_I8_SNORM:
 332         case PIPE_FORMAT_I8_UINT:
 333         case PIPE_FORMAT_I8_SINT:
 334         case PIPE_FORMAT_L8_UNORM:
 335         case PIPE_FORMAT_L8_SNORM:
 336         case PIPE_FORMAT_L8_UINT:
 337         case PIPE_FORMAT_L8_SINT:
 338         case PIPE_FORMAT_L8_SRGB:
 339         case PIPE_FORMAT_R8_UNORM:
 340         case PIPE_FORMAT_R8_SNORM:
 341         case PIPE_FORMAT_R8_UINT:
 342         case PIPE_FORMAT_R8_SINT:
 343                 return V_0280A0_COLOR_8;
 344
 345         /* 16-bit buffers. */
 346         case PIPE_FORMAT_B5G6R5_UNORM:
 347                 return V_0280A0_COLOR_5_6_5;
 348
 349         case PIPE_FORMAT_B5G5R5A1_UNORM:
 350         case PIPE_FORMAT_B5G5R5X1_UNORM:
 351                 return V_0280A0_COLOR_1_5_5_5;
 352
 353         case PIPE_FORMAT_B4G4R4A4_UNORM:
 354         case PIPE_FORMAT_B4G4R4X4_UNORM:
 355                 return V_0280A0_COLOR_4_4_4_4;
 356
 357         case PIPE_FORMAT_Z16_UNORM:
 358                 return V_0280A0_COLOR_16;
 359
 360         case PIPE_FORMAT_L8A8_UNORM:
 361         case PIPE_FORMAT_L8A8_SNORM:
 362         case PIPE_FORMAT_L8A8_UINT:
 363         case PIPE_FORMAT_L8A8_SINT:
 364         case PIPE_FORMAT_L8A8_SRGB:
 365         case PIPE_FORMAT_R8G8_UNORM:
 366         case PIPE_FORMAT_R8G8_SNORM:
 367         case PIPE_FORMAT_R8G8_UINT:
 368         case PIPE_FORMAT_R8G8_SINT:
 369                 return V_0280A0_COLOR_8_8;
 370
 371         case PIPE_FORMAT_R16_UNORM:
 372         case PIPE_FORMAT_R16_SNORM:
 373         case PIPE_FORMAT_R16_UINT:
 374         case PIPE_FORMAT_R16_SINT:
 375         case PIPE_FORMAT_A16_UNORM:
 376         case PIPE_FORMAT_A16_SNORM:
 377         case PIPE_FORMAT_A16_UINT:
 378         case PIPE_FORMAT_A16_SINT:
 379         case PIPE_FORMAT_L16_UNORM:
 380         case PIPE_FORMAT_L16_SNORM:
 381         case PIPE_FORMAT_L16_UINT:
 382         case PIPE_FORMAT_L16_SINT:
 383         case PIPE_FORMAT_I16_UNORM:
 384         case PIPE_FORMAT_I16_SNORM:
 385         case PIPE_FORMAT_I16_UINT:
 386         case PIPE_FORMAT_I16_SINT:
 387                 return V_0280A0_COLOR_16;
 388
 389         case PIPE_FORMAT_R16_FLOAT:
 390         case PIPE_FORMAT_A16_FLOAT:
 391         case PIPE_FORMAT_L16_FLOAT:
 392         case PIPE_FORMAT_I16_FLOAT:
 393                 return V_0280A0_COLOR_16_FLOAT;
 394
 395         /* 32-bit buffers. */
 396         case PIPE_FORMAT_A8B8G8R8_SRGB:
 397         case PIPE_FORMAT_A8B8G8R8_UNORM:
 398         case PIPE_FORMAT_A8R8G8B8_UNORM:
 399         case PIPE_FORMAT_B8G8R8A8_SRGB:
 400         case PIPE_FORMAT_B8G8R8A8_UNORM:
 401         case PIPE_FORMAT_B8G8R8X8_UNORM:
 402         case PIPE_FORMAT_R8G8B8A8_SNORM:
 403         case PIPE_FORMAT_R8G8B8A8_UNORM:
 404         case PIPE_FORMAT_R8G8B8X8_UNORM:
 405         case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
 406         case PIPE_FORMAT_X8B8G8R8_UNORM:
 407         case PIPE_FORMAT_X8R8G8B8_UNORM:
 408         case PIPE_FORMAT_R8G8B8_UNORM:
 409         case PIPE_FORMAT_R8G8B8A8_SINT:
 410         case PIPE_FORMAT_R8G8B8A8_UINT:
 411                 return V_0280A0_COLOR_8_8_8_8;
 412
 413         case PIPE_FORMAT_R10G10B10A2_UNORM:
 414         case PIPE_FORMAT_R10G10B10X2_SNORM:
 415         case PIPE_FORMAT_B10G10R10A2_UNORM:
 416         case PIPE_FORMAT_B10G10R10A2_UINT:
 417         case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
 418                 return V_0280A0_COLOR_2_10_10_10;
 419
 420         case PIPE_FORMAT_Z24X8_UNORM:
 421         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 422                 return V_0280A0_COLOR_8_24;
 423
 424         case PIPE_FORMAT_X8Z24_UNORM:
 425         case PIPE_FORMAT_S8_UINT_Z24_UNORM:
 426                 return V_0280A0_COLOR_24_8;
 427
 428         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 429                 return V_0280A0_COLOR_X24_8_32_FLOAT;
 430
 431         case PIPE_FORMAT_R32_UINT:
 432         case PIPE_FORMAT_R32_SINT:
 433         case PIPE_FORMAT_A32_UINT:
 434         case PIPE_FORMAT_A32_SINT:
 435         case PIPE_FORMAT_L32_UINT:
 436         case PIPE_FORMAT_L32_SINT:
 437         case PIPE_FORMAT_I32_UINT:
 438         case PIPE_FORMAT_I32_SINT:
 439                 return V_0280A0_COLOR_32;
 440
 441         case PIPE_FORMAT_R32_FLOAT:
 442         case PIPE_FORMAT_A32_FLOAT:
 443         case PIPE_FORMAT_L32_FLOAT:
 444         case PIPE_FORMAT_I32_FLOAT:
 445         case PIPE_FORMAT_Z32_FLOAT:
 446                 return V_0280A0_COLOR_32_FLOAT;
 447
 448         case PIPE_FORMAT_R16G16_FLOAT:
 449         case PIPE_FORMAT_L16A16_FLOAT:
 450                 return V_0280A0_COLOR_16_16_FLOAT;
 451
 452         case PIPE_FORMAT_R16G16_UNORM:
 453         case PIPE_FORMAT_R16G16_SNORM:
 454         case PIPE_FORMAT_R16G16_UINT:
 455         case PIPE_FORMAT_R16G16_SINT:
 456         case PIPE_FORMAT_L16A16_UNORM:
 457         case PIPE_FORMAT_L16A16_SNORM:
 458         case PIPE_FORMAT_L16A16_UINT:
 459         case PIPE_FORMAT_L16A16_SINT:
 460                 return V_0280A0_COLOR_16_16;
 461
 462         case PIPE_FORMAT_R11G11B10_FLOAT:
 463                 return V_0280A0_COLOR_10_11_11_FLOAT;
 464
 465         /* 64-bit buffers. */
 466         case PIPE_FORMAT_R16G16B16A16_UINT:
 467         case PIPE_FORMAT_R16G16B16A16_SINT:
 468         case PIPE_FORMAT_R16G16B16A16_UNORM:
 469         case PIPE_FORMAT_R16G16B16A16_SNORM:
 470                 return V_0280A0_COLOR_16_16_16_16;
 471
 472         case PIPE_FORMAT_R16G16B16_FLOAT:
 473         case PIPE_FORMAT_R16G16B16A16_FLOAT:
 474                 return V_0280A0_COLOR_16_16_16_16_FLOAT;
 475
 476         case PIPE_FORMAT_R32G32_FLOAT:
 477         case PIPE_FORMAT_L32A32_FLOAT:
 478                 return V_0280A0_COLOR_32_32_FLOAT;
 479
 480         case PIPE_FORMAT_R32G32_SINT:
 481         case PIPE_FORMAT_R32G32_UINT:
 482         case PIPE_FORMAT_L32A32_UINT:
 483         case PIPE_FORMAT_L32A32_SINT:
 484                 return V_0280A0_COLOR_32_32;
 485
 486         /* 96-bit buffers. */
 487         case PIPE_FORMAT_R32G32B32_FLOAT:
 488                 return V_0280A0_COLOR_32_32_32_FLOAT;
 489
 490         /* 128-bit buffers. */
 491         case PIPE_FORMAT_R32G32B32A32_FLOAT:
 492                 return V_0280A0_COLOR_32_32_32_32_FLOAT;
 493         case PIPE_FORMAT_R32G32B32A32_SNORM:
 494         case PIPE_FORMAT_R32G32B32A32_UNORM:
 495         case PIPE_FORMAT_R32G32B32A32_SINT:
 496         case PIPE_FORMAT_R32G32B32A32_UINT:
 497                 return V_0280A0_COLOR_32_32_32_32;
 498
 499         /* YUV buffers. */
 500         case PIPE_FORMAT_UYVY:
 501         case PIPE_FORMAT_YUYV:
 502         default:
 503                 return ~0U; /* Unsupported. */
 504         }
 505 }
 506
 507 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
 508 {
 509         if (R600_BIG_ENDIAN) {
 510                 switch(colorformat) {
 511                 case V_0280A0_COLOR_4_4:
 512                         return ENDIAN_NONE;
 513
 514                 /* 8-bit buffers. */
 515                 case V_0280A0_COLOR_8:
 516                         return ENDIAN_NONE;
 517
 518                 /* 16-bit buffers. */
 519                 case V_0280A0_COLOR_5_6_5:
 520                 case V_0280A0_COLOR_1_5_5_5:
 521                 case V_0280A0_COLOR_4_4_4_4:
 522                 case V_0280A0_COLOR_16:
 523                 case V_0280A0_COLOR_8_8:
 524                         return ENDIAN_8IN16;
 525
 526                 /* 32-bit buffers. */
 527                 case V_0280A0_COLOR_8_8_8_8:
 528                 case V_0280A0_COLOR_2_10_10_10:
 529                 case V_0280A0_COLOR_8_24:
 530                 case V_0280A0_COLOR_24_8:
 531                 case V_0280A0_COLOR_32_FLOAT:
 532                 case V_0280A0_COLOR_16_16_FLOAT:
 533                 case V_0280A0_COLOR_16_16:
 534                         return ENDIAN_8IN32;
 535
 536                 /* 64-bit buffers. */
 537                 case V_0280A0_COLOR_16_16_16_16:
 538                 case V_0280A0_COLOR_16_16_16_16_FLOAT:
 539                         return ENDIAN_8IN16;
 540
 541                 case V_0280A0_COLOR_32_32_FLOAT:
 542                 case V_0280A0_COLOR_32_32:
 543                 case V_0280A0_COLOR_X24_8_32_FLOAT:
 544                         return ENDIAN_8IN32;
 545
 546                 /* 128-bit buffers. */
 547                 case V_0280A0_COLOR_32_32_32_FLOAT:
 548                 case V_0280A0_COLOR_32_32_32_32_FLOAT:
 549                 case V_0280A0_COLOR_32_32_32_32:
 550                         return ENDIAN_8IN32;
 551                 default:
 552                         return ENDIAN_NONE; /* Unsupported. */
 553                 }
 554         } else {
 555                 return ENDIAN_NONE;
 556         }
 557 }
 558
 559 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
 560 {
 561         return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
 562 }
 563
 564 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
 565 {
 566         return r600_translate_colorformat(format) != ~0U &&
 567                r600_translate_colorswap(format) != ~0U;
 568 }
 569
 570 static bool r600_is_zs_format_supported(enum pipe_format format)
 571 {
 572         return r600_translate_dbformat(format) != ~0U;
 573 }
 574
 575 boolean r600_is_format_supported(struct pipe_screen *screen,
 576                                  enum pipe_format format,
 577                                  enum pipe_texture_target target,
 578                                  unsigned sample_count,
 579                                  unsigned usage)
 580 {
 581         unsigned retval = 0;
 582
 583         if (target >= PIPE_MAX_TEXTURE_TYPES) {
 584                 R600_ERR("r600: unsupported texture type %d\n", target);
 585                 return FALSE;
 586         }
 587
 588         if (!util_format_is_supported(format, usage))
 589                 return FALSE;
 590
 591         /* Multisample */
 592         if (sample_count > 1)
 593                 return FALSE;
 594
 595         if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
 596             r600_is_sampler_format_supported(screen, format)) {
 597                 retval |= PIPE_BIND_SAMPLER_VIEW;
 598         }
 599
 600         if ((usage & (PIPE_BIND_RENDER_TARGET |
 601                       PIPE_BIND_DISPLAY_TARGET |
 602                       PIPE_BIND_SCANOUT |
 603                       PIPE_BIND_SHARED)) &&
 604             r600_is_colorbuffer_format_supported(format)) {
 605                 retval |= usage &
 606                           (PIPE_BIND_RENDER_TARGET |
 607                            PIPE_BIND_DISPLAY_TARGET |
 608                            PIPE_BIND_SCANOUT |
 609                            PIPE_BIND_SHARED);
 610         }
 611
 612         if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
 613             r600_is_zs_format_supported(format)) {
 614                 retval |= PIPE_BIND_DEPTH_STENCIL;
 615         }
 616
 617         if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
 618             r600_is_vertex_format_supported(format)) {
 619                 retval |= PIPE_BIND_VERTEX_BUFFER;
 620         }
 621
 622         if (usage & PIPE_BIND_TRANSFER_READ)
 623                 retval |= PIPE_BIND_TRANSFER_READ;
 624         if (usage & PIPE_BIND_TRANSFER_WRITE)
 625                 retval |= PIPE_BIND_TRANSFER_WRITE;
 626
 627         return retval == usage;
 628 }
 629
 630 void r600_polygon_offset_update(struct r600_context *rctx)
 631 {
 632         struct r600_pipe_state state;
 633
 634         state.id = R600_PIPE_STATE_POLYGON_OFFSET;
 635         state.nregs = 0;
 636         if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
 637                 float offset_units = rctx->rasterizer->offset_units;
 638                 unsigned offset_db_fmt_cntl = 0, depth;
 639
 640                 switch (rctx->framebuffer.zsbuf->format) {
 641                 case PIPE_FORMAT_Z24X8_UNORM:
 642                 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 643                         depth = -24;
 644                         offset_units *= 2.0f;
 645                         break;
 646                 case PIPE_FORMAT_Z32_FLOAT:
 647                 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 648                         depth = -23;
 649                         offset_units *= 1.0f;
 650                         offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
 651                         break;
 652                 case PIPE_FORMAT_Z16_UNORM:
 653                         depth = -16;
 654                         offset_units *= 4.0f;
 655                         break;
 656                 default:
 657                         return;
 658                 }
 659                 /* XXX some of those reg can be computed with cso */
 660                 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
 661                 r600_pipe_state_add_reg(&state,
 662                                 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
 663                                 fui(rctx->rasterizer->offset_scale));
 664                 r600_pipe_state_add_reg(&state,
 665                                 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
 666                                 fui(offset_units));
 667                 r600_pipe_state_add_reg(&state,
 668                                 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
 669                                 fui(rctx->rasterizer->offset_scale));
 670                 r600_pipe_state_add_reg(&state,
 671                                 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
 672                                 fui(offset_units));
 673                 r600_pipe_state_add_reg(&state,
 674                                 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
 675                                 offset_db_fmt_cntl);
 676                 r600_context_pipe_state_set(rctx, &state);
 677         }
 678 }
 679
 680 static void *r600_create_blend_state(struct pipe_context *ctx,
 681                                         const struct pipe_blend_state *state)
 682 {
 683         struct r600_context *rctx = (struct r600_context *)ctx;
 684         struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
 685         struct r600_pipe_state *rstate;
 686         uint32_t color_control = 0, target_mask;
 687
 688         if (blend == NULL) {
 689                 return NULL;
 690         }
 691         rstate = &blend->rstate;
 692
 693         rstate->id = R600_PIPE_STATE_BLEND;
 694
 695         target_mask = 0;
 696
 697         /* R600 does not support per-MRT blends */
 698         if (rctx->family > CHIP_R600)
 699                 color_control |= S_028808_PER_MRT_BLEND(1);
 700         if (state->logicop_enable) {
 701                 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
 702         } else {
 703                 color_control |= (0xcc << 16);
 704         }
 705         /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
 706         if (state->independent_blend_enable) {
 707                 for (int i = 0; i < 8; i++) {
 708                         if (state->rt[i].blend_enable) {
 709                                 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
 710                         }
 711                         target_mask |= (state->rt[i].colormask << (4 * i));
 712                 }
 713         } else {
 714                 for (int i = 0; i < 8; i++) {
 715                         if (state->rt[0].blend_enable) {
 716                                 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
 717                         }
 718                         target_mask |= (state->rt[0].colormask << (4 * i));
 719                 }
 720         }
 721         blend->cb_target_mask = target_mask;
 722         blend->cb_color_control = color_control;
 723         /* only MRT0 has dual src blend */
 724         blend->dual_src_blend = util_blend_state_is_dual(state, 0);
 725         for (int i = 0; i < 8; i++) {
 726                 /* state->rt entries > 0 only written if independent blending */
 727                 const int j = state->independent_blend_enable ? i : 0;
 728
 729                 unsigned eqRGB = state->rt[j].rgb_func;
 730                 unsigned srcRGB = state->rt[j].rgb_src_factor;
 731                 unsigned dstRGB = state->rt[j].rgb_dst_factor;
 732
 733                 unsigned eqA = state->rt[j].alpha_func;
 734                 unsigned srcA = state->rt[j].alpha_src_factor;
 735                 unsigned dstA = state->rt[j].alpha_dst_factor;
 736                 uint32_t bc = 0;
 737
 738                 if (!state->rt[j].blend_enable)
 739                         continue;
 740
 741                 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
 742                 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
 743                 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
 744
 745                 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
 746                         bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
 747                         bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
 748                         bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
 749                         bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
 750                 }
 751
 752                 /* R600 does not support per-MRT blends */
 753                 if (rctx->family > CHIP_R600)
 754                         r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc);
 755                 if (i == 0)
 756                         r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc);
 757         }
 758         return rstate;
 759 }
 760
 761 static void *r600_create_dsa_state(struct pipe_context *ctx,
 762                                    const struct pipe_depth_stencil_alpha_state *state)
 763 {
 764         struct r600_context *rctx = (struct r600_context *)ctx;
 765         struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
 766         unsigned db_depth_control, alpha_test_control, alpha_ref;
 767         struct r600_pipe_state *rstate;
 768
 769         if (dsa == NULL) {
 770                 return NULL;
 771         }
 772
 773         dsa->valuemask[0] = state->stencil[0].valuemask;
 774         dsa->valuemask[1] = state->stencil[1].valuemask;
 775         dsa->writemask[0] = state->stencil[0].writemask;
 776         dsa->writemask[1] = state->stencil[1].writemask;
 777
 778         rstate = &dsa->rstate;
 779
 780         rstate->id = R600_PIPE_STATE_DSA;
 781         db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
 782                 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
 783                 S_028800_ZFUNC(state->depth.func);
 784
 785         /* stencil */
 786         if (state->stencil[0].enabled) {
 787                 db_depth_control |= S_028800_STENCIL_ENABLE(1);
 788                 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
 789                 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
 790                 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
 791                 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
 792
 793                 if (state->stencil[1].enabled) {
 794                         db_depth_control |= S_028800_BACKFACE_ENABLE(1);
 795                         db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
 796                         db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
 797                         db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
 798                         db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
 799                 }
 800         }
 801
 802         /* alpha */
 803         alpha_test_control = 0;
 804         alpha_ref = 0;
 805         if (state->alpha.enabled) {
 806                 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
 807                 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
 808                 alpha_ref = fui(state->alpha.ref_value);
 809         }
 810         dsa->sx_alpha_test_control = alpha_test_control & 0xff;
 811         dsa->alpha_ref = alpha_ref;
 812
 813         r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
 814         return rstate;
 815 }
 816
 817 static void *r600_create_rs_state(struct pipe_context *ctx,
 818                                   const struct pipe_rasterizer_state *state)
 819 {
 820         struct r600_context *rctx = (struct r600_context *)ctx;
 821         struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
 822         struct r600_pipe_state *rstate;
 823         unsigned tmp;
 824         unsigned prov_vtx = 1, polygon_dual_mode;
 825         unsigned sc_mode_cntl;
 826         float psize_min, psize_max;
 827
 828         if (rs == NULL) {
 829                 return NULL;
 830         }
 831
 832         polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
 833                                 state->fill_back != PIPE_POLYGON_MODE_FILL);
 834
 835         if (state->flatshade_first)
 836                 prov_vtx = 0;
 837
 838         rstate = &rs->rstate;
 839         rs->flatshade = state->flatshade;
 840         rs->sprite_coord_enable = state->sprite_coord_enable;
 841         rs->two_side = state->light_twoside;
 842         rs->clip_plane_enable = state->clip_plane_enable;
 843         rs->pa_sc_line_stipple = state->line_stipple_enable ?
 844                                 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
 845                                 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
 846         rs->pa_cl_clip_cntl =
 847                 S_028810_PS_UCP_MODE(3) |
 848                 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
 849                 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
 850                 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
 851
 852         /* offset */
 853         rs->offset_units = state->offset_units;
 854         rs->offset_scale = state->offset_scale * 12.0f;
 855
 856         rstate->id = R600_PIPE_STATE_RASTERIZER;
 857         tmp = S_0286D4_FLAT_SHADE_ENA(1);
 858         if (state->sprite_coord_enable) {
 859                 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
 860                         S_0286D4_PNT_SPRITE_OVRD_X(2) |
 861                         S_0286D4_PNT_SPRITE_OVRD_Y(3) |
 862                         S_0286D4_PNT_SPRITE_OVRD_Z(0) |
 863                         S_0286D4_PNT_SPRITE_OVRD_W(1);
 864                 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
 865                         tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
 866                 }
 867         }
 868         r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
 869
 870         /* point size 12.4 fixed point */
 871         tmp = r600_pack_float_12p4(state->point_size/2);
 872         r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
 873
 874         if (state->point_size_per_vertex) {
 875                 psize_min = util_get_min_point_size(state);
 876                 psize_max = 8192;
 877         } else {
 878                 /* Force the point size to be as if the vertex output was disabled. */
 879                 psize_min = state->point_size;
 880                 psize_max = state->point_size;
 881         }
 882         /* Divide by two, because 0.5 = 1 pixel. */
 883         r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
 884                                 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
 885                                 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
 886
 887         tmp = r600_pack_float_12p4(state->line_width/2);
 888         r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
 889
 890         if (rctx->chip_class >= R700) {
 891                 sc_mode_cntl =
 892                         S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
 893                         S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
 894                         S_028A4C_R700_ZMM_LINE_OFFSET(1) |
 895                         S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor);
 896         } else {
 897                 sc_mode_cntl =
 898                         S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
 899                         S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
 900                 rs->scissor_enable = state->scissor;
 901         }
 902         sc_mode_cntl |= S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable);
 903
 904         r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
 905
 906         r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
 907                                 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules));
 908
 909         r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
 910         r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
 911                                 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
 912                                 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
 913                                 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
 914                                 S_028814_FACE(!state->front_ccw) |
 915                                 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
 916                                 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
 917                                 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
 918                                 S_028814_POLY_MODE(polygon_dual_mode) |
 919                                 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
 920                                 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
 921         r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
 922         return rstate;
 923 }
 924
 925 static void *r600_create_sampler_state(struct pipe_context *ctx,
 926                                         const struct pipe_sampler_state *state)
 927 {
 928         struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
 929         struct r600_pipe_state *rstate;
 930         union util_color uc;
 931         unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
 932
 933         if (ss == NULL) {
 934                 return NULL;
 935         }
 936
 937         ss->seamless_cube_map = state->seamless_cube_map;
 938         rstate = &ss->rstate;
 939         rstate->id = R600_PIPE_STATE_SAMPLER;
 940         util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
 941         r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
 942                                         S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
 943                                         S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
 944                                         S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
 945                                         S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
 946                                         S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
 947                                         S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
 948                                         S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
 949                                         S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
 950                                         S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), NULL, 0);
 951         r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
 952                                         S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
 953                                         S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
 954                                         S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), NULL, 0);
 955         r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), NULL, 0);
 956         if (uc.ui) {
 957                 r600_pipe_state_add_reg_noblock(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), NULL, 0);
 958                 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), NULL, 0);
 959                 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), NULL, 0);
 960                 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), NULL, 0);
 961         }
 962         return rstate;
 963 }
 964
 965 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
 966                                                         struct pipe_resource *texture,
 967                                                         const struct pipe_sampler_view *state)
 968 {
 969         struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
 970         struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
 971         struct r600_pipe_resource_state *rstate;
 972         struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
 973         unsigned format, endian;
 974         uint32_t word4 = 0, yuv_format = 0, pitch = 0;
 975         unsigned char swizzle[4], array_mode = 0, tile_type = 0;
 976         unsigned width, height, depth, offset_level, last_level;
 977
 978         if (view == NULL)
 979                 return NULL;
 980         rstate = &view->state;
 981
 982         /* initialize base object */
 983         view->base = *state;
 984         view->base.texture = NULL;
 985         pipe_reference(NULL, &texture->reference);
 986         view->base.texture = texture;
 987         view->base.reference.count = 1;
 988         view->base.context = ctx;
 989
 990         swizzle[0] = state->swizzle_r;
 991         swizzle[1] = state->swizzle_g;
 992         swizzle[2] = state->swizzle_b;
 993         swizzle[3] = state->swizzle_a;
 994
 995         format = r600_translate_texformat(ctx->screen, state->format,
 996                                           swizzle,
 997                                           &word4, &yuv_format);
 998         assert(format != ~0);
 999         if (format == ~0) {
1000                 FREE(view);
1001                 return NULL;
1002         }
1003
1004         if (tmp->is_depth && !tmp->is_flushing_texture) {
1005                 r600_init_flushed_depth_texture(ctx, texture);
1006                 tmp = tmp->flushed_depth_texture;
1007                 if (!tmp) {
1008                         FREE(view);
1009                         return NULL;
1010                 }
1011         }
1012
1013         endian = r600_colorformat_endian_swap(format);
1014
1015         offset_level = state->u.tex.first_level;
1016         last_level = state->u.tex.last_level - offset_level;
1017         if (!rscreen->use_surface_alloc) {
1018                 width = u_minify(texture->width0, offset_level);
1019                 height = u_minify(texture->height0, offset_level);
1020                 depth = u_minify(texture->depth0, offset_level);
1021
1022                 pitch = align(tmp->pitch_in_blocks[offset_level] *
1023                                 util_format_get_blockwidth(state->format), 8);
1024                 array_mode = tmp->array_mode[offset_level];
1025                 tile_type = tmp->tile_type;
1026
1027                 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1028                         height = 1;
1029                         depth = texture->array_size;
1030                 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1031                         depth = texture->array_size;
1032                 }
1033
1034                 rstate->bo[0] = &tmp->resource;
1035                 rstate->bo[1] = &tmp->resource;
1036                 rstate->bo_usage[0] = RADEON_USAGE_READ;
1037                 rstate->bo_usage[1] = RADEON_USAGE_READ;
1038
1039                 rstate->val[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
1040                                 S_038000_TILE_MODE(array_mode) |
1041                                 S_038000_TILE_TYPE(tile_type) |
1042                                 S_038000_PITCH((pitch / 8) - 1) |
1043                                 S_038000_TEX_WIDTH(width - 1));
1044                 rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) |
1045                                 S_038004_TEX_DEPTH(depth - 1) |
1046                                 S_038004_DATA_FORMAT(format));
1047                 rstate->val[2] = tmp->offset[offset_level] >> 8;
1048                 rstate->val[3] = tmp->offset[offset_level+1] >> 8;
1049                 rstate->val[4] = (word4 |
1050                                 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1051                                 S_038010_REQUEST_SIZE(1) |
1052                                 S_038010_ENDIAN_SWAP(endian) |
1053                                 S_038010_BASE_LEVEL(0));
1054                 rstate->val[5] = (S_038014_LAST_LEVEL(last_level) |
1055                                 S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1056                                 S_038014_LAST_ARRAY(state->u.tex.last_layer));
1057                 rstate->val[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1058                                 S_038018_MAX_ANISO(4 /* max 16 samples */));
1059         } else {
1060                 width = tmp->surface.level[offset_level].npix_x;
1061                 height = tmp->surface.level[offset_level].npix_y;
1062                 depth = tmp->surface.level[offset_level].npix_z;
1063                 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
1064                 tile_type = tmp->tile_type;
1065
1066                 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1067                         height = 1;
1068                         depth = texture->array_size;
1069                 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1070                         depth = texture->array_size;
1071                 }
1072                 switch (tmp->surface.level[offset_level].mode) {
1073                 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1074                         array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
1075                         break;
1076                 case RADEON_SURF_MODE_1D:
1077                         array_mode = V_038000_ARRAY_1D_TILED_THIN1;
1078                         break;
1079                 case RADEON_SURF_MODE_2D:
1080                         array_mode = V_038000_ARRAY_2D_TILED_THIN1;
1081                         break;
1082                 case RADEON_SURF_MODE_LINEAR:
1083                 default:
1084                         array_mode = V_038000_ARRAY_LINEAR_GENERAL;
1085                         break;
1086                 }
1087
1088                 rstate->bo[0] = &tmp->resource;
1089                 rstate->bo[1] = &tmp->resource;
1090                 rstate->bo_usage[0] = RADEON_USAGE_READ;
1091                 rstate->bo_usage[1] = RADEON_USAGE_READ;
1092
1093                 rstate->val[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
1094                                 S_038000_TILE_MODE(array_mode) |
1095                                 S_038000_TILE_TYPE(tile_type) |
1096                                 S_038000_PITCH((pitch / 8) - 1) |
1097                                 S_038000_TEX_WIDTH(width - 1));
1098                 rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) |
1099                                 S_038004_TEX_DEPTH(depth - 1) |
1100                                 S_038004_DATA_FORMAT(format));
1101                 rstate->val[2] = tmp->surface.level[offset_level].offset >> 8;
1102                 if (offset_level >= tmp->surface.last_level) {
1103                         rstate->val[3] = tmp->surface.level[offset_level].offset >> 8;
1104                 } else {
1105                         rstate->val[3] = tmp->surface.level[offset_level + 1].offset >> 8;
1106                 }
1107                 rstate->val[4] = (word4 |
1108                                 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1109                                 S_038010_REQUEST_SIZE(1) |
1110                                 S_038010_ENDIAN_SWAP(endian) |
1111                                 S_038010_BASE_LEVEL(0));
1112                 rstate->val[5] = (S_038014_LAST_LEVEL(last_level) |
1113                                 S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1114                                 S_038014_LAST_ARRAY(state->u.tex.last_layer));
1115                 rstate->val[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1116                                 S_038018_MAX_ANISO(4 /* max 16 samples */));
1117         }
1118         return &view->base;
1119 }
1120
1121 static void r600_set_sampler_views(struct r600_context *rctx,
1122                                    struct r600_textures_info *dst,
1123                                    unsigned count,
1124                                    struct pipe_sampler_view **views,
1125                                    void (*set_resource)(struct r600_context*, struct r600_pipe_resource_state*, unsigned))
1126 {
1127         struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
1128         unsigned i;
1129
1130         if (count)
1131                 r600_inval_texture_cache(rctx);
1132
1133         for (i = 0; i < count; i++) {
1134                 if (rviews[i]) {
1135                         if (((struct r600_resource_texture *)rviews[i]->base.texture)->is_depth)
1136                                 rctx->have_depth_texture = true;
1137
1138                         /* Changing from array to non-arrays textures and vice versa requires updating TEX_ARRAY_OVERRIDE. */
1139                         if ((rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
1140                              rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i])
1141                                 dst->samplers_dirty = true;
1142
1143                         set_resource(rctx, &rviews[i]->state, i + R600_MAX_CONST_BUFFERS);
1144                 } else {
1145                         set_resource(rctx, NULL, i + R600_MAX_CONST_BUFFERS);
1146                 }
1147
1148                 pipe_sampler_view_reference(
1149                         (struct pipe_sampler_view **)&dst->views[i],
1150                         views[i]);
1151         }
1152
1153         for (i = count; i < dst->n_views; i++) {
1154                 if (dst->views[i]) {
1155                         set_resource(rctx, NULL, i + R600_MAX_CONST_BUFFERS);
1156                         pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views[i], NULL);
1157                 }
1158         }
1159
1160         dst->n_views = count;
1161 }
1162
1163 static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
1164                                       struct pipe_sampler_view **views)
1165 {
1166         struct r600_context *rctx = (struct r600_context *)ctx;
1167         r600_set_sampler_views(rctx, &rctx->vs_samplers, count, views,
1168                                r600_context_pipe_state_set_vs_resource);
1169 }
1170
1171 static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
1172                                       struct pipe_sampler_view **views)
1173 {
1174         struct r600_context *rctx = (struct r600_context *)ctx;
1175         r600_set_sampler_views(rctx, &rctx->ps_samplers, count, views,
1176                                r600_context_pipe_state_set_ps_resource);
1177 }
1178
1179 static void r600_set_seamless_cubemap(struct r600_context *rctx, boolean enable)
1180 {
1181         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1182         if (rstate == NULL)
1183                 return;
1184
1185         rstate->id = R600_PIPE_STATE_SEAMLESS_CUBEMAP;
1186         r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
1187                                 (enable ? 0 : S_009508_DISABLE_CUBE_WRAP(1)) |
1188                                 S_009508_DISABLE_CUBE_ANISO(1) |
1189                                 S_009508_SYNC_GRADIENT(1) |
1190                                 S_009508_SYNC_WALKER(1) |
1191                                 S_009508_SYNC_ALIGNER(1));
1192
1193         free(rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP]);
1194         rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP] = rstate;
1195         r600_context_pipe_state_set(rctx, rstate);
1196 }
1197
1198 static void r600_bind_samplers(struct r600_context *rctx,
1199                                struct r600_textures_info *dst,
1200                                unsigned count, void **states)
1201 {
1202         memcpy(dst->samplers, states, sizeof(void*) * count);
1203         dst->n_samplers = count;
1204         dst->samplers_dirty = true;
1205 }
1206
1207 static void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states)
1208 {
1209         struct r600_context *rctx = (struct r600_context *)ctx;
1210         r600_bind_samplers(rctx, &rctx->vs_samplers, count, states);
1211 }
1212
1213 static void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states)
1214 {
1215         struct r600_context *rctx = (struct r600_context *)ctx;
1216         r600_bind_samplers(rctx, &rctx->ps_samplers, count, states);
1217 }
1218
1219 static void r600_update_samplers(struct r600_context *rctx,
1220                                  struct r600_textures_info *tex,
1221                                  void (*set_sampler)(struct r600_context*, struct r600_pipe_state*, unsigned))
1222 {
1223         unsigned i;
1224
1225         if (tex->samplers_dirty) {
1226                 int seamless = -1;
1227                 for (i = 0; i < tex->n_samplers; i++) {
1228                         if (!tex->samplers[i])
1229                                 continue;
1230
1231                         /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1232                          * filtering between layers.
1233                          * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view. */
1234                         if (tex->views[i]) {
1235                                 if (tex->views[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
1236                                     tex->views[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) {
1237                                         tex->samplers[i]->rstate.regs[0].value |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1238                                         tex->is_array_sampler[i] = true;
1239                                 } else {
1240                                         tex->samplers[i]->rstate.regs[0].value &= C_03C000_TEX_ARRAY_OVERRIDE;
1241                                         tex->is_array_sampler[i] = false;
1242                                 }
1243                         }
1244
1245                         set_sampler(rctx, &tex->samplers[i]->rstate, i);
1246
1247                         if (tex->samplers[i])
1248                                 seamless = tex->samplers[i]->seamless_cube_map;
1249                 }
1250
1251                 if (seamless != -1)
1252                         r600_set_seamless_cubemap(rctx, seamless);
1253
1254                 tex->samplers_dirty = false;
1255         }
1256 }
1257
1258 void r600_update_sampler_states(struct r600_context *rctx)
1259 {
1260         r600_update_samplers(rctx, &rctx->vs_samplers,
1261                              r600_context_pipe_state_set_vs_sampler);
1262         r600_update_samplers(rctx, &rctx->ps_samplers,
1263                              r600_context_pipe_state_set_ps_sampler);
1264 }
1265
1266 static void r600_set_clip_state(struct pipe_context *ctx,
1267                                 const struct pipe_clip_state *state)
1268 {
1269         struct r600_context *rctx = (struct r600_context *)ctx;
1270         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1271         struct pipe_constant_buffer cb;
1272
1273         if (rstate == NULL)
1274                 return;
1275
1276         rctx->clip = *state;
1277         rstate->id = R600_PIPE_STATE_CLIP;
1278         for (int i = 0; i < 6; i++) {
1279                 r600_pipe_state_add_reg(rstate,
1280                                         R_028E20_PA_CL_UCP0_X + i * 16,
1281                                         fui(state->ucp[i][0]));
1282                 r600_pipe_state_add_reg(rstate,
1283                                         R_028E24_PA_CL_UCP0_Y + i * 16,
1284                                         fui(state->ucp[i][1]) );
1285                 r600_pipe_state_add_reg(rstate,
1286                                         R_028E28_PA_CL_UCP0_Z + i * 16,
1287                                         fui(state->ucp[i][2]));
1288                 r600_pipe_state_add_reg(rstate,
1289                                         R_028E2C_PA_CL_UCP0_W + i * 16,
1290                                         fui(state->ucp[i][3]));
1291         }
1292
1293         free(rctx->states[R600_PIPE_STATE_CLIP]);
1294         rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1295         r600_context_pipe_state_set(rctx, rstate);
1296
1297         cb.buffer = NULL;
1298         cb.user_buffer = state->ucp;
1299         cb.buffer_offset = 0;
1300         cb.buffer_size = 4*4*8;
1301         r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
1302         pipe_resource_reference(&cb.buffer, NULL);
1303 }
1304
1305 static void r600_set_polygon_stipple(struct pipe_context *ctx,
1306                                          const struct pipe_poly_stipple *state)
1307 {
1308 }
1309
1310 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1311 {
1312 }
1313
1314 void r600_set_scissor_state(struct r600_context *rctx,
1315                             const struct pipe_scissor_state *state)
1316 {
1317         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1318         uint32_t tl, br;
1319
1320         if (rstate == NULL)
1321                 return;
1322
1323         rstate->id = R600_PIPE_STATE_SCISSOR;
1324         tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
1325         br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1326         r600_pipe_state_add_reg(rstate,
1327                                 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1328         r600_pipe_state_add_reg(rstate,
1329                                 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1330
1331         free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1332         rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1333         r600_context_pipe_state_set(rctx, rstate);
1334 }
1335
1336 static void r600_pipe_set_scissor_state(struct pipe_context *ctx,
1337                                         const struct pipe_scissor_state *state)
1338 {
1339         struct r600_context *rctx = (struct r600_context *)ctx;
1340
1341         if (rctx->chip_class == R600) {
1342                 rctx->scissor_state = *state;
1343
1344                 if (!rctx->scissor_enable)
1345                         return;
1346         }
1347
1348         r600_set_scissor_state(rctx, state);
1349 }
1350
1351 static void r600_set_viewport_state(struct pipe_context *ctx,
1352                                         const struct pipe_viewport_state *state)
1353 {
1354         struct r600_context *rctx = (struct r600_context *)ctx;
1355         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1356
1357         if (rstate == NULL)
1358                 return;
1359
1360         rctx->viewport = *state;
1361         rstate->id = R600_PIPE_STATE_VIEWPORT;
1362         r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
1363         r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
1364         r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
1365         r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
1366         r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
1367         r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
1368
1369         free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1370         rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1371         r600_context_pipe_state_set(rctx, rstate);
1372 }
1373
1374 static void r600_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
1375                         const struct pipe_framebuffer_state *state, int cb)
1376 {
1377         struct r600_screen *rscreen = rctx->screen;
1378         struct r600_resource_texture *rtex;
1379         struct r600_surface *surf;
1380         unsigned level = state->cbufs[cb]->u.tex.level;
1381         unsigned pitch, slice;
1382         unsigned color_info;
1383         unsigned format, swap, ntype, endian;
1384         unsigned offset;
1385         const struct util_format_description *desc;
1386         int i;
1387         unsigned blend_bypass = 0, blend_clamp = 1;
1388
1389         surf = (struct r600_surface *)state->cbufs[cb];
1390         rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1391
1392         if (rtex->is_depth)
1393                 rctx->have_depth_fb = TRUE;
1394
1395         if (rtex->is_depth && !rtex->is_flushing_texture) {
1396                 rtex = rtex->flushed_depth_texture;
1397         }
1398
1399         /* XXX quite sure for dx10+ hw don't need any offset hacks */
1400         if (!rscreen->use_surface_alloc) {
1401                 offset = r600_texture_get_offset(rtex,
1402                                                  level, state->cbufs[cb]->u.tex.first_layer);
1403                 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1404                 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64;
1405                 if (slice) {
1406                         slice = slice - 1;
1407                 }
1408                 color_info = S_0280A0_ARRAY_MODE(rtex->array_mode[level]);
1409         } else {
1410                 offset = rtex->surface.level[level].offset;
1411                 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1412                         offset += rtex->surface.level[level].slice_size *
1413                                   state->cbufs[cb]->u.tex.first_layer;
1414                 }
1415                 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1416                 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1417                 if (slice) {
1418                         slice = slice - 1;
1419                 }
1420                 color_info = 0;
1421                 switch (rtex->surface.level[level].mode) {
1422                 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1423                         color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
1424                         break;
1425                 case RADEON_SURF_MODE_1D:
1426                         color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1427                         break;
1428                 case RADEON_SURF_MODE_2D:
1429                         color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1430                         break;
1431                 case RADEON_SURF_MODE_LINEAR:
1432                 default:
1433                         color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
1434                         break;
1435                 }
1436         }
1437         desc = util_format_description(surf->base.format);
1438
1439         for (i = 0; i < 4; i++) {
1440                 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1441                         break;
1442                 }
1443         }
1444
1445         ntype = V_0280A0_NUMBER_UNORM;
1446         if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1447                 ntype = V_0280A0_NUMBER_SRGB;
1448         else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1449                 if (desc->channel[i].normalized)
1450                         ntype = V_0280A0_NUMBER_SNORM;
1451                 else if (desc->channel[i].pure_integer)
1452                         ntype = V_0280A0_NUMBER_SINT;
1453         } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1454                 if (desc->channel[i].normalized)
1455                         ntype = V_0280A0_NUMBER_UNORM;
1456                 else if (desc->channel[i].pure_integer)
1457                         ntype = V_0280A0_NUMBER_UINT;
1458         }
1459
1460         format = r600_translate_colorformat(surf->base.format);
1461         assert(format != ~0);
1462
1463         swap = r600_translate_colorswap(surf->base.format);
1464         assert(swap != ~0);
1465
1466         if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1467                 endian = ENDIAN_NONE;
1468         } else {
1469                 endian = r600_colorformat_endian_swap(format);
1470         }
1471
1472         /* set blend bypass according to docs if SINT/UINT or
1473            8/24 COLOR variants */
1474         if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
1475             format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
1476             format == V_0280A0_COLOR_X24_8_32_FLOAT) {
1477                 blend_clamp = 0;
1478                 blend_bypass = 1;
1479         }
1480
1481         if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT)
1482                 rctx->sx_alpha_test_control |= S_028410_ALPHA_TEST_BYPASS(1);
1483         else
1484                 rctx->sx_alpha_test_control &= C_028410_ALPHA_TEST_BYPASS;
1485
1486         color_info |= S_0280A0_FORMAT(format) |
1487                 S_0280A0_COMP_SWAP(swap) |
1488                 S_0280A0_BLEND_BYPASS(blend_bypass) |
1489                 S_0280A0_BLEND_CLAMP(blend_clamp) |
1490                 S_0280A0_NUMBER_TYPE(ntype) |
1491                 S_0280A0_ENDIAN(endian);
1492
1493         /* EXPORT_NORM is an optimzation that can be enabled for better
1494          * performance in certain cases
1495          */
1496         if (rctx->chip_class == R600) {
1497                 /* EXPORT_NORM can be enabled if:
1498                  * - 11-bit or smaller UNORM/SNORM/SRGB
1499                  * - BLEND_CLAMP is enabled
1500                  * - BLEND_FLOAT32 is disabled
1501                  */
1502                 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1503                     (desc->channel[i].size < 12 &&
1504                      desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1505                      ntype != V_0280A0_NUMBER_UINT &&
1506                      ntype != V_0280A0_NUMBER_SINT) &&
1507                     G_0280A0_BLEND_CLAMP(color_info) &&
1508                     !G_0280A0_BLEND_FLOAT32(color_info)) {
1509                         color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1510                 } else {
1511                         rctx->export_16bpc = false;
1512                 }
1513         } else {
1514                 /* EXPORT_NORM can be enabled if:
1515                  * - 11-bit or smaller UNORM/SNORM/SRGB
1516                  * - 16-bit or smaller FLOAT
1517                  */
1518                 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1519                     ((desc->channel[i].size < 12 &&
1520                       desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1521                       ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1522                     (desc->channel[i].size < 17 &&
1523                      desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1524                         color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1525                 } else {
1526                         rctx->export_16bpc = false;
1527                 }
1528         }
1529
1530         /* for possible dual-src MRT write color info 1 */
1531         if (cb == 0 && rctx->framebuffer.nr_cbufs == 1) {
1532                 r600_pipe_state_add_reg_bo(rstate,
1533                                 R_0280A0_CB_COLOR0_INFO + 1 * 4,
1534                                 color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1535         }
1536
1537         r600_pipe_state_add_reg_bo(rstate,
1538                                 R_028040_CB_COLOR0_BASE + cb * 4,
1539                                 offset >> 8, &rtex->resource, RADEON_USAGE_READWRITE);
1540         r600_pipe_state_add_reg_bo(rstate,
1541                                 R_0280A0_CB_COLOR0_INFO + cb * 4,
1542                                 color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1543         r600_pipe_state_add_reg(rstate,
1544                                 R_028060_CB_COLOR0_SIZE + cb * 4,
1545                                 S_028060_PITCH_TILE_MAX(pitch) |
1546                                 S_028060_SLICE_TILE_MAX(slice));
1547         if (!rscreen->use_surface_alloc) {
1548                 r600_pipe_state_add_reg(rstate,
1549                                         R_028080_CB_COLOR0_VIEW + cb * 4,
1550                                         0x00000000);
1551         } else {
1552                 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1553                         r600_pipe_state_add_reg(rstate,
1554                                                 R_028080_CB_COLOR0_VIEW + cb * 4,
1555                                                 0x00000000);
1556                 } else {
1557                         r600_pipe_state_add_reg(rstate,
1558                                                 R_028080_CB_COLOR0_VIEW + cb * 4,
1559                                                 S_028080_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1560                                                 S_028080_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer));
1561                 }
1562         }
1563         r600_pipe_state_add_reg_bo(rstate,
1564                                    R_0280E0_CB_COLOR0_FRAG + cb * 4,
1565                                    0, &rtex->resource, RADEON_USAGE_READWRITE);
1566         r600_pipe_state_add_reg_bo(rstate,
1567                                    R_0280C0_CB_COLOR0_TILE + cb * 4,
1568                                    0, &rtex->resource, RADEON_USAGE_READWRITE);
1569 }
1570
1571 static void r600_db(struct r600_context *rctx, struct r600_pipe_state *rstate,
1572                         const struct pipe_framebuffer_state *state)
1573 {
1574         struct r600_screen *rscreen = rctx->screen;
1575         struct r600_resource_texture *rtex;
1576         struct r600_surface *surf;
1577         unsigned level, pitch, slice, format, offset, array_mode;
1578
1579         if (state->zsbuf == NULL)
1580                 return;
1581
1582         level = state->zsbuf->u.tex.level;
1583
1584         surf = (struct r600_surface *)state->zsbuf;
1585         rtex = (struct r600_resource_texture*)state->zsbuf->texture;
1586
1587         if (!rscreen->use_surface_alloc) {
1588                 /* XXX remove this once tiling is properly supported */
1589                 array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
1590                         V_0280A0_ARRAY_1D_TILED_THIN1;
1591
1592                 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1593                 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
1594                                 level, state->zsbuf->u.tex.first_layer);
1595                 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1596                 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64;
1597                 if (slice) {
1598                         slice = slice - 1;
1599                 }
1600         } else {
1601                 offset = rtex->surface.level[level].offset;
1602                 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1603                 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1604                 if (slice) {
1605                         slice = slice - 1;
1606                 }
1607                 switch (rtex->surface.level[level].mode) {
1608                 case RADEON_SURF_MODE_2D:
1609                         array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1610                         break;
1611                 case RADEON_SURF_MODE_1D:
1612                 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1613                 case RADEON_SURF_MODE_LINEAR:
1614                 default:
1615                         array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1616                         break;
1617                 }
1618         }
1619
1620         format = r600_translate_dbformat(state->zsbuf->format);
1621         assert(format != ~0);
1622
1623         r600_pipe_state_add_reg_bo(rstate, R_02800C_DB_DEPTH_BASE,
1624                                 offset >> 8, &rtex->resource, RADEON_USAGE_READWRITE);
1625         r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
1626                                 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice));
1627         if (!rscreen->use_surface_alloc) {
1628                 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000);
1629         } else {
1630                 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW,
1631                                         S_028004_SLICE_START(state->zsbuf->u.tex.first_layer) |
1632                                         S_028004_SLICE_MAX(state->zsbuf->u.tex.last_layer));
1633         }
1634         r600_pipe_state_add_reg_bo(rstate, R_028010_DB_DEPTH_INFO,
1635                                 S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format),
1636                                 &rtex->resource, RADEON_USAGE_READWRITE);
1637         r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
1638                                 (surf->aligned_height / 8) - 1);
1639 }
1640
1641 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1642                                         const struct pipe_framebuffer_state *state)
1643 {
1644         struct r600_context *rctx = (struct r600_context *)ctx;
1645         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1646         uint32_t tl, br, shader_control;
1647
1648         if (rstate == NULL)
1649                 return;
1650
1651         r600_flush_framebuffer(rctx, false);
1652
1653         /* unreference old buffer and reference new one */
1654         rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1655
1656         util_copy_framebuffer_state(&rctx->framebuffer, state);
1657
1658         /* build states */
1659         rctx->have_depth_fb = 0;
1660         rctx->export_16bpc = true;
1661         rctx->nr_cbufs = state->nr_cbufs;
1662
1663         for (int i = 0; i < state->nr_cbufs; i++) {
1664                 r600_cb(rctx, rstate, state, i);
1665         }
1666         if (state->zsbuf) {
1667                 r600_db(rctx, rstate, state);
1668         }
1669
1670         shader_control = 0;
1671         rctx->fb_cb_shader_mask = 0;
1672         for (int i = 0; i < state->nr_cbufs; i++) {
1673                 shader_control |= 1 << i;
1674                 rctx->fb_cb_shader_mask |= 0xf << (i * 4);
1675         }
1676         tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1677         br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1678
1679         r600_pipe_state_add_reg(rstate,
1680                                 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1681         r600_pipe_state_add_reg(rstate,
1682                                 R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1683
1684         r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1685                                 shader_control);
1686
1687         free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1688         rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1689         r600_context_pipe_state_set(rctx, rstate);
1690
1691         if (state->zsbuf) {
1692                 r600_polygon_offset_update(rctx);
1693         }
1694 }
1695
1696 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1697 {
1698         struct radeon_winsys_cs *cs = rctx->cs;
1699         struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1700         unsigned db_render_control = 0;
1701         unsigned db_render_override =
1702                 S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
1703                 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1704                 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1705
1706         if (a->occlusion_query_enabled) {
1707                 if (rctx->chip_class >= R700) {
1708                         db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1709                 }
1710                 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1711         }
1712         if (a->flush_depthstencil_enabled) {
1713                 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(1) |
1714                                      S_028D0C_STENCIL_COPY_ENABLE(1) |
1715                                      S_028D0C_COPY_CENTROID(1);
1716         }
1717
1718         r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1719         r600_write_value(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1720         r600_write_value(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1721 }
1722
1723 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1724 {
1725         struct radeon_winsys_cs *cs = rctx->cs;
1726         struct pipe_vertex_buffer *vb = rctx->vertex_buffer;
1727         unsigned count = rctx->nr_vertex_buffers;
1728         unsigned i, offset;
1729
1730         for (i = 0; i < count; i++) {
1731                 struct r600_resource *rbuffer = (struct r600_resource*)vb[i].buffer;
1732
1733                 if (!rbuffer) {
1734                         continue;
1735                 }
1736
1737                 offset = vb[i].buffer_offset;
1738
1739                 /* fetch resources start at index 320 */
1740                 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1741                 r600_write_value(cs, (320 + i) * 7);
1742                 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1743                 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1744                 r600_write_value(cs, /* RESOURCEi_WORD2 */
1745                                  S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1746                                  S_038008_STRIDE(vb[i].stride));
1747                 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1748                 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1749                 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1750                 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1751
1752                 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1753                 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1754         }
1755 }
1756
1757 static void r600_emit_constant_buffers(struct r600_context *rctx,
1758                                        struct r600_constbuf_state *state,
1759                                        unsigned buffer_id_base,
1760                                        unsigned reg_alu_constbuf_size,
1761                                        unsigned reg_alu_const_cache)
1762 {
1763         struct radeon_winsys_cs *cs = rctx->cs;
1764         uint32_t dirty_mask = state->dirty_mask;
1765
1766         while (dirty_mask) {
1767                 struct pipe_constant_buffer *cb;
1768                 struct r600_resource *rbuffer;
1769                 unsigned offset;
1770                 unsigned buffer_index = ffs(dirty_mask) - 1;
1771
1772                 cb = &state->cb[buffer_index];
1773                 rbuffer = (struct r600_resource*)cb->buffer;
1774                 assert(rbuffer);
1775
1776                 offset = cb->buffer_offset;
1777
1778                 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1779                                        ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1780                 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1781
1782                 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1783                 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1784
1785                 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1786                 r600_write_value(cs, (buffer_id_base + buffer_index) * 7);
1787                 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1788                 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1789                 r600_write_value(cs, /* RESOURCEi_WORD2 */
1790                                  S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1791                                  S_038008_STRIDE(16));
1792                 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1793                 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1794                 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1795                 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1796
1797                 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1798                 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1799
1800                 dirty_mask &= ~(1 << buffer_index);
1801         }
1802         state->dirty_mask = 0;
1803 }
1804
1805 static void r600_emit_vs_constant_buffer(struct r600_context *rctx, struct r600_atom *atom)
1806 {
1807         r600_emit_constant_buffers(rctx, &rctx->vs_constbuf_state, 160,
1808                                    R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1809                                    R_028980_ALU_CONST_CACHE_VS_0);
1810 }
1811
1812 static void r600_emit_ps_constant_buffer(struct r600_context *rctx, struct r600_atom *atom)
1813 {
1814         r600_emit_constant_buffers(rctx, &rctx->ps_constbuf_state, 0,
1815                                    R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1816                                    R_028940_ALU_CONST_CACHE_PS_0);
1817 }
1818
1819 void r600_init_state_functions(struct r600_context *rctx)
1820 {
1821         r600_init_atom(&rctx->db_misc_state.atom, r600_emit_db_misc_state, 4, 0);
1822         r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
1823         r600_init_atom(&rctx->vertex_buffer_state, r600_emit_vertex_buffers, 0, 0);
1824         r600_init_atom(&rctx->vs_constbuf_state.atom, r600_emit_vs_constant_buffer, 0, 0);
1825         r600_init_atom(&rctx->ps_constbuf_state.atom, r600_emit_ps_constant_buffer, 0, 0);
1826
1827         rctx->context.create_blend_state = r600_create_blend_state;
1828         rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
1829         rctx->context.create_fs_state = r600_create_shader_state_ps;
1830         rctx->context.create_rasterizer_state = r600_create_rs_state;
1831         rctx->context.create_sampler_state = r600_create_sampler_state;
1832         rctx->context.create_sampler_view = r600_create_sampler_view;
1833         rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1834         rctx->context.create_vs_state = r600_create_shader_state_vs;
1835         rctx->context.bind_blend_state = r600_bind_blend_state;
1836         rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1837         rctx->context.bind_fragment_sampler_states = r600_bind_ps_samplers;
1838         rctx->context.bind_fs_state = r600_bind_ps_shader;
1839         rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1840         rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1841         rctx->context.bind_vertex_sampler_states = r600_bind_vs_samplers;
1842         rctx->context.bind_vs_state = r600_bind_vs_shader;
1843         rctx->context.delete_blend_state = r600_delete_state;
1844         rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1845         rctx->context.delete_fs_state = r600_delete_ps_shader;
1846         rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1847         rctx->context.delete_sampler_state = r600_delete_state;
1848         rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1849         rctx->context.delete_vs_state = r600_delete_vs_shader;
1850         rctx->context.set_blend_color = r600_set_blend_color;
1851         rctx->context.set_clip_state = r600_set_clip_state;
1852         rctx->context.set_constant_buffer = r600_set_constant_buffer;
1853         rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views;
1854         rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1855         rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1856         rctx->context.set_sample_mask = r600_set_sample_mask;
1857         rctx->context.set_scissor_state = r600_pipe_set_scissor_state;
1858         rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1859         rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1860         rctx->context.set_index_buffer = r600_set_index_buffer;
1861         rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
1862         rctx->context.set_viewport_state = r600_set_viewport_state;
1863         rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1864         rctx->context.texture_barrier = r600_texture_barrier;
1865         rctx->context.create_stream_output_target = r600_create_so_target;
1866         rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1867         rctx->context.set_stream_output_targets = r600_set_so_targets;
1868 }
1869
1870 /* Adjust GPR allocation on R6xx/R7xx */
1871 void r600_adjust_gprs(struct r600_context *rctx)
1872 {
1873         struct r600_pipe_state rstate;
1874         unsigned num_ps_gprs = rctx->default_ps_gprs;
1875         unsigned num_vs_gprs = rctx->default_vs_gprs;
1876         unsigned tmp;
1877         int diff;
1878
1879         /* XXX: Following call moved from r600_bind_[ps|vs]_shader,
1880          * it seems eg+ doesn't need it, r6xx/7xx probably need it only for
1881          * adjusting the GPR allocation?
1882          * Do we need this if we aren't really changing config below? */
1883         r600_inval_shader_cache(rctx);
1884
1885         if (rctx->ps_shader->current->shader.bc.ngpr > rctx->default_ps_gprs)
1886         {
1887                 diff = rctx->ps_shader->current->shader.bc.ngpr - rctx->default_ps_gprs;
1888                 num_vs_gprs -= diff;
1889                 num_ps_gprs += diff;
1890         }
1891
1892         if (rctx->vs_shader->current->shader.bc.ngpr > rctx->default_vs_gprs)
1893         {
1894                 diff = rctx->vs_shader->current->shader.bc.ngpr - rctx->default_vs_gprs;
1895                 num_ps_gprs -= diff;
1896                 num_vs_gprs += diff;
1897         }
1898
1899         tmp = 0;
1900         tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1901         tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1902         tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs);
1903         rstate.nregs = 0;
1904         r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp);
1905
1906         r600_context_pipe_state_set(rctx, &rstate);
1907 }
1908
1909 void r600_init_atom_start_cs(struct r600_context *rctx)
1910 {
1911         int ps_prio;
1912         int vs_prio;
1913         int gs_prio;
1914         int es_prio;
1915         int num_ps_gprs;
1916         int num_vs_gprs;
1917         int num_gs_gprs;
1918         int num_es_gprs;
1919         int num_temp_gprs;
1920         int num_ps_threads;
1921         int num_vs_threads;
1922         int num_gs_threads;
1923         int num_es_threads;
1924         int num_ps_stack_entries;
1925         int num_vs_stack_entries;
1926         int num_gs_stack_entries;
1927         int num_es_stack_entries;
1928         enum radeon_family family;
1929         struct r600_command_buffer *cb = &rctx->start_cs_cmd;
1930         uint32_t tmp;
1931         unsigned i;
1932
1933         r600_init_command_buffer(cb, 256, EMIT_EARLY);
1934
1935         /* R6xx requires this packet at the start of each command buffer */
1936         if (rctx->chip_class == R600) {
1937                 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
1938                 r600_store_value(cb, 0);
1939         }
1940         /* All asics require this one */
1941         r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1942         r600_store_value(cb, 0x80000000);
1943         r600_store_value(cb, 0x80000000);
1944
1945         family = rctx->family;
1946         ps_prio = 0;
1947         vs_prio = 1;
1948         gs_prio = 2;
1949         es_prio = 3;
1950         switch (family) {
1951         case CHIP_R600:
1952                 num_ps_gprs = 192;
1953                 num_vs_gprs = 56;
1954                 num_temp_gprs = 4;
1955                 num_gs_gprs = 0;
1956                 num_es_gprs = 0;
1957                 num_ps_threads = 136;
1958                 num_vs_threads = 48;
1959                 num_gs_threads = 4;
1960                 num_es_threads = 4;
1961                 num_ps_stack_entries = 128;
1962                 num_vs_stack_entries = 128;
1963                 num_gs_stack_entries = 0;
1964                 num_es_stack_entries = 0;
1965                 break;
1966         case CHIP_RV630:
1967         case CHIP_RV635:
1968                 num_ps_gprs = 84;
1969                 num_vs_gprs = 36;
1970                 num_temp_gprs = 4;
1971                 num_gs_gprs = 0;
1972                 num_es_gprs = 0;
1973                 num_ps_threads = 144;
1974                 num_vs_threads = 40;
1975                 num_gs_threads = 4;
1976                 num_es_threads = 4;
1977                 num_ps_stack_entries = 40;
1978                 num_vs_stack_entries = 40;
1979                 num_gs_stack_entries = 32;
1980                 num_es_stack_entries = 16;
1981                 break;
1982         case CHIP_RV610:
1983         case CHIP_RV620:
1984         case CHIP_RS780:
1985         case CHIP_RS880:
1986         default:
1987                 num_ps_gprs = 84;
1988                 num_vs_gprs = 36;
1989                 num_temp_gprs = 4;
1990                 num_gs_gprs = 0;
1991                 num_es_gprs = 0;
1992                 num_ps_threads = 136;
1993                 num_vs_threads = 48;
1994                 num_gs_threads = 4;
1995                 num_es_threads = 4;
1996                 num_ps_stack_entries = 40;
1997                 num_vs_stack_entries = 40;
1998                 num_gs_stack_entries = 32;
1999                 num_es_stack_entries = 16;
2000                 break;
2001         case CHIP_RV670:
2002                 num_ps_gprs = 144;
2003                 num_vs_gprs = 40;
2004                 num_temp_gprs = 4;
2005                 num_gs_gprs = 0;
2006                 num_es_gprs = 0;
2007                 num_ps_threads = 136;
2008                 num_vs_threads = 48;
2009                 num_gs_threads = 4;
2010                 num_es_threads = 4;
2011                 num_ps_stack_entries = 40;
2012                 num_vs_stack_entries = 40;
2013                 num_gs_stack_entries = 32;
2014                 num_es_stack_entries = 16;
2015                 break;
2016         case CHIP_RV770:
2017                 num_ps_gprs = 192;
2018                 num_vs_gprs = 56;
2019                 num_temp_gprs = 4;
2020                 num_gs_gprs = 0;
2021                 num_es_gprs = 0;
2022                 num_ps_threads = 188;
2023                 num_vs_threads = 60;
2024                 num_gs_threads = 0;
2025                 num_es_threads = 0;
2026                 num_ps_stack_entries = 256;
2027                 num_vs_stack_entries = 256;
2028                 num_gs_stack_entries = 0;
2029                 num_es_stack_entries = 0;
2030                 break;
2031         case CHIP_RV730:
2032         case CHIP_RV740:
2033                 num_ps_gprs = 84;
2034                 num_vs_gprs = 36;
2035                 num_temp_gprs = 4;
2036                 num_gs_gprs = 0;
2037                 num_es_gprs = 0;
2038                 num_ps_threads = 188;
2039                 num_vs_threads = 60;
2040                 num_gs_threads = 0;
2041                 num_es_threads = 0;
2042                 num_ps_stack_entries = 128;
2043                 num_vs_stack_entries = 128;
2044                 num_gs_stack_entries = 0;
2045                 num_es_stack_entries = 0;
2046                 break;
2047         case CHIP_RV710:
2048                 num_ps_gprs = 192;
2049                 num_vs_gprs = 56;
2050                 num_temp_gprs = 4;
2051                 num_gs_gprs = 0;
2052                 num_es_gprs = 0;
2053                 num_ps_threads = 144;
2054                 num_vs_threads = 48;
2055                 num_gs_threads = 0;
2056                 num_es_threads = 0;
2057                 num_ps_stack_entries = 128;
2058                 num_vs_stack_entries = 128;
2059                 num_gs_stack_entries = 0;
2060                 num_es_stack_entries = 0;
2061                 break;
2062         }
2063
2064         rctx->default_ps_gprs = num_ps_gprs;
2065         rctx->default_vs_gprs = num_vs_gprs;
2066         rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2067
2068         /* SQ_CONFIG */
2069         tmp = 0;
2070         switch (family) {
2071         case CHIP_RV610:
2072         case CHIP_RV620:
2073         case CHIP_RS780:
2074         case CHIP_RS880:
2075         case CHIP_RV710:
2076                 break;
2077         default:
2078                 tmp |= S_008C00_VC_ENABLE(1);
2079                 break;
2080         }
2081         tmp |= S_008C00_DX9_CONSTS(0);
2082         tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2083         tmp |= S_008C00_PS_PRIO(ps_prio);
2084         tmp |= S_008C00_VS_PRIO(vs_prio);
2085         tmp |= S_008C00_GS_PRIO(gs_prio);
2086         tmp |= S_008C00_ES_PRIO(es_prio);
2087         r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2088
2089         /* SQ_GPR_RESOURCE_MGMT_2 */
2090         tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2091         tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2092         r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2093         r600_store_value(cb, tmp);
2094
2095         /* SQ_THREAD_RESOURCE_MGMT */
2096         tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2097         tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2098         tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2099         tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2100         r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2101
2102         /* SQ_STACK_RESOURCE_MGMT_1 */
2103         tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2104         tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2105         r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2106
2107         /* SQ_STACK_RESOURCE_MGMT_2 */
2108         tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2109         tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2110         r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2111
2112         r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2113
2114         if (rctx->chip_class >= R700) {
2115                 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2116                 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2117                 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2118                 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2119         } else {
2120                 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2121                 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2122                 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2123                 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2124         }
2125         r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2126         r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2127         r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2128         r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2129         r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2130         r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2131         r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2132         r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2133         r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2134         r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2135
2136         r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2137         r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2138         r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2139         r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2140         r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2141         r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2142         r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2143         r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2144         r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2145         r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2146         r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2147         r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2148         r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2149         r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2150
2151         r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2152         r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2153         r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2154
2155         r600_store_context_reg_seq(cb, R_028AB0_VGT_STRMOUT_EN, 3);
2156         r600_store_value(cb, 0); /* R_028AB0_VGT_STRMOUT_EN */
2157         r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2158         r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2159
2160         r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2161
2162         r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2163         r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2164         r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2165
2166         r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2167
2168         r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2169         r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2170         r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2171
2172         r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2173         r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2174         r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2175         r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2176
2177         r600_store_context_reg_seq(cb, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 2);
2178         r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2179         r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2180
2181         r600_store_context_reg(cb, R_028D44_DB_ALPHA_TO_MASK, 0xAA00);
2182
2183         r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2184         r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2185
2186         r600_store_context_reg_seq(cb, R_028C00_PA_SC_LINE_CNTL, 2);
2187         r600_store_value(cb, 0x400); /* R_028C00_PA_SC_LINE_CNTL */
2188         r600_store_value(cb, 0); /* R_028C04_PA_SC_AA_CONFIG */
2189
2190         r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 6);
2191         r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2192         r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2193         r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2194         r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2195         r600_store_value(cb, 0); /* R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX */
2196         r600_store_value(cb, 0); /* R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX */
2197
2198         r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2199         r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2200         r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2201
2202         r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F);
2203
2204         r600_store_context_reg_seq(cb, R_028100_CB_COLOR0_MASK, 8);
2205         for (i = 0; i < 8; i++) {
2206                 r600_store_value(cb, 0);
2207         }
2208
2209         r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2210         r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2211
2212         if (rctx->chip_class >= R700) {
2213                 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2214         }
2215
2216         r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2217         r600_store_value(cb, 0x1000000);  /* R_028C30_CB_CLRCMP_CONTROL */
2218         r600_store_value(cb, 0);          /* R_028C34_CB_CLRCMP_SRC */
2219         r600_store_value(cb, 0xFF);       /* R_028C38_CB_CLRCMP_DST */
2220         r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2221
2222         r600_store_context_reg(cb, R_028C48_PA_SC_AA_MASK, 0xFFFFFFFF);
2223
2224         r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2225         r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2226         r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2227
2228         r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2229         r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2230         r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2231
2232         r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 2);
2233         r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2234         r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2235
2236         r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2237         r600_store_context_reg(cb, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0);
2238
2239         if (rctx->chip_class == R700 && rctx->screen->has_streamout)
2240                 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2241         r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2242
2243         r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2244         r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2245 }
2246
2247 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2248 {
2249         struct r600_context *rctx = (struct r600_context *)ctx;
2250         struct r600_pipe_state *rstate = &shader->rstate;
2251         struct r600_shader *rshader = &shader->shader;
2252         unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2253         int pos_index = -1, face_index = -1;
2254         unsigned tmp, sid, ufi = 0;
2255         int need_linear = 0;
2256         unsigned z_export = 0, stencil_export = 0;
2257
2258         rstate->nregs = 0;
2259
2260         for (i = 0; i < rshader->ninput; i++) {
2261                 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2262                         pos_index = i;
2263                 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2264                         face_index = i;
2265
2266                 sid = rshader->input[i].spi_sid;
2267
2268                 tmp = S_028644_SEMANTIC(sid);
2269
2270                 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2271                         rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2272                         (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2273                                 rctx->rasterizer && rctx->rasterizer->flatshade))
2274                         tmp |= S_028644_FLAT_SHADE(1);
2275
2276                 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2277                                 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
2278                         tmp |= S_028644_PT_SPRITE_TEX(1);
2279                 }
2280
2281                 if (rshader->input[i].centroid)
2282                         tmp |= S_028644_SEL_CENTROID(1);
2283
2284                 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2285                         need_linear = 1;
2286                         tmp |= S_028644_SEL_LINEAR(1);
2287                 }
2288
2289                 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4,
2290                                 tmp);
2291         }
2292
2293         db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2294         for (i = 0; i < rshader->noutput; i++) {
2295                 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2296                         z_export = 1;
2297                 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2298                         stencil_export = 1;
2299         }
2300         db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2301         db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2302         if (rshader->uses_kill)
2303                 db_shader_control |= S_02880C_KILL_ENABLE(1);
2304
2305         exports_ps = 0;
2306         for (i = 0; i < rshader->noutput; i++) {
2307                 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2308                     rshader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2309                         exports_ps |= 1;
2310                 }
2311         }
2312         num_cout = rshader->nr_ps_color_exports;
2313         exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2314         if (!exports_ps) {
2315                 /* always at least export 1 component per pixel */
2316                 exports_ps = 2;
2317         }
2318
2319         shader->ps_cb_shader_mask = (1ULL << ((unsigned)num_cout * 4)) - 1;
2320
2321         spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2322                                 S_0286CC_PERSP_GRADIENT_ENA(1)|
2323                                 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2324         spi_input_z = 0;
2325         if (pos_index != -1) {
2326                 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2327                                         S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2328                                         S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2329                                         S_0286CC_BARYC_SAMPLE_CNTL(1));
2330                 spi_input_z |= 1;
2331         }
2332
2333         spi_ps_in_control_1 = 0;
2334         if (face_index != -1) {
2335                 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2336                         S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2337         }
2338
2339         /* HW bug in original R600 */
2340         if (rctx->family == CHIP_R600)
2341                 ufi = 1;
2342
2343         r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0);
2344         r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1);
2345         r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
2346         r600_pipe_state_add_reg_bo(rstate,
2347                                    R_028840_SQ_PGM_START_PS,
2348                                    0, shader->bo, RADEON_USAGE_READ);
2349         r600_pipe_state_add_reg(rstate,
2350                                 R_028850_SQ_PGM_RESOURCES_PS,
2351                                 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2352                                 S_028850_STACK_SIZE(rshader->bc.nstack) |
2353                                 S_028850_UNCACHED_FIRST_INST(ufi));
2354         r600_pipe_state_add_reg(rstate,
2355                                 R_028854_SQ_PGM_EXPORTS_PS,
2356                                 exports_ps);
2357         /* only set some bits here, the other bits are set in the dsa state */
2358         shader->db_shader_control = db_shader_control;
2359         shader->ps_depth_export = z_export | stencil_export;
2360
2361         shader->sprite_coord_enable = rctx->sprite_coord_enable;
2362         if (rctx->rasterizer)
2363                 shader->flatshade = rctx->rasterizer->flatshade;
2364 }
2365
2366 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2367 {
2368         struct r600_context *rctx = (struct r600_context *)ctx;
2369         struct r600_pipe_state *rstate = &shader->rstate;
2370         struct r600_shader *rshader = &shader->shader;
2371         unsigned spi_vs_out_id[10] = {};
2372         unsigned i, tmp, nparams = 0;
2373
2374         /* clear previous register */
2375         rstate->nregs = 0;
2376
2377         for (i = 0; i < rshader->noutput; i++) {
2378                 if (rshader->output[i].spi_sid) {
2379                         tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2380                         spi_vs_out_id[nparams / 4] |= tmp;
2381                         nparams++;
2382                 }
2383         }
2384
2385         for (i = 0; i < 10; i++) {
2386                 r600_pipe_state_add_reg(rstate,
2387                                         R_028614_SPI_VS_OUT_ID_0 + i * 4,
2388                                         spi_vs_out_id[i]);
2389         }
2390
2391         /* Certain attributes (position, psize, etc.) don't count as params.
2392          * VS is required to export at least one param and r600_shader_from_tgsi()
2393          * takes care of adding a dummy export.
2394          */
2395         if (nparams < 1)
2396                 nparams = 1;
2397
2398         r600_pipe_state_add_reg(rstate,
2399                                 R_0286C4_SPI_VS_OUT_CONFIG,
2400                                 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2401         r600_pipe_state_add_reg(rstate,
2402                                 R_028868_SQ_PGM_RESOURCES_VS,
2403                                 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2404                                 S_028868_STACK_SIZE(rshader->bc.nstack));
2405         r600_pipe_state_add_reg_bo(rstate,
2406                         R_028858_SQ_PGM_START_VS,
2407                         0, shader->bo, RADEON_USAGE_READ);
2408
2409         shader->pa_cl_vs_out_cntl =
2410                 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2411                 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2412                 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2413                 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2414 }
2415
2416 void r600_fetch_shader(struct pipe_context *ctx,
2417                        struct r600_vertex_element *ve)
2418 {
2419         struct r600_pipe_state *rstate;
2420         struct r600_context *rctx = (struct r600_context *)ctx;
2421
2422         rstate = &ve->rstate;
2423         rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2424         rstate->nregs = 0;
2425         r600_pipe_state_add_reg_bo(rstate, R_028894_SQ_PGM_START_FS,
2426                                 0,
2427                                 ve->fetch_shader, RADEON_USAGE_READ);
2428 }
2429
2430 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2431 {
2432         struct pipe_depth_stencil_alpha_state dsa;
2433         struct r600_pipe_state *rstate;
2434         struct r600_pipe_dsa *dsa_state;
2435         boolean quirk = false;
2436
2437         if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
2438                 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
2439                 quirk = true;
2440
2441         memset(&dsa, 0, sizeof(dsa));
2442
2443         if (quirk) {
2444                 dsa.depth.enabled = 1;
2445                 dsa.depth.func = PIPE_FUNC_LEQUAL;
2446                 dsa.stencil[0].enabled = 1;
2447                 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2448                 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2449                 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2450                 dsa.stencil[0].writemask = 0xff;
2451         }
2452
2453         rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2454         dsa_state = (struct r600_pipe_dsa*)rstate;
2455         dsa_state->is_flush = true;
2456         return rstate;
2457 }
2458
2459 void r600_update_dual_export_state(struct r600_context * rctx)
2460 {
2461         unsigned dual_export = rctx->export_16bpc && rctx->nr_cbufs &&
2462                                !rctx->ps_shader->current->ps_depth_export;
2463         unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
2464                                      S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2465
2466         if (db_shader_control != rctx->db_shader_control) {
2467                 struct r600_pipe_state rstate;
2468
2469                 rctx->db_shader_control = db_shader_control;
2470                 rstate.nregs = 0;
2471                 r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
2472                 r600_context_pipe_state_set(rctx, &rstate);
2473         }
2474 }