src/gallium/drivers/r600/r600_state.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /* TODO:
  25  *      - fix mask for depth control & cull for query
  26  */
  27 #include <stdio.h>
  28 #include <errno.h>
  29 #include "pipe/p_defines.h"
  30 #include "pipe/p_state.h"
  31 #include "pipe/p_context.h"
  32 #include "tgsi/tgsi_scan.h"
  33 #include "tgsi/tgsi_parse.h"
  34 #include "tgsi/tgsi_util.h"
  35 #include "util/u_double_list.h"
  36 #include "util/u_pack_color.h"
  37 #include "util/u_memory.h"
  38 #include "util/u_inlines.h"
  39 #include "util/u_framebuffer.h"
  40 #include "util/u_transfer.h"
  41 #include "pipebuffer/pb_buffer.h"
  42 #include "r600.h"
  43 #include "r600d.h"
  44 #include "r600_resource.h"
  45 #include "r600_shader.h"
  46 #include "r600_pipe.h"
  47 #include "r600_formats.h"
  48
  49 static uint32_t r600_translate_blend_function(int blend_func)
  50 {
  51         switch (blend_func) {
  52         case PIPE_BLEND_ADD:
  53                 return V_028804_COMB_DST_PLUS_SRC;
  54         case PIPE_BLEND_SUBTRACT:
  55                 return V_028804_COMB_SRC_MINUS_DST;
  56         case PIPE_BLEND_REVERSE_SUBTRACT:
  57                 return V_028804_COMB_DST_MINUS_SRC;
  58         case PIPE_BLEND_MIN:
  59                 return V_028804_COMB_MIN_DST_SRC;
  60         case PIPE_BLEND_MAX:
  61                 return V_028804_COMB_MAX_DST_SRC;
  62         default:
  63                 R600_ERR("Unknown blend function %d\n", blend_func);
  64                 assert(0);
  65                 break;
  66         }
  67         return 0;
  68 }
  69
  70 static uint32_t r600_translate_blend_factor(int blend_fact)
  71 {
  72         switch (blend_fact) {
  73         case PIPE_BLENDFACTOR_ONE:
  74                 return V_028804_BLEND_ONE;
  75         case PIPE_BLENDFACTOR_SRC_COLOR:
  76                 return V_028804_BLEND_SRC_COLOR;
  77         case PIPE_BLENDFACTOR_SRC_ALPHA:
  78                 return V_028804_BLEND_SRC_ALPHA;
  79         case PIPE_BLENDFACTOR_DST_ALPHA:
  80                 return V_028804_BLEND_DST_ALPHA;
  81         case PIPE_BLENDFACTOR_DST_COLOR:
  82                 return V_028804_BLEND_DST_COLOR;
  83         case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
  84                 return V_028804_BLEND_SRC_ALPHA_SATURATE;
  85         case PIPE_BLENDFACTOR_CONST_COLOR:
  86                 return V_028804_BLEND_CONST_COLOR;
  87         case PIPE_BLENDFACTOR_CONST_ALPHA:
  88                 return V_028804_BLEND_CONST_ALPHA;
  89         case PIPE_BLENDFACTOR_ZERO:
  90                 return V_028804_BLEND_ZERO;
  91         case PIPE_BLENDFACTOR_INV_SRC_COLOR:
  92                 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
  93         case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
  94                 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
  95         case PIPE_BLENDFACTOR_INV_DST_ALPHA:
  96                 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
  97         case PIPE_BLENDFACTOR_INV_DST_COLOR:
  98                 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
  99         case PIPE_BLENDFACTOR_INV_CONST_COLOR:
 100                 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
 101         case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
 102                 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
 103         case PIPE_BLENDFACTOR_SRC1_COLOR:
 104                 return V_028804_BLEND_SRC1_COLOR;
 105         case PIPE_BLENDFACTOR_SRC1_ALPHA:
 106                 return V_028804_BLEND_SRC1_ALPHA;
 107         case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
 108                 return V_028804_BLEND_INV_SRC1_COLOR;
 109         case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
 110                 return V_028804_BLEND_INV_SRC1_ALPHA;
 111         default:
 112                 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
 113                 assert(0);
 114                 break;
 115         }
 116         return 0;
 117 }
 118
 119 static unsigned r600_tex_wrap(unsigned wrap)
 120 {
 121         switch (wrap) {
 122         default:
 123         case PIPE_TEX_WRAP_REPEAT:
 124                 return V_03C000_SQ_TEX_WRAP;
 125         case PIPE_TEX_WRAP_CLAMP:
 126                 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
 127         case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
 128                 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
 129         case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
 130                 return V_03C000_SQ_TEX_CLAMP_BORDER;
 131         case PIPE_TEX_WRAP_MIRROR_REPEAT:
 132                 return V_03C000_SQ_TEX_MIRROR;
 133         case PIPE_TEX_WRAP_MIRROR_CLAMP:
 134                 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
 135         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
 136                 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
 137         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
 138                 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
 139         }
 140 }
 141
 142 static unsigned r600_tex_filter(unsigned filter)
 143 {
 144         switch (filter) {
 145         default:
 146         case PIPE_TEX_FILTER_NEAREST:
 147                 return V_03C000_SQ_TEX_XY_FILTER_POINT;
 148         case PIPE_TEX_FILTER_LINEAR:
 149                 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
 150         }
 151 }
 152
 153 static unsigned r600_tex_mipfilter(unsigned filter)
 154 {
 155         switch (filter) {
 156         case PIPE_TEX_MIPFILTER_NEAREST:
 157                 return V_03C000_SQ_TEX_Z_FILTER_POINT;
 158         case PIPE_TEX_MIPFILTER_LINEAR:
 159                 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
 160         default:
 161         case PIPE_TEX_MIPFILTER_NONE:
 162                 return V_03C000_SQ_TEX_Z_FILTER_NONE;
 163         }
 164 }
 165
 166 static unsigned r600_tex_compare(unsigned compare)
 167 {
 168         switch (compare) {
 169         default:
 170         case PIPE_FUNC_NEVER:
 171                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
 172         case PIPE_FUNC_LESS:
 173                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
 174         case PIPE_FUNC_EQUAL:
 175                 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
 176         case PIPE_FUNC_LEQUAL:
 177                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
 178         case PIPE_FUNC_GREATER:
 179                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
 180         case PIPE_FUNC_NOTEQUAL:
 181                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
 182         case PIPE_FUNC_GEQUAL:
 183                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
 184         case PIPE_FUNC_ALWAYS:
 185                 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
 186         }
 187 }
 188
 189 static unsigned r600_tex_dim(unsigned dim)
 190 {
 191         switch (dim) {
 192         default:
 193         case PIPE_TEXTURE_1D:
 194                 return V_038000_SQ_TEX_DIM_1D;
 195         case PIPE_TEXTURE_1D_ARRAY:
 196                 return V_038000_SQ_TEX_DIM_1D_ARRAY;
 197         case PIPE_TEXTURE_2D:
 198         case PIPE_TEXTURE_RECT:
 199                 return V_038000_SQ_TEX_DIM_2D;
 200         case PIPE_TEXTURE_2D_ARRAY:
 201                 return V_038000_SQ_TEX_DIM_2D_ARRAY;
 202         case PIPE_TEXTURE_3D:
 203                 return V_038000_SQ_TEX_DIM_3D;
 204         case PIPE_TEXTURE_CUBE:
 205                 return V_038000_SQ_TEX_DIM_CUBEMAP;
 206         }
 207 }
 208
 209 static uint32_t r600_translate_dbformat(enum pipe_format format)
 210 {
 211         switch (format) {
 212         case PIPE_FORMAT_Z16_UNORM:
 213                 return V_028010_DEPTH_16;
 214         case PIPE_FORMAT_Z24X8_UNORM:
 215                 return V_028010_DEPTH_X8_24;
 216         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 217                 return V_028010_DEPTH_8_24;
 218         case PIPE_FORMAT_Z32_FLOAT:
 219                 return V_028010_DEPTH_32_FLOAT;
 220         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 221                 return V_028010_DEPTH_X24_8_32_FLOAT;
 222         default:
 223                 return ~0U;
 224         }
 225 }
 226
 227 static uint32_t r600_translate_colorswap(enum pipe_format format)
 228 {
 229         switch (format) {
 230         /* 8-bit buffers. */
 231         case PIPE_FORMAT_A8_UNORM:
 232         case PIPE_FORMAT_A8_UINT:
 233         case PIPE_FORMAT_A8_SINT:
 234         case PIPE_FORMAT_R4A4_UNORM:
 235                 return V_0280A0_SWAP_ALT_REV;
 236         case PIPE_FORMAT_I8_UNORM:
 237         case PIPE_FORMAT_L8_UNORM:
 238         case PIPE_FORMAT_I8_UINT:
 239         case PIPE_FORMAT_I8_SINT:
 240         case PIPE_FORMAT_L8_UINT:
 241         case PIPE_FORMAT_L8_SINT:
 242         case PIPE_FORMAT_L8_SRGB:
 243         case PIPE_FORMAT_R8_UNORM:
 244         case PIPE_FORMAT_R8_SNORM:
 245         case PIPE_FORMAT_R8_UINT:
 246         case PIPE_FORMAT_R8_SINT:
 247                 return V_0280A0_SWAP_STD;
 248
 249         case PIPE_FORMAT_L4A4_UNORM:
 250         case PIPE_FORMAT_A4R4_UNORM:
 251                 return V_0280A0_SWAP_ALT;
 252
 253         /* 16-bit buffers. */
 254         case PIPE_FORMAT_B5G6R5_UNORM:
 255                 return V_0280A0_SWAP_STD_REV;
 256
 257         case PIPE_FORMAT_B5G5R5A1_UNORM:
 258         case PIPE_FORMAT_B5G5R5X1_UNORM:
 259                 return V_0280A0_SWAP_ALT;
 260
 261         case PIPE_FORMAT_B4G4R4A4_UNORM:
 262         case PIPE_FORMAT_B4G4R4X4_UNORM:
 263                 return V_0280A0_SWAP_ALT;
 264
 265         case PIPE_FORMAT_Z16_UNORM:
 266                 return V_0280A0_SWAP_STD;
 267
 268         case PIPE_FORMAT_L8A8_UNORM:
 269         case PIPE_FORMAT_L8A8_UINT:
 270         case PIPE_FORMAT_L8A8_SINT:
 271         case PIPE_FORMAT_L8A8_SRGB:
 272                 return V_0280A0_SWAP_ALT;
 273         case PIPE_FORMAT_R8G8_UNORM:
 274         case PIPE_FORMAT_R8G8_UINT:
 275         case PIPE_FORMAT_R8G8_SINT:
 276                 return V_0280A0_SWAP_STD;
 277
 278         case PIPE_FORMAT_R16_UNORM:
 279         case PIPE_FORMAT_R16_UINT:
 280         case PIPE_FORMAT_R16_SINT:
 281         case PIPE_FORMAT_R16_FLOAT:
 282                 return V_0280A0_SWAP_STD;
 283
 284         /* 32-bit buffers. */
 285
 286         case PIPE_FORMAT_A8B8G8R8_SRGB:
 287                 return V_0280A0_SWAP_STD_REV;
 288         case PIPE_FORMAT_B8G8R8A8_SRGB:
 289                 return V_0280A0_SWAP_ALT;
 290
 291         case PIPE_FORMAT_B8G8R8A8_UNORM:
 292         case PIPE_FORMAT_B8G8R8X8_UNORM:
 293                 return V_0280A0_SWAP_ALT;
 294
 295         case PIPE_FORMAT_A8R8G8B8_UNORM:
 296         case PIPE_FORMAT_X8R8G8B8_UNORM:
 297                 return V_0280A0_SWAP_ALT_REV;
 298         case PIPE_FORMAT_R8G8B8A8_SNORM:
 299         case PIPE_FORMAT_R8G8B8A8_UNORM:
 300         case PIPE_FORMAT_R8G8B8X8_UNORM:
 301         case PIPE_FORMAT_R8G8B8A8_SSCALED:
 302         case PIPE_FORMAT_R8G8B8A8_USCALED:
 303         case PIPE_FORMAT_R8G8B8A8_SINT:
 304         case PIPE_FORMAT_R8G8B8A8_UINT:
 305                 return V_0280A0_SWAP_STD;
 306
 307         case PIPE_FORMAT_A8B8G8R8_UNORM:
 308         case PIPE_FORMAT_X8B8G8R8_UNORM:
 309         /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
 310                 return V_0280A0_SWAP_STD_REV;
 311
 312         case PIPE_FORMAT_Z24X8_UNORM:
 313         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 314                 return V_0280A0_SWAP_STD;
 315
 316         case PIPE_FORMAT_X8Z24_UNORM:
 317         case PIPE_FORMAT_S8_UINT_Z24_UNORM:
 318                 return V_0280A0_SWAP_STD;
 319
 320         case PIPE_FORMAT_R10G10B10A2_UNORM:
 321         case PIPE_FORMAT_R10G10B10X2_SNORM:
 322         case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
 323                 return V_0280A0_SWAP_STD;
 324
 325         case PIPE_FORMAT_B10G10R10A2_UNORM:
 326         case PIPE_FORMAT_B10G10R10A2_UINT:
 327                 return V_0280A0_SWAP_ALT;
 328
 329         case PIPE_FORMAT_R11G11B10_FLOAT:
 330         case PIPE_FORMAT_R16G16_UNORM:
 331         case PIPE_FORMAT_R16G16_FLOAT:
 332         case PIPE_FORMAT_R16G16_UINT:
 333         case PIPE_FORMAT_R16G16_SINT:
 334         case PIPE_FORMAT_R32_UINT:
 335         case PIPE_FORMAT_R32_SINT:
 336         case PIPE_FORMAT_R32_FLOAT:
 337         case PIPE_FORMAT_Z32_FLOAT:
 338                 return V_0280A0_SWAP_STD;
 339
 340         /* 64-bit buffers. */
 341         case PIPE_FORMAT_R32G32_FLOAT:
 342         case PIPE_FORMAT_R32G32_UINT:
 343         case PIPE_FORMAT_R32G32_SINT:
 344         case PIPE_FORMAT_R16G16B16A16_UNORM:
 345         case PIPE_FORMAT_R16G16B16A16_SNORM:
 346         case PIPE_FORMAT_R16G16B16A16_USCALED:
 347         case PIPE_FORMAT_R16G16B16A16_SSCALED:
 348         case PIPE_FORMAT_R16G16B16A16_UINT:
 349         case PIPE_FORMAT_R16G16B16A16_SINT:
 350         case PIPE_FORMAT_R16G16B16A16_FLOAT:
 351         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 352
 353         /* 128-bit buffers. */
 354         case PIPE_FORMAT_R32G32B32A32_FLOAT:
 355         case PIPE_FORMAT_R32G32B32A32_SNORM:
 356         case PIPE_FORMAT_R32G32B32A32_UNORM:
 357         case PIPE_FORMAT_R32G32B32A32_USCALED:
 358         case PIPE_FORMAT_R32G32B32A32_SSCALED:
 359         case PIPE_FORMAT_R32G32B32A32_SINT:
 360         case PIPE_FORMAT_R32G32B32A32_UINT:
 361                 return V_0280A0_SWAP_STD;
 362         default:
 363                 R600_ERR("unsupported colorswap format %d\n", format);
 364                 return ~0U;
 365         }
 366         return ~0U;
 367 }
 368
 369 static uint32_t r600_translate_colorformat(enum pipe_format format)
 370 {
 371         switch (format) {
 372         case PIPE_FORMAT_L4A4_UNORM:
 373         case PIPE_FORMAT_R4A4_UNORM:
 374         case PIPE_FORMAT_A4R4_UNORM:
 375                 return V_0280A0_COLOR_4_4;
 376
 377         /* 8-bit buffers. */
 378         case PIPE_FORMAT_A8_UNORM:
 379         case PIPE_FORMAT_A8_UINT:
 380         case PIPE_FORMAT_A8_SINT:
 381         case PIPE_FORMAT_I8_UNORM:
 382         case PIPE_FORMAT_I8_UINT:
 383         case PIPE_FORMAT_I8_SINT:
 384         case PIPE_FORMAT_L8_UNORM:
 385         case PIPE_FORMAT_L8_UINT:
 386         case PIPE_FORMAT_L8_SINT:
 387         case PIPE_FORMAT_L8_SRGB:
 388         case PIPE_FORMAT_R8_UNORM:
 389         case PIPE_FORMAT_R8_SNORM:
 390         case PIPE_FORMAT_R8_UINT:
 391         case PIPE_FORMAT_R8_SINT:
 392                 return V_0280A0_COLOR_8;
 393
 394         /* 16-bit buffers. */
 395         case PIPE_FORMAT_B5G6R5_UNORM:
 396                 return V_0280A0_COLOR_5_6_5;
 397
 398         case PIPE_FORMAT_B5G5R5A1_UNORM:
 399         case PIPE_FORMAT_B5G5R5X1_UNORM:
 400                 return V_0280A0_COLOR_1_5_5_5;
 401
 402         case PIPE_FORMAT_B4G4R4A4_UNORM:
 403         case PIPE_FORMAT_B4G4R4X4_UNORM:
 404                 return V_0280A0_COLOR_4_4_4_4;
 405
 406         case PIPE_FORMAT_Z16_UNORM:
 407                 return V_0280A0_COLOR_16;
 408
 409         case PIPE_FORMAT_L8A8_UNORM:
 410         case PIPE_FORMAT_L8A8_UINT:
 411         case PIPE_FORMAT_L8A8_SINT:
 412         case PIPE_FORMAT_L8A8_SRGB:
 413         case PIPE_FORMAT_R8G8_UNORM:
 414         case PIPE_FORMAT_R8G8_UINT:
 415         case PIPE_FORMAT_R8G8_SINT:
 416                 return V_0280A0_COLOR_8_8;
 417
 418         case PIPE_FORMAT_R16_UNORM:
 419         case PIPE_FORMAT_R16_UINT:
 420         case PIPE_FORMAT_R16_SINT:
 421                 return V_0280A0_COLOR_16;
 422
 423         case PIPE_FORMAT_R16_FLOAT:
 424                 return V_0280A0_COLOR_16_FLOAT;
 425
 426         /* 32-bit buffers. */
 427         case PIPE_FORMAT_A8B8G8R8_SRGB:
 428         case PIPE_FORMAT_A8B8G8R8_UNORM:
 429         case PIPE_FORMAT_A8R8G8B8_UNORM:
 430         case PIPE_FORMAT_B8G8R8A8_SRGB:
 431         case PIPE_FORMAT_B8G8R8A8_UNORM:
 432         case PIPE_FORMAT_B8G8R8X8_UNORM:
 433         case PIPE_FORMAT_R8G8B8A8_SNORM:
 434         case PIPE_FORMAT_R8G8B8A8_UNORM:
 435         case PIPE_FORMAT_R8G8B8A8_SSCALED:
 436         case PIPE_FORMAT_R8G8B8A8_USCALED:
 437         case PIPE_FORMAT_R8G8B8X8_UNORM:
 438         case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
 439         case PIPE_FORMAT_X8B8G8R8_UNORM:
 440         case PIPE_FORMAT_X8R8G8B8_UNORM:
 441         case PIPE_FORMAT_R8G8B8_UNORM:
 442         case PIPE_FORMAT_R8G8B8A8_SINT:
 443         case PIPE_FORMAT_R8G8B8A8_UINT:
 444                 return V_0280A0_COLOR_8_8_8_8;
 445
 446         case PIPE_FORMAT_R10G10B10A2_UNORM:
 447         case PIPE_FORMAT_R10G10B10X2_SNORM:
 448         case PIPE_FORMAT_B10G10R10A2_UNORM:
 449         case PIPE_FORMAT_B10G10R10A2_UINT:
 450         case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
 451                 return V_0280A0_COLOR_2_10_10_10;
 452
 453         case PIPE_FORMAT_Z24X8_UNORM:
 454         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 455                 return V_0280A0_COLOR_8_24;
 456
 457         case PIPE_FORMAT_X8Z24_UNORM:
 458         case PIPE_FORMAT_S8_UINT_Z24_UNORM:
 459                 return V_0280A0_COLOR_24_8;
 460
 461         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 462                 return V_0280A0_COLOR_X24_8_32_FLOAT;
 463
 464         case PIPE_FORMAT_R32_UINT:
 465         case PIPE_FORMAT_R32_SINT:
 466                 return V_0280A0_COLOR_32;
 467
 468         case PIPE_FORMAT_R32_FLOAT:
 469         case PIPE_FORMAT_Z32_FLOAT:
 470                 return V_0280A0_COLOR_32_FLOAT;
 471
 472         case PIPE_FORMAT_R16G16_FLOAT:
 473                 return V_0280A0_COLOR_16_16_FLOAT;
 474
 475         case PIPE_FORMAT_R16G16_SSCALED:
 476         case PIPE_FORMAT_R16G16_UNORM:
 477         case PIPE_FORMAT_R16G16_UINT:
 478         case PIPE_FORMAT_R16G16_SINT:
 479                 return V_0280A0_COLOR_16_16;
 480
 481         case PIPE_FORMAT_R11G11B10_FLOAT:
 482                 return V_0280A0_COLOR_10_11_11_FLOAT;
 483
 484         /* 64-bit buffers. */
 485         case PIPE_FORMAT_R16G16B16_USCALED:
 486         case PIPE_FORMAT_R16G16B16A16_USCALED:
 487         case PIPE_FORMAT_R16G16B16_SSCALED:
 488         case PIPE_FORMAT_R16G16B16A16_UINT:
 489         case PIPE_FORMAT_R16G16B16A16_SINT:
 490         case PIPE_FORMAT_R16G16B16A16_SSCALED:
 491         case PIPE_FORMAT_R16G16B16A16_UNORM:
 492         case PIPE_FORMAT_R16G16B16A16_SNORM:
 493                 return V_0280A0_COLOR_16_16_16_16;
 494
 495         case PIPE_FORMAT_R16G16B16_FLOAT:
 496         case PIPE_FORMAT_R16G16B16A16_FLOAT:
 497                 return V_0280A0_COLOR_16_16_16_16_FLOAT;
 498
 499         case PIPE_FORMAT_R32G32_FLOAT:
 500                 return V_0280A0_COLOR_32_32_FLOAT;
 501
 502         case PIPE_FORMAT_R32G32_USCALED:
 503         case PIPE_FORMAT_R32G32_SSCALED:
 504         case PIPE_FORMAT_R32G32_SINT:
 505         case PIPE_FORMAT_R32G32_UINT:
 506                 return V_0280A0_COLOR_32_32;
 507
 508         /* 96-bit buffers. */
 509         case PIPE_FORMAT_R32G32B32_FLOAT:
 510                 return V_0280A0_COLOR_32_32_32_FLOAT;
 511
 512         /* 128-bit buffers. */
 513         case PIPE_FORMAT_R32G32B32A32_FLOAT:
 514                 return V_0280A0_COLOR_32_32_32_32_FLOAT;
 515         case PIPE_FORMAT_R32G32B32A32_SNORM:
 516         case PIPE_FORMAT_R32G32B32A32_UNORM:
 517         case PIPE_FORMAT_R32G32B32A32_SSCALED:
 518         case PIPE_FORMAT_R32G32B32A32_USCALED:
 519         case PIPE_FORMAT_R32G32B32A32_SINT:
 520         case PIPE_FORMAT_R32G32B32A32_UINT:
 521                 return V_0280A0_COLOR_32_32_32_32;
 522
 523         /* YUV buffers. */
 524         case PIPE_FORMAT_UYVY:
 525         case PIPE_FORMAT_YUYV:
 526         default:
 527                 return ~0U; /* Unsupported. */
 528         }
 529 }
 530
 531 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
 532 {
 533         if (R600_BIG_ENDIAN) {
 534                 switch(colorformat) {
 535                 case V_0280A0_COLOR_4_4:
 536                         return ENDIAN_NONE;
 537
 538                 /* 8-bit buffers. */
 539                 case V_0280A0_COLOR_8:
 540                         return ENDIAN_NONE;
 541
 542                 /* 16-bit buffers. */
 543                 case V_0280A0_COLOR_5_6_5:
 544                 case V_0280A0_COLOR_1_5_5_5:
 545                 case V_0280A0_COLOR_4_4_4_4:
 546                 case V_0280A0_COLOR_16:
 547                 case V_0280A0_COLOR_8_8:
 548                         return ENDIAN_8IN16;
 549
 550                 /* 32-bit buffers. */
 551                 case V_0280A0_COLOR_8_8_8_8:
 552                 case V_0280A0_COLOR_2_10_10_10:
 553                 case V_0280A0_COLOR_8_24:
 554                 case V_0280A0_COLOR_24_8:
 555                 case V_0280A0_COLOR_32_FLOAT:
 556                 case V_0280A0_COLOR_16_16_FLOAT:
 557                 case V_0280A0_COLOR_16_16:
 558                         return ENDIAN_8IN32;
 559
 560                 /* 64-bit buffers. */
 561                 case V_0280A0_COLOR_16_16_16_16:
 562                 case V_0280A0_COLOR_16_16_16_16_FLOAT:
 563                         return ENDIAN_8IN16;
 564
 565                 case V_0280A0_COLOR_32_32_FLOAT:
 566                 case V_0280A0_COLOR_32_32:
 567                 case V_0280A0_COLOR_X24_8_32_FLOAT:
 568                         return ENDIAN_8IN32;
 569
 570                 /* 128-bit buffers. */
 571                 case V_0280A0_COLOR_32_32_32_FLOAT:
 572                 case V_0280A0_COLOR_32_32_32_32_FLOAT:
 573                 case V_0280A0_COLOR_32_32_32_32:
 574                         return ENDIAN_8IN32;
 575                 default:
 576                         return ENDIAN_NONE; /* Unsupported. */
 577                 }
 578         } else {
 579                 return ENDIAN_NONE;
 580         }
 581 }
 582
 583 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
 584 {
 585         return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
 586 }
 587
 588 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
 589 {
 590         return r600_translate_colorformat(format) != ~0U &&
 591                r600_translate_colorswap(format) != ~0U;
 592 }
 593
 594 static bool r600_is_zs_format_supported(enum pipe_format format)
 595 {
 596         return r600_translate_dbformat(format) != ~0U;
 597 }
 598
 599 boolean r600_is_format_supported(struct pipe_screen *screen,
 600                                  enum pipe_format format,
 601                                  enum pipe_texture_target target,
 602                                  unsigned sample_count,
 603                                  unsigned usage)
 604 {
 605         unsigned retval = 0;
 606
 607         if (target >= PIPE_MAX_TEXTURE_TYPES) {
 608                 R600_ERR("r600: unsupported texture type %d\n", target);
 609                 return FALSE;
 610         }
 611
 612         if (!util_format_is_supported(format, usage))
 613                 return FALSE;
 614
 615         /* Multisample */
 616         if (sample_count > 1)
 617                 return FALSE;
 618
 619         if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
 620             r600_is_sampler_format_supported(screen, format)) {
 621                 retval |= PIPE_BIND_SAMPLER_VIEW;
 622         }
 623
 624         if ((usage & (PIPE_BIND_RENDER_TARGET |
 625                       PIPE_BIND_DISPLAY_TARGET |
 626                       PIPE_BIND_SCANOUT |
 627                       PIPE_BIND_SHARED)) &&
 628             r600_is_colorbuffer_format_supported(format)) {
 629                 retval |= usage &
 630                           (PIPE_BIND_RENDER_TARGET |
 631                            PIPE_BIND_DISPLAY_TARGET |
 632                            PIPE_BIND_SCANOUT |
 633                            PIPE_BIND_SHARED);
 634         }
 635
 636         if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
 637             r600_is_zs_format_supported(format)) {
 638                 retval |= PIPE_BIND_DEPTH_STENCIL;
 639         }
 640
 641         if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
 642             r600_is_vertex_format_supported(format)) {
 643                 retval |= PIPE_BIND_VERTEX_BUFFER;
 644         }
 645
 646         if (usage & PIPE_BIND_TRANSFER_READ)
 647                 retval |= PIPE_BIND_TRANSFER_READ;
 648         if (usage & PIPE_BIND_TRANSFER_WRITE)
 649                 retval |= PIPE_BIND_TRANSFER_WRITE;
 650
 651         return retval == usage;
 652 }
 653
 654 void r600_polygon_offset_update(struct r600_context *rctx)
 655 {
 656         struct r600_pipe_state state;
 657
 658         state.id = R600_PIPE_STATE_POLYGON_OFFSET;
 659         state.nregs = 0;
 660         if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
 661                 float offset_units = rctx->rasterizer->offset_units;
 662                 unsigned offset_db_fmt_cntl = 0, depth;
 663
 664                 switch (rctx->framebuffer.zsbuf->texture->format) {
 665                 case PIPE_FORMAT_Z24X8_UNORM:
 666                 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 667                         depth = -24;
 668                         offset_units *= 2.0f;
 669                         break;
 670                 case PIPE_FORMAT_Z32_FLOAT:
 671                 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 672                         depth = -23;
 673                         offset_units *= 1.0f;
 674                         offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
 675                         break;
 676                 case PIPE_FORMAT_Z16_UNORM:
 677                         depth = -16;
 678                         offset_units *= 4.0f;
 679                         break;
 680                 default:
 681                         return;
 682                 }
 683                 /* FIXME some of those reg can be computed with cso */
 684                 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
 685                 r600_pipe_state_add_reg(&state,
 686                                 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
 687                                 fui(rctx->rasterizer->offset_scale), NULL, 0);
 688                 r600_pipe_state_add_reg(&state,
 689                                 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
 690                                 fui(offset_units), NULL, 0);
 691                 r600_pipe_state_add_reg(&state,
 692                                 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
 693                                 fui(rctx->rasterizer->offset_scale), NULL, 0);
 694                 r600_pipe_state_add_reg(&state,
 695                                 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
 696                                 fui(offset_units), NULL, 0);
 697                 r600_pipe_state_add_reg(&state,
 698                                 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
 699                                 offset_db_fmt_cntl, NULL, 0);
 700                 r600_context_pipe_state_set(rctx, &state);
 701         }
 702 }
 703
 704 static void r600_set_blend_color(struct pipe_context *ctx,
 705                                         const struct pipe_blend_color *state)
 706 {
 707         struct r600_context *rctx = (struct r600_context *)ctx;
 708         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 709
 710         if (rstate == NULL)
 711                 return;
 712
 713         rstate->id = R600_PIPE_STATE_BLEND_COLOR;
 714         r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), NULL, 0);
 715         r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), NULL, 0);
 716         r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), NULL, 0);
 717         r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), NULL, 0);
 718         free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
 719         rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
 720         r600_context_pipe_state_set(rctx, rstate);
 721 }
 722
 723 static void *r600_create_blend_state(struct pipe_context *ctx,
 724                                         const struct pipe_blend_state *state)
 725 {
 726         struct r600_context *rctx = (struct r600_context *)ctx;
 727         struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
 728         struct r600_pipe_state *rstate;
 729         uint32_t color_control = 0, target_mask;
 730
 731         if (blend == NULL) {
 732                 return NULL;
 733         }
 734         rstate = &blend->rstate;
 735
 736         rstate->id = R600_PIPE_STATE_BLEND;
 737
 738         target_mask = 0;
 739
 740         /* R600 does not support per-MRT blends */
 741         if (rctx->family > CHIP_R600)
 742                 color_control |= S_028808_PER_MRT_BLEND(1);
 743         if (state->logicop_enable) {
 744                 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
 745         } else {
 746                 color_control |= (0xcc << 16);
 747         }
 748         /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
 749         if (state->independent_blend_enable) {
 750                 for (int i = 0; i < 8; i++) {
 751                         if (state->rt[i].blend_enable) {
 752                                 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
 753                         }
 754                         target_mask |= (state->rt[i].colormask << (4 * i));
 755                 }
 756         } else {
 757                 for (int i = 0; i < 8; i++) {
 758                         if (state->rt[0].blend_enable) {
 759                                 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
 760                         }
 761                         target_mask |= (state->rt[0].colormask << (4 * i));
 762                 }
 763         }
 764         blend->cb_target_mask = target_mask;
 765         blend->cb_color_control = color_control;
 766
 767         for (int i = 0; i < 8; i++) {
 768                 /* state->rt entries > 0 only written if independent blending */
 769                 const int j = state->independent_blend_enable ? i : 0;
 770
 771                 unsigned eqRGB = state->rt[j].rgb_func;
 772                 unsigned srcRGB = state->rt[j].rgb_src_factor;
 773                 unsigned dstRGB = state->rt[j].rgb_dst_factor;
 774
 775                 unsigned eqA = state->rt[j].alpha_func;
 776                 unsigned srcA = state->rt[j].alpha_src_factor;
 777                 unsigned dstA = state->rt[j].alpha_dst_factor;
 778                 uint32_t bc = 0;
 779
 780                 if (!state->rt[j].blend_enable)
 781                         continue;
 782
 783                 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
 784                 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
 785                 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
 786
 787                 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
 788                         bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
 789                         bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
 790                         bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
 791                         bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
 792                 }
 793
 794                 /* R600 does not support per-MRT blends */
 795                 if (rctx->family > CHIP_R600)
 796                         r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, NULL, 0);
 797                 if (i == 0)
 798                         r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, NULL, 0);
 799         }
 800         return rstate;
 801 }
 802
 803 static void *r600_create_dsa_state(struct pipe_context *ctx,
 804                                    const struct pipe_depth_stencil_alpha_state *state)
 805 {
 806         struct r600_context *rctx = (struct r600_context *)ctx;
 807         struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
 808         unsigned db_depth_control, alpha_test_control, alpha_ref;
 809         unsigned db_render_override, db_render_control;
 810         struct r600_pipe_state *rstate;
 811
 812         if (dsa == NULL) {
 813                 return NULL;
 814         }
 815
 816         dsa->valuemask[0] = state->stencil[0].valuemask;
 817         dsa->valuemask[1] = state->stencil[1].valuemask;
 818         dsa->writemask[0] = state->stencil[0].writemask;
 819         dsa->writemask[1] = state->stencil[1].writemask;
 820
 821         rstate = &dsa->rstate;
 822
 823         rstate->id = R600_PIPE_STATE_DSA;
 824         db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
 825                 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
 826                 S_028800_ZFUNC(state->depth.func);
 827
 828         /* stencil */
 829         if (state->stencil[0].enabled) {
 830                 db_depth_control |= S_028800_STENCIL_ENABLE(1);
 831                 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
 832                 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
 833                 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
 834                 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
 835
 836                 if (state->stencil[1].enabled) {
 837                         db_depth_control |= S_028800_BACKFACE_ENABLE(1);
 838                         db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
 839                         db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
 840                         db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
 841                         db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
 842                 }
 843         }
 844
 845         /* alpha */
 846         alpha_test_control = 0;
 847         alpha_ref = 0;
 848         if (state->alpha.enabled) {
 849                 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
 850                 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
 851                 alpha_ref = fui(state->alpha.ref_value);
 852         }
 853         dsa->alpha_ref = alpha_ref;
 854
 855         /* misc */
 856         db_render_control = 0;
 857         db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
 858                 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
 859                 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
 860         /* TODO db_render_override depends on query */
 861         r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, NULL, 0);
 862         r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, NULL, 0);
 863         r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, NULL, 0);
 864         r600_pipe_state_add_reg(rstate, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, NULL, 0);
 865         r600_pipe_state_add_reg(rstate, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, NULL, 0);
 866         r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, NULL, 0);
 867         r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, NULL, 0);
 868         r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, NULL, 0);
 869         r600_pipe_state_add_reg(rstate, R_028D10_DB_RENDER_OVERRIDE, db_render_override, NULL, 0);
 870         r600_pipe_state_add_reg(rstate, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, NULL, 0);
 871         r600_pipe_state_add_reg(rstate, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, NULL, 0);
 872         r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, NULL, 0);
 873
 874         dsa->db_render_override = db_render_override;
 875         dsa->db_render_control = db_render_control;
 876
 877         return rstate;
 878 }
 879
 880 static void *r600_create_rs_state(struct pipe_context *ctx,
 881                                   const struct pipe_rasterizer_state *state)
 882 {
 883         struct r600_context *rctx = (struct r600_context *)ctx;
 884         struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
 885         struct r600_pipe_state *rstate;
 886         unsigned tmp;
 887         unsigned prov_vtx = 1, polygon_dual_mode;
 888         unsigned clip_rule;
 889         unsigned sc_mode_cntl;
 890         float psize_min, psize_max;
 891
 892         if (rs == NULL) {
 893                 return NULL;
 894         }
 895
 896         polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
 897                                 state->fill_back != PIPE_POLYGON_MODE_FILL);
 898
 899         if (state->flatshade_first)
 900                 prov_vtx = 0;
 901
 902         rstate = &rs->rstate;
 903         rs->flatshade = state->flatshade;
 904         rs->sprite_coord_enable = state->sprite_coord_enable;
 905         rs->two_side = state->light_twoside;
 906         rs->clip_plane_enable = state->clip_plane_enable;
 907         rs->pa_sc_line_stipple = state->line_stipple_enable ?
 908                                 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
 909                                 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
 910         rs->pa_su_sc_mode_cntl =
 911                 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
 912                 S_028814_CULL_FRONT(state->rasterizer_discard || (state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
 913                 S_028814_CULL_BACK(state->rasterizer_discard || (state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
 914                 S_028814_FACE(!state->front_ccw) |
 915                 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
 916                 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
 917                 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
 918                 S_028814_POLY_MODE(polygon_dual_mode) |
 919                 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
 920                 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back));
 921         rs->pa_cl_clip_cntl =
 922                 S_028810_PS_UCP_MODE(3) |
 923                 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
 924                 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
 925                 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
 926
 927         clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
 928         /* offset */
 929         rs->offset_units = state->offset_units;
 930         rs->offset_scale = state->offset_scale * 12.0f;
 931
 932         rstate->id = R600_PIPE_STATE_RASTERIZER;
 933         tmp = S_0286D4_FLAT_SHADE_ENA(1);
 934         if (state->sprite_coord_enable) {
 935                 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
 936                         S_0286D4_PNT_SPRITE_OVRD_X(2) |
 937                         S_0286D4_PNT_SPRITE_OVRD_Y(3) |
 938                         S_0286D4_PNT_SPRITE_OVRD_Z(0) |
 939                         S_0286D4_PNT_SPRITE_OVRD_W(1);
 940                 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
 941                         tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
 942                 }
 943         }
 944         r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, NULL, 0);
 945
 946         r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, NULL, 0);
 947         /* point size 12.4 fixed point */
 948         tmp = (unsigned)(state->point_size * 8.0);
 949         r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), NULL, 0);
 950
 951         if (state->point_size_per_vertex) {
 952                 psize_min = util_get_min_point_size(state);
 953                 psize_max = 8192;
 954         } else {
 955                 /* Force the point size to be as if the vertex output was disabled. */
 956                 psize_min = state->point_size;
 957                 psize_max = state->point_size;
 958         }
 959         /* Divide by two, because 0.5 = 1 pixel. */
 960         r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
 961                                 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
 962                                 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)),
 963                                 NULL, 0);
 964
 965         tmp = (unsigned)state->line_width * 8;
 966         r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), NULL, 0);
 967
 968         if (rctx->chip_class >= R700)
 969                 sc_mode_cntl = 0x514002;
 970         else
 971                 sc_mode_cntl = 0x4102;
 972         sc_mode_cntl |= S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable);
 973
 974         r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl,
 975                                 NULL, 0);
 976         r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, NULL, 0);
 977         r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, NULL, 0);
 978
 979         r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
 980                                 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
 981                                 NULL, 0);
 982
 983         r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, NULL, 0);
 984         r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, NULL, 0);
 985         r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, NULL, 0);
 986         r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, NULL, 0);
 987         r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp), NULL, 0);
 988         r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, NULL, 0);
 989         return rstate;
 990 }
 991
 992 static void *r600_create_sampler_state(struct pipe_context *ctx,
 993                                         const struct pipe_sampler_state *state)
 994 {
 995         struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
 996         struct r600_pipe_state *rstate;
 997         union util_color uc;
 998         unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
 999
1000         if (ss == NULL) {
1001                 return NULL;
1002         }
1003
1004         ss->seamless_cube_map = state->seamless_cube_map;
1005         rstate = &ss->rstate;
1006         rstate->id = R600_PIPE_STATE_SAMPLER;
1007         util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
1008         r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
1009                                         S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
1010                                         S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
1011                                         S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
1012                                         S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
1013                                         S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
1014                                         S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
1015                                         S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
1016                                         S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
1017                                         S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), NULL, 0);
1018         r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
1019                                         S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
1020                                         S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
1021                                         S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), NULL, 0);
1022         r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), NULL, 0);
1023         if (uc.ui) {
1024                 r600_pipe_state_add_reg_noblock(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color.f[0]), NULL, 0);
1025                 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color.f[1]), NULL, 0);
1026                 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color.f[2]), NULL, 0);
1027                 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color.f[3]), NULL, 0);
1028         }
1029         return rstate;
1030 }
1031
1032 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
1033                                                         struct pipe_resource *texture,
1034                                                         const struct pipe_sampler_view *state)
1035 {
1036         struct r600_screen *rscreen = (struct r600_screen*)ctx->screen;
1037         struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
1038         struct r600_pipe_resource_state *rstate;
1039         struct r600_resource_texture *tmp = (struct r600_resource_texture*)texture;
1040         unsigned format, endian;
1041         uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1042         unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1043         unsigned width, height, depth, offset_level, last_level;
1044
1045         if (view == NULL)
1046                 return NULL;
1047         rstate = &view->state;
1048
1049         /* initialize base object */
1050         view->base = *state;
1051         view->base.texture = NULL;
1052         pipe_reference(NULL, &texture->reference);
1053         view->base.texture = texture;
1054         view->base.reference.count = 1;
1055         view->base.context = ctx;
1056
1057         swizzle[0] = state->swizzle_r;
1058         swizzle[1] = state->swizzle_g;
1059         swizzle[2] = state->swizzle_b;
1060         swizzle[3] = state->swizzle_a;
1061
1062         format = r600_translate_texformat(ctx->screen, state->format,
1063                                           swizzle,
1064                                           &word4, &yuv_format);
1065         if (format == ~0) {
1066                 format = 0;
1067         }
1068
1069         if (tmp->depth && !tmp->is_flushing_texture) {
1070                 r600_texture_depth_flush(ctx, texture, TRUE);
1071                 tmp = tmp->flushed_depth_texture;
1072         }
1073
1074         endian = r600_colorformat_endian_swap(format);
1075
1076         offset_level = state->u.tex.first_level;
1077         last_level = state->u.tex.last_level - offset_level;
1078         if (!rscreen->use_surface) {
1079                 width = u_minify(texture->width0, offset_level);
1080                 height = u_minify(texture->height0, offset_level);
1081                 depth = u_minify(texture->depth0, offset_level);
1082
1083                 pitch = align(tmp->pitch_in_blocks[offset_level] *
1084                                 util_format_get_blockwidth(state->format), 8);
1085                 array_mode = tmp->array_mode[offset_level];
1086                 tile_type = tmp->tile_type;
1087
1088                 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1089                         height = 1;
1090                         depth = texture->array_size;
1091                 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1092                         depth = texture->array_size;
1093                 }
1094
1095                 rstate->bo[0] = &tmp->resource;
1096                 rstate->bo[1] = &tmp->resource;
1097                 rstate->bo_usage[0] = RADEON_USAGE_READ;
1098                 rstate->bo_usage[1] = RADEON_USAGE_READ;
1099
1100                 rstate->val[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
1101                                 S_038000_TILE_MODE(array_mode) |
1102                                 S_038000_TILE_TYPE(tile_type) |
1103                                 S_038000_PITCH((pitch / 8) - 1) |
1104                                 S_038000_TEX_WIDTH(width - 1));
1105                 rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) |
1106                                 S_038004_TEX_DEPTH(depth - 1) |
1107                                 S_038004_DATA_FORMAT(format));
1108                 rstate->val[2] = tmp->offset[offset_level] >> 8;
1109                 rstate->val[3] = tmp->offset[offset_level+1] >> 8;
1110                 rstate->val[4] = (word4 |
1111                                 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1112                                 S_038010_REQUEST_SIZE(1) |
1113                                 S_038010_ENDIAN_SWAP(endian) |
1114                                 S_038010_BASE_LEVEL(0));
1115                 rstate->val[5] = (S_038014_LAST_LEVEL(last_level) |
1116                                 S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1117                                 S_038014_LAST_ARRAY(state->u.tex.last_layer));
1118                 rstate->val[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1119                                 S_038018_MAX_ANISO(4 /* max 16 samples */));
1120         } else {
1121                 width = tmp->surface.level[offset_level].npix_x;
1122                 height = tmp->surface.level[offset_level].npix_y;
1123                 depth = tmp->surface.level[offset_level].npix_z;
1124                 pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
1125                 tile_type = tmp->tile_type;
1126
1127                 if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1128                         height = 1;
1129                         depth = texture->array_size;
1130                 } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1131                         depth = texture->array_size;
1132                 }
1133                 switch (tmp->surface.level[offset_level].mode) {
1134                 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1135                         array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
1136                         break;
1137                 case RADEON_SURF_MODE_1D:
1138                         array_mode = V_038000_ARRAY_1D_TILED_THIN1;
1139                         break;
1140                 case RADEON_SURF_MODE_2D:
1141                         array_mode = V_038000_ARRAY_2D_TILED_THIN1;
1142                         break;
1143                 case RADEON_SURF_MODE_LINEAR:
1144                 default:
1145                         array_mode = V_038000_ARRAY_LINEAR_GENERAL;
1146                         break;
1147                 }
1148
1149                 rstate->bo[0] = &tmp->resource;
1150                 rstate->bo[1] = &tmp->resource;
1151                 rstate->bo_usage[0] = RADEON_USAGE_READ;
1152                 rstate->bo_usage[1] = RADEON_USAGE_READ;
1153
1154                 rstate->val[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
1155                                 S_038000_TILE_MODE(array_mode) |
1156                                 S_038000_TILE_TYPE(tile_type) |
1157                                 S_038000_PITCH((pitch / 8) - 1) |
1158                                 S_038000_TEX_WIDTH(width - 1));
1159                 rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) |
1160                                 S_038004_TEX_DEPTH(depth - 1) |
1161                                 S_038004_DATA_FORMAT(format));
1162                 rstate->val[2] = tmp->surface.level[offset_level].offset >> 8;
1163                 if (offset_level >= tmp->surface.last_level) {
1164                         rstate->val[3] = tmp->surface.level[offset_level].offset >> 8;
1165                 } else {
1166                         rstate->val[3] = tmp->surface.level[offset_level + 1].offset >> 8;
1167                 }
1168                 rstate->val[4] = (word4 |
1169                                 S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1170                                 S_038010_REQUEST_SIZE(1) |
1171                                 S_038010_ENDIAN_SWAP(endian) |
1172                                 S_038010_BASE_LEVEL(0));
1173                 rstate->val[5] = (S_038014_LAST_LEVEL(last_level) |
1174                                 S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1175                                 S_038014_LAST_ARRAY(state->u.tex.last_layer));
1176                 rstate->val[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1177                                 S_038018_MAX_ANISO(4 /* max 16 samples */));
1178         }
1179         return &view->base;
1180 }
1181
1182 static void r600_set_sampler_views(struct r600_context *rctx,
1183                                    struct r600_textures_info *dst,
1184                                    unsigned count,
1185                                    struct pipe_sampler_view **views,
1186                                    void (*set_resource)(struct r600_context*, struct r600_pipe_resource_state*, unsigned))
1187 {
1188         struct r600_pipe_sampler_view **rviews = (struct r600_pipe_sampler_view **)views;
1189         unsigned i;
1190
1191         if (count)
1192                 r600_inval_texture_cache(rctx);
1193
1194         for (i = 0; i < count; i++) {
1195                 if (rviews[i]) {
1196                         if (((struct r600_resource_texture *)rviews[i]->base.texture)->depth)
1197                                 rctx->have_depth_texture = true;
1198
1199                         /* Changing from array to non-arrays textures and vice versa requires updating TEX_ARRAY_OVERRIDE. */
1200                         if ((rviews[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
1201                              rviews[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) != dst->is_array_sampler[i])
1202                                 dst->samplers_dirty = true;
1203
1204                         set_resource(rctx, &rviews[i]->state, i + R600_MAX_CONST_BUFFERS);
1205                 } else {
1206                         set_resource(rctx, NULL, i + R600_MAX_CONST_BUFFERS);
1207                 }
1208
1209                 pipe_sampler_view_reference(
1210                         (struct pipe_sampler_view **)&dst->views[i],
1211                         views[i]);
1212         }
1213
1214         for (i = count; i < dst->n_views; i++) {
1215                 if (dst->views[i]) {
1216                         set_resource(rctx, NULL, i + R600_MAX_CONST_BUFFERS);
1217                         pipe_sampler_view_reference((struct pipe_sampler_view **)&dst->views[i], NULL);
1218                 }
1219         }
1220
1221         dst->n_views = count;
1222 }
1223
1224 static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
1225                                       struct pipe_sampler_view **views)
1226 {
1227         struct r600_context *rctx = (struct r600_context *)ctx;
1228         r600_set_sampler_views(rctx, &rctx->vs_samplers, count, views,
1229                                r600_context_pipe_state_set_vs_resource);
1230 }
1231
1232 static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
1233                                       struct pipe_sampler_view **views)
1234 {
1235         struct r600_context *rctx = (struct r600_context *)ctx;
1236         r600_set_sampler_views(rctx, &rctx->ps_samplers, count, views,
1237                                r600_context_pipe_state_set_ps_resource);
1238 }
1239
1240 static void r600_set_seamless_cubemap(struct r600_context *rctx, boolean enable)
1241 {
1242         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1243         if (rstate == NULL)
1244                 return;
1245
1246         rstate->id = R600_PIPE_STATE_SEAMLESS_CUBEMAP;
1247         r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
1248                                 (enable ? 0 : S_009508_DISABLE_CUBE_WRAP(1)) |
1249                                 S_009508_DISABLE_CUBE_ANISO(1) |
1250                                 S_009508_SYNC_GRADIENT(1) |
1251                                 S_009508_SYNC_WALKER(1) |
1252                                 S_009508_SYNC_ALIGNER(1),
1253                                 NULL, 0);
1254
1255         free(rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP]);
1256         rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP] = rstate;
1257         r600_context_pipe_state_set(rctx, rstate);
1258 }
1259
1260 static void r600_bind_samplers(struct r600_context *rctx,
1261                                struct r600_textures_info *dst,
1262                                unsigned count, void **states)
1263 {
1264         memcpy(dst->samplers, states, sizeof(void*) * count);
1265         dst->n_samplers = count;
1266         dst->samplers_dirty = true;
1267 }
1268
1269 static void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states)
1270 {
1271         struct r600_context *rctx = (struct r600_context *)ctx;
1272         r600_bind_samplers(rctx, &rctx->vs_samplers, count, states);
1273 }
1274
1275 static void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states)
1276 {
1277         struct r600_context *rctx = (struct r600_context *)ctx;
1278         r600_bind_samplers(rctx, &rctx->ps_samplers, count, states);
1279 }
1280
1281 static void r600_update_samplers(struct r600_context *rctx,
1282                                  struct r600_textures_info *tex,
1283                                  void (*set_sampler)(struct r600_context*, struct r600_pipe_state*, unsigned))
1284 {
1285         unsigned i;
1286
1287         if (tex->samplers_dirty) {
1288                 int seamless = -1;
1289                 for (i = 0; i < tex->n_samplers; i++) {
1290                         if (!tex->samplers[i])
1291                                 continue;
1292
1293                         /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1294                          * filtering between layers.
1295                          * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view. */
1296                         if (tex->views[i]) {
1297                                 if (tex->views[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
1298                                     tex->views[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) {
1299                                         tex->samplers[i]->rstate.regs[0].value |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1300                                         tex->is_array_sampler[i] = true;
1301                                 } else {
1302                                         tex->samplers[i]->rstate.regs[0].value &= C_03C000_TEX_ARRAY_OVERRIDE;
1303                                         tex->is_array_sampler[i] = false;
1304                                 }
1305                         }
1306
1307                         set_sampler(rctx, &tex->samplers[i]->rstate, i);
1308
1309                         if (tex->samplers[i])
1310                                 seamless = tex->samplers[i]->seamless_cube_map;
1311                 }
1312
1313                 if (seamless != -1)
1314                         r600_set_seamless_cubemap(rctx, seamless);
1315
1316                 tex->samplers_dirty = false;
1317         }
1318 }
1319
1320 void r600_update_sampler_states(struct r600_context *rctx)
1321 {
1322         r600_update_samplers(rctx, &rctx->vs_samplers,
1323                              r600_context_pipe_state_set_vs_sampler);
1324         r600_update_samplers(rctx, &rctx->ps_samplers,
1325                              r600_context_pipe_state_set_ps_sampler);
1326 }
1327
1328 static void r600_set_clip_state(struct pipe_context *ctx,
1329                                 const struct pipe_clip_state *state)
1330 {
1331         struct r600_context *rctx = (struct r600_context *)ctx;
1332         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1333         struct pipe_resource * cbuf;
1334
1335         if (rstate == NULL)
1336                 return;
1337
1338         rctx->clip = *state;
1339         rstate->id = R600_PIPE_STATE_CLIP;
1340         for (int i = 0; i < 6; i++) {
1341                 r600_pipe_state_add_reg(rstate,
1342                                         R_028E20_PA_CL_UCP0_X + i * 16,
1343                                         fui(state->ucp[i][0]), NULL, 0);
1344                 r600_pipe_state_add_reg(rstate,
1345                                         R_028E24_PA_CL_UCP0_Y + i * 16,
1346                                         fui(state->ucp[i][1]) , NULL, 0);
1347                 r600_pipe_state_add_reg(rstate,
1348                                         R_028E28_PA_CL_UCP0_Z + i * 16,
1349                                         fui(state->ucp[i][2]), NULL, 0);
1350                 r600_pipe_state_add_reg(rstate,
1351                                         R_028E2C_PA_CL_UCP0_W + i * 16,
1352                                         fui(state->ucp[i][3]), NULL, 0);
1353         }
1354
1355         free(rctx->states[R600_PIPE_STATE_CLIP]);
1356         rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1357         r600_context_pipe_state_set(rctx, rstate);
1358
1359         cbuf = pipe_user_buffer_create(ctx->screen,
1360                                    state->ucp,
1361                                    4*4*8, /* 8*4 floats */
1362                                    PIPE_BIND_CONSTANT_BUFFER);
1363         r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, cbuf);
1364         pipe_resource_reference(&cbuf, NULL);
1365 }
1366
1367 static void r600_set_polygon_stipple(struct pipe_context *ctx,
1368                                          const struct pipe_poly_stipple *state)
1369 {
1370 }
1371
1372 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1373 {
1374 }
1375
1376 static void r600_set_scissor_state(struct pipe_context *ctx,
1377                                         const struct pipe_scissor_state *state)
1378 {
1379         struct r600_context *rctx = (struct r600_context *)ctx;
1380         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1381         uint32_t tl, br;
1382
1383         if (rstate == NULL)
1384                 return;
1385
1386         rstate->id = R600_PIPE_STATE_SCISSOR;
1387         tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
1388         br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1389         r600_pipe_state_add_reg(rstate,
1390                                 R_028210_PA_SC_CLIPRECT_0_TL, tl,
1391                                 NULL, 0);
1392         r600_pipe_state_add_reg(rstate,
1393                                 R_028214_PA_SC_CLIPRECT_0_BR, br,
1394                                 NULL, 0);
1395         r600_pipe_state_add_reg(rstate,
1396                                 R_028218_PA_SC_CLIPRECT_1_TL, tl,
1397                                 NULL, 0);
1398         r600_pipe_state_add_reg(rstate,
1399                                 R_02821C_PA_SC_CLIPRECT_1_BR, br,
1400                                 NULL, 0);
1401         r600_pipe_state_add_reg(rstate,
1402                                 R_028220_PA_SC_CLIPRECT_2_TL, tl,
1403                                 NULL, 0);
1404         r600_pipe_state_add_reg(rstate,
1405                                 R_028224_PA_SC_CLIPRECT_2_BR, br,
1406                                 NULL, 0);
1407         r600_pipe_state_add_reg(rstate,
1408                                 R_028228_PA_SC_CLIPRECT_3_TL, tl,
1409                                 NULL, 0);
1410         r600_pipe_state_add_reg(rstate,
1411                                 R_02822C_PA_SC_CLIPRECT_3_BR, br,
1412                                 NULL, 0);
1413
1414         free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1415         rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1416         r600_context_pipe_state_set(rctx, rstate);
1417 }
1418
1419 static void r600_set_viewport_state(struct pipe_context *ctx,
1420                                         const struct pipe_viewport_state *state)
1421 {
1422         struct r600_context *rctx = (struct r600_context *)ctx;
1423         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1424
1425         if (rstate == NULL)
1426                 return;
1427
1428         rctx->viewport = *state;
1429         rstate->id = R600_PIPE_STATE_VIEWPORT;
1430         r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, NULL, 0);
1431         r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, NULL, 0);
1432         r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), NULL, 0);
1433         r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), NULL, 0);
1434         r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), NULL, 0);
1435         r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), NULL, 0);
1436         r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), NULL, 0);
1437         r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), NULL, 0);
1438         r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, NULL, 0);
1439
1440         free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1441         rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1442         r600_context_pipe_state_set(rctx, rstate);
1443 }
1444
1445 static void r600_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
1446                         const struct pipe_framebuffer_state *state, int cb)
1447 {
1448         struct r600_screen *rscreen = rctx->screen;
1449         struct r600_resource_texture *rtex;
1450         struct r600_surface *surf;
1451         unsigned level = state->cbufs[cb]->u.tex.level;
1452         unsigned pitch, slice;
1453         unsigned color_info;
1454         unsigned format, swap, ntype, endian;
1455         unsigned offset;
1456         const struct util_format_description *desc;
1457         int i;
1458         unsigned blend_bypass = 0, blend_clamp = 1;
1459
1460         surf = (struct r600_surface *)state->cbufs[cb];
1461         rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1462
1463         if (rtex->depth)
1464                 rctx->have_depth_fb = TRUE;
1465
1466         if (rtex->depth && !rtex->is_flushing_texture) {
1467                 rtex = rtex->flushed_depth_texture;
1468         }
1469
1470         /* XXX quite sure for dx10+ hw don't need any offset hacks */
1471         if (!rscreen->use_surface) {
1472                 offset = r600_texture_get_offset(rtex,
1473                                                  level, state->cbufs[cb]->u.tex.first_layer);
1474                 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1475                 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64;
1476                 if (slice) {
1477                         slice = slice - 1;
1478                 }
1479                 color_info = S_0280A0_ARRAY_MODE(rtex->array_mode[level]);
1480         } else {
1481                 offset = rtex->surface.level[level].offset;
1482                 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1483                         offset += rtex->surface.level[level].slice_size *
1484                                   state->cbufs[cb]->u.tex.first_layer;
1485                 }
1486                 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1487                 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1488                 if (slice) {
1489                         slice = slice - 1;
1490                 }
1491                 color_info = 0;
1492                 switch (rtex->surface.level[level].mode) {
1493                 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1494                         color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
1495                         break;
1496                 case RADEON_SURF_MODE_1D:
1497                         color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1498                         break;
1499                 case RADEON_SURF_MODE_2D:
1500                         color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1501                         break;
1502                 case RADEON_SURF_MODE_LINEAR:
1503                 default:
1504                         color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
1505                         break;
1506                 }
1507         }
1508         desc = util_format_description(surf->base.format);
1509
1510         for (i = 0; i < 4; i++) {
1511                 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1512                         break;
1513                 }
1514         }
1515
1516         ntype = V_0280A0_NUMBER_UNORM;
1517         if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1518                 ntype = V_0280A0_NUMBER_SRGB;
1519         else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1520                 if (desc->channel[i].normalized)
1521                         ntype = V_0280A0_NUMBER_SNORM;
1522                 else if (desc->channel[i].pure_integer)
1523                         ntype = V_0280A0_NUMBER_SINT;
1524         } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1525                 if (desc->channel[i].normalized)
1526                         ntype = V_0280A0_NUMBER_UNORM;
1527                 else if (desc->channel[i].pure_integer)
1528                         ntype = V_0280A0_NUMBER_UINT;
1529         }
1530
1531         format = r600_translate_colorformat(surf->base.format);
1532         swap = r600_translate_colorswap(surf->base.format);
1533         if(rtex->resource.b.b.b.usage == PIPE_USAGE_STAGING) {
1534                 endian = ENDIAN_NONE;
1535         } else {
1536                 endian = r600_colorformat_endian_swap(format);
1537         }
1538
1539         /* set blend bypass according to docs if SINT/UINT or
1540            8/24 COLOR variants */
1541         if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
1542             format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
1543             format == V_0280A0_COLOR_X24_8_32_FLOAT) {
1544                 blend_clamp = 0;
1545                 blend_bypass = 1;
1546         }
1547
1548         color_info |= S_0280A0_FORMAT(format) |
1549                 S_0280A0_COMP_SWAP(swap) |
1550                 S_0280A0_BLEND_BYPASS(blend_bypass) |
1551                 S_0280A0_BLEND_CLAMP(blend_clamp) |
1552                 S_0280A0_NUMBER_TYPE(ntype) |
1553                 S_0280A0_ENDIAN(endian);
1554
1555         /* EXPORT_NORM is an optimzation that can be enabled for better
1556          * performance in certain cases
1557          */
1558         if (rctx->chip_class == R600) {
1559                 /* EXPORT_NORM can be enabled if:
1560                  * - 11-bit or smaller UNORM/SNORM/SRGB
1561                  * - BLEND_CLAMP is enabled
1562                  * - BLEND_FLOAT32 is disabled
1563                  */
1564                 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1565                     (desc->channel[i].size < 12 &&
1566                      desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1567                      ntype != V_0280A0_NUMBER_UINT &&
1568                      ntype != V_0280A0_NUMBER_SINT) &&
1569                     G_0280A0_BLEND_CLAMP(color_info) &&
1570                     !G_0280A0_BLEND_FLOAT32(color_info))
1571                         color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1572         } else {
1573                 /* EXPORT_NORM can be enabled if:
1574                  * - 11-bit or smaller UNORM/SNORM/SRGB
1575                  * - 16-bit or smaller FLOAT
1576                  */
1577                 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1578                     ((desc->channel[i].size < 12 &&
1579                       desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1580                       ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1581                     (desc->channel[i].size < 17 &&
1582                      desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT)))
1583                         color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1584         }
1585
1586         r600_pipe_state_add_reg(rstate,
1587                                 R_028040_CB_COLOR0_BASE + cb * 4,
1588                                 offset >> 8, &rtex->resource, RADEON_USAGE_READWRITE);
1589         r600_pipe_state_add_reg(rstate,
1590                                 R_0280A0_CB_COLOR0_INFO + cb * 4,
1591                                 color_info, &rtex->resource, RADEON_USAGE_READWRITE);
1592         r600_pipe_state_add_reg(rstate,
1593                                 R_028060_CB_COLOR0_SIZE + cb * 4,
1594                                 S_028060_PITCH_TILE_MAX(pitch) |
1595                                 S_028060_SLICE_TILE_MAX(slice),
1596                                 NULL, 0);
1597         if (!rscreen->use_surface) {
1598                 r600_pipe_state_add_reg(rstate,
1599                                         R_028080_CB_COLOR0_VIEW + cb * 4,
1600                                         0x00000000, NULL, 0);
1601         } else {
1602                 if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1603                         r600_pipe_state_add_reg(rstate,
1604                                                 R_028080_CB_COLOR0_VIEW + cb * 4,
1605                                                 0x00000000, NULL, 0);
1606                 } else {
1607                         r600_pipe_state_add_reg(rstate,
1608                                                 R_028080_CB_COLOR0_VIEW + cb * 4,
1609                                                 S_028080_SLICE_START(state->cbufs[cb]->u.tex.first_layer) |
1610                                                 S_028080_SLICE_MAX(state->cbufs[cb]->u.tex.last_layer),
1611                                                 NULL, 0);
1612                 }
1613         }
1614         r600_pipe_state_add_reg(rstate,
1615                                 R_0280E0_CB_COLOR0_FRAG + cb * 4,
1616                                 0, &rtex->resource, RADEON_USAGE_READWRITE);
1617         r600_pipe_state_add_reg(rstate,
1618                                 R_0280C0_CB_COLOR0_TILE + cb * 4,
1619                                 0, &rtex->resource, RADEON_USAGE_READWRITE);
1620         r600_pipe_state_add_reg(rstate,
1621                                 R_028100_CB_COLOR0_MASK + cb * 4,
1622                                 0x00000000, NULL, 0);
1623 }
1624
1625 static void r600_db(struct r600_context *rctx, struct r600_pipe_state *rstate,
1626                         const struct pipe_framebuffer_state *state)
1627 {
1628         struct r600_screen *rscreen = rctx->screen;
1629         struct r600_resource_texture *rtex;
1630         struct r600_surface *surf;
1631         unsigned level, pitch, slice, format, offset, array_mode;
1632
1633         if (state->zsbuf == NULL)
1634                 return;
1635
1636         level = state->zsbuf->u.tex.level;
1637
1638         surf = (struct r600_surface *)state->zsbuf;
1639         rtex = (struct r600_resource_texture*)state->zsbuf->texture;
1640
1641         if (!rscreen->use_surface) {
1642                 /* XXX remove this once tiling is properly supported */
1643                 array_mode = rtex->array_mode[level] ? rtex->array_mode[level] :
1644                         V_0280A0_ARRAY_1D_TILED_THIN1;
1645
1646                 /* XXX quite sure for dx10+ hw don't need any offset hacks */
1647                 offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
1648                                 level, state->zsbuf->u.tex.first_layer);
1649                 pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1650                 slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64;
1651                 if (slice) {
1652                         slice = slice - 1;
1653                 }
1654         } else {
1655                 offset = rtex->surface.level[level].offset;
1656                 pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1657                 slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1658                 if (slice) {
1659                         slice = slice - 1;
1660                 }
1661                 switch (rtex->surface.level[level].mode) {
1662                 case RADEON_SURF_MODE_2D:
1663                         array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1664                         break;
1665                 case RADEON_SURF_MODE_1D:
1666                 case RADEON_SURF_MODE_LINEAR_ALIGNED:
1667                 case RADEON_SURF_MODE_LINEAR:
1668                 default:
1669                         array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1670                         break;
1671                 }
1672         }
1673
1674         format = r600_translate_dbformat(state->zsbuf->texture->format);
1675
1676         r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE,
1677                                 offset >> 8, &rtex->resource, RADEON_USAGE_READWRITE);
1678         r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
1679                                 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
1680                                 NULL, 0);
1681         if (!rscreen->use_surface) {
1682                 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, NULL, 0);
1683         } else {
1684                 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW,
1685                                         S_028004_SLICE_START(state->zsbuf->u.tex.first_layer) |
1686                                         S_028004_SLICE_MAX(state->zsbuf->u.tex.last_layer),
1687                                         NULL, 0);
1688         }
1689         r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO,
1690                                 S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format),
1691                                 &rtex->resource, RADEON_USAGE_READWRITE);
1692         r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
1693                                 (surf->aligned_height / 8) - 1, NULL, 0);
1694 }
1695
1696 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1697                                         const struct pipe_framebuffer_state *state)
1698 {
1699         struct r600_context *rctx = (struct r600_context *)ctx;
1700         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1701         uint32_t shader_mask, tl, br, shader_control;
1702
1703         if (rstate == NULL)
1704                 return;
1705
1706         r600_flush_framebuffer(rctx, false);
1707
1708         /* unreference old buffer and reference new one */
1709         rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1710
1711         util_copy_framebuffer_state(&rctx->framebuffer, state);
1712
1713         /* build states */
1714         rctx->have_depth_fb = 0;
1715         for (int i = 0; i < state->nr_cbufs; i++) {
1716                 r600_cb(rctx, rstate, state, i);
1717         }
1718         if (state->zsbuf) {
1719                 r600_db(rctx, rstate, state);
1720         }
1721
1722         shader_mask = 0;
1723         shader_control = 0;
1724         for (int i = 0; i < state->nr_cbufs; i++) {
1725                 shader_mask |= 0xf << (i * 4);
1726                 shader_control |= 1 << i;
1727         }
1728         tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1729         br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1730
1731         r600_pipe_state_add_reg(rstate,
1732                                 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1733                                 NULL, 0);
1734         r600_pipe_state_add_reg(rstate,
1735                                 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1736                                 NULL, 0);
1737         r600_pipe_state_add_reg(rstate,
1738                                 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1739                                 NULL, 0);
1740         r600_pipe_state_add_reg(rstate,
1741                                 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1742                                 NULL, 0);
1743         r600_pipe_state_add_reg(rstate,
1744                                 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1745                                 NULL, 0);
1746         r600_pipe_state_add_reg(rstate,
1747                                 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1748                                 NULL, 0);
1749         r600_pipe_state_add_reg(rstate,
1750                                 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1751                                 NULL, 0);
1752         r600_pipe_state_add_reg(rstate,
1753                                 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1754                                 NULL, 0);
1755         r600_pipe_state_add_reg(rstate,
1756                                 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1757                                 NULL, 0);
1758         if (rctx->chip_class >= R700) {
1759                 r600_pipe_state_add_reg(rstate,
1760                                         R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1761                                         NULL, 0);
1762         }
1763
1764         r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1765                                 shader_control, NULL, 0);
1766         r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1767                                 shader_mask, NULL, 0);
1768         r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1769                                 0x00000000, NULL, 0);
1770         r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
1771                                 0x00000000, NULL, 0);
1772         r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
1773                                 0x00000000, NULL, 0);
1774         r600_pipe_state_add_reg(rstate, R_028C30_CB_CLRCMP_CONTROL,
1775                                 0x01000000, NULL, 0);
1776         r600_pipe_state_add_reg(rstate, R_028C34_CB_CLRCMP_SRC,
1777                                 0x00000000, NULL, 0);
1778         r600_pipe_state_add_reg(rstate, R_028C38_CB_CLRCMP_DST,
1779                                 0x000000FF, NULL, 0);
1780         r600_pipe_state_add_reg(rstate, R_028C3C_CB_CLRCMP_MSK,
1781                                 0xFFFFFFFF, NULL, 0);
1782         r600_pipe_state_add_reg(rstate, R_028C48_PA_SC_AA_MASK,
1783                                 0xFFFFFFFF, NULL, 0);
1784
1785         free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1786         rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1787         r600_context_pipe_state_set(rctx, rstate);
1788
1789         if (state->zsbuf) {
1790                 r600_polygon_offset_update(rctx);
1791         }
1792 }
1793
1794 void r600_init_state_functions(struct r600_context *rctx)
1795 {
1796         rctx->context.create_blend_state = r600_create_blend_state;
1797         rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
1798         rctx->context.create_fs_state = r600_create_shader_state;
1799         rctx->context.create_rasterizer_state = r600_create_rs_state;
1800         rctx->context.create_sampler_state = r600_create_sampler_state;
1801         rctx->context.create_sampler_view = r600_create_sampler_view;
1802         rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1803         rctx->context.create_vs_state = r600_create_shader_state;
1804         rctx->context.bind_blend_state = r600_bind_blend_state;
1805         rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1806         rctx->context.bind_fragment_sampler_states = r600_bind_ps_samplers;
1807         rctx->context.bind_fs_state = r600_bind_ps_shader;
1808         rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1809         rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1810         rctx->context.bind_vertex_sampler_states = r600_bind_vs_samplers;
1811         rctx->context.bind_vs_state = r600_bind_vs_shader;
1812         rctx->context.delete_blend_state = r600_delete_state;
1813         rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1814         rctx->context.delete_fs_state = r600_delete_ps_shader;
1815         rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1816         rctx->context.delete_sampler_state = r600_delete_state;
1817         rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1818         rctx->context.delete_vs_state = r600_delete_vs_shader;
1819         rctx->context.set_blend_color = r600_set_blend_color;
1820         rctx->context.set_clip_state = r600_set_clip_state;
1821         rctx->context.set_constant_buffer = r600_set_constant_buffer;
1822         rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views;
1823         rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1824         rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1825         rctx->context.set_sample_mask = r600_set_sample_mask;
1826         rctx->context.set_scissor_state = r600_set_scissor_state;
1827         rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
1828         rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1829         rctx->context.set_index_buffer = r600_set_index_buffer;
1830         rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
1831         rctx->context.set_viewport_state = r600_set_viewport_state;
1832         rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1833         rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1834         rctx->context.texture_barrier = r600_texture_barrier;
1835         rctx->context.create_stream_output_target = r600_create_so_target;
1836         rctx->context.stream_output_target_destroy = r600_so_target_destroy;
1837         rctx->context.set_stream_output_targets = r600_set_so_targets;
1838 }
1839
1840 void r600_adjust_gprs(struct r600_context *rctx)
1841 {
1842         struct r600_pipe_state rstate;
1843         unsigned num_ps_gprs = rctx->default_ps_gprs;
1844         unsigned num_vs_gprs = rctx->default_vs_gprs;
1845         unsigned tmp;
1846         int diff;
1847
1848         if (rctx->chip_class >= EVERGREEN)
1849                 return;
1850
1851         if (!rctx->ps_shader || !rctx->vs_shader)
1852                 return;
1853
1854         if (rctx->ps_shader->shader.bc.ngpr > rctx->default_ps_gprs)
1855         {
1856                 diff = rctx->ps_shader->shader.bc.ngpr - rctx->default_ps_gprs;
1857                 num_vs_gprs -= diff;
1858                 num_ps_gprs += diff;
1859         }
1860
1861         if (rctx->vs_shader->shader.bc.ngpr > rctx->default_vs_gprs)
1862         {
1863                 diff = rctx->vs_shader->shader.bc.ngpr - rctx->default_vs_gprs;
1864                 num_ps_gprs -= diff;
1865                 num_vs_gprs += diff;
1866         }
1867
1868         tmp = 0;
1869         tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1870         tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1871         tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs);
1872         rstate.nregs = 0;
1873         r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, NULL, 0);
1874
1875         r600_context_pipe_state_set(rctx, &rstate);
1876 }
1877
1878 void r600_init_config(struct r600_context *rctx)
1879 {
1880         int ps_prio;
1881         int vs_prio;
1882         int gs_prio;
1883         int es_prio;
1884         int num_ps_gprs;
1885         int num_vs_gprs;
1886         int num_gs_gprs;
1887         int num_es_gprs;
1888         int num_temp_gprs;
1889         int num_ps_threads;
1890         int num_vs_threads;
1891         int num_gs_threads;
1892         int num_es_threads;
1893         int num_ps_stack_entries;
1894         int num_vs_stack_entries;
1895         int num_gs_stack_entries;
1896         int num_es_stack_entries;
1897         enum radeon_family family;
1898         struct r600_pipe_state *rstate = &rctx->config;
1899         uint32_t tmp;
1900
1901         family = rctx->family;
1902         ps_prio = 0;
1903         vs_prio = 1;
1904         gs_prio = 2;
1905         es_prio = 3;
1906         switch (family) {
1907         case CHIP_R600:
1908                 num_ps_gprs = 192;
1909                 num_vs_gprs = 56;
1910                 num_temp_gprs = 4;
1911                 num_gs_gprs = 0;
1912                 num_es_gprs = 0;
1913                 num_ps_threads = 136;
1914                 num_vs_threads = 48;
1915                 num_gs_threads = 4;
1916                 num_es_threads = 4;
1917                 num_ps_stack_entries = 128;
1918                 num_vs_stack_entries = 128;
1919                 num_gs_stack_entries = 0;
1920                 num_es_stack_entries = 0;
1921                 break;
1922         case CHIP_RV630:
1923         case CHIP_RV635:
1924                 num_ps_gprs = 84;
1925                 num_vs_gprs = 36;
1926                 num_temp_gprs = 4;
1927                 num_gs_gprs = 0;
1928                 num_es_gprs = 0;
1929                 num_ps_threads = 144;
1930                 num_vs_threads = 40;
1931                 num_gs_threads = 4;
1932                 num_es_threads = 4;
1933                 num_ps_stack_entries = 40;
1934                 num_vs_stack_entries = 40;
1935                 num_gs_stack_entries = 32;
1936                 num_es_stack_entries = 16;
1937                 break;
1938         case CHIP_RV610:
1939         case CHIP_RV620:
1940         case CHIP_RS780:
1941         case CHIP_RS880:
1942         default:
1943                 num_ps_gprs = 84;
1944                 num_vs_gprs = 36;
1945                 num_temp_gprs = 4;
1946                 num_gs_gprs = 0;
1947                 num_es_gprs = 0;
1948                 num_ps_threads = 136;
1949                 num_vs_threads = 48;
1950                 num_gs_threads = 4;
1951                 num_es_threads = 4;
1952                 num_ps_stack_entries = 40;
1953                 num_vs_stack_entries = 40;
1954                 num_gs_stack_entries = 32;
1955                 num_es_stack_entries = 16;
1956                 break;
1957         case CHIP_RV670:
1958                 num_ps_gprs = 144;
1959                 num_vs_gprs = 40;
1960                 num_temp_gprs = 4;
1961                 num_gs_gprs = 0;
1962                 num_es_gprs = 0;
1963                 num_ps_threads = 136;
1964                 num_vs_threads = 48;
1965                 num_gs_threads = 4;
1966                 num_es_threads = 4;
1967                 num_ps_stack_entries = 40;
1968                 num_vs_stack_entries = 40;
1969                 num_gs_stack_entries = 32;
1970                 num_es_stack_entries = 16;
1971                 break;
1972         case CHIP_RV770:
1973                 num_ps_gprs = 192;
1974                 num_vs_gprs = 56;
1975                 num_temp_gprs = 4;
1976                 num_gs_gprs = 0;
1977                 num_es_gprs = 0;
1978                 num_ps_threads = 188;
1979                 num_vs_threads = 60;
1980                 num_gs_threads = 0;
1981                 num_es_threads = 0;
1982                 num_ps_stack_entries = 256;
1983                 num_vs_stack_entries = 256;
1984                 num_gs_stack_entries = 0;
1985                 num_es_stack_entries = 0;
1986                 break;
1987         case CHIP_RV730:
1988         case CHIP_RV740:
1989                 num_ps_gprs = 84;
1990                 num_vs_gprs = 36;
1991                 num_temp_gprs = 4;
1992                 num_gs_gprs = 0;
1993                 num_es_gprs = 0;
1994                 num_ps_threads = 188;
1995                 num_vs_threads = 60;
1996                 num_gs_threads = 0;
1997                 num_es_threads = 0;
1998                 num_ps_stack_entries = 128;
1999                 num_vs_stack_entries = 128;
2000                 num_gs_stack_entries = 0;
2001                 num_es_stack_entries = 0;
2002                 break;
2003         case CHIP_RV710:
2004                 num_ps_gprs = 192;
2005                 num_vs_gprs = 56;
2006                 num_temp_gprs = 4;
2007                 num_gs_gprs = 0;
2008                 num_es_gprs = 0;
2009                 num_ps_threads = 144;
2010                 num_vs_threads = 48;
2011                 num_gs_threads = 0;
2012                 num_es_threads = 0;
2013                 num_ps_stack_entries = 128;
2014                 num_vs_stack_entries = 128;
2015                 num_gs_stack_entries = 0;
2016                 num_es_stack_entries = 0;
2017                 break;
2018         }
2019
2020         rctx->default_ps_gprs = num_ps_gprs;
2021         rctx->default_vs_gprs = num_vs_gprs;
2022
2023         rstate->id = R600_PIPE_STATE_CONFIG;
2024
2025         /* SQ_CONFIG */
2026         tmp = 0;
2027         switch (family) {
2028         case CHIP_RV610:
2029         case CHIP_RV620:
2030         case CHIP_RS780:
2031         case CHIP_RS880:
2032         case CHIP_RV710:
2033                 break;
2034         default:
2035                 tmp |= S_008C00_VC_ENABLE(1);
2036                 break;
2037         }
2038         tmp |= S_008C00_DX9_CONSTS(0);
2039         tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2040         tmp |= S_008C00_PS_PRIO(ps_prio);
2041         tmp |= S_008C00_VS_PRIO(vs_prio);
2042         tmp |= S_008C00_GS_PRIO(gs_prio);
2043         tmp |= S_008C00_ES_PRIO(es_prio);
2044         r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, NULL, 0);
2045
2046         /* SQ_GPR_RESOURCE_MGMT_1 */
2047         tmp = 0;
2048         tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
2049         tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2050         tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
2051         rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2052         r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, NULL, 0);
2053
2054         /* SQ_GPR_RESOURCE_MGMT_2 */
2055         tmp = 0;
2056         tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
2057         tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2058         r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, NULL, 0);
2059
2060         /* SQ_THREAD_RESOURCE_MGMT */
2061         tmp = 0;
2062         tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
2063         tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2064         tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2065         tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2066         r600_pipe_state_add_reg(rstate, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, NULL, 0);
2067
2068         /* SQ_STACK_RESOURCE_MGMT_1 */
2069         tmp = 0;
2070         tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2071         tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2072         r600_pipe_state_add_reg(rstate, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, NULL, 0);
2073
2074         /* SQ_STACK_RESOURCE_MGMT_2 */
2075         tmp = 0;
2076         tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2077         tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2078         r600_pipe_state_add_reg(rstate, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, NULL, 0);
2079
2080         r600_pipe_state_add_reg(rstate, R_009714_VC_ENHANCE, 0x00000000, NULL, 0);
2081         r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x00000000, NULL, 0);
2082
2083         if (rctx->chip_class >= R700) {
2084                 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, NULL, 0);
2085                 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x00000000, NULL, 0);
2086                 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x00420204, NULL, 0);
2087                 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, NULL, 0);
2088         } else {
2089                 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, NULL, 0);
2090                 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x82000000, NULL, 0);
2091                 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x01020204, NULL, 0);
2092                 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, NULL, 0);
2093         }
2094         r600_pipe_state_add_reg(rstate, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, NULL, 0);
2095         r600_pipe_state_add_reg(rstate, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, NULL, 0);
2096         r600_pipe_state_add_reg(rstate, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, NULL, 0);
2097         r600_pipe_state_add_reg(rstate, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, NULL, 0);
2098         r600_pipe_state_add_reg(rstate, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, NULL, 0);
2099         r600_pipe_state_add_reg(rstate, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, NULL, 0);
2100         r600_pipe_state_add_reg(rstate, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, NULL, 0);
2101         r600_pipe_state_add_reg(rstate, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, NULL, 0);
2102         r600_pipe_state_add_reg(rstate, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, NULL, 0);
2103         r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, NULL, 0);
2104         r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x00000000, NULL, 0);
2105         r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, NULL, 0);
2106         r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, NULL, 0);
2107         r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, NULL, 0);
2108         r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, NULL, 0);
2109         r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, NULL, 0);
2110         r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x00000000, NULL, 0);
2111         r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, NULL, 0);
2112         r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, NULL, 0);
2113         r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, NULL, 0);
2114         r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, NULL, 0);
2115         r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x00000000, NULL, 0);
2116         r600_pipe_state_add_reg(rstate, R_028AB0_VGT_STRMOUT_EN, 0x00000000, NULL, 0);
2117         r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000001, NULL, 0);
2118         r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, NULL, 0);
2119         r600_pipe_state_add_reg(rstate, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, NULL, 0);
2120
2121         r600_pipe_state_add_reg(rstate, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, NULL, 0);
2122         r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, NULL, 0);
2123         r600_pipe_state_add_reg(rstate, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, NULL, 0);
2124         r600_pipe_state_add_reg(rstate, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, NULL, 0);
2125         r600_pipe_state_add_reg(rstate, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, NULL, 0);
2126         r600_context_pipe_state_set(rctx, rstate);
2127
2128         r600_set_seamless_cubemap(rctx, FALSE);
2129 }
2130
2131 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2132 {
2133         struct r600_context *rctx = (struct r600_context *)ctx;
2134         struct r600_pipe_state *rstate = &shader->rstate;
2135         struct r600_shader *rshader = &shader->shader;
2136         unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2137         int pos_index = -1, face_index = -1;
2138         unsigned tmp, sid, ufi = 0;
2139         int need_linear = 0;
2140
2141         rstate->nregs = 0;
2142
2143         for (i = 0; i < rshader->ninput; i++) {
2144                 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2145                         pos_index = i;
2146                 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2147                         face_index = i;
2148
2149                 sid = rshader->input[i].spi_sid;
2150
2151                 tmp = S_028644_SEMANTIC(sid);
2152
2153                 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2154                         rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2155                         (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2156                                 rctx->rasterizer && rctx->rasterizer->flatshade))
2157                         tmp |= S_028644_FLAT_SHADE(1);
2158
2159                 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2160                                 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
2161                         tmp |= S_028644_PT_SPRITE_TEX(1);
2162                 }
2163
2164                 if (rshader->input[i].centroid)
2165                         tmp |= S_028644_SEL_CENTROID(1);
2166
2167                 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2168                         need_linear = 1;
2169                         tmp |= S_028644_SEL_LINEAR(1);
2170                 }
2171
2172                 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4,
2173                                 tmp, NULL, 0);
2174         }
2175
2176         db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2177         for (i = 0; i < rshader->noutput; i++) {
2178                 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2179                         db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
2180                 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2181                         db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(1);
2182         }
2183         if (rshader->uses_kill)
2184                 db_shader_control |= S_02880C_KILL_ENABLE(1);
2185
2186         exports_ps = 0;
2187         num_cout = 0;
2188         for (i = 0; i < rshader->noutput; i++) {
2189                 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2190                     rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2191                         exports_ps |= 1;
2192                 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
2193                         num_cout++;
2194                 }
2195         }
2196         exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2197         if (!exports_ps) {
2198                 /* always at least export 1 component per pixel */
2199                 exports_ps = 2;
2200         }
2201
2202         spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2203                                 S_0286CC_PERSP_GRADIENT_ENA(1)|
2204                                 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2205         spi_input_z = 0;
2206         if (pos_index != -1) {
2207                 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2208                                         S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2209                                         S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2210                                         S_0286CC_BARYC_SAMPLE_CNTL(1));
2211                 spi_input_z |= 1;
2212         }
2213
2214         spi_ps_in_control_1 = 0;
2215         if (face_index != -1) {
2216                 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2217                         S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2218         }
2219
2220         /* HW bug in original R600 */
2221         if (rctx->family == CHIP_R600)
2222                 ufi = 1;
2223
2224         r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, NULL, 0);
2225         r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1, NULL, 0);
2226         r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, NULL, 0);
2227         r600_pipe_state_add_reg(rstate,
2228                                 R_028840_SQ_PGM_START_PS,
2229                                 0, shader->bo, RADEON_USAGE_READ);
2230         r600_pipe_state_add_reg(rstate,
2231                                 R_028850_SQ_PGM_RESOURCES_PS,
2232                                 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2233                                 S_028850_STACK_SIZE(rshader->bc.nstack) |
2234                                 S_028850_UNCACHED_FIRST_INST(ufi),
2235                                 NULL, 0);
2236         r600_pipe_state_add_reg(rstate,
2237                                 R_028854_SQ_PGM_EXPORTS_PS,
2238                                 exports_ps, NULL, 0);
2239         r600_pipe_state_add_reg(rstate,
2240                                 R_0288CC_SQ_PGM_CF_OFFSET_PS,
2241                                 0x00000000, NULL, 0);
2242         /* only set some bits here, the other bits are set in the dsa state */
2243         r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
2244                                 db_shader_control,
2245                                 NULL, 0);
2246
2247         r600_pipe_state_add_reg(rstate,
2248                                 R_03E200_SQ_LOOP_CONST_0, 0x01000FFF,
2249                                 NULL, 0);
2250
2251         shader->sprite_coord_enable = rctx->sprite_coord_enable;
2252         if (rctx->rasterizer)
2253                 shader->flatshade = rctx->rasterizer->flatshade;
2254 }
2255
2256 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2257 {
2258         struct r600_context *rctx = (struct r600_context *)ctx;
2259         struct r600_pipe_state *rstate = &shader->rstate;
2260         struct r600_shader *rshader = &shader->shader;
2261         unsigned spi_vs_out_id[10] = {};
2262         unsigned i, tmp, nparams = 0;
2263
2264         /* clear previous register */
2265         rstate->nregs = 0;
2266
2267         for (i = 0; i < rshader->noutput; i++) {
2268                 if (rshader->output[i].spi_sid) {
2269                         tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2270                         spi_vs_out_id[nparams / 4] |= tmp;
2271                         nparams++;
2272                 }
2273         }
2274
2275         for (i = 0; i < 10; i++) {
2276                 r600_pipe_state_add_reg(rstate,
2277                                         R_028614_SPI_VS_OUT_ID_0 + i * 4,
2278                                         spi_vs_out_id[i], NULL, 0);
2279         }
2280
2281         /* Certain attributes (position, psize, etc.) don't count as params.
2282          * VS is required to export at least one param and r600_shader_from_tgsi()
2283          * takes care of adding a dummy export.
2284          */
2285         if (nparams < 1)
2286                 nparams = 1;
2287
2288         r600_pipe_state_add_reg(rstate,
2289                         R_0286C4_SPI_VS_OUT_CONFIG,
2290                         S_0286C4_VS_EXPORT_COUNT(nparams - 1),
2291                         NULL, 0);
2292         r600_pipe_state_add_reg(rstate,
2293                         R_028868_SQ_PGM_RESOURCES_VS,
2294                         S_028868_NUM_GPRS(rshader->bc.ngpr) |
2295                         S_028868_STACK_SIZE(rshader->bc.nstack),
2296                         NULL, 0);
2297         r600_pipe_state_add_reg(rstate,
2298                         R_0288D0_SQ_PGM_CF_OFFSET_VS,
2299                         0x00000000, NULL, 0);
2300         r600_pipe_state_add_reg(rstate,
2301                         R_028858_SQ_PGM_START_VS,
2302                         0, shader->bo, RADEON_USAGE_READ);
2303
2304         r600_pipe_state_add_reg(rstate,
2305                                 R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
2306                                 NULL, 0);
2307
2308         shader->pa_cl_vs_out_cntl =
2309                 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2310                 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2311                 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2312                 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2313 }
2314
2315 void r600_fetch_shader(struct pipe_context *ctx,
2316                        struct r600_vertex_element *ve)
2317 {
2318         struct r600_pipe_state *rstate;
2319         struct r600_context *rctx = (struct r600_context *)ctx;
2320
2321         rstate = &ve->rstate;
2322         rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2323         rstate->nregs = 0;
2324         r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_RESOURCES_FS,
2325                                 0x00000000, NULL, 0);
2326         r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS,
2327                                 0x00000000, NULL, 0);
2328         r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
2329                                 0,
2330                                 ve->fetch_shader, RADEON_USAGE_READ);
2331 }
2332
2333 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2334 {
2335         struct pipe_depth_stencil_alpha_state dsa;
2336         struct r600_pipe_state *rstate;
2337         struct r600_pipe_dsa *dsa_state;
2338         unsigned db_render_control;
2339         boolean quirk = false;
2340
2341         if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
2342                 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
2343                 quirk = true;
2344
2345         memset(&dsa, 0, sizeof(dsa));
2346
2347         if (quirk) {
2348                 dsa.depth.enabled = 1;
2349                 dsa.depth.func = PIPE_FUNC_LEQUAL;
2350                 dsa.stencil[0].enabled = 1;
2351                 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2352                 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2353                 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2354                 dsa.stencil[0].writemask = 0xff;
2355         }
2356
2357         rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2358         dsa_state = (struct r600_pipe_dsa*)rstate;
2359
2360         db_render_control =
2361                 S_028D0C_DEPTH_COPY_ENABLE(1) |
2362                 S_028D0C_STENCIL_COPY_ENABLE(1) |
2363                 S_028D0C_COPY_CENTROID(1);
2364
2365         r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, NULL, 0);
2366
2367         dsa_state->db_render_control = db_render_control;
2368
2369         return rstate;
2370 }
2371
2372 void r600_pipe_init_buffer_resource(struct r600_context *rctx,
2373                                     struct r600_pipe_resource_state *rstate)
2374 {
2375         rstate->id = R600_PIPE_STATE_RESOURCE;
2376
2377         rstate->bo[0] = NULL;
2378         rstate->val[0] = 0;
2379         rstate->val[1] = 0;
2380         rstate->val[2] = 0;
2381         rstate->val[3] = 0;
2382         rstate->val[4] = 0;
2383         rstate->val[5] = 0;
2384         rstate->val[6] = 0xc0000000;
2385 }
2386
2387 void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
2388                                    struct r600_resource *rbuffer,
2389                                    unsigned offset, unsigned stride,
2390                                    enum radeon_bo_usage usage)
2391 {
2392         rstate->val[0] = offset;
2393         rstate->bo[0] = rbuffer;
2394         rstate->bo_usage[0] = usage;
2395         rstate->val[1] = rbuffer->buf->size - offset - 1;
2396         rstate->val[2] = S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
2397                          S_038008_STRIDE(stride);
2398 }