src/gallium/drivers/r600/r600_state.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23 #include "r600_formats.h"
  24 #include "r600d.h"
  25
  26 #include "pipe/p_shader_tokens.h"
  27 #include "util/u_pack_color.h"
  28 #include "util/u_memory.h"
  29 #include "util/u_framebuffer.h"
  30 #include "util/u_dual_blend.h"
  31
  32 static uint32_t r600_translate_blend_function(int blend_func)
  33 {
  34         switch (blend_func) {
  35         case PIPE_BLEND_ADD:
  36                 return V_028804_COMB_DST_PLUS_SRC;
  37         case PIPE_BLEND_SUBTRACT:
  38                 return V_028804_COMB_SRC_MINUS_DST;
  39         case PIPE_BLEND_REVERSE_SUBTRACT:
  40                 return V_028804_COMB_DST_MINUS_SRC;
  41         case PIPE_BLEND_MIN:
  42                 return V_028804_COMB_MIN_DST_SRC;
  43         case PIPE_BLEND_MAX:
  44                 return V_028804_COMB_MAX_DST_SRC;
  45         default:
  46                 R600_ERR("Unknown blend function %d\n", blend_func);
  47                 assert(0);
  48                 break;
  49         }
  50         return 0;
  51 }
  52
  53 static uint32_t r600_translate_blend_factor(int blend_fact)
  54 {
  55         switch (blend_fact) {
  56         case PIPE_BLENDFACTOR_ONE:
  57                 return V_028804_BLEND_ONE;
  58         case PIPE_BLENDFACTOR_SRC_COLOR:
  59                 return V_028804_BLEND_SRC_COLOR;
  60         case PIPE_BLENDFACTOR_SRC_ALPHA:
  61                 return V_028804_BLEND_SRC_ALPHA;
  62         case PIPE_BLENDFACTOR_DST_ALPHA:
  63                 return V_028804_BLEND_DST_ALPHA;
  64         case PIPE_BLENDFACTOR_DST_COLOR:
  65                 return V_028804_BLEND_DST_COLOR;
  66         case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
  67                 return V_028804_BLEND_SRC_ALPHA_SATURATE;
  68         case PIPE_BLENDFACTOR_CONST_COLOR:
  69                 return V_028804_BLEND_CONST_COLOR;
  70         case PIPE_BLENDFACTOR_CONST_ALPHA:
  71                 return V_028804_BLEND_CONST_ALPHA;
  72         case PIPE_BLENDFACTOR_ZERO:
  73                 return V_028804_BLEND_ZERO;
  74         case PIPE_BLENDFACTOR_INV_SRC_COLOR:
  75                 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
  76         case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
  77                 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
  78         case PIPE_BLENDFACTOR_INV_DST_ALPHA:
  79                 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
  80         case PIPE_BLENDFACTOR_INV_DST_COLOR:
  81                 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
  82         case PIPE_BLENDFACTOR_INV_CONST_COLOR:
  83                 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
  84         case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
  85                 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
  86         case PIPE_BLENDFACTOR_SRC1_COLOR:
  87                 return V_028804_BLEND_SRC1_COLOR;
  88         case PIPE_BLENDFACTOR_SRC1_ALPHA:
  89                 return V_028804_BLEND_SRC1_ALPHA;
  90         case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
  91                 return V_028804_BLEND_INV_SRC1_COLOR;
  92         case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
  93                 return V_028804_BLEND_INV_SRC1_ALPHA;
  94         default:
  95                 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
  96                 assert(0);
  97                 break;
  98         }
  99         return 0;
 100 }
 101
 102 static unsigned r600_tex_dim(unsigned dim, unsigned nr_samples)
 103 {
 104         switch (dim) {
 105         default:
 106         case PIPE_TEXTURE_1D:
 107                 return V_038000_SQ_TEX_DIM_1D;
 108         case PIPE_TEXTURE_1D_ARRAY:
 109                 return V_038000_SQ_TEX_DIM_1D_ARRAY;
 110         case PIPE_TEXTURE_2D:
 111         case PIPE_TEXTURE_RECT:
 112                 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_MSAA :
 113                                         V_038000_SQ_TEX_DIM_2D;
 114         case PIPE_TEXTURE_2D_ARRAY:
 115                 return nr_samples > 1 ? V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA :
 116                                         V_038000_SQ_TEX_DIM_2D_ARRAY;
 117         case PIPE_TEXTURE_3D:
 118                 return V_038000_SQ_TEX_DIM_3D;
 119         case PIPE_TEXTURE_CUBE:
 120                 return V_038000_SQ_TEX_DIM_CUBEMAP;
 121         }
 122 }
 123
 124 static uint32_t r600_translate_dbformat(enum pipe_format format)
 125 {
 126         switch (format) {
 127         case PIPE_FORMAT_Z16_UNORM:
 128                 return V_028010_DEPTH_16;
 129         case PIPE_FORMAT_Z24X8_UNORM:
 130                 return V_028010_DEPTH_X8_24;
 131         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 132                 return V_028010_DEPTH_8_24;
 133         case PIPE_FORMAT_Z32_FLOAT:
 134                 return V_028010_DEPTH_32_FLOAT;
 135         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 136                 return V_028010_DEPTH_X24_8_32_FLOAT;
 137         default:
 138                 return ~0U;
 139         }
 140 }
 141
 142 static uint32_t r600_translate_colorswap(enum pipe_format format)
 143 {
 144         switch (format) {
 145         /* 8-bit buffers. */
 146         case PIPE_FORMAT_A8_UNORM:
 147         case PIPE_FORMAT_A8_SNORM:
 148         case PIPE_FORMAT_A8_UINT:
 149         case PIPE_FORMAT_A8_SINT:
 150         case PIPE_FORMAT_A16_UNORM:
 151         case PIPE_FORMAT_A16_SNORM:
 152         case PIPE_FORMAT_A16_UINT:
 153         case PIPE_FORMAT_A16_SINT:
 154         case PIPE_FORMAT_A16_FLOAT:
 155         case PIPE_FORMAT_A32_UINT:
 156         case PIPE_FORMAT_A32_SINT:
 157         case PIPE_FORMAT_A32_FLOAT:
 158         case PIPE_FORMAT_R4A4_UNORM:
 159                 return V_0280A0_SWAP_ALT_REV;
 160         case PIPE_FORMAT_I8_UNORM:
 161         case PIPE_FORMAT_I8_SNORM:
 162         case PIPE_FORMAT_I8_UINT:
 163         case PIPE_FORMAT_I8_SINT:
 164         case PIPE_FORMAT_L8_UNORM:
 165         case PIPE_FORMAT_L8_SNORM:
 166         case PIPE_FORMAT_L8_UINT:
 167         case PIPE_FORMAT_L8_SINT:
 168         case PIPE_FORMAT_L8_SRGB:
 169         case PIPE_FORMAT_L16_UNORM:
 170         case PIPE_FORMAT_L16_SNORM:
 171         case PIPE_FORMAT_L16_UINT:
 172         case PIPE_FORMAT_L16_SINT:
 173         case PIPE_FORMAT_L16_FLOAT:
 174         case PIPE_FORMAT_L32_UINT:
 175         case PIPE_FORMAT_L32_SINT:
 176         case PIPE_FORMAT_L32_FLOAT:
 177         case PIPE_FORMAT_I16_UNORM:
 178         case PIPE_FORMAT_I16_SNORM:
 179         case PIPE_FORMAT_I16_UINT:
 180         case PIPE_FORMAT_I16_SINT:
 181         case PIPE_FORMAT_I16_FLOAT:
 182         case PIPE_FORMAT_I32_UINT:
 183         case PIPE_FORMAT_I32_SINT:
 184         case PIPE_FORMAT_I32_FLOAT:
 185         case PIPE_FORMAT_R8_UNORM:
 186         case PIPE_FORMAT_R8_SNORM:
 187         case PIPE_FORMAT_R8_UINT:
 188         case PIPE_FORMAT_R8_SINT:
 189                 return V_0280A0_SWAP_STD;
 190
 191         case PIPE_FORMAT_L4A4_UNORM:
 192         case PIPE_FORMAT_A4R4_UNORM:
 193                 return V_0280A0_SWAP_ALT;
 194
 195         /* 16-bit buffers. */
 196         case PIPE_FORMAT_B5G6R5_UNORM:
 197                 return V_0280A0_SWAP_STD_REV;
 198
 199         case PIPE_FORMAT_B5G5R5A1_UNORM:
 200         case PIPE_FORMAT_B5G5R5X1_UNORM:
 201                 return V_0280A0_SWAP_ALT;
 202
 203         case PIPE_FORMAT_B4G4R4A4_UNORM:
 204         case PIPE_FORMAT_B4G4R4X4_UNORM:
 205                 return V_0280A0_SWAP_ALT;
 206
 207         case PIPE_FORMAT_Z16_UNORM:
 208                 return V_0280A0_SWAP_STD;
 209
 210         case PIPE_FORMAT_L8A8_UNORM:
 211         case PIPE_FORMAT_L8A8_SNORM:
 212         case PIPE_FORMAT_L8A8_UINT:
 213         case PIPE_FORMAT_L8A8_SINT:
 214         case PIPE_FORMAT_L8A8_SRGB:
 215         case PIPE_FORMAT_L16A16_UNORM:
 216         case PIPE_FORMAT_L16A16_SNORM:
 217         case PIPE_FORMAT_L16A16_UINT:
 218         case PIPE_FORMAT_L16A16_SINT:
 219         case PIPE_FORMAT_L16A16_FLOAT:
 220         case PIPE_FORMAT_L32A32_UINT:
 221         case PIPE_FORMAT_L32A32_SINT:
 222         case PIPE_FORMAT_L32A32_FLOAT:
 223                 return V_0280A0_SWAP_ALT;
 224         case PIPE_FORMAT_R8G8_UNORM:
 225         case PIPE_FORMAT_R8G8_SNORM:
 226         case PIPE_FORMAT_R8G8_UINT:
 227         case PIPE_FORMAT_R8G8_SINT:
 228                 return V_0280A0_SWAP_STD;
 229
 230         case PIPE_FORMAT_R16_UNORM:
 231         case PIPE_FORMAT_R16_SNORM:
 232         case PIPE_FORMAT_R16_UINT:
 233         case PIPE_FORMAT_R16_SINT:
 234         case PIPE_FORMAT_R16_FLOAT:
 235                 return V_0280A0_SWAP_STD;
 236
 237         /* 32-bit buffers. */
 238
 239         case PIPE_FORMAT_A8B8G8R8_SRGB:
 240                 return V_0280A0_SWAP_STD_REV;
 241         case PIPE_FORMAT_B8G8R8A8_SRGB:
 242                 return V_0280A0_SWAP_ALT;
 243
 244         case PIPE_FORMAT_B8G8R8A8_UNORM:
 245         case PIPE_FORMAT_B8G8R8X8_UNORM:
 246                 return V_0280A0_SWAP_ALT;
 247
 248         case PIPE_FORMAT_A8R8G8B8_UNORM:
 249         case PIPE_FORMAT_X8R8G8B8_UNORM:
 250                 return V_0280A0_SWAP_ALT_REV;
 251         case PIPE_FORMAT_R8G8B8A8_SNORM:
 252         case PIPE_FORMAT_R8G8B8A8_UNORM:
 253         case PIPE_FORMAT_R8G8B8X8_UNORM:
 254         case PIPE_FORMAT_R8G8B8A8_SINT:
 255         case PIPE_FORMAT_R8G8B8A8_UINT:
 256                 return V_0280A0_SWAP_STD;
 257
 258         case PIPE_FORMAT_A8B8G8R8_UNORM:
 259         case PIPE_FORMAT_X8B8G8R8_UNORM:
 260         /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
 261                 return V_0280A0_SWAP_STD_REV;
 262
 263         case PIPE_FORMAT_Z24X8_UNORM:
 264         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 265                 return V_0280A0_SWAP_STD;
 266
 267         case PIPE_FORMAT_X8Z24_UNORM:
 268         case PIPE_FORMAT_S8_UINT_Z24_UNORM:
 269                 return V_0280A0_SWAP_STD;
 270
 271         case PIPE_FORMAT_R10G10B10A2_UNORM:
 272         case PIPE_FORMAT_R10G10B10X2_SNORM:
 273         case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
 274                 return V_0280A0_SWAP_STD;
 275
 276         case PIPE_FORMAT_B10G10R10A2_UNORM:
 277         case PIPE_FORMAT_B10G10R10A2_UINT:
 278                 return V_0280A0_SWAP_ALT;
 279
 280         case PIPE_FORMAT_R11G11B10_FLOAT:
 281         case PIPE_FORMAT_R16G16_UNORM:
 282         case PIPE_FORMAT_R16G16_SNORM:
 283         case PIPE_FORMAT_R16G16_FLOAT:
 284         case PIPE_FORMAT_R16G16_UINT:
 285         case PIPE_FORMAT_R16G16_SINT:
 286         case PIPE_FORMAT_R32_UINT:
 287         case PIPE_FORMAT_R32_SINT:
 288         case PIPE_FORMAT_R32_FLOAT:
 289         case PIPE_FORMAT_Z32_FLOAT:
 290                 return V_0280A0_SWAP_STD;
 291
 292         /* 64-bit buffers. */
 293         case PIPE_FORMAT_R32G32_FLOAT:
 294         case PIPE_FORMAT_R32G32_UINT:
 295         case PIPE_FORMAT_R32G32_SINT:
 296         case PIPE_FORMAT_R16G16B16A16_UNORM:
 297         case PIPE_FORMAT_R16G16B16A16_SNORM:
 298         case PIPE_FORMAT_R16G16B16A16_UINT:
 299         case PIPE_FORMAT_R16G16B16A16_SINT:
 300         case PIPE_FORMAT_R16G16B16A16_FLOAT:
 301         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 302
 303         /* 128-bit buffers. */
 304         case PIPE_FORMAT_R32G32B32A32_FLOAT:
 305         case PIPE_FORMAT_R32G32B32A32_SNORM:
 306         case PIPE_FORMAT_R32G32B32A32_UNORM:
 307         case PIPE_FORMAT_R32G32B32A32_SINT:
 308         case PIPE_FORMAT_R32G32B32A32_UINT:
 309                 return V_0280A0_SWAP_STD;
 310         default:
 311                 R600_ERR("unsupported colorswap format %d\n", format);
 312                 return ~0U;
 313         }
 314         return ~0U;
 315 }
 316
 317 static uint32_t r600_translate_colorformat(enum pipe_format format)
 318 {
 319         switch (format) {
 320         case PIPE_FORMAT_L4A4_UNORM:
 321         case PIPE_FORMAT_R4A4_UNORM:
 322         case PIPE_FORMAT_A4R4_UNORM:
 323                 return V_0280A0_COLOR_4_4;
 324
 325         /* 8-bit buffers. */
 326         case PIPE_FORMAT_A8_UNORM:
 327         case PIPE_FORMAT_A8_SNORM:
 328         case PIPE_FORMAT_A8_UINT:
 329         case PIPE_FORMAT_A8_SINT:
 330         case PIPE_FORMAT_I8_UNORM:
 331         case PIPE_FORMAT_I8_SNORM:
 332         case PIPE_FORMAT_I8_UINT:
 333         case PIPE_FORMAT_I8_SINT:
 334         case PIPE_FORMAT_L8_UNORM:
 335         case PIPE_FORMAT_L8_SNORM:
 336         case PIPE_FORMAT_L8_UINT:
 337         case PIPE_FORMAT_L8_SINT:
 338         case PIPE_FORMAT_L8_SRGB:
 339         case PIPE_FORMAT_R8_UNORM:
 340         case PIPE_FORMAT_R8_SNORM:
 341         case PIPE_FORMAT_R8_UINT:
 342         case PIPE_FORMAT_R8_SINT:
 343                 return V_0280A0_COLOR_8;
 344
 345         /* 16-bit buffers. */
 346         case PIPE_FORMAT_B5G6R5_UNORM:
 347                 return V_0280A0_COLOR_5_6_5;
 348
 349         case PIPE_FORMAT_B5G5R5A1_UNORM:
 350         case PIPE_FORMAT_B5G5R5X1_UNORM:
 351                 return V_0280A0_COLOR_1_5_5_5;
 352
 353         case PIPE_FORMAT_B4G4R4A4_UNORM:
 354         case PIPE_FORMAT_B4G4R4X4_UNORM:
 355                 return V_0280A0_COLOR_4_4_4_4;
 356
 357         case PIPE_FORMAT_Z16_UNORM:
 358                 return V_0280A0_COLOR_16;
 359
 360         case PIPE_FORMAT_L8A8_UNORM:
 361         case PIPE_FORMAT_L8A8_SNORM:
 362         case PIPE_FORMAT_L8A8_UINT:
 363         case PIPE_FORMAT_L8A8_SINT:
 364         case PIPE_FORMAT_L8A8_SRGB:
 365         case PIPE_FORMAT_R8G8_UNORM:
 366         case PIPE_FORMAT_R8G8_SNORM:
 367         case PIPE_FORMAT_R8G8_UINT:
 368         case PIPE_FORMAT_R8G8_SINT:
 369                 return V_0280A0_COLOR_8_8;
 370
 371         case PIPE_FORMAT_R16_UNORM:
 372         case PIPE_FORMAT_R16_SNORM:
 373         case PIPE_FORMAT_R16_UINT:
 374         case PIPE_FORMAT_R16_SINT:
 375         case PIPE_FORMAT_A16_UNORM:
 376         case PIPE_FORMAT_A16_SNORM:
 377         case PIPE_FORMAT_A16_UINT:
 378         case PIPE_FORMAT_A16_SINT:
 379         case PIPE_FORMAT_L16_UNORM:
 380         case PIPE_FORMAT_L16_SNORM:
 381         case PIPE_FORMAT_L16_UINT:
 382         case PIPE_FORMAT_L16_SINT:
 383         case PIPE_FORMAT_I16_UNORM:
 384         case PIPE_FORMAT_I16_SNORM:
 385         case PIPE_FORMAT_I16_UINT:
 386         case PIPE_FORMAT_I16_SINT:
 387                 return V_0280A0_COLOR_16;
 388
 389         case PIPE_FORMAT_R16_FLOAT:
 390         case PIPE_FORMAT_A16_FLOAT:
 391         case PIPE_FORMAT_L16_FLOAT:
 392         case PIPE_FORMAT_I16_FLOAT:
 393                 return V_0280A0_COLOR_16_FLOAT;
 394
 395         /* 32-bit buffers. */
 396         case PIPE_FORMAT_A8B8G8R8_SRGB:
 397         case PIPE_FORMAT_A8B8G8R8_UNORM:
 398         case PIPE_FORMAT_A8R8G8B8_UNORM:
 399         case PIPE_FORMAT_B8G8R8A8_SRGB:
 400         case PIPE_FORMAT_B8G8R8A8_UNORM:
 401         case PIPE_FORMAT_B8G8R8X8_UNORM:
 402         case PIPE_FORMAT_R8G8B8A8_SNORM:
 403         case PIPE_FORMAT_R8G8B8A8_UNORM:
 404         case PIPE_FORMAT_R8G8B8X8_UNORM:
 405         case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
 406         case PIPE_FORMAT_X8B8G8R8_UNORM:
 407         case PIPE_FORMAT_X8R8G8B8_UNORM:
 408         case PIPE_FORMAT_R8G8B8A8_SINT:
 409         case PIPE_FORMAT_R8G8B8A8_UINT:
 410                 return V_0280A0_COLOR_8_8_8_8;
 411
 412         case PIPE_FORMAT_R10G10B10A2_UNORM:
 413         case PIPE_FORMAT_R10G10B10X2_SNORM:
 414         case PIPE_FORMAT_B10G10R10A2_UNORM:
 415         case PIPE_FORMAT_B10G10R10A2_UINT:
 416         case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
 417                 return V_0280A0_COLOR_2_10_10_10;
 418
 419         case PIPE_FORMAT_Z24X8_UNORM:
 420         case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 421                 return V_0280A0_COLOR_8_24;
 422
 423         case PIPE_FORMAT_X8Z24_UNORM:
 424         case PIPE_FORMAT_S8_UINT_Z24_UNORM:
 425                 return V_0280A0_COLOR_24_8;
 426
 427         case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 428                 return V_0280A0_COLOR_X24_8_32_FLOAT;
 429
 430         case PIPE_FORMAT_R32_UINT:
 431         case PIPE_FORMAT_R32_SINT:
 432         case PIPE_FORMAT_A32_UINT:
 433         case PIPE_FORMAT_A32_SINT:
 434         case PIPE_FORMAT_L32_UINT:
 435         case PIPE_FORMAT_L32_SINT:
 436         case PIPE_FORMAT_I32_UINT:
 437         case PIPE_FORMAT_I32_SINT:
 438                 return V_0280A0_COLOR_32;
 439
 440         case PIPE_FORMAT_R32_FLOAT:
 441         case PIPE_FORMAT_A32_FLOAT:
 442         case PIPE_FORMAT_L32_FLOAT:
 443         case PIPE_FORMAT_I32_FLOAT:
 444         case PIPE_FORMAT_Z32_FLOAT:
 445                 return V_0280A0_COLOR_32_FLOAT;
 446
 447         case PIPE_FORMAT_R16G16_FLOAT:
 448         case PIPE_FORMAT_L16A16_FLOAT:
 449                 return V_0280A0_COLOR_16_16_FLOAT;
 450
 451         case PIPE_FORMAT_R16G16_UNORM:
 452         case PIPE_FORMAT_R16G16_SNORM:
 453         case PIPE_FORMAT_R16G16_UINT:
 454         case PIPE_FORMAT_R16G16_SINT:
 455         case PIPE_FORMAT_L16A16_UNORM:
 456         case PIPE_FORMAT_L16A16_SNORM:
 457         case PIPE_FORMAT_L16A16_UINT:
 458         case PIPE_FORMAT_L16A16_SINT:
 459                 return V_0280A0_COLOR_16_16;
 460
 461         case PIPE_FORMAT_R11G11B10_FLOAT:
 462                 return V_0280A0_COLOR_10_11_11_FLOAT;
 463
 464         /* 64-bit buffers. */
 465         case PIPE_FORMAT_R16G16B16A16_UINT:
 466         case PIPE_FORMAT_R16G16B16A16_SINT:
 467         case PIPE_FORMAT_R16G16B16A16_UNORM:
 468         case PIPE_FORMAT_R16G16B16A16_SNORM:
 469                 return V_0280A0_COLOR_16_16_16_16;
 470
 471         case PIPE_FORMAT_R16G16B16A16_FLOAT:
 472                 return V_0280A0_COLOR_16_16_16_16_FLOAT;
 473
 474         case PIPE_FORMAT_R32G32_FLOAT:
 475         case PIPE_FORMAT_L32A32_FLOAT:
 476                 return V_0280A0_COLOR_32_32_FLOAT;
 477
 478         case PIPE_FORMAT_R32G32_SINT:
 479         case PIPE_FORMAT_R32G32_UINT:
 480         case PIPE_FORMAT_L32A32_UINT:
 481         case PIPE_FORMAT_L32A32_SINT:
 482                 return V_0280A0_COLOR_32_32;
 483
 484         /* 128-bit buffers. */
 485         case PIPE_FORMAT_R32G32B32A32_FLOAT:
 486                 return V_0280A0_COLOR_32_32_32_32_FLOAT;
 487         case PIPE_FORMAT_R32G32B32A32_SNORM:
 488         case PIPE_FORMAT_R32G32B32A32_UNORM:
 489         case PIPE_FORMAT_R32G32B32A32_SINT:
 490         case PIPE_FORMAT_R32G32B32A32_UINT:
 491                 return V_0280A0_COLOR_32_32_32_32;
 492
 493         /* YUV buffers. */
 494         case PIPE_FORMAT_UYVY:
 495         case PIPE_FORMAT_YUYV:
 496         default:
 497                 return ~0U; /* Unsupported. */
 498         }
 499 }
 500
 501 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
 502 {
 503         if (R600_BIG_ENDIAN) {
 504                 switch(colorformat) {
 505                 case V_0280A0_COLOR_4_4:
 506                         return ENDIAN_NONE;
 507
 508                 /* 8-bit buffers. */
 509                 case V_0280A0_COLOR_8:
 510                         return ENDIAN_NONE;
 511
 512                 /* 16-bit buffers. */
 513                 case V_0280A0_COLOR_5_6_5:
 514                 case V_0280A0_COLOR_1_5_5_5:
 515                 case V_0280A0_COLOR_4_4_4_4:
 516                 case V_0280A0_COLOR_16:
 517                 case V_0280A0_COLOR_8_8:
 518                         return ENDIAN_8IN16;
 519
 520                 /* 32-bit buffers. */
 521                 case V_0280A0_COLOR_8_8_8_8:
 522                 case V_0280A0_COLOR_2_10_10_10:
 523                 case V_0280A0_COLOR_8_24:
 524                 case V_0280A0_COLOR_24_8:
 525                 case V_0280A0_COLOR_32_FLOAT:
 526                 case V_0280A0_COLOR_16_16_FLOAT:
 527                 case V_0280A0_COLOR_16_16:
 528                         return ENDIAN_8IN32;
 529
 530                 /* 64-bit buffers. */
 531                 case V_0280A0_COLOR_16_16_16_16:
 532                 case V_0280A0_COLOR_16_16_16_16_FLOAT:
 533                         return ENDIAN_8IN16;
 534
 535                 case V_0280A0_COLOR_32_32_FLOAT:
 536                 case V_0280A0_COLOR_32_32:
 537                 case V_0280A0_COLOR_X24_8_32_FLOAT:
 538                         return ENDIAN_8IN32;
 539
 540                 /* 128-bit buffers. */
 541                 case V_0280A0_COLOR_32_32_32_FLOAT:
 542                 case V_0280A0_COLOR_32_32_32_32_FLOAT:
 543                 case V_0280A0_COLOR_32_32_32_32:
 544                         return ENDIAN_8IN32;
 545                 default:
 546                         return ENDIAN_NONE; /* Unsupported. */
 547                 }
 548         } else {
 549                 return ENDIAN_NONE;
 550         }
 551 }
 552
 553 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
 554 {
 555         return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
 556 }
 557
 558 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
 559 {
 560         return r600_translate_colorformat(format) != ~0U &&
 561                r600_translate_colorswap(format) != ~0U;
 562 }
 563
 564 static bool r600_is_zs_format_supported(enum pipe_format format)
 565 {
 566         return r600_translate_dbformat(format) != ~0U;
 567 }
 568
 569 boolean r600_is_format_supported(struct pipe_screen *screen,
 570                                  enum pipe_format format,
 571                                  enum pipe_texture_target target,
 572                                  unsigned sample_count,
 573                                  unsigned usage)
 574 {
 575         struct r600_screen *rscreen = (struct r600_screen*)screen;
 576         unsigned retval = 0;
 577
 578         if (target >= PIPE_MAX_TEXTURE_TYPES) {
 579                 R600_ERR("r600: unsupported texture type %d\n", target);
 580                 return FALSE;
 581         }
 582
 583         if (!util_format_is_supported(format, usage))
 584                 return FALSE;
 585
 586         if (sample_count > 1) {
 587                 if (rscreen->info.drm_minor < 22)
 588                         return FALSE;
 589
 590                 /* R11G11B10 is broken on R6xx. */
 591                 if (rscreen->chip_class == R600 &&
 592                     format == PIPE_FORMAT_R11G11B10_FLOAT)
 593                         return FALSE;
 594
 595                 /* MSAA integer colorbuffers hang. */
 596                 if (util_format_is_pure_integer(format))
 597                         return FALSE;
 598
 599                 switch (sample_count) {
 600                 case 2:
 601                 case 4:
 602                 case 8:
 603                         break;
 604                 default:
 605                         return FALSE;
 606                 }
 607         }
 608
 609         if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
 610             r600_is_sampler_format_supported(screen, format)) {
 611                 retval |= PIPE_BIND_SAMPLER_VIEW;
 612         }
 613
 614         if ((usage & (PIPE_BIND_RENDER_TARGET |
 615                       PIPE_BIND_DISPLAY_TARGET |
 616                       PIPE_BIND_SCANOUT |
 617                       PIPE_BIND_SHARED)) &&
 618             r600_is_colorbuffer_format_supported(format)) {
 619                 retval |= usage &
 620                           (PIPE_BIND_RENDER_TARGET |
 621                            PIPE_BIND_DISPLAY_TARGET |
 622                            PIPE_BIND_SCANOUT |
 623                            PIPE_BIND_SHARED);
 624         }
 625
 626         if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
 627             r600_is_zs_format_supported(format)) {
 628                 retval |= PIPE_BIND_DEPTH_STENCIL;
 629         }
 630
 631         if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
 632             r600_is_vertex_format_supported(format)) {
 633                 retval |= PIPE_BIND_VERTEX_BUFFER;
 634         }
 635
 636         if (usage & PIPE_BIND_TRANSFER_READ)
 637                 retval |= PIPE_BIND_TRANSFER_READ;
 638         if (usage & PIPE_BIND_TRANSFER_WRITE)
 639                 retval |= PIPE_BIND_TRANSFER_WRITE;
 640
 641         return retval == usage;
 642 }
 643
 644 void r600_polygon_offset_update(struct r600_context *rctx)
 645 {
 646         struct r600_pipe_state state;
 647
 648         state.id = R600_PIPE_STATE_POLYGON_OFFSET;
 649         state.nregs = 0;
 650         if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
 651                 float offset_units = rctx->rasterizer->offset_units;
 652                 unsigned offset_db_fmt_cntl = 0, depth;
 653
 654                 switch (rctx->framebuffer.zsbuf->format) {
 655                 case PIPE_FORMAT_Z24X8_UNORM:
 656                 case PIPE_FORMAT_Z24_UNORM_S8_UINT:
 657                         depth = -24;
 658                         offset_units *= 2.0f;
 659                         break;
 660                 case PIPE_FORMAT_Z32_FLOAT:
 661                 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
 662                         depth = -23;
 663                         offset_units *= 1.0f;
 664                         offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
 665                         break;
 666                 case PIPE_FORMAT_Z16_UNORM:
 667                         depth = -16;
 668                         offset_units *= 4.0f;
 669                         break;
 670                 default:
 671                         return;
 672                 }
 673                 /* XXX some of those reg can be computed with cso */
 674                 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
 675                 r600_pipe_state_add_reg(&state,
 676                                 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
 677                                 fui(rctx->rasterizer->offset_scale));
 678                 r600_pipe_state_add_reg(&state,
 679                                 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
 680                                 fui(offset_units));
 681                 r600_pipe_state_add_reg(&state,
 682                                 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
 683                                 fui(rctx->rasterizer->offset_scale));
 684                 r600_pipe_state_add_reg(&state,
 685                                 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
 686                                 fui(offset_units));
 687                 r600_pipe_state_add_reg(&state,
 688                                 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
 689                                 offset_db_fmt_cntl);
 690                 r600_context_pipe_state_set(rctx, &state);
 691         }
 692 }
 693
 694 static void *r600_create_blend_state_mode(struct pipe_context *ctx,
 695                                           const struct pipe_blend_state *state,
 696                                           int mode)
 697 {
 698         struct r600_context *rctx = (struct r600_context *)ctx;
 699         struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
 700         struct r600_pipe_state *rstate;
 701         uint32_t color_control = 0, target_mask = 0;
 702
 703         if (blend == NULL) {
 704                 return NULL;
 705         }
 706         rstate = &blend->rstate;
 707
 708         rstate->id = R600_PIPE_STATE_BLEND;
 709
 710         /* R600 does not support per-MRT blends */
 711         if (rctx->family > CHIP_R600)
 712                 color_control |= S_028808_PER_MRT_BLEND(1);
 713
 714         if (state->logicop_enable) {
 715                 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
 716         } else {
 717                 color_control |= (0xcc << 16);
 718         }
 719         /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
 720         if (state->independent_blend_enable) {
 721                 for (int i = 0; i < 8; i++) {
 722                         if (state->rt[i].blend_enable) {
 723                                 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
 724                         }
 725                         target_mask |= (state->rt[i].colormask << (4 * i));
 726                 }
 727         } else {
 728                 for (int i = 0; i < 8; i++) {
 729                         if (state->rt[0].blend_enable) {
 730                                 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
 731                         }
 732                         target_mask |= (state->rt[0].colormask << (4 * i));
 733                 }
 734         }
 735
 736         if (target_mask)
 737                 color_control |= S_028808_SPECIAL_OP(mode);
 738         else
 739                 color_control |= S_028808_SPECIAL_OP(V_028808_DISABLE);
 740
 741         blend->cb_target_mask = target_mask;
 742         blend->cb_color_control = color_control;
 743         /* only MRT0 has dual src blend */
 744         blend->dual_src_blend = util_blend_state_is_dual(state, 0);
 745         for (int i = 0; i < 8; i++) {
 746                 /* state->rt entries > 0 only written if independent blending */
 747                 const int j = state->independent_blend_enable ? i : 0;
 748
 749                 unsigned eqRGB = state->rt[j].rgb_func;
 750                 unsigned srcRGB = state->rt[j].rgb_src_factor;
 751                 unsigned dstRGB = state->rt[j].rgb_dst_factor;
 752
 753                 unsigned eqA = state->rt[j].alpha_func;
 754                 unsigned srcA = state->rt[j].alpha_src_factor;
 755                 unsigned dstA = state->rt[j].alpha_dst_factor;
 756                 uint32_t bc = 0;
 757
 758                 if (!state->rt[j].blend_enable)
 759                         continue;
 760
 761                 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
 762                 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
 763                 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
 764
 765                 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
 766                         bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
 767                         bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
 768                         bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
 769                         bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
 770                 }
 771
 772                 /* R600 does not support per-MRT blends */
 773                 if (rctx->family > CHIP_R600)
 774                         r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc);
 775                 if (i == 0)
 776                         r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc);
 777         }
 778
 779         r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK,
 780                                 S_028D44_ALPHA_TO_MASK_ENABLE(state->alpha_to_coverage) |
 781                                 S_028D44_ALPHA_TO_MASK_OFFSET0(2) |
 782                                 S_028D44_ALPHA_TO_MASK_OFFSET1(2) |
 783                                 S_028D44_ALPHA_TO_MASK_OFFSET2(2) |
 784                                 S_028D44_ALPHA_TO_MASK_OFFSET3(2));
 785
 786         blend->alpha_to_one = state->alpha_to_one;
 787         return rstate;
 788 }
 789
 790
 791 static void *r600_create_blend_state(struct pipe_context *ctx,
 792                                      const struct pipe_blend_state *state)
 793 {
 794         return r600_create_blend_state_mode(ctx, state, V_028808_SPECIAL_NORMAL);
 795 }
 796
 797 static void *r600_create_dsa_state(struct pipe_context *ctx,
 798                                    const struct pipe_depth_stencil_alpha_state *state)
 799 {
 800         struct r600_context *rctx = (struct r600_context *)ctx;
 801         struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
 802         unsigned db_depth_control, alpha_test_control, alpha_ref;
 803         struct r600_pipe_state *rstate;
 804
 805         if (dsa == NULL) {
 806                 return NULL;
 807         }
 808
 809         dsa->valuemask[0] = state->stencil[0].valuemask;
 810         dsa->valuemask[1] = state->stencil[1].valuemask;
 811         dsa->writemask[0] = state->stencil[0].writemask;
 812         dsa->writemask[1] = state->stencil[1].writemask;
 813
 814         rstate = &dsa->rstate;
 815
 816         rstate->id = R600_PIPE_STATE_DSA;
 817         db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
 818                 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
 819                 S_028800_ZFUNC(state->depth.func);
 820
 821         /* stencil */
 822         if (state->stencil[0].enabled) {
 823                 db_depth_control |= S_028800_STENCIL_ENABLE(1);
 824                 db_depth_control |= S_028800_STENCILFUNC(state->stencil[0].func); /* translates straight */
 825                 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
 826                 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
 827                 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
 828
 829                 if (state->stencil[1].enabled) {
 830                         db_depth_control |= S_028800_BACKFACE_ENABLE(1);
 831                         db_depth_control |= S_028800_STENCILFUNC_BF(state->stencil[1].func); /* translates straight */
 832                         db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
 833                         db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
 834                         db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
 835                 }
 836         }
 837
 838         /* alpha */
 839         alpha_test_control = 0;
 840         alpha_ref = 0;
 841         if (state->alpha.enabled) {
 842                 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
 843                 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
 844                 alpha_ref = fui(state->alpha.ref_value);
 845         }
 846         dsa->sx_alpha_test_control = alpha_test_control & 0xff;
 847         dsa->alpha_ref = alpha_ref;
 848
 849         r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control);
 850         return rstate;
 851 }
 852
 853 static void *r600_create_rs_state(struct pipe_context *ctx,
 854                                   const struct pipe_rasterizer_state *state)
 855 {
 856         struct r600_context *rctx = (struct r600_context *)ctx;
 857         struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
 858         struct r600_pipe_state *rstate;
 859         unsigned tmp;
 860         unsigned prov_vtx = 1, polygon_dual_mode;
 861         unsigned sc_mode_cntl;
 862         float psize_min, psize_max;
 863
 864         if (rs == NULL) {
 865                 return NULL;
 866         }
 867
 868         polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
 869                                 state->fill_back != PIPE_POLYGON_MODE_FILL);
 870
 871         if (state->flatshade_first)
 872                 prov_vtx = 0;
 873
 874         rstate = &rs->rstate;
 875         rs->flatshade = state->flatshade;
 876         rs->sprite_coord_enable = state->sprite_coord_enable;
 877         rs->two_side = state->light_twoside;
 878         rs->clip_plane_enable = state->clip_plane_enable;
 879         rs->pa_sc_line_stipple = state->line_stipple_enable ?
 880                                 S_028A0C_LINE_PATTERN(state->line_stipple_pattern) |
 881                                 S_028A0C_REPEAT_COUNT(state->line_stipple_factor) : 0;
 882         rs->pa_cl_clip_cntl =
 883                 S_028810_PS_UCP_MODE(3) |
 884                 S_028810_ZCLIP_NEAR_DISABLE(!state->depth_clip) |
 885                 S_028810_ZCLIP_FAR_DISABLE(!state->depth_clip) |
 886                 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1);
 887         rs->multisample_enable = state->multisample;
 888
 889         /* offset */
 890         rs->offset_units = state->offset_units;
 891         rs->offset_scale = state->offset_scale * 12.0f;
 892
 893         rstate->id = R600_PIPE_STATE_RASTERIZER;
 894         tmp = S_0286D4_FLAT_SHADE_ENA(1);
 895         if (state->sprite_coord_enable) {
 896                 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
 897                         S_0286D4_PNT_SPRITE_OVRD_X(2) |
 898                         S_0286D4_PNT_SPRITE_OVRD_Y(3) |
 899                         S_0286D4_PNT_SPRITE_OVRD_Z(0) |
 900                         S_0286D4_PNT_SPRITE_OVRD_W(1);
 901                 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
 902                         tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
 903                 }
 904         }
 905         r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp);
 906
 907         /* point size 12.4 fixed point */
 908         tmp = r600_pack_float_12p4(state->point_size/2);
 909         r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp));
 910
 911         if (state->point_size_per_vertex) {
 912                 psize_min = util_get_min_point_size(state);
 913                 psize_max = 8192;
 914         } else {
 915                 /* Force the point size to be as if the vertex output was disabled. */
 916                 psize_min = state->point_size;
 917                 psize_max = state->point_size;
 918         }
 919         /* Divide by two, because 0.5 = 1 pixel. */
 920         r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX,
 921                                 S_028A04_MIN_SIZE(r600_pack_float_12p4(psize_min/2)) |
 922                                 S_028A04_MAX_SIZE(r600_pack_float_12p4(psize_max/2)));
 923
 924         tmp = r600_pack_float_12p4(state->line_width/2);
 925         r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
 926
 927         if (rctx->chip_class >= R700) {
 928                 sc_mode_cntl =
 929                         S_028A4C_MSAA_ENABLE(state->multisample) |
 930                         S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
 931                         S_028A4C_FORCE_EOV_REZ_ENABLE(1) |
 932                         S_028A4C_R700_ZMM_LINE_OFFSET(1) |
 933                         S_028A4C_R700_VPORT_SCISSOR_ENABLE(state->scissor);
 934         } else {
 935                 sc_mode_cntl =
 936                         S_028A4C_MSAA_ENABLE(state->multisample) |
 937                         S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
 938                         S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1);
 939                 rs->scissor_enable = state->scissor;
 940         }
 941         sc_mode_cntl |= S_028A4C_LINE_STIPPLE_ENABLE(state->line_stipple_enable);
 942
 943         r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, sc_mode_cntl);
 944
 945         r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
 946                                 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules) |
 947                                 S_028C08_QUANT_MODE(V_028C08_X_1_256TH));
 948
 949         r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, fui(state->offset_clamp));
 950         r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
 951                                 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
 952                                 S_028814_CULL_FRONT(state->cull_face & PIPE_FACE_FRONT ? 1 : 0) |
 953                                 S_028814_CULL_BACK(state->cull_face & PIPE_FACE_BACK ? 1 : 0) |
 954                                 S_028814_FACE(!state->front_ccw) |
 955                                 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
 956                                 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
 957                                 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
 958                                 S_028814_POLY_MODE(polygon_dual_mode) |
 959                                 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
 960                                 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)));
 961         r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, S_028350_MULTIPASS(state->rasterizer_discard));
 962         return rstate;
 963 }
 964
 965 static void *r600_create_sampler_state(struct pipe_context *ctx,
 966                                         const struct pipe_sampler_state *state)
 967 {
 968         struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
 969         union util_color uc;
 970         unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
 971
 972         if (ss == NULL) {
 973                 return NULL;
 974         }
 975
 976         ss->seamless_cube_map = state->seamless_cube_map;
 977         ss->border_color_use = false;
 978         util_pack_color(state->border_color.f, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
 979         /* R_03C000_SQ_TEX_SAMPLER_WORD0_0 */
 980         ss->tex_sampler_words[0] = S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
 981                                 S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
 982                                 S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
 983                                 S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
 984                                 S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
 985                                 S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
 986                                 S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
 987                                 S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
 988                                 S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0);
 989         /* R_03C004_SQ_TEX_SAMPLER_WORD1_0 */
 990         ss->tex_sampler_words[1] = S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
 991                                 S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
 992                                 S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6));
 993         /* R_03C008_SQ_TEX_SAMPLER_WORD2_0 */
 994         ss->tex_sampler_words[2] = S_03C008_TYPE(1);
 995         if (uc.ui) {
 996                 ss->border_color_use = true;
 997                 /* R_00A400_TD_PS_SAMPLER0_BORDER_RED */
 998                 ss->border_color[0] = fui(state->border_color.f[0]);
 999                 /* R_00A404_TD_PS_SAMPLER0_BORDER_GREEN */
1000                 ss->border_color[1] = fui(state->border_color.f[1]);
1001                 /* R_00A408_TD_PS_SAMPLER0_BORDER_BLUE */
1002                 ss->border_color[2] = fui(state->border_color.f[2]);
1003                 /* R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA */
1004                 ss->border_color[3] = fui(state->border_color.f[3]);
1005         }
1006         return ss;
1007 }
1008
1009 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
1010                                                         struct pipe_resource *texture,
1011                                                         const struct pipe_sampler_view *state)
1012 {
1013         struct r600_pipe_sampler_view *view = CALLOC_STRUCT(r600_pipe_sampler_view);
1014         struct r600_texture *tmp = (struct r600_texture*)texture;
1015         unsigned format, endian;
1016         uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1017         unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1018         unsigned width, height, depth, offset_level, last_level;
1019
1020         if (view == NULL)
1021                 return NULL;
1022
1023         /* initialize base object */
1024         view->base = *state;
1025         view->base.texture = NULL;
1026         pipe_reference(NULL, &texture->reference);
1027         view->base.texture = texture;
1028         view->base.reference.count = 1;
1029         view->base.context = ctx;
1030
1031         swizzle[0] = state->swizzle_r;
1032         swizzle[1] = state->swizzle_g;
1033         swizzle[2] = state->swizzle_b;
1034         swizzle[3] = state->swizzle_a;
1035
1036         format = r600_translate_texformat(ctx->screen, state->format,
1037                                           swizzle,
1038                                           &word4, &yuv_format);
1039         assert(format != ~0);
1040         if (format == ~0) {
1041                 FREE(view);
1042                 return NULL;
1043         }
1044
1045         if (tmp->is_depth && !tmp->is_flushing_texture) {
1046                 if (!r600_init_flushed_depth_texture(ctx, texture, NULL)) {
1047                         FREE(view);
1048                         return NULL;
1049                 }
1050                 tmp = tmp->flushed_depth_texture;
1051         }
1052
1053         endian = r600_colorformat_endian_swap(format);
1054
1055         offset_level = state->u.tex.first_level;
1056         last_level = state->u.tex.last_level - offset_level;
1057         width = tmp->surface.level[offset_level].npix_x;
1058         height = tmp->surface.level[offset_level].npix_y;
1059         depth = tmp->surface.level[offset_level].npix_z;
1060         pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
1061         tile_type = tmp->tile_type;
1062
1063         if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1064                 height = 1;
1065                 depth = texture->array_size;
1066         } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1067                 depth = texture->array_size;
1068         }
1069         switch (tmp->surface.level[offset_level].mode) {
1070         case RADEON_SURF_MODE_LINEAR_ALIGNED:
1071                 array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
1072                 break;
1073         case RADEON_SURF_MODE_1D:
1074                 array_mode = V_038000_ARRAY_1D_TILED_THIN1;
1075                 break;
1076         case RADEON_SURF_MODE_2D:
1077                 array_mode = V_038000_ARRAY_2D_TILED_THIN1;
1078                 break;
1079         case RADEON_SURF_MODE_LINEAR:
1080         default:
1081                 array_mode = V_038000_ARRAY_LINEAR_GENERAL;
1082                 break;
1083         }
1084
1085         view->tex_resource = &tmp->resource;
1086         view->tex_resource_words[0] = (S_038000_DIM(r600_tex_dim(texture->target, texture->nr_samples)) |
1087                                        S_038000_TILE_MODE(array_mode) |
1088                                        S_038000_TILE_TYPE(tile_type) |
1089                                        S_038000_PITCH((pitch / 8) - 1) |
1090                                        S_038000_TEX_WIDTH(width - 1));
1091         view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
1092                                        S_038004_TEX_DEPTH(depth - 1) |
1093                                        S_038004_DATA_FORMAT(format));
1094         view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
1095         if (offset_level >= tmp->surface.last_level) {
1096                 view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
1097         } else {
1098                 view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
1099         }
1100         view->tex_resource_words[4] = (word4 |
1101                                        S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1102                                        S_038010_REQUEST_SIZE(1) |
1103                                        S_038010_ENDIAN_SWAP(endian) |
1104                                        S_038010_BASE_LEVEL(0));
1105         view->tex_resource_words[5] = (S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1106                                        S_038014_LAST_ARRAY(state->u.tex.last_layer));
1107         if (texture->nr_samples > 1) {
1108                 /* LAST_LEVEL holds log2(nr_samples) for multisample textures */
1109                 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(util_logbase2(texture->nr_samples));
1110         } else {
1111                 view->tex_resource_words[5] |= S_038014_LAST_LEVEL(last_level);
1112         }
1113         view->tex_resource_words[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1114                                        S_038018_MAX_ANISO(4 /* max 16 samples */));
1115         return &view->base;
1116 }
1117
1118 static void r600_set_vs_sampler_views(struct pipe_context *ctx, unsigned count,
1119                                       struct pipe_sampler_view **views)
1120 {
1121         r600_set_sampler_views(ctx, PIPE_SHADER_VERTEX, 0, count, views);
1122 }
1123
1124 static void r600_set_ps_sampler_views(struct pipe_context *ctx, unsigned count,
1125                                       struct pipe_sampler_view **views)
1126 {
1127         r600_set_sampler_views(ctx, PIPE_SHADER_FRAGMENT, 0, count, views);
1128 }
1129
1130 static void r600_set_clip_state(struct pipe_context *ctx,
1131                                 const struct pipe_clip_state *state)
1132 {
1133         struct r600_context *rctx = (struct r600_context *)ctx;
1134         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1135         struct pipe_constant_buffer cb;
1136
1137         if (rstate == NULL)
1138                 return;
1139
1140         rctx->clip = *state;
1141         rstate->id = R600_PIPE_STATE_CLIP;
1142         for (int i = 0; i < 6; i++) {
1143                 r600_pipe_state_add_reg(rstate,
1144                                         R_028E20_PA_CL_UCP0_X + i * 16,
1145                                         fui(state->ucp[i][0]));
1146                 r600_pipe_state_add_reg(rstate,
1147                                         R_028E24_PA_CL_UCP0_Y + i * 16,
1148                                         fui(state->ucp[i][1]) );
1149                 r600_pipe_state_add_reg(rstate,
1150                                         R_028E28_PA_CL_UCP0_Z + i * 16,
1151                                         fui(state->ucp[i][2]));
1152                 r600_pipe_state_add_reg(rstate,
1153                                         R_028E2C_PA_CL_UCP0_W + i * 16,
1154                                         fui(state->ucp[i][3]));
1155         }
1156
1157         free(rctx->states[R600_PIPE_STATE_CLIP]);
1158         rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1159         r600_context_pipe_state_set(rctx, rstate);
1160
1161         cb.buffer = NULL;
1162         cb.user_buffer = state->ucp;
1163         cb.buffer_offset = 0;
1164         cb.buffer_size = 4*4*8;
1165         r600_set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
1166         pipe_resource_reference(&cb.buffer, NULL);
1167 }
1168
1169 static void r600_set_polygon_stipple(struct pipe_context *ctx,
1170                                          const struct pipe_poly_stipple *state)
1171 {
1172 }
1173
1174 void r600_set_scissor_state(struct r600_context *rctx,
1175                             const struct pipe_scissor_state *state)
1176 {
1177         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1178         uint32_t tl, br;
1179
1180         if (rstate == NULL)
1181                 return;
1182
1183         rstate->id = R600_PIPE_STATE_SCISSOR;
1184         tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
1185         br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1186         r600_pipe_state_add_reg(rstate,
1187                                 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl);
1188         r600_pipe_state_add_reg(rstate,
1189                                 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br);
1190
1191         free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1192         rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1193         r600_context_pipe_state_set(rctx, rstate);
1194 }
1195
1196 static void r600_pipe_set_scissor_state(struct pipe_context *ctx,
1197                                         const struct pipe_scissor_state *state)
1198 {
1199         struct r600_context *rctx = (struct r600_context *)ctx;
1200
1201         if (rctx->chip_class == R600) {
1202                 rctx->scissor_state = *state;
1203
1204                 if (!rctx->scissor_enable)
1205                         return;
1206         }
1207
1208         r600_set_scissor_state(rctx, state);
1209 }
1210
1211 static void r600_set_viewport_state(struct pipe_context *ctx,
1212                                         const struct pipe_viewport_state *state)
1213 {
1214         struct r600_context *rctx = (struct r600_context *)ctx;
1215         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1216
1217         if (rstate == NULL)
1218                 return;
1219
1220         rctx->viewport = *state;
1221         rstate->id = R600_PIPE_STATE_VIEWPORT;
1222         r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]));
1223         r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]));
1224         r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]));
1225         r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]));
1226         r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]));
1227         r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]));
1228
1229         free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1230         rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1231         r600_context_pipe_state_set(rctx, rstate);
1232 }
1233
1234 static struct r600_resource *r600_buffer_create_helper(struct r600_screen *rscreen,
1235                                                        unsigned size, unsigned alignment)
1236 {
1237         struct pipe_resource buffer;
1238
1239         memset(&buffer, 0, sizeof buffer);
1240         buffer.target = PIPE_BUFFER;
1241         buffer.format = PIPE_FORMAT_R8_UNORM;
1242         buffer.bind = PIPE_BIND_CUSTOM;
1243         buffer.usage = PIPE_USAGE_STATIC;
1244         buffer.flags = 0;
1245         buffer.width0 = size;
1246         buffer.height0 = 1;
1247         buffer.depth0 = 1;
1248         buffer.array_size = 1;
1249
1250         return (struct r600_resource*)
1251                 r600_buffer_create(&rscreen->screen, &buffer, alignment);
1252 }
1253
1254 static void r600_init_color_surface(struct r600_context *rctx,
1255                                     struct r600_surface *surf,
1256                                     bool force_cmask_fmask)
1257 {
1258         struct r600_screen *rscreen = rctx->screen;
1259         struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1260         unsigned level = surf->base.u.tex.level;
1261         unsigned pitch, slice;
1262         unsigned color_info;
1263         unsigned format, swap, ntype, endian;
1264         unsigned offset;
1265         const struct util_format_description *desc;
1266         int i;
1267         bool blend_bypass = 0, blend_clamp = 1;
1268
1269         if (rtex->is_depth && !rtex->is_flushing_texture) {
1270                 r600_init_flushed_depth_texture(&rctx->context, surf->base.texture, NULL);
1271                 rtex = rtex->flushed_depth_texture;
1272                 assert(rtex);
1273         }
1274
1275         offset = rtex->surface.level[level].offset;
1276         if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1277                 offset += rtex->surface.level[level].slice_size *
1278                           surf->base.u.tex.first_layer;
1279         }
1280         pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1281         slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1282         if (slice) {
1283                 slice = slice - 1;
1284         }
1285         color_info = 0;
1286         switch (rtex->surface.level[level].mode) {
1287         case RADEON_SURF_MODE_LINEAR_ALIGNED:
1288                 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
1289                 break;
1290         case RADEON_SURF_MODE_1D:
1291                 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_1D_TILED_THIN1);
1292                 break;
1293         case RADEON_SURF_MODE_2D:
1294                 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_2D_TILED_THIN1);
1295                 break;
1296         case RADEON_SURF_MODE_LINEAR:
1297         default:
1298                 color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_GENERAL);
1299                 break;
1300         }
1301
1302         desc = util_format_description(surf->base.format);
1303
1304         for (i = 0; i < 4; i++) {
1305                 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1306                         break;
1307                 }
1308         }
1309
1310         ntype = V_0280A0_NUMBER_UNORM;
1311         if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1312                 ntype = V_0280A0_NUMBER_SRGB;
1313         else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED) {
1314                 if (desc->channel[i].normalized)
1315                         ntype = V_0280A0_NUMBER_SNORM;
1316                 else if (desc->channel[i].pure_integer)
1317                         ntype = V_0280A0_NUMBER_SINT;
1318         } else if (desc->channel[i].type == UTIL_FORMAT_TYPE_UNSIGNED) {
1319                 if (desc->channel[i].normalized)
1320                         ntype = V_0280A0_NUMBER_UNORM;
1321                 else if (desc->channel[i].pure_integer)
1322                         ntype = V_0280A0_NUMBER_UINT;
1323         }
1324
1325         format = r600_translate_colorformat(surf->base.format);
1326         assert(format != ~0);
1327
1328         swap = r600_translate_colorswap(surf->base.format);
1329         assert(swap != ~0);
1330
1331         if (rtex->resource.b.b.usage == PIPE_USAGE_STAGING) {
1332                 endian = ENDIAN_NONE;
1333         } else {
1334                 endian = r600_colorformat_endian_swap(format);
1335         }
1336
1337         /* set blend bypass according to docs if SINT/UINT or
1338            8/24 COLOR variants */
1339         if (ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT ||
1340             format == V_0280A0_COLOR_8_24 || format == V_0280A0_COLOR_24_8 ||
1341             format == V_0280A0_COLOR_X24_8_32_FLOAT) {
1342                 blend_clamp = 0;
1343                 blend_bypass = 1;
1344         }
1345
1346         surf->alphatest_bypass = ntype == V_0280A0_NUMBER_UINT || ntype == V_0280A0_NUMBER_SINT;
1347
1348         color_info |= S_0280A0_FORMAT(format) |
1349                 S_0280A0_COMP_SWAP(swap) |
1350                 S_0280A0_BLEND_BYPASS(blend_bypass) |
1351                 S_0280A0_BLEND_CLAMP(blend_clamp) |
1352                 S_0280A0_NUMBER_TYPE(ntype) |
1353                 S_0280A0_ENDIAN(endian);
1354
1355         /* EXPORT_NORM is an optimzation that can be enabled for better
1356          * performance in certain cases
1357          */
1358         if (rctx->chip_class == R600) {
1359                 /* EXPORT_NORM can be enabled if:
1360                  * - 11-bit or smaller UNORM/SNORM/SRGB
1361                  * - BLEND_CLAMP is enabled
1362                  * - BLEND_FLOAT32 is disabled
1363                  */
1364                 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1365                     (desc->channel[i].size < 12 &&
1366                      desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1367                      ntype != V_0280A0_NUMBER_UINT &&
1368                      ntype != V_0280A0_NUMBER_SINT) &&
1369                     G_0280A0_BLEND_CLAMP(color_info) &&
1370                     !G_0280A0_BLEND_FLOAT32(color_info)) {
1371                         color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1372                         surf->export_16bpc = true;
1373                 }
1374         } else {
1375                 /* EXPORT_NORM can be enabled if:
1376                  * - 11-bit or smaller UNORM/SNORM/SRGB
1377                  * - 16-bit or smaller FLOAT
1378                  */
1379                 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1380                     ((desc->channel[i].size < 12 &&
1381                       desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1382                       ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1383                     (desc->channel[i].size < 17 &&
1384                      desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT))) {
1385                         color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1386                         surf->export_16bpc = true;
1387                 }
1388         }
1389
1390         /* These might not always be initialized to zero. */
1391         surf->cb_color_base = offset >> 8;
1392         surf->cb_color_size = S_028060_PITCH_TILE_MAX(pitch) |
1393                               S_028060_SLICE_TILE_MAX(slice);
1394         surf->cb_color_fmask = surf->cb_color_base;
1395         surf->cb_color_cmask = surf->cb_color_base;
1396         surf->cb_color_mask = 0;
1397
1398         pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1399                                 &rtex->resource.b.b);
1400         pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1401                                 &rtex->resource.b.b);
1402
1403         if (rtex->cmask_size) {
1404                 surf->cb_color_cmask = rtex->cmask_offset >> 8;
1405                 surf->cb_color_mask |= S_028100_CMASK_BLOCK_MAX(rtex->cmask_slice_tile_max);
1406
1407                 if (rtex->fmask_size) {
1408                         color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1409                         surf->cb_color_fmask = rtex->fmask_offset >> 8;
1410                         surf->cb_color_mask |= S_028100_FMASK_TILE_MAX(slice);
1411                 } else { /* cmask only */
1412                         color_info |= S_0280A0_TILE_MODE(V_0280A0_CLEAR_ENABLE);
1413                 }
1414         } else if (force_cmask_fmask) {
1415                 /* Allocate dummy FMASK and CMASK if they aren't allocated already.
1416                  *
1417                  * R6xx needs FMASK and CMASK for the destination buffer of color resolve,
1418                  * otherwise it hangs. We don't have FMASK and CMASK pre-allocated,
1419                  * because it's not an MSAA buffer.
1420                  */
1421                 struct r600_cmask_info cmask;
1422                 struct r600_fmask_info fmask;
1423
1424                 r600_texture_get_cmask_info(rscreen, rtex, &cmask);
1425                 r600_texture_get_fmask_info(rscreen, rtex, 8, &fmask);
1426
1427                 /* CMASK. */
1428                 if (!rctx->dummy_cmask ||
1429                     rctx->dummy_cmask->buf->size < cmask.size ||
1430                     rctx->dummy_cmask->buf->alignment % cmask.alignment != 0) {
1431                         struct pipe_transfer *transfer;
1432                         void *ptr;
1433
1434                         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_cmask, NULL);
1435                         rctx->dummy_cmask = r600_buffer_create_helper(rscreen, cmask.size, cmask.alignment);
1436
1437                         /* Set the contents to 0xCC. */
1438                         ptr = pipe_buffer_map(&rctx->context, &rctx->dummy_cmask->b.b, PIPE_TRANSFER_WRITE, &transfer);
1439                         memset(ptr, 0xCC, cmask.size);
1440                         pipe_buffer_unmap(&rctx->context, transfer);
1441                 }
1442                 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_cmask,
1443                                         &rctx->dummy_cmask->b.b);
1444
1445                 /* FMASK. */
1446                 if (!rctx->dummy_fmask ||
1447                     rctx->dummy_fmask->buf->size < fmask.size ||
1448                     rctx->dummy_fmask->buf->alignment % fmask.alignment != 0) {
1449                         pipe_resource_reference((struct pipe_resource**)&rctx->dummy_fmask, NULL);
1450                         rctx->dummy_fmask = r600_buffer_create_helper(rscreen, fmask.size, fmask.alignment);
1451
1452                 }
1453                 pipe_resource_reference((struct pipe_resource**)&surf->cb_buffer_fmask,
1454                                         &rctx->dummy_fmask->b.b);
1455
1456                 /* Init the registers. */
1457                 color_info |= S_0280A0_TILE_MODE(V_0280A0_FRAG_ENABLE);
1458                 surf->cb_color_cmask = 0;
1459                 surf->cb_color_fmask = 0;
1460                 surf->cb_color_mask = S_028100_CMASK_BLOCK_MAX(cmask.slice_tile_max) |
1461                                       S_028100_FMASK_TILE_MAX(slice);
1462         }
1463
1464         surf->cb_color_info = color_info;
1465
1466         if (rtex->surface.level[level].mode < RADEON_SURF_MODE_1D) {
1467                 surf->cb_color_view = 0;
1468         } else {
1469                 surf->cb_color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
1470                                       S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
1471         }
1472
1473         surf->color_initialized = true;
1474 }
1475
1476 static void r600_init_depth_surface(struct r600_context *rctx,
1477                                     struct r600_surface *surf)
1478 {
1479         struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
1480         unsigned level, pitch, slice, format, offset, array_mode;
1481
1482         level = surf->base.u.tex.level;
1483         offset = rtex->surface.level[level].offset;
1484         pitch = rtex->surface.level[level].nblk_x / 8 - 1;
1485         slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
1486         if (slice) {
1487                 slice = slice - 1;
1488         }
1489         switch (rtex->surface.level[level].mode) {
1490         case RADEON_SURF_MODE_2D:
1491                 array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
1492                 break;
1493         case RADEON_SURF_MODE_1D:
1494         case RADEON_SURF_MODE_LINEAR_ALIGNED:
1495         case RADEON_SURF_MODE_LINEAR:
1496         default:
1497                 array_mode = V_0280A0_ARRAY_1D_TILED_THIN1;
1498                 break;
1499         }
1500
1501         format = r600_translate_dbformat(surf->base.format);
1502         assert(format != ~0);
1503
1504         surf->db_depth_info = S_028010_ARRAY_MODE(array_mode) | S_028010_FORMAT(format);
1505         surf->db_depth_base = offset >> 8;
1506         surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
1507                               S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
1508         surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
1509         surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
1510
1511         surf->depth_initialized = true;
1512 }
1513
1514 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
1515         (((s0x) & 0xf) | (((s0y) & 0xf) << 4) |            \
1516         (((s1x) & 0xf) << 8) | (((s1y) & 0xf) << 12) |     \
1517         (((s2x) & 0xf) << 16) | (((s2y) & 0xf) << 20) |    \
1518          (((s3x) & 0xf) << 24) | (((s3y) & 0xf) << 28))
1519
1520 static uint32_t r600_set_ms_pos(struct pipe_context *ctx, struct r600_pipe_state *rstate, int nsample)
1521 {
1522         static uint32_t sample_locs_2x[] = {
1523                 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1524                 FILL_SREG(-4, 4, 4, -4, -4, 4, 4, -4),
1525         };
1526         static unsigned max_dist_2x = 4;
1527         static uint32_t sample_locs_4x[] = {
1528                 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1529                 FILL_SREG(-2, -2, 2, 2, -6, 6, 6, -6),
1530         };
1531         static unsigned max_dist_4x = 6;
1532         static uint32_t sample_locs_8x[] = {
1533                 FILL_SREG(-2, -5, 3, -4, -1, 5, -6, -2),
1534                 FILL_SREG( 6,  0, 0,  0, -5, 3,  4,  4),
1535         };
1536         static unsigned max_dist_8x = 8;
1537         struct r600_context *rctx = (struct r600_context *)ctx;
1538
1539         if (rctx->family == CHIP_R600) {
1540                 switch (nsample) {
1541                 case 0:
1542                 case 1:
1543                         return 0;
1544                 case 2:
1545                         r600_pipe_state_add_reg(rstate, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]);
1546                         return max_dist_2x;
1547                 case 4:
1548                         r600_pipe_state_add_reg(rstate, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]);
1549                         return max_dist_4x;
1550                 case 8:
1551                         r600_pipe_state_add_reg(rstate, R_008B48_PA_SC_AA_SAMPLE_LOCS_8S_WD0, sample_locs_8x[0]);
1552                         r600_pipe_state_add_reg(rstate, R_008B4C_PA_SC_AA_SAMPLE_LOCS_8S_WD1, sample_locs_8x[1]);
1553                         return max_dist_8x;
1554                 }
1555         } else {
1556                 switch (nsample) {
1557                 case 0:
1558                 case 1:
1559                         r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, 0);
1560                         r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, 0);
1561                         return 0;
1562                 case 2:
1563                         r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, sample_locs_2x[0]);
1564                         r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, sample_locs_2x[1]);
1565                         return max_dist_2x;
1566                 case 4:
1567                         r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, sample_locs_4x[0]);
1568                         r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, sample_locs_4x[1]);
1569                         return max_dist_4x;
1570                 case 8:
1571                         r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX, sample_locs_8x[0]);
1572                         r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8D_WD1_MCTX, sample_locs_8x[1]);
1573                         return max_dist_8x;
1574                 }
1575         }
1576         R600_ERR("Invalid nr_samples %i\n", nsample);
1577         return 0;
1578 }
1579
1580 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1581                                         const struct pipe_framebuffer_state *state)
1582 {
1583         struct r600_context *rctx = (struct r600_context *)ctx;
1584         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1585         struct r600_surface *surf;
1586         struct r600_resource *res;
1587         struct r600_texture *rtex;
1588         uint32_t tl, br, i, nr_samples, max_dist;
1589         bool is_resolve = state->nr_cbufs == 2 &&
1590                           state->cbufs[0]->texture->nr_samples > 1 &&
1591                           state->cbufs[1]->texture->nr_samples <= 1;
1592         /* The resolve buffer must have CMASK and FMASK to prevent hardlocks on R6xx. */
1593         bool cb1_force_cmask_fmask = rctx->chip_class == R600 && is_resolve;
1594
1595         if (rstate == NULL)
1596                 return;
1597
1598         r600_flush_framebuffer(rctx, false);
1599
1600         /* unreference old buffer and reference new one */
1601         rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1602
1603         util_copy_framebuffer_state(&rctx->framebuffer, state);
1604
1605         /* Colorbuffers. */
1606         rctx->export_16bpc = true;
1607         rctx->nr_cbufs = state->nr_cbufs;
1608         rctx->cb0_is_integer = state->nr_cbufs &&
1609                                util_format_is_pure_integer(state->cbufs[0]->format);
1610         rctx->compressed_cb_mask = 0;
1611
1612         for (i = 0; i < state->nr_cbufs; i++) {
1613                 bool force_cmask_fmask = cb1_force_cmask_fmask && i == 1;
1614                 surf = (struct r600_surface*)state->cbufs[i];
1615                 res = (struct r600_resource*)surf->base.texture;
1616                 rtex = (struct r600_texture*)res;
1617
1618                 r600_context_add_resource_size(ctx, state->cbufs[i]->texture);
1619
1620                 if (!surf->color_initialized || force_cmask_fmask) {
1621                         r600_init_color_surface(rctx, surf, force_cmask_fmask);
1622                         if (force_cmask_fmask) {
1623                                 /* re-initialize later without compression */
1624                                 surf->color_initialized = false;
1625                         }
1626                 }
1627
1628                 if (!surf->export_16bpc) {
1629                         rctx->export_16bpc = false;
1630                 }
1631
1632                 r600_pipe_state_add_reg_bo(rstate, R_028040_CB_COLOR0_BASE + i * 4,
1633                                            surf->cb_color_base, res, RADEON_USAGE_READWRITE);
1634                 r600_pipe_state_add_reg_bo(rstate, R_0280A0_CB_COLOR0_INFO + i * 4,
1635                                            surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1636                 r600_pipe_state_add_reg(rstate, R_028060_CB_COLOR0_SIZE + i * 4,
1637                                         surf->cb_color_size);
1638                 r600_pipe_state_add_reg(rstate, R_028080_CB_COLOR0_VIEW + i * 4,
1639                                         surf->cb_color_view);
1640                 r600_pipe_state_add_reg_bo(rstate, R_0280E0_CB_COLOR0_FRAG + i * 4,
1641                                            surf->cb_color_fmask, surf->cb_buffer_fmask,
1642                                            RADEON_USAGE_READWRITE);
1643                 r600_pipe_state_add_reg_bo(rstate, R_0280C0_CB_COLOR0_TILE + i * 4,
1644                                            surf->cb_color_cmask, surf->cb_buffer_cmask,
1645                                            RADEON_USAGE_READWRITE);
1646                 r600_pipe_state_add_reg(rstate, R_028100_CB_COLOR0_MASK + i * 4,
1647                                         surf->cb_color_mask);
1648
1649                 if (rtex->fmask_size && rtex->cmask_size) {
1650                         rctx->compressed_cb_mask |= 1 << i;
1651                 }
1652         }
1653         /* set CB_COLOR1_INFO for possible dual-src blending */
1654         if (i == 1) {
1655                 r600_pipe_state_add_reg_bo(rstate, R_0280A0_CB_COLOR0_INFO + 1 * 4,
1656                                            surf->cb_color_info, res, RADEON_USAGE_READWRITE);
1657                 i++;
1658         }
1659         for (; i < 8 ; i++) {
1660                 r600_pipe_state_add_reg(rstate, R_0280A0_CB_COLOR0_INFO + i * 4, 0);
1661         }
1662
1663         /* Update alpha-test state dependencies.
1664          * Alpha-test is done on the first colorbuffer only. */
1665         if (state->nr_cbufs) {
1666                 surf = (struct r600_surface*)state->cbufs[0];
1667                 if (rctx->alphatest_state.bypass != surf->alphatest_bypass) {
1668                         rctx->alphatest_state.bypass = surf->alphatest_bypass;
1669                         r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1670                 }
1671         }
1672
1673         /* ZS buffer. */
1674         if (state->zsbuf) {
1675                 surf = (struct r600_surface*)state->zsbuf;
1676                 res = (struct r600_resource*)surf->base.texture;
1677
1678                 r600_context_add_resource_size(ctx, state->zsbuf->texture);
1679
1680                 if (!surf->depth_initialized) {
1681                         r600_init_depth_surface(rctx, surf);
1682                 }
1683
1684                 r600_pipe_state_add_reg_bo(rstate, R_02800C_DB_DEPTH_BASE, surf->db_depth_base,
1685                                            res, RADEON_USAGE_READWRITE);
1686                 r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE, surf->db_depth_size);
1687                 r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, surf->db_depth_view);
1688                 r600_pipe_state_add_reg_bo(rstate, R_028010_DB_DEPTH_INFO, surf->db_depth_info,
1689                                            res, RADEON_USAGE_READWRITE);
1690                 r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT, surf->db_prefetch_limit);
1691         }
1692
1693         /* Framebuffer dimensions. */
1694         tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1695         br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1696
1697         r600_pipe_state_add_reg(rstate,
1698                                 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl);
1699         r600_pipe_state_add_reg(rstate,
1700                                 R_028208_PA_SC_WINDOW_SCISSOR_BR, br);
1701
1702         /* If we're doing MSAA resolve... */
1703         if (is_resolve) {
1704                 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL, 1);
1705         } else {
1706                 /* Always enable the first colorbuffer in CB_SHADER_CONTROL. This
1707                  * will assure that the alpha-test will work even if there is
1708                  * no colorbuffer bound. */
1709                 r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1710                                         (1ull << MAX2(state->nr_cbufs, 1)) - 1);
1711         }
1712
1713         /* Multisampling */
1714         if (state->nr_cbufs)
1715                 nr_samples = state->cbufs[0]->texture->nr_samples;
1716         else if (state->zsbuf)
1717                 nr_samples = state->zsbuf->texture->nr_samples;
1718         else
1719                 nr_samples = 0;
1720
1721         max_dist = r600_set_ms_pos(ctx, rstate, nr_samples);
1722
1723         if (nr_samples > 1) {
1724                 unsigned log_samples = util_logbase2(nr_samples);
1725
1726                 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL,
1727                                         S_028C00_LAST_PIXEL(1) |
1728                                         S_028C00_EXPAND_LINE_WIDTH(1));
1729                 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1730                                         S_028C04_MSAA_NUM_SAMPLES(log_samples) |
1731                                         S_028C04_MAX_SAMPLE_DIST(max_dist));
1732         } else {
1733                 r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, S_028C00_LAST_PIXEL(1));
1734                 r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG, 0);
1735         }
1736
1737         free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1738         rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1739         r600_context_pipe_state_set(rctx, rstate);
1740
1741         if (state->zsbuf) {
1742                 r600_polygon_offset_update(rctx);
1743         }
1744
1745         if (rctx->cb_misc_state.nr_cbufs != state->nr_cbufs) {
1746                 rctx->cb_misc_state.nr_cbufs = state->nr_cbufs;
1747                 r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
1748         }
1749
1750         if (state->nr_cbufs == 0 && rctx->alphatest_state.bypass) {
1751                 rctx->alphatest_state.bypass = false;
1752                 r600_atom_dirty(rctx, &rctx->alphatest_state.atom);
1753         }
1754 }
1755
1756 static void r600_emit_cb_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1757 {
1758         struct radeon_winsys_cs *cs = rctx->cs;
1759         struct r600_cb_misc_state *a = (struct r600_cb_misc_state*)atom;
1760
1761         if (G_028808_SPECIAL_OP(a->cb_color_control) == V_028808_SPECIAL_RESOLVE_BOX) {
1762                 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1763                 if (rctx->chip_class == R600) {
1764                         r600_write_value(cs, 0xff); /* R_028238_CB_TARGET_MASK */
1765                         r600_write_value(cs, 0xff); /* R_02823C_CB_SHADER_MASK */
1766                 } else {
1767                         r600_write_value(cs, 0xf); /* R_028238_CB_TARGET_MASK */
1768                         r600_write_value(cs, 0xf); /* R_02823C_CB_SHADER_MASK */
1769                 }
1770                 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL, a->cb_color_control);
1771         } else {
1772                 unsigned fb_colormask = (1ULL << ((unsigned)a->nr_cbufs * 4)) - 1;
1773                 unsigned ps_colormask = (1ULL << ((unsigned)a->nr_ps_color_outputs * 4)) - 1;
1774                 unsigned multiwrite = a->multiwrite && a->nr_cbufs > 1;
1775
1776                 r600_write_context_reg_seq(cs, R_028238_CB_TARGET_MASK, 2);
1777                 r600_write_value(cs, a->blend_colormask & fb_colormask); /* R_028238_CB_TARGET_MASK */
1778                 /* Always enable the first color output to make sure alpha-test works even without one. */
1779                 r600_write_value(cs, 0xf | (multiwrite ? fb_colormask : ps_colormask)); /* R_02823C_CB_SHADER_MASK */
1780                 r600_write_context_reg(cs, R_028808_CB_COLOR_CONTROL,
1781                                        a->cb_color_control |
1782                                        S_028808_MULTIWRITE_ENABLE(multiwrite));
1783         }
1784 }
1785
1786 static void r600_emit_db_misc_state(struct r600_context *rctx, struct r600_atom *atom)
1787 {
1788         struct radeon_winsys_cs *cs = rctx->cs;
1789         struct r600_db_misc_state *a = (struct r600_db_misc_state*)atom;
1790         unsigned db_render_control = 0;
1791         unsigned db_render_override =
1792                 S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
1793                 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
1794                 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
1795
1796         if (a->occlusion_query_enabled) {
1797                 if (rctx->chip_class >= R700) {
1798                         db_render_control |= S_028D0C_R700_PERFECT_ZPASS_COUNTS(1);
1799                 }
1800                 db_render_override |= S_028D10_NOOP_CULL_DISABLE(1);
1801         }
1802         if (a->flush_depthstencil_through_cb) {
1803                 assert(a->copy_depth || a->copy_stencil);
1804
1805                 db_render_control |= S_028D0C_DEPTH_COPY_ENABLE(a->copy_depth) |
1806                                      S_028D0C_STENCIL_COPY_ENABLE(a->copy_stencil) |
1807                                      S_028D0C_COPY_CENTROID(1) |
1808                                      S_028D0C_COPY_SAMPLE(a->copy_sample);
1809         }
1810
1811         r600_write_context_reg_seq(cs, R_028D0C_DB_RENDER_CONTROL, 2);
1812         r600_write_value(cs, db_render_control); /* R_028D0C_DB_RENDER_CONTROL */
1813         r600_write_value(cs, db_render_override); /* R_028D10_DB_RENDER_OVERRIDE */
1814 }
1815
1816 static void r600_emit_vertex_buffers(struct r600_context *rctx, struct r600_atom *atom)
1817 {
1818         struct radeon_winsys_cs *cs = rctx->cs;
1819         uint32_t dirty_mask = rctx->vertex_buffer_state.dirty_mask;
1820
1821         while (dirty_mask) {
1822                 struct pipe_vertex_buffer *vb;
1823                 struct r600_resource *rbuffer;
1824                 unsigned offset;
1825                 unsigned buffer_index = u_bit_scan(&dirty_mask);
1826
1827                 vb = &rctx->vertex_buffer_state.vb[buffer_index];
1828                 rbuffer = (struct r600_resource*)vb->buffer;
1829                 assert(rbuffer);
1830
1831                 offset = vb->buffer_offset;
1832
1833                 /* fetch resources start at index 320 */
1834                 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1835                 r600_write_value(cs, (320 + buffer_index) * 7);
1836                 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1837                 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1838                 r600_write_value(cs, /* RESOURCEi_WORD2 */
1839                                  S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1840                                  S_038008_STRIDE(vb->stride));
1841                 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1842                 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1843                 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1844                 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1845
1846                 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1847                 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1848         }
1849 }
1850
1851 static void r600_emit_constant_buffers(struct r600_context *rctx,
1852                                        struct r600_constbuf_state *state,
1853                                        unsigned buffer_id_base,
1854                                        unsigned reg_alu_constbuf_size,
1855                                        unsigned reg_alu_const_cache)
1856 {
1857         struct radeon_winsys_cs *cs = rctx->cs;
1858         uint32_t dirty_mask = state->dirty_mask;
1859
1860         while (dirty_mask) {
1861                 struct pipe_constant_buffer *cb;
1862                 struct r600_resource *rbuffer;
1863                 unsigned offset;
1864                 unsigned buffer_index = ffs(dirty_mask) - 1;
1865
1866                 cb = &state->cb[buffer_index];
1867                 rbuffer = (struct r600_resource*)cb->buffer;
1868                 assert(rbuffer);
1869
1870                 offset = cb->buffer_offset;
1871
1872                 r600_write_context_reg(cs, reg_alu_constbuf_size + buffer_index * 4,
1873                                        ALIGN_DIVUP(cb->buffer_size >> 4, 16));
1874                 r600_write_context_reg(cs, reg_alu_const_cache + buffer_index * 4, offset >> 8);
1875
1876                 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1877                 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1878
1879                 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1880                 r600_write_value(cs, (buffer_id_base + buffer_index) * 7);
1881                 r600_write_value(cs, offset); /* RESOURCEi_WORD0 */
1882                 r600_write_value(cs, rbuffer->buf->size - offset - 1); /* RESOURCEi_WORD1 */
1883                 r600_write_value(cs, /* RESOURCEi_WORD2 */
1884                                  S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
1885                                  S_038008_STRIDE(16));
1886                 r600_write_value(cs, 0); /* RESOURCEi_WORD3 */
1887                 r600_write_value(cs, 0); /* RESOURCEi_WORD4 */
1888                 r600_write_value(cs, 0); /* RESOURCEi_WORD5 */
1889                 r600_write_value(cs, 0xc0000000); /* RESOURCEi_WORD6 */
1890
1891                 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1892                 r600_write_value(cs, r600_context_bo_reloc(rctx, rbuffer, RADEON_USAGE_READ));
1893
1894                 dirty_mask &= ~(1 << buffer_index);
1895         }
1896         state->dirty_mask = 0;
1897 }
1898
1899 static void r600_emit_vs_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1900 {
1901         r600_emit_constant_buffers(rctx, &rctx->vs_constbuf_state, 160,
1902                                    R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
1903                                    R_028980_ALU_CONST_CACHE_VS_0);
1904 }
1905
1906 static void r600_emit_ps_constant_buffers(struct r600_context *rctx, struct r600_atom *atom)
1907 {
1908         r600_emit_constant_buffers(rctx, &rctx->ps_constbuf_state, 0,
1909                                    R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
1910                                    R_028940_ALU_CONST_CACHE_PS_0);
1911 }
1912
1913 static void r600_emit_sampler_views(struct r600_context *rctx,
1914                                     struct r600_samplerview_state *state,
1915                                     unsigned resource_id_base)
1916 {
1917         struct radeon_winsys_cs *cs = rctx->cs;
1918         uint32_t dirty_mask = state->dirty_mask;
1919
1920         while (dirty_mask) {
1921                 struct r600_pipe_sampler_view *rview;
1922                 unsigned resource_index = u_bit_scan(&dirty_mask);
1923                 unsigned reloc;
1924
1925                 rview = state->views[resource_index];
1926                 assert(rview);
1927
1928                 r600_write_value(cs, PKT3(PKT3_SET_RESOURCE, 7, 0));
1929                 r600_write_value(cs, (resource_id_base + resource_index) * 7);
1930                 r600_write_array(cs, 7, rview->tex_resource_words);
1931
1932                 /* XXX The kernel needs two relocations. This is stupid. */
1933                 reloc = r600_context_bo_reloc(rctx, rview->tex_resource,
1934                                               RADEON_USAGE_READ);
1935                 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1936                 r600_write_value(cs, reloc);
1937                 r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
1938                 r600_write_value(cs, reloc);
1939         }
1940         state->dirty_mask = 0;
1941 }
1942
1943 static void r600_emit_vs_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1944 {
1945         r600_emit_sampler_views(rctx, &rctx->vs_samplers.views, 160 + R600_MAX_CONST_BUFFERS);
1946 }
1947
1948 static void r600_emit_ps_sampler_views(struct r600_context *rctx, struct r600_atom *atom)
1949 {
1950         r600_emit_sampler_views(rctx, &rctx->ps_samplers.views, R600_MAX_CONST_BUFFERS);
1951 }
1952
1953 static void r600_emit_sampler(struct r600_context *rctx,
1954                                 struct r600_textures_info *texinfo,
1955                                 unsigned resource_id_base,
1956                                 unsigned border_color_reg)
1957 {
1958         struct radeon_winsys_cs *cs = rctx->cs;
1959         unsigned i;
1960
1961         for (i = 0; i < texinfo->n_samplers; i++) {
1962
1963                 if (texinfo->samplers[i] == NULL) {
1964                         continue;
1965                 }
1966
1967                 /* TEX_ARRAY_OVERRIDE must be set for array textures to disable
1968                  * filtering between layers.
1969                  * Don't update TEX_ARRAY_OVERRIDE if we don't have the sampler view.
1970                  */
1971                 if (texinfo->views.views[i]) {
1972                         if (texinfo->views.views[i]->base.texture->target == PIPE_TEXTURE_1D_ARRAY ||
1973                             texinfo->views.views[i]->base.texture->target == PIPE_TEXTURE_2D_ARRAY) {
1974                                 texinfo->samplers[i]->tex_sampler_words[0] |= S_03C000_TEX_ARRAY_OVERRIDE(1);
1975                                 texinfo->is_array_sampler[i] = true;
1976                         } else {
1977                                 texinfo->samplers[i]->tex_sampler_words[0] &= C_03C000_TEX_ARRAY_OVERRIDE;
1978                                 texinfo->is_array_sampler[i] = false;
1979                         }
1980                 }
1981
1982                 r600_write_value(cs, PKT3(PKT3_SET_SAMPLER, 3, 0));
1983                 r600_write_value(cs, (resource_id_base + i) * 3);
1984                 r600_write_array(cs, 3, texinfo->samplers[i]->tex_sampler_words);
1985
1986                 if (texinfo->samplers[i]->border_color_use) {
1987                         unsigned offset;
1988
1989                         offset = border_color_reg;
1990                         offset += i * 16;
1991                         r600_write_config_reg_seq(cs, offset, 4);
1992                         r600_write_array(cs, 4, texinfo->samplers[i]->border_color);
1993                 }
1994         }
1995 }
1996
1997 static void r600_emit_vs_sampler(struct r600_context *rctx, struct r600_atom *atom)
1998 {
1999         r600_emit_sampler(rctx, &rctx->vs_samplers, 18, R_00A600_TD_VS_SAMPLER0_BORDER_RED);
2000 }
2001
2002 static void r600_emit_ps_sampler(struct r600_context *rctx, struct r600_atom *atom)
2003 {
2004         r600_emit_sampler(rctx, &rctx->ps_samplers, 0, R_00A400_TD_PS_SAMPLER0_BORDER_RED);
2005 }
2006
2007 static void r600_emit_seamless_cube_map(struct r600_context *rctx, struct r600_atom *atom)
2008 {
2009         struct radeon_winsys_cs *cs = rctx->cs;
2010         unsigned tmp;
2011
2012         tmp = S_009508_DISABLE_CUBE_ANISO(1) |
2013                 S_009508_SYNC_GRADIENT(1) |
2014                 S_009508_SYNC_WALKER(1) |
2015                 S_009508_SYNC_ALIGNER(1);
2016         if (!rctx->seamless_cube_map.enabled) {
2017                 tmp |= S_009508_DISABLE_CUBE_WRAP(1);
2018         }
2019         r600_write_config_reg(cs, R_009508_TA_CNTL_AUX, tmp);
2020 }
2021
2022 static void r600_emit_sample_mask(struct r600_context *rctx, struct r600_atom *a)
2023 {
2024         struct r600_sample_mask *s = (struct r600_sample_mask*)a;
2025         uint8_t mask = s->sample_mask;
2026
2027         r600_write_context_reg(rctx->cs, R_028C48_PA_SC_AA_MASK,
2028                                mask | (mask << 8) | (mask << 16) | (mask << 24));
2029 }
2030
2031 void r600_init_state_functions(struct r600_context *rctx)
2032 {
2033         r600_init_atom(&rctx->seamless_cube_map.atom, r600_emit_seamless_cube_map, 3, 0);
2034         r600_atom_dirty(rctx, &rctx->seamless_cube_map.atom);
2035         r600_init_atom(&rctx->cb_misc_state.atom, r600_emit_cb_misc_state, 0, 0);
2036         r600_atom_dirty(rctx, &rctx->cb_misc_state.atom);
2037         r600_init_atom(&rctx->db_misc_state.atom, r600_emit_db_misc_state, 4, 0);
2038         r600_atom_dirty(rctx, &rctx->db_misc_state.atom);
2039         r600_init_atom(&rctx->vertex_buffer_state.atom, r600_emit_vertex_buffers, 0, 0);
2040         r600_init_atom(&rctx->vs_constbuf_state.atom, r600_emit_vs_constant_buffers, 0, 0);
2041         r600_init_atom(&rctx->ps_constbuf_state.atom, r600_emit_ps_constant_buffers, 0, 0);
2042         r600_init_atom(&rctx->vs_samplers.views.atom, r600_emit_vs_sampler_views, 0, 0);
2043         r600_init_atom(&rctx->ps_samplers.views.atom, r600_emit_ps_sampler_views, 0, 0);
2044         /* sampler must be emited before TA_CNTL_AUX otherwise DISABLE_CUBE_WRAP change
2045          * does not take effect
2046          */
2047         r600_init_atom(&rctx->vs_samplers.atom_sampler, r600_emit_vs_sampler, 0, EMIT_EARLY);
2048         r600_init_atom(&rctx->ps_samplers.atom_sampler, r600_emit_ps_sampler, 0, EMIT_EARLY);
2049
2050         r600_init_atom(&rctx->sample_mask.atom, r600_emit_sample_mask, 3, 0);
2051         rctx->sample_mask.sample_mask = ~0;
2052         r600_atom_dirty(rctx, &rctx->sample_mask.atom);
2053
2054         rctx->context.create_blend_state = r600_create_blend_state;
2055         rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
2056         rctx->context.create_fs_state = r600_create_shader_state_ps;
2057         rctx->context.create_rasterizer_state = r600_create_rs_state;
2058         rctx->context.create_sampler_state = r600_create_sampler_state;
2059         rctx->context.create_sampler_view = r600_create_sampler_view;
2060         rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
2061         rctx->context.create_vs_state = r600_create_shader_state_vs;
2062         rctx->context.bind_blend_state = r600_bind_blend_state;
2063         rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
2064         rctx->context.bind_fragment_sampler_states = r600_bind_ps_samplers;
2065         rctx->context.bind_fs_state = r600_bind_ps_shader;
2066         rctx->context.bind_rasterizer_state = r600_bind_rs_state;
2067         rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
2068         rctx->context.bind_vertex_sampler_states = r600_bind_vs_samplers;
2069         rctx->context.bind_vs_state = r600_bind_vs_shader;
2070         rctx->context.delete_blend_state = r600_delete_state;
2071         rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
2072         rctx->context.delete_fs_state = r600_delete_ps_shader;
2073         rctx->context.delete_rasterizer_state = r600_delete_rs_state;
2074         rctx->context.delete_sampler_state = r600_delete_sampler;
2075         rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
2076         rctx->context.delete_vs_state = r600_delete_vs_shader;
2077         rctx->context.set_blend_color = r600_set_blend_color;
2078         rctx->context.set_clip_state = r600_set_clip_state;
2079         rctx->context.set_constant_buffer = r600_set_constant_buffer;
2080         rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_views;
2081         rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
2082         rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
2083         rctx->context.set_sample_mask = r600_set_sample_mask;
2084         rctx->context.set_scissor_state = r600_pipe_set_scissor_state;
2085         rctx->context.set_stencil_ref = r600_set_pipe_stencil_ref;
2086         rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
2087         rctx->context.set_index_buffer = r600_set_index_buffer;
2088         rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_views;
2089         rctx->context.set_viewport_state = r600_set_viewport_state;
2090         rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
2091         rctx->context.texture_barrier = r600_texture_barrier;
2092         rctx->context.create_stream_output_target = r600_create_so_target;
2093         rctx->context.stream_output_target_destroy = r600_so_target_destroy;
2094         rctx->context.set_stream_output_targets = r600_set_so_targets;
2095 }
2096
2097 /* Adjust GPR allocation on R6xx/R7xx */
2098 void r600_adjust_gprs(struct r600_context *rctx)
2099 {
2100         struct r600_pipe_state rstate;
2101         unsigned num_ps_gprs = rctx->default_ps_gprs;
2102         unsigned num_vs_gprs = rctx->default_vs_gprs;
2103         unsigned tmp;
2104         int diff;
2105
2106         /* XXX: Following call moved from r600_bind_[ps|vs]_shader,
2107          * it seems eg+ doesn't need it, r6xx/7xx probably need it only for
2108          * adjusting the GPR allocation?
2109          * Do we need this if we aren't really changing config below? */
2110         r600_inval_shader_cache(rctx);
2111
2112         if (rctx->ps_shader->current->shader.bc.ngpr > rctx->default_ps_gprs)
2113         {
2114                 diff = rctx->ps_shader->current->shader.bc.ngpr - rctx->default_ps_gprs;
2115                 num_vs_gprs -= diff;
2116                 num_ps_gprs += diff;
2117         }
2118
2119         if (rctx->vs_shader->current->shader.bc.ngpr > rctx->default_vs_gprs)
2120         {
2121                 diff = rctx->vs_shader->current->shader.bc.ngpr - rctx->default_vs_gprs;
2122                 num_ps_gprs -= diff;
2123                 num_vs_gprs += diff;
2124         }
2125
2126         tmp = 0;
2127         tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
2128         tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
2129         tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx->r6xx_num_clause_temp_gprs);
2130         rstate.nregs = 0;
2131         r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp);
2132
2133         r600_context_pipe_state_set(rctx, &rstate);
2134 }
2135
2136 void r600_init_atom_start_cs(struct r600_context *rctx)
2137 {
2138         int ps_prio;
2139         int vs_prio;
2140         int gs_prio;
2141         int es_prio;
2142         int num_ps_gprs;
2143         int num_vs_gprs;
2144         int num_gs_gprs;
2145         int num_es_gprs;
2146         int num_temp_gprs;
2147         int num_ps_threads;
2148         int num_vs_threads;
2149         int num_gs_threads;
2150         int num_es_threads;
2151         int num_ps_stack_entries;
2152         int num_vs_stack_entries;
2153         int num_gs_stack_entries;
2154         int num_es_stack_entries;
2155         enum radeon_family family;
2156         struct r600_command_buffer *cb = &rctx->start_cs_cmd;
2157         uint32_t tmp;
2158
2159         r600_init_command_buffer(cb, 256, EMIT_EARLY);
2160
2161         /* R6xx requires this packet at the start of each command buffer */
2162         if (rctx->chip_class == R600) {
2163                 r600_store_value(cb, PKT3(PKT3_START_3D_CMDBUF, 0, 0));
2164                 r600_store_value(cb, 0);
2165         }
2166         /* All asics require this one */
2167         r600_store_value(cb, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2168         r600_store_value(cb, 0x80000000);
2169         r600_store_value(cb, 0x80000000);
2170
2171         family = rctx->family;
2172         ps_prio = 0;
2173         vs_prio = 1;
2174         gs_prio = 2;
2175         es_prio = 3;
2176         switch (family) {
2177         case CHIP_R600:
2178                 num_ps_gprs = 192;
2179                 num_vs_gprs = 56;
2180                 num_temp_gprs = 4;
2181                 num_gs_gprs = 0;
2182                 num_es_gprs = 0;
2183                 num_ps_threads = 136;
2184                 num_vs_threads = 48;
2185                 num_gs_threads = 4;
2186                 num_es_threads = 4;
2187                 num_ps_stack_entries = 128;
2188                 num_vs_stack_entries = 128;
2189                 num_gs_stack_entries = 0;
2190                 num_es_stack_entries = 0;
2191                 break;
2192         case CHIP_RV630:
2193         case CHIP_RV635:
2194                 num_ps_gprs = 84;
2195                 num_vs_gprs = 36;
2196                 num_temp_gprs = 4;
2197                 num_gs_gprs = 0;
2198                 num_es_gprs = 0;
2199                 num_ps_threads = 144;
2200                 num_vs_threads = 40;
2201                 num_gs_threads = 4;
2202                 num_es_threads = 4;
2203                 num_ps_stack_entries = 40;
2204                 num_vs_stack_entries = 40;
2205                 num_gs_stack_entries = 32;
2206                 num_es_stack_entries = 16;
2207                 break;
2208         case CHIP_RV610:
2209         case CHIP_RV620:
2210         case CHIP_RS780:
2211         case CHIP_RS880:
2212         default:
2213                 num_ps_gprs = 84;
2214                 num_vs_gprs = 36;
2215                 num_temp_gprs = 4;
2216                 num_gs_gprs = 0;
2217                 num_es_gprs = 0;
2218                 num_ps_threads = 136;
2219                 num_vs_threads = 48;
2220                 num_gs_threads = 4;
2221                 num_es_threads = 4;
2222                 num_ps_stack_entries = 40;
2223                 num_vs_stack_entries = 40;
2224                 num_gs_stack_entries = 32;
2225                 num_es_stack_entries = 16;
2226                 break;
2227         case CHIP_RV670:
2228                 num_ps_gprs = 144;
2229                 num_vs_gprs = 40;
2230                 num_temp_gprs = 4;
2231                 num_gs_gprs = 0;
2232                 num_es_gprs = 0;
2233                 num_ps_threads = 136;
2234                 num_vs_threads = 48;
2235                 num_gs_threads = 4;
2236                 num_es_threads = 4;
2237                 num_ps_stack_entries = 40;
2238                 num_vs_stack_entries = 40;
2239                 num_gs_stack_entries = 32;
2240                 num_es_stack_entries = 16;
2241                 break;
2242         case CHIP_RV770:
2243                 num_ps_gprs = 192;
2244                 num_vs_gprs = 56;
2245                 num_temp_gprs = 4;
2246                 num_gs_gprs = 0;
2247                 num_es_gprs = 0;
2248                 num_ps_threads = 188;
2249                 num_vs_threads = 60;
2250                 num_gs_threads = 0;
2251                 num_es_threads = 0;
2252                 num_ps_stack_entries = 256;
2253                 num_vs_stack_entries = 256;
2254                 num_gs_stack_entries = 0;
2255                 num_es_stack_entries = 0;
2256                 break;
2257         case CHIP_RV730:
2258         case CHIP_RV740:
2259                 num_ps_gprs = 84;
2260                 num_vs_gprs = 36;
2261                 num_temp_gprs = 4;
2262                 num_gs_gprs = 0;
2263                 num_es_gprs = 0;
2264                 num_ps_threads = 188;
2265                 num_vs_threads = 60;
2266                 num_gs_threads = 0;
2267                 num_es_threads = 0;
2268                 num_ps_stack_entries = 128;
2269                 num_vs_stack_entries = 128;
2270                 num_gs_stack_entries = 0;
2271                 num_es_stack_entries = 0;
2272                 break;
2273         case CHIP_RV710:
2274                 num_ps_gprs = 192;
2275                 num_vs_gprs = 56;
2276                 num_temp_gprs = 4;
2277                 num_gs_gprs = 0;
2278                 num_es_gprs = 0;
2279                 num_ps_threads = 144;
2280                 num_vs_threads = 48;
2281                 num_gs_threads = 0;
2282                 num_es_threads = 0;
2283                 num_ps_stack_entries = 128;
2284                 num_vs_stack_entries = 128;
2285                 num_gs_stack_entries = 0;
2286                 num_es_stack_entries = 0;
2287                 break;
2288         }
2289
2290         rctx->default_ps_gprs = num_ps_gprs;
2291         rctx->default_vs_gprs = num_vs_gprs;
2292         rctx->r6xx_num_clause_temp_gprs = num_temp_gprs;
2293
2294         /* SQ_CONFIG */
2295         tmp = 0;
2296         switch (family) {
2297         case CHIP_RV610:
2298         case CHIP_RV620:
2299         case CHIP_RS780:
2300         case CHIP_RS880:
2301         case CHIP_RV710:
2302                 break;
2303         default:
2304                 tmp |= S_008C00_VC_ENABLE(1);
2305                 break;
2306         }
2307         tmp |= S_008C00_DX9_CONSTS(0);
2308         tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
2309         tmp |= S_008C00_PS_PRIO(ps_prio);
2310         tmp |= S_008C00_VS_PRIO(vs_prio);
2311         tmp |= S_008C00_GS_PRIO(gs_prio);
2312         tmp |= S_008C00_ES_PRIO(es_prio);
2313         r600_store_config_reg(cb, R_008C00_SQ_CONFIG, tmp);
2314
2315         /* SQ_GPR_RESOURCE_MGMT_2 */
2316         tmp = S_008C08_NUM_GS_GPRS(num_gs_gprs);
2317         tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
2318         r600_store_config_reg_seq(cb, R_008C08_SQ_GPR_RESOURCE_MGMT_2, 4);
2319         r600_store_value(cb, tmp);
2320
2321         /* SQ_THREAD_RESOURCE_MGMT */
2322         tmp = S_008C0C_NUM_PS_THREADS(num_ps_threads);
2323         tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
2324         tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
2325         tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
2326         r600_store_value(cb, tmp); /* R_008C0C_SQ_THREAD_RESOURCE_MGMT */
2327
2328         /* SQ_STACK_RESOURCE_MGMT_1 */
2329         tmp = S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
2330         tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
2331         r600_store_value(cb, tmp); /* R_008C10_SQ_STACK_RESOURCE_MGMT_1 */
2332
2333         /* SQ_STACK_RESOURCE_MGMT_2 */
2334         tmp = S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
2335         tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
2336         r600_store_value(cb, tmp); /* R_008C14_SQ_STACK_RESOURCE_MGMT_2 */
2337
2338         r600_store_config_reg(cb, R_009714_VC_ENHANCE, 0);
2339
2340         if (rctx->chip_class >= R700) {
2341                 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000);
2342                 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0);
2343                 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x00420204);
2344                 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 0);
2345         } else {
2346                 r600_store_config_reg(cb, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2347                 r600_store_config_reg(cb, R_009830_DB_DEBUG, 0x82000000);
2348                 r600_store_config_reg(cb, R_009838_DB_WATERMARKS, 0x01020204);
2349                 r600_store_context_reg(cb, R_0286C8_SPI_THREAD_GROUPING, 1);
2350         }
2351         r600_store_context_reg_seq(cb, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 9);
2352         r600_store_value(cb, 0); /* R_0288A8_SQ_ESGS_RING_ITEMSIZE */
2353         r600_store_value(cb, 0); /* R_0288AC_SQ_GSVS_RING_ITEMSIZE */
2354         r600_store_value(cb, 0); /* R_0288B0_SQ_ESTMP_RING_ITEMSIZE */
2355         r600_store_value(cb, 0); /* R_0288B4_SQ_GSTMP_RING_ITEMSIZE */
2356         r600_store_value(cb, 0); /* R_0288B8_SQ_VSTMP_RING_ITEMSIZE */
2357         r600_store_value(cb, 0); /* R_0288BC_SQ_PSTMP_RING_ITEMSIZE */
2358         r600_store_value(cb, 0); /* R_0288C0_SQ_FBUF_RING_ITEMSIZE */
2359         r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */
2360         r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */
2361
2362         r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13);
2363         r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */
2364         r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */
2365         r600_store_value(cb, 0); /* R_028A18_VGT_HOS_MAX_TESS_LEVEL */
2366         r600_store_value(cb, 0); /* R_028A1C_VGT_HOS_MIN_TESS_LEVEL */
2367         r600_store_value(cb, 0); /* R_028A20_VGT_HOS_REUSE_DEPTH */
2368         r600_store_value(cb, 0); /* R_028A24_VGT_GROUP_PRIM_TYPE */
2369         r600_store_value(cb, 0); /* R_028A28_VGT_GROUP_FIRST_DECR */
2370         r600_store_value(cb, 0); /* R_028A2C_VGT_GROUP_DECR */
2371         r600_store_value(cb, 0); /* R_028A30_VGT_GROUP_VECT_0_CNTL */
2372         r600_store_value(cb, 0); /* R_028A34_VGT_GROUP_VECT_1_CNTL */
2373         r600_store_value(cb, 0); /* R_028A38_VGT_GROUP_VECT_0_FMT_CNTL */
2374         r600_store_value(cb, 0); /* R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL */
2375         r600_store_value(cb, 0); /* R_028A40_VGT_GS_MODE, 0); */
2376
2377         r600_store_context_reg(cb, R_028A84_VGT_PRIMITIVEID_EN, 0);
2378         r600_store_context_reg(cb, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0);
2379         r600_store_context_reg(cb, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0);
2380
2381         r600_store_context_reg_seq(cb, R_028AB0_VGT_STRMOUT_EN, 3);
2382         r600_store_value(cb, 0); /* R_028AB0_VGT_STRMOUT_EN */
2383         r600_store_value(cb, 1); /* R_028AB4_VGT_REUSE_OFF */
2384         r600_store_value(cb, 0); /* R_028AB8_VGT_VTX_CNT_EN */
2385
2386         r600_store_context_reg(cb, R_028B20_VGT_STRMOUT_BUFFER_EN, 0);
2387
2388         r600_store_context_reg_seq(cb, R_028400_VGT_MAX_VTX_INDX, 2);
2389         r600_store_value(cb, ~0); /* R_028400_VGT_MAX_VTX_INDX */
2390         r600_store_value(cb, 0); /* R_028404_VGT_MIN_VTX_INDX */
2391
2392         r600_store_ctl_const(cb, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0);
2393
2394         r600_store_context_reg_seq(cb, R_028028_DB_STENCIL_CLEAR, 2);
2395         r600_store_value(cb, 0); /* R_028028_DB_STENCIL_CLEAR */
2396         r600_store_value(cb, 0x3F800000); /* R_02802C_DB_DEPTH_CLEAR */
2397
2398         r600_store_context_reg_seq(cb, R_0286DC_SPI_FOG_CNTL, 3);
2399         r600_store_value(cb, 0); /* R_0286DC_SPI_FOG_CNTL */
2400         r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */
2401         r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */
2402
2403         r600_store_context_reg_seq(cb, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 2);
2404         r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */
2405         r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */
2406
2407         r600_store_context_reg(cb, R_028820_PA_CL_NANINF_CNTL, 0);
2408         r600_store_context_reg(cb, R_028A48_PA_SC_MPASS_PS_CNTL, 0);
2409
2410         r600_store_context_reg_seq(cb, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
2411         r600_store_value(cb, 0x3F800000); /* R_028C0C_PA_CL_GB_VERT_CLIP_ADJ */
2412         r600_store_value(cb, 0x3F800000); /* R_028C10_PA_CL_GB_VERT_DISC_ADJ */
2413         r600_store_value(cb, 0x3F800000); /* R_028C14_PA_CL_GB_HORZ_CLIP_ADJ */
2414         r600_store_value(cb, 0x3F800000); /* R_028C18_PA_CL_GB_HORZ_DISC_ADJ */
2415
2416         r600_store_context_reg_seq(cb, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
2417         r600_store_value(cb, 0); /* R_0282D0_PA_SC_VPORT_ZMIN_0 */
2418         r600_store_value(cb, 0x3F800000); /* R_0282D4_PA_SC_VPORT_ZMAX_0 */
2419
2420         r600_store_context_reg(cb, R_028818_PA_CL_VTE_CNTL, 0x43F);
2421
2422         r600_store_context_reg(cb, R_028200_PA_SC_WINDOW_OFFSET, 0);
2423         r600_store_context_reg(cb, R_02820C_PA_SC_CLIPRECT_RULE, 0xFFFF);
2424
2425         if (rctx->chip_class >= R700) {
2426                 r600_store_context_reg(cb, R_028230_PA_SC_EDGERULE, 0xAAAAAAAA);
2427         }
2428
2429         r600_store_context_reg_seq(cb, R_028C30_CB_CLRCMP_CONTROL, 4);
2430         r600_store_value(cb, 0x1000000);  /* R_028C30_CB_CLRCMP_CONTROL */
2431         r600_store_value(cb, 0);          /* R_028C34_CB_CLRCMP_SRC */
2432         r600_store_value(cb, 0xFF);       /* R_028C38_CB_CLRCMP_DST */
2433         r600_store_value(cb, 0xFFFFFFFF); /* R_028C3C_CB_CLRCMP_MSK */
2434
2435         r600_store_context_reg_seq(cb, R_028030_PA_SC_SCREEN_SCISSOR_TL, 2);
2436         r600_store_value(cb, 0); /* R_028030_PA_SC_SCREEN_SCISSOR_TL */
2437         r600_store_value(cb, S_028034_BR_X(8192) | S_028034_BR_Y(8192)); /* R_028034_PA_SC_SCREEN_SCISSOR_BR */
2438
2439         r600_store_context_reg_seq(cb, R_028240_PA_SC_GENERIC_SCISSOR_TL, 2);
2440         r600_store_value(cb, 0); /* R_028240_PA_SC_GENERIC_SCISSOR_TL */
2441         r600_store_value(cb, S_028244_BR_X(8192) | S_028244_BR_Y(8192)); /* R_028244_PA_SC_GENERIC_SCISSOR_BR */
2442
2443         r600_store_context_reg_seq(cb, R_0288CC_SQ_PGM_CF_OFFSET_PS, 2);
2444         r600_store_value(cb, 0); /* R_0288CC_SQ_PGM_CF_OFFSET_PS */
2445         r600_store_value(cb, 0); /* R_0288D0_SQ_PGM_CF_OFFSET_VS */
2446
2447         r600_store_context_reg(cb, R_0288A4_SQ_PGM_RESOURCES_FS, 0);
2448         r600_store_context_reg(cb, R_0288DC_SQ_PGM_CF_OFFSET_FS, 0);
2449
2450         if (rctx->chip_class == R700 && rctx->screen->has_streamout)
2451                 r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf));
2452         r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
2453         if (rctx->screen->has_streamout) {
2454                 r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
2455         }
2456
2457         r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
2458         r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x1000FFF);
2459 }
2460
2461 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2462 {
2463         struct r600_context *rctx = (struct r600_context *)ctx;
2464         struct r600_pipe_state *rstate = &shader->rstate;
2465         struct r600_shader *rshader = &shader->shader;
2466         unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
2467         int pos_index = -1, face_index = -1;
2468         unsigned tmp, sid, ufi = 0;
2469         int need_linear = 0;
2470         unsigned z_export = 0, stencil_export = 0;
2471
2472         rstate->nregs = 0;
2473
2474         for (i = 0; i < rshader->ninput; i++) {
2475                 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
2476                         pos_index = i;
2477                 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
2478                         face_index = i;
2479
2480                 sid = rshader->input[i].spi_sid;
2481
2482                 tmp = S_028644_SEMANTIC(sid);
2483
2484                 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION ||
2485                         rshader->input[i].interpolate == TGSI_INTERPOLATE_CONSTANT ||
2486                         (rshader->input[i].interpolate == TGSI_INTERPOLATE_COLOR &&
2487                                 rctx->rasterizer && rctx->rasterizer->flatshade))
2488                         tmp |= S_028644_FLAT_SHADE(1);
2489
2490                 if (rshader->input[i].name == TGSI_SEMANTIC_GENERIC &&
2491                                 rctx->sprite_coord_enable & (1 << rshader->input[i].sid)) {
2492                         tmp |= S_028644_PT_SPRITE_TEX(1);
2493                 }
2494
2495                 if (rshader->input[i].centroid)
2496                         tmp |= S_028644_SEL_CENTROID(1);
2497
2498                 if (rshader->input[i].interpolate == TGSI_INTERPOLATE_LINEAR) {
2499                         need_linear = 1;
2500                         tmp |= S_028644_SEL_LINEAR(1);
2501                 }
2502
2503                 r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 + i * 4,
2504                                 tmp);
2505         }
2506
2507         db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2508         for (i = 0; i < rshader->noutput; i++) {
2509                 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
2510                         z_export = 1;
2511                 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
2512                         stencil_export = 1;
2513         }
2514         db_shader_control |= S_02880C_Z_EXPORT_ENABLE(z_export);
2515         db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(stencil_export);
2516         if (rshader->uses_kill)
2517                 db_shader_control |= S_02880C_KILL_ENABLE(1);
2518
2519         exports_ps = 0;
2520         for (i = 0; i < rshader->noutput; i++) {
2521                 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
2522                     rshader->output[i].name == TGSI_SEMANTIC_STENCIL) {
2523                         exports_ps |= 1;
2524                 }
2525         }
2526         num_cout = rshader->nr_ps_color_exports;
2527         exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2528         if (!exports_ps) {
2529                 /* always at least export 1 component per pixel */
2530                 exports_ps = 2;
2531         }
2532
2533         shader->nr_ps_color_outputs = num_cout;
2534
2535         spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2536                                 S_0286CC_PERSP_GRADIENT_ENA(1)|
2537                                 S_0286CC_LINEAR_GRADIENT_ENA(need_linear);
2538         spi_input_z = 0;
2539         if (pos_index != -1) {
2540                 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2541                                         S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2542                                         S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2543                                         S_0286CC_BARYC_SAMPLE_CNTL(1));
2544                 spi_input_z |= 1;
2545         }
2546
2547         spi_ps_in_control_1 = 0;
2548         if (face_index != -1) {
2549                 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2550                         S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2551         }
2552
2553         /* HW bug in original R600 */
2554         if (rctx->family == CHIP_R600)
2555                 ufi = 1;
2556
2557         r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0);
2558         r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1);
2559         r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z);
2560         r600_pipe_state_add_reg_bo(rstate,
2561                                    R_028840_SQ_PGM_START_PS,
2562                                    0, shader->bo, RADEON_USAGE_READ);
2563         r600_pipe_state_add_reg(rstate,
2564                                 R_028850_SQ_PGM_RESOURCES_PS,
2565                                 S_028850_NUM_GPRS(rshader->bc.ngpr) |
2566                                 S_028850_STACK_SIZE(rshader->bc.nstack) |
2567                                 S_028850_UNCACHED_FIRST_INST(ufi));
2568         r600_pipe_state_add_reg(rstate,
2569                                 R_028854_SQ_PGM_EXPORTS_PS,
2570                                 exports_ps);
2571         /* only set some bits here, the other bits are set in the dsa state */
2572         shader->db_shader_control = db_shader_control;
2573         shader->ps_depth_export = z_export | stencil_export;
2574
2575         shader->sprite_coord_enable = rctx->sprite_coord_enable;
2576         if (rctx->rasterizer)
2577                 shader->flatshade = rctx->rasterizer->flatshade;
2578 }
2579
2580 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2581 {
2582         struct r600_context *rctx = (struct r600_context *)ctx;
2583         struct r600_pipe_state *rstate = &shader->rstate;
2584         struct r600_shader *rshader = &shader->shader;
2585         unsigned spi_vs_out_id[10] = {};
2586         unsigned i, tmp, nparams = 0;
2587
2588         /* clear previous register */
2589         rstate->nregs = 0;
2590
2591         for (i = 0; i < rshader->noutput; i++) {
2592                 if (rshader->output[i].spi_sid) {
2593                         tmp = rshader->output[i].spi_sid << ((nparams & 3) * 8);
2594                         spi_vs_out_id[nparams / 4] |= tmp;
2595                         nparams++;
2596                 }
2597         }
2598
2599         for (i = 0; i < 10; i++) {
2600                 r600_pipe_state_add_reg(rstate,
2601                                         R_028614_SPI_VS_OUT_ID_0 + i * 4,
2602                                         spi_vs_out_id[i]);
2603         }
2604
2605         /* Certain attributes (position, psize, etc.) don't count as params.
2606          * VS is required to export at least one param and r600_shader_from_tgsi()
2607          * takes care of adding a dummy export.
2608          */
2609         if (nparams < 1)
2610                 nparams = 1;
2611
2612         r600_pipe_state_add_reg(rstate,
2613                                 R_0286C4_SPI_VS_OUT_CONFIG,
2614                                 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
2615         r600_pipe_state_add_reg(rstate,
2616                                 R_028868_SQ_PGM_RESOURCES_VS,
2617                                 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2618                                 S_028868_STACK_SIZE(rshader->bc.nstack));
2619         r600_pipe_state_add_reg_bo(rstate,
2620                         R_028858_SQ_PGM_START_VS,
2621                         0, shader->bo, RADEON_USAGE_READ);
2622
2623         shader->pa_cl_vs_out_cntl =
2624                 S_02881C_VS_OUT_CCDIST0_VEC_ENA((rshader->clip_dist_write & 0x0F) != 0) |
2625                 S_02881C_VS_OUT_CCDIST1_VEC_ENA((rshader->clip_dist_write & 0xF0) != 0) |
2626                 S_02881C_VS_OUT_MISC_VEC_ENA(rshader->vs_out_misc_write) |
2627                 S_02881C_USE_VTX_POINT_SIZE(rshader->vs_out_point_size);
2628 }
2629
2630 void r600_fetch_shader(struct pipe_context *ctx,
2631                        struct r600_vertex_element *ve)
2632 {
2633         struct r600_pipe_state *rstate;
2634         struct r600_context *rctx = (struct r600_context *)ctx;
2635
2636         rstate = &ve->rstate;
2637         rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2638         rstate->nregs = 0;
2639         r600_pipe_state_add_reg_bo(rstate, R_028894_SQ_PGM_START_FS,
2640                                 0,
2641                                 ve->fetch_shader, RADEON_USAGE_READ);
2642 }
2643
2644 void *r600_create_resolve_blend(struct r600_context *rctx)
2645 {
2646         struct pipe_blend_state blend;
2647         struct r600_pipe_state *rstate;
2648         unsigned i;
2649
2650         memset(&blend, 0, sizeof(blend));
2651         blend.independent_blend_enable = true;
2652         for (i = 0; i < 2; i++) {
2653                 blend.rt[i].colormask = 0xf;
2654                 blend.rt[i].blend_enable = 1;
2655                 blend.rt[i].rgb_func = PIPE_BLEND_ADD;
2656                 blend.rt[i].alpha_func = PIPE_BLEND_ADD;
2657                 blend.rt[i].rgb_src_factor = PIPE_BLENDFACTOR_ZERO;
2658                 blend.rt[i].rgb_dst_factor = PIPE_BLENDFACTOR_ZERO;
2659                 blend.rt[i].alpha_src_factor = PIPE_BLENDFACTOR_ZERO;
2660                 blend.rt[i].alpha_dst_factor = PIPE_BLENDFACTOR_ZERO;
2661         }
2662         rstate = r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2663         return rstate;
2664 }
2665
2666 void *r700_create_resolve_blend(struct r600_context *rctx)
2667 {
2668         struct pipe_blend_state blend;
2669         struct r600_pipe_state *rstate;
2670
2671         memset(&blend, 0, sizeof(blend));
2672         blend.independent_blend_enable = true;
2673         blend.rt[0].colormask = 0xf;
2674         rstate = r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_RESOLVE_BOX);
2675         return rstate;
2676 }
2677
2678 void *r600_create_decompress_blend(struct r600_context *rctx)
2679 {
2680         struct pipe_blend_state blend;
2681         struct r600_pipe_state *rstate;
2682
2683         memset(&blend, 0, sizeof(blend));
2684         blend.independent_blend_enable = true;
2685         blend.rt[0].colormask = 0xf;
2686         rstate = r600_create_blend_state_mode(&rctx->context, &blend, V_028808_SPECIAL_EXPAND_SAMPLES);
2687         return rstate;
2688 }
2689
2690 void *r600_create_db_flush_dsa(struct r600_context *rctx)
2691 {
2692         struct pipe_depth_stencil_alpha_state dsa;
2693         boolean quirk = false;
2694
2695         if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
2696                 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
2697                 quirk = true;
2698
2699         memset(&dsa, 0, sizeof(dsa));
2700
2701         if (quirk) {
2702                 dsa.depth.enabled = 1;
2703                 dsa.depth.func = PIPE_FUNC_LEQUAL;
2704                 dsa.stencil[0].enabled = 1;
2705                 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2706                 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2707                 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2708                 dsa.stencil[0].writemask = 0xff;
2709         }
2710
2711         return rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2712 }
2713
2714 void r600_update_dual_export_state(struct r600_context * rctx)
2715 {
2716         unsigned dual_export = rctx->export_16bpc && rctx->nr_cbufs &&
2717                                !rctx->ps_shader->current->ps_depth_export;
2718         unsigned db_shader_control = rctx->ps_shader->current->db_shader_control |
2719                                      S_02880C_DUAL_EXPORT_ENABLE(dual_export);
2720
2721         if (db_shader_control != rctx->db_shader_control) {
2722                 struct r600_pipe_state rstate;
2723
2724                 rctx->db_shader_control = db_shader_control;
2725                 rstate.nregs = 0;
2726                 r600_pipe_state_add_reg(&rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control);
2727                 r600_context_pipe_state_set(rctx, &rstate);
2728         }
2729 }