src/gallium/drivers/r600/r600_state.c

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /* TODO:
  25  *      - fix mask for depth control & cull for query
  26  */
  27 #include <stdio.h>
  28 #include <errno.h>
  29 #include <pipe/p_defines.h>
  30 #include <pipe/p_state.h>
  31 #include <pipe/p_context.h>
  32 #include <tgsi/tgsi_scan.h>
  33 #include <tgsi/tgsi_parse.h>
  34 #include <tgsi/tgsi_util.h>
  35 #include <util/u_double_list.h>
  36 #include <util/u_pack_color.h>
  37 #include <util/u_memory.h>
  38 #include <util/u_inlines.h>
  39 #include <util/u_framebuffer.h>
  40 #include "util/u_transfer.h"
  41 #include <pipebuffer/pb_buffer.h>
  42 #include "r600.h"
  43 #include "r600d.h"
  44 #include "r600_resource.h"
  45 #include "r600_shader.h"
  46 #include "r600_pipe.h"
  47 #include "r600_formats.h"
  48
  49 static uint32_t r600_translate_blend_function(int blend_func)
  50 {
  51         switch (blend_func) {
  52         case PIPE_BLEND_ADD:
  53                 return V_028804_COMB_DST_PLUS_SRC;
  54         case PIPE_BLEND_SUBTRACT:
  55                 return V_028804_COMB_SRC_MINUS_DST;
  56         case PIPE_BLEND_REVERSE_SUBTRACT:
  57                 return V_028804_COMB_DST_MINUS_SRC;
  58         case PIPE_BLEND_MIN:
  59                 return V_028804_COMB_MIN_DST_SRC;
  60         case PIPE_BLEND_MAX:
  61                 return V_028804_COMB_MAX_DST_SRC;
  62         default:
  63                 R600_ERR("Unknown blend function %d\n", blend_func);
  64                 assert(0);
  65                 break;
  66         }
  67         return 0;
  68 }
  69
  70 static uint32_t r600_translate_blend_factor(int blend_fact)
  71 {
  72         switch (blend_fact) {
  73         case PIPE_BLENDFACTOR_ONE:
  74                 return V_028804_BLEND_ONE;
  75         case PIPE_BLENDFACTOR_SRC_COLOR:
  76                 return V_028804_BLEND_SRC_COLOR;
  77         case PIPE_BLENDFACTOR_SRC_ALPHA:
  78                 return V_028804_BLEND_SRC_ALPHA;
  79         case PIPE_BLENDFACTOR_DST_ALPHA:
  80                 return V_028804_BLEND_DST_ALPHA;
  81         case PIPE_BLENDFACTOR_DST_COLOR:
  82                 return V_028804_BLEND_DST_COLOR;
  83         case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
  84                 return V_028804_BLEND_SRC_ALPHA_SATURATE;
  85         case PIPE_BLENDFACTOR_CONST_COLOR:
  86                 return V_028804_BLEND_CONST_COLOR;
  87         case PIPE_BLENDFACTOR_CONST_ALPHA:
  88                 return V_028804_BLEND_CONST_ALPHA;
  89         case PIPE_BLENDFACTOR_ZERO:
  90                 return V_028804_BLEND_ZERO;
  91         case PIPE_BLENDFACTOR_INV_SRC_COLOR:
  92                 return V_028804_BLEND_ONE_MINUS_SRC_COLOR;
  93         case PIPE_BLENDFACTOR_INV_SRC_ALPHA:
  94                 return V_028804_BLEND_ONE_MINUS_SRC_ALPHA;
  95         case PIPE_BLENDFACTOR_INV_DST_ALPHA:
  96                 return V_028804_BLEND_ONE_MINUS_DST_ALPHA;
  97         case PIPE_BLENDFACTOR_INV_DST_COLOR:
  98                 return V_028804_BLEND_ONE_MINUS_DST_COLOR;
  99         case PIPE_BLENDFACTOR_INV_CONST_COLOR:
 100                 return V_028804_BLEND_ONE_MINUS_CONST_COLOR;
 101         case PIPE_BLENDFACTOR_INV_CONST_ALPHA:
 102                 return V_028804_BLEND_ONE_MINUS_CONST_ALPHA;
 103         case PIPE_BLENDFACTOR_SRC1_COLOR:
 104                 return V_028804_BLEND_SRC1_COLOR;
 105         case PIPE_BLENDFACTOR_SRC1_ALPHA:
 106                 return V_028804_BLEND_SRC1_ALPHA;
 107         case PIPE_BLENDFACTOR_INV_SRC1_COLOR:
 108                 return V_028804_BLEND_INV_SRC1_COLOR;
 109         case PIPE_BLENDFACTOR_INV_SRC1_ALPHA:
 110                 return V_028804_BLEND_INV_SRC1_ALPHA;
 111         default:
 112                 R600_ERR("Bad blend factor %d not supported!\n", blend_fact);
 113                 assert(0);
 114                 break;
 115         }
 116         return 0;
 117 }
 118
 119 static uint32_t r600_translate_stencil_op(int s_op)
 120 {
 121         switch (s_op) {
 122         case PIPE_STENCIL_OP_KEEP:
 123                 return V_028800_STENCIL_KEEP;
 124         case PIPE_STENCIL_OP_ZERO:
 125                 return V_028800_STENCIL_ZERO;
 126         case PIPE_STENCIL_OP_REPLACE:
 127                 return V_028800_STENCIL_REPLACE;
 128         case PIPE_STENCIL_OP_INCR:
 129                 return V_028800_STENCIL_INCR;
 130         case PIPE_STENCIL_OP_DECR:
 131                 return V_028800_STENCIL_DECR;
 132         case PIPE_STENCIL_OP_INCR_WRAP:
 133                 return V_028800_STENCIL_INCR_WRAP;
 134         case PIPE_STENCIL_OP_DECR_WRAP:
 135                 return V_028800_STENCIL_DECR_WRAP;
 136         case PIPE_STENCIL_OP_INVERT:
 137                 return V_028800_STENCIL_INVERT;
 138         default:
 139                 R600_ERR("Unknown stencil op %d", s_op);
 140                 assert(0);
 141                 break;
 142         }
 143         return 0;
 144 }
 145
 146 static uint32_t r600_translate_fill(uint32_t func)
 147 {
 148         switch(func) {
 149         case PIPE_POLYGON_MODE_FILL:
 150                 return 2;
 151         case PIPE_POLYGON_MODE_LINE:
 152                 return 1;
 153         case PIPE_POLYGON_MODE_POINT:
 154                 return 0;
 155         default:
 156                 assert(0);
 157                 return 0;
 158         }
 159 }
 160
 161 /* translates straight */
 162 static uint32_t r600_translate_ds_func(int func)
 163 {
 164         return func;
 165 }
 166
 167 static unsigned r600_tex_wrap(unsigned wrap)
 168 {
 169         switch (wrap) {
 170         default:
 171         case PIPE_TEX_WRAP_REPEAT:
 172                 return V_03C000_SQ_TEX_WRAP;
 173         case PIPE_TEX_WRAP_CLAMP:
 174                 return V_03C000_SQ_TEX_CLAMP_HALF_BORDER;
 175         case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
 176                 return V_03C000_SQ_TEX_CLAMP_LAST_TEXEL;
 177         case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
 178                 return V_03C000_SQ_TEX_CLAMP_BORDER;
 179         case PIPE_TEX_WRAP_MIRROR_REPEAT:
 180                 return V_03C000_SQ_TEX_MIRROR;
 181         case PIPE_TEX_WRAP_MIRROR_CLAMP:
 182                 return V_03C000_SQ_TEX_MIRROR_ONCE_HALF_BORDER;
 183         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
 184                 return V_03C000_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
 185         case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
 186                 return V_03C000_SQ_TEX_MIRROR_ONCE_BORDER;
 187         }
 188 }
 189
 190 static unsigned r600_tex_filter(unsigned filter)
 191 {
 192         switch (filter) {
 193         default:
 194         case PIPE_TEX_FILTER_NEAREST:
 195                 return V_03C000_SQ_TEX_XY_FILTER_POINT;
 196         case PIPE_TEX_FILTER_LINEAR:
 197                 return V_03C000_SQ_TEX_XY_FILTER_BILINEAR;
 198         }
 199 }
 200
 201 static unsigned r600_tex_mipfilter(unsigned filter)
 202 {
 203         switch (filter) {
 204         case PIPE_TEX_MIPFILTER_NEAREST:
 205                 return V_03C000_SQ_TEX_Z_FILTER_POINT;
 206         case PIPE_TEX_MIPFILTER_LINEAR:
 207                 return V_03C000_SQ_TEX_Z_FILTER_LINEAR;
 208         default:
 209         case PIPE_TEX_MIPFILTER_NONE:
 210                 return V_03C000_SQ_TEX_Z_FILTER_NONE;
 211         }
 212 }
 213
 214 static unsigned r600_tex_compare(unsigned compare)
 215 {
 216         switch (compare) {
 217         default:
 218         case PIPE_FUNC_NEVER:
 219                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NEVER;
 220         case PIPE_FUNC_LESS:
 221                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESS;
 222         case PIPE_FUNC_EQUAL:
 223                 return V_03C000_SQ_TEX_DEPTH_COMPARE_EQUAL;
 224         case PIPE_FUNC_LEQUAL:
 225                 return V_03C000_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
 226         case PIPE_FUNC_GREATER:
 227                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATER;
 228         case PIPE_FUNC_NOTEQUAL:
 229                 return V_03C000_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
 230         case PIPE_FUNC_GEQUAL:
 231                 return V_03C000_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
 232         case PIPE_FUNC_ALWAYS:
 233                 return V_03C000_SQ_TEX_DEPTH_COMPARE_ALWAYS;
 234         }
 235 }
 236
 237 static unsigned r600_tex_dim(unsigned dim)
 238 {
 239         switch (dim) {
 240         default:
 241         case PIPE_TEXTURE_1D:
 242                 return V_038000_SQ_TEX_DIM_1D;
 243         case PIPE_TEXTURE_1D_ARRAY:
 244                 return V_038000_SQ_TEX_DIM_1D_ARRAY;
 245         case PIPE_TEXTURE_2D:
 246         case PIPE_TEXTURE_RECT:
 247                 return V_038000_SQ_TEX_DIM_2D;
 248         case PIPE_TEXTURE_2D_ARRAY:
 249                 return V_038000_SQ_TEX_DIM_2D_ARRAY;
 250         case PIPE_TEXTURE_3D:
 251                 return V_038000_SQ_TEX_DIM_3D;
 252         case PIPE_TEXTURE_CUBE:
 253                 return V_038000_SQ_TEX_DIM_CUBEMAP;
 254         }
 255 }
 256
 257 static uint32_t r600_translate_dbformat(enum pipe_format format)
 258 {
 259         switch (format) {
 260         case PIPE_FORMAT_Z16_UNORM:
 261                 return V_028010_DEPTH_16;
 262         case PIPE_FORMAT_Z24X8_UNORM:
 263                 return V_028010_DEPTH_X8_24;
 264         case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
 265                 return V_028010_DEPTH_8_24;
 266         case PIPE_FORMAT_Z32_FLOAT:
 267                 return V_028010_DEPTH_32_FLOAT;
 268         case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
 269                 return V_028010_DEPTH_X24_8_32_FLOAT;
 270         default:
 271                 return ~0U;
 272         }
 273 }
 274
 275 static uint32_t r600_translate_colorswap(enum pipe_format format)
 276 {
 277         switch (format) {
 278         /* 8-bit buffers. */
 279         case PIPE_FORMAT_A8_UNORM:
 280                 return V_0280A0_SWAP_ALT_REV;
 281         case PIPE_FORMAT_I8_UNORM:
 282         case PIPE_FORMAT_L8_UNORM:
 283         case PIPE_FORMAT_L8_SRGB:
 284         case PIPE_FORMAT_R8_UNORM:
 285         case PIPE_FORMAT_R8_SNORM:
 286                 return V_0280A0_SWAP_STD;
 287
 288         case PIPE_FORMAT_L4A4_UNORM:
 289                 return V_0280A0_SWAP_ALT;
 290
 291         /* 16-bit buffers. */
 292         case PIPE_FORMAT_B5G6R5_UNORM:
 293                 return V_0280A0_SWAP_STD_REV;
 294
 295         case PIPE_FORMAT_B5G5R5A1_UNORM:
 296         case PIPE_FORMAT_B5G5R5X1_UNORM:
 297                 return V_0280A0_SWAP_ALT;
 298
 299         case PIPE_FORMAT_B4G4R4A4_UNORM:
 300         case PIPE_FORMAT_B4G4R4X4_UNORM:
 301                 return V_0280A0_SWAP_ALT;
 302
 303         case PIPE_FORMAT_Z16_UNORM:
 304                 return V_0280A0_SWAP_STD;
 305
 306         case PIPE_FORMAT_L8A8_UNORM:
 307         case PIPE_FORMAT_L8A8_SRGB:
 308                 return V_0280A0_SWAP_ALT;
 309         case PIPE_FORMAT_R8G8_UNORM:
 310                 return V_0280A0_SWAP_STD;
 311
 312         case PIPE_FORMAT_R16_UNORM:
 313         case PIPE_FORMAT_R16_FLOAT:
 314                 return V_0280A0_SWAP_STD;
 315
 316         /* 32-bit buffers. */
 317
 318         case PIPE_FORMAT_A8B8G8R8_SRGB:
 319                 return V_0280A0_SWAP_STD_REV;
 320         case PIPE_FORMAT_B8G8R8A8_SRGB:
 321                 return V_0280A0_SWAP_ALT;
 322
 323         case PIPE_FORMAT_B8G8R8A8_UNORM:
 324         case PIPE_FORMAT_B8G8R8X8_UNORM:
 325                 return V_0280A0_SWAP_ALT;
 326
 327         case PIPE_FORMAT_A8R8G8B8_UNORM:
 328         case PIPE_FORMAT_X8R8G8B8_UNORM:
 329                 return V_0280A0_SWAP_ALT_REV;
 330         case PIPE_FORMAT_R8G8B8A8_SNORM:
 331         case PIPE_FORMAT_R8G8B8A8_UNORM:
 332         case PIPE_FORMAT_R8G8B8X8_UNORM:
 333                 return V_0280A0_SWAP_STD;
 334
 335         case PIPE_FORMAT_A8B8G8R8_UNORM:
 336         case PIPE_FORMAT_X8B8G8R8_UNORM:
 337         /* case PIPE_FORMAT_R8SG8SB8UX8U_NORM: */
 338                 return V_0280A0_SWAP_STD_REV;
 339
 340         case PIPE_FORMAT_Z24X8_UNORM:
 341         case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
 342                 return V_0280A0_SWAP_STD;
 343
 344         case PIPE_FORMAT_X8Z24_UNORM:
 345         case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 346                 return V_0280A0_SWAP_STD;
 347
 348         case PIPE_FORMAT_R10G10B10A2_UNORM:
 349         case PIPE_FORMAT_R10G10B10X2_SNORM:
 350         case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
 351                 return V_0280A0_SWAP_STD;
 352
 353         case PIPE_FORMAT_B10G10R10A2_UNORM:
 354                 return V_0280A0_SWAP_ALT;
 355
 356         case PIPE_FORMAT_R11G11B10_FLOAT:
 357         case PIPE_FORMAT_R16G16_UNORM:
 358         case PIPE_FORMAT_R16G16_FLOAT:
 359         case PIPE_FORMAT_R32_FLOAT:
 360         case PIPE_FORMAT_Z32_FLOAT:
 361                 return V_0280A0_SWAP_STD;
 362
 363         /* 64-bit buffers. */
 364         case PIPE_FORMAT_R32G32_FLOAT:
 365         case PIPE_FORMAT_R16G16B16A16_UNORM:
 366         case PIPE_FORMAT_R16G16B16A16_SNORM:
 367         case PIPE_FORMAT_R16G16B16A16_FLOAT:
 368         case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
 369
 370         /* 128-bit buffers. */
 371         case PIPE_FORMAT_R32G32B32A32_FLOAT:
 372         case PIPE_FORMAT_R32G32B32A32_SNORM:
 373         case PIPE_FORMAT_R32G32B32A32_UNORM:
 374                 return V_0280A0_SWAP_STD;
 375         default:
 376                 R600_ERR("unsupported colorswap format %d\n", format);
 377                 return ~0U;
 378         }
 379         return ~0U;
 380 }
 381
 382 static uint32_t r600_translate_colorformat(enum pipe_format format)
 383 {
 384         switch (format) {
 385         case PIPE_FORMAT_L4A4_UNORM:
 386                 return V_0280A0_COLOR_4_4;
 387
 388         /* 8-bit buffers. */
 389         case PIPE_FORMAT_A8_UNORM:
 390         case PIPE_FORMAT_I8_UNORM:
 391         case PIPE_FORMAT_L8_UNORM:
 392         case PIPE_FORMAT_L8_SRGB:
 393         case PIPE_FORMAT_R8_UNORM:
 394         case PIPE_FORMAT_R8_SNORM:
 395                 return V_0280A0_COLOR_8;
 396
 397         /* 16-bit buffers. */
 398         case PIPE_FORMAT_B5G6R5_UNORM:
 399                 return V_0280A0_COLOR_5_6_5;
 400
 401         case PIPE_FORMAT_B5G5R5A1_UNORM:
 402         case PIPE_FORMAT_B5G5R5X1_UNORM:
 403                 return V_0280A0_COLOR_1_5_5_5;
 404
 405         case PIPE_FORMAT_B4G4R4A4_UNORM:
 406         case PIPE_FORMAT_B4G4R4X4_UNORM:
 407                 return V_0280A0_COLOR_4_4_4_4;
 408
 409         case PIPE_FORMAT_Z16_UNORM:
 410                 return V_0280A0_COLOR_16;
 411
 412         case PIPE_FORMAT_L8A8_UNORM:
 413         case PIPE_FORMAT_L8A8_SRGB:
 414         case PIPE_FORMAT_R8G8_UNORM:
 415                 return V_0280A0_COLOR_8_8;
 416
 417         case PIPE_FORMAT_R16_UNORM:
 418                 return V_0280A0_COLOR_16;
 419
 420         case PIPE_FORMAT_R16_FLOAT:
 421                 return V_0280A0_COLOR_16_FLOAT;
 422
 423         /* 32-bit buffers. */
 424         case PIPE_FORMAT_A8B8G8R8_SRGB:
 425         case PIPE_FORMAT_A8B8G8R8_UNORM:
 426         case PIPE_FORMAT_A8R8G8B8_UNORM:
 427         case PIPE_FORMAT_B8G8R8A8_SRGB:
 428         case PIPE_FORMAT_B8G8R8A8_UNORM:
 429         case PIPE_FORMAT_B8G8R8X8_UNORM:
 430         case PIPE_FORMAT_R8G8B8A8_SNORM:
 431         case PIPE_FORMAT_R8G8B8A8_UNORM:
 432         case PIPE_FORMAT_R8G8B8X8_UNORM:
 433         case PIPE_FORMAT_R8SG8SB8UX8U_NORM:
 434         case PIPE_FORMAT_X8B8G8R8_UNORM:
 435         case PIPE_FORMAT_X8R8G8B8_UNORM:
 436         case PIPE_FORMAT_R8G8B8_UNORM:
 437                 return V_0280A0_COLOR_8_8_8_8;
 438
 439         case PIPE_FORMAT_R10G10B10A2_UNORM:
 440         case PIPE_FORMAT_R10G10B10X2_SNORM:
 441         case PIPE_FORMAT_B10G10R10A2_UNORM:
 442         case PIPE_FORMAT_R10SG10SB10SA2U_NORM:
 443                 return V_0280A0_COLOR_2_10_10_10;
 444
 445         case PIPE_FORMAT_Z24X8_UNORM:
 446         case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
 447                 return V_0280A0_COLOR_8_24;
 448
 449         case PIPE_FORMAT_X8Z24_UNORM:
 450         case PIPE_FORMAT_S8_USCALED_Z24_UNORM:
 451                 return V_0280A0_COLOR_24_8;
 452
 453         case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
 454                 return V_0280A0_COLOR_X24_8_32_FLOAT;
 455
 456         case PIPE_FORMAT_R32_FLOAT:
 457         case PIPE_FORMAT_Z32_FLOAT:
 458                 return V_0280A0_COLOR_32_FLOAT;
 459
 460         case PIPE_FORMAT_R16G16_FLOAT:
 461                 return V_0280A0_COLOR_16_16_FLOAT;
 462
 463         case PIPE_FORMAT_R16G16_SSCALED:
 464         case PIPE_FORMAT_R16G16_UNORM:
 465                 return V_0280A0_COLOR_16_16;
 466
 467         case PIPE_FORMAT_R11G11B10_FLOAT:
 468                 return V_0280A0_COLOR_10_11_11_FLOAT;
 469
 470         /* 64-bit buffers. */
 471         case PIPE_FORMAT_R16G16B16_USCALED:
 472         case PIPE_FORMAT_R16G16B16A16_USCALED:
 473         case PIPE_FORMAT_R16G16B16_SSCALED:
 474         case PIPE_FORMAT_R16G16B16A16_SSCALED:
 475         case PIPE_FORMAT_R16G16B16A16_UNORM:
 476         case PIPE_FORMAT_R16G16B16A16_SNORM:
 477                 return V_0280A0_COLOR_16_16_16_16;
 478
 479         case PIPE_FORMAT_R16G16B16_FLOAT:
 480         case PIPE_FORMAT_R16G16B16A16_FLOAT:
 481                 return V_0280A0_COLOR_16_16_16_16_FLOAT;
 482
 483         case PIPE_FORMAT_R32G32_FLOAT:
 484                 return V_0280A0_COLOR_32_32_FLOAT;
 485
 486         case PIPE_FORMAT_R32G32_USCALED:
 487         case PIPE_FORMAT_R32G32_SSCALED:
 488                 return V_0280A0_COLOR_32_32;
 489
 490         /* 96-bit buffers. */
 491         case PIPE_FORMAT_R32G32B32_FLOAT:
 492                 return V_0280A0_COLOR_32_32_32_FLOAT;
 493
 494         /* 128-bit buffers. */
 495         case PIPE_FORMAT_R32G32B32A32_FLOAT:
 496                 return V_0280A0_COLOR_32_32_32_32_FLOAT;
 497         case PIPE_FORMAT_R32G32B32A32_SNORM:
 498         case PIPE_FORMAT_R32G32B32A32_UNORM:
 499                 return V_0280A0_COLOR_32_32_32_32;
 500
 501         /* YUV buffers. */
 502         case PIPE_FORMAT_UYVY:
 503         case PIPE_FORMAT_YUYV:
 504         default:
 505                 return ~0U; /* Unsupported. */
 506         }
 507 }
 508
 509 static uint32_t r600_colorformat_endian_swap(uint32_t colorformat)
 510 {
 511         if (R600_BIG_ENDIAN) {
 512                 switch(colorformat) {
 513                 case V_0280A0_COLOR_4_4:
 514                         return ENDIAN_NONE;
 515
 516                 /* 8-bit buffers. */
 517                 case V_0280A0_COLOR_8:
 518                         return ENDIAN_NONE;
 519
 520                 /* 16-bit buffers. */
 521                 case V_0280A0_COLOR_5_6_5:
 522                 case V_0280A0_COLOR_1_5_5_5:
 523                 case V_0280A0_COLOR_4_4_4_4:
 524                 case V_0280A0_COLOR_16:
 525                 case V_0280A0_COLOR_8_8:
 526                         return ENDIAN_8IN16;
 527
 528                 /* 32-bit buffers. */
 529                 case V_0280A0_COLOR_8_8_8_8:
 530                 case V_0280A0_COLOR_2_10_10_10:
 531                 case V_0280A0_COLOR_8_24:
 532                 case V_0280A0_COLOR_24_8:
 533                 case V_0280A0_COLOR_32_FLOAT:
 534                 case V_0280A0_COLOR_16_16_FLOAT:
 535                 case V_0280A0_COLOR_16_16:
 536                         return ENDIAN_8IN32;
 537
 538                 /* 64-bit buffers. */
 539                 case V_0280A0_COLOR_16_16_16_16:
 540                 case V_0280A0_COLOR_16_16_16_16_FLOAT:
 541                         return ENDIAN_8IN16;
 542
 543                 case V_0280A0_COLOR_32_32_FLOAT:
 544                 case V_0280A0_COLOR_32_32:
 545                 case V_0280A0_COLOR_X24_8_32_FLOAT:
 546                         return ENDIAN_8IN32;
 547
 548                 /* 128-bit buffers. */
 549                 case V_0280A0_COLOR_32_32_32_FLOAT:
 550                 case V_0280A0_COLOR_32_32_32_32_FLOAT:
 551                 case V_0280A0_COLOR_32_32_32_32:
 552                         return ENDIAN_8IN32;
 553                 default:
 554                         return ENDIAN_NONE; /* Unsupported. */
 555                 }
 556         } else {
 557                 return ENDIAN_NONE;
 558         }
 559 }
 560
 561 static bool r600_is_sampler_format_supported(struct pipe_screen *screen, enum pipe_format format)
 562 {
 563         return r600_translate_texformat(screen, format, NULL, NULL, NULL) != ~0U;
 564 }
 565
 566 static bool r600_is_colorbuffer_format_supported(enum pipe_format format)
 567 {
 568         return r600_translate_colorformat(format) != ~0U &&
 569                r600_translate_colorswap(format) != ~0U;
 570 }
 571
 572 static bool r600_is_zs_format_supported(enum pipe_format format)
 573 {
 574         return r600_translate_dbformat(format) != ~0U;
 575 }
 576
 577 boolean r600_is_format_supported(struct pipe_screen *screen,
 578                                  enum pipe_format format,
 579                                  enum pipe_texture_target target,
 580                                  unsigned sample_count,
 581                                  unsigned usage)
 582 {
 583         unsigned retval = 0;
 584
 585         if (target >= PIPE_MAX_TEXTURE_TYPES) {
 586                 R600_ERR("r600: unsupported texture type %d\n", target);
 587                 return FALSE;
 588         }
 589
 590         if (!util_format_is_supported(format, usage))
 591                 return FALSE;
 592
 593         /* Multisample */
 594         if (sample_count > 1)
 595                 return FALSE;
 596
 597         if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
 598             r600_is_sampler_format_supported(screen, format)) {
 599                 retval |= PIPE_BIND_SAMPLER_VIEW;
 600         }
 601
 602         if ((usage & (PIPE_BIND_RENDER_TARGET |
 603                       PIPE_BIND_DISPLAY_TARGET |
 604                       PIPE_BIND_SCANOUT |
 605                       PIPE_BIND_SHARED)) &&
 606             r600_is_colorbuffer_format_supported(format)) {
 607                 retval |= usage &
 608                           (PIPE_BIND_RENDER_TARGET |
 609                            PIPE_BIND_DISPLAY_TARGET |
 610                            PIPE_BIND_SCANOUT |
 611                            PIPE_BIND_SHARED);
 612         }
 613
 614         if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
 615             r600_is_zs_format_supported(format)) {
 616                 retval |= PIPE_BIND_DEPTH_STENCIL;
 617         }
 618
 619         if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
 620             r600_is_vertex_format_supported(format)) {
 621                 retval |= PIPE_BIND_VERTEX_BUFFER;
 622         }
 623
 624         if (usage & PIPE_BIND_TRANSFER_READ)
 625                 retval |= PIPE_BIND_TRANSFER_READ;
 626         if (usage & PIPE_BIND_TRANSFER_WRITE)
 627                 retval |= PIPE_BIND_TRANSFER_WRITE;
 628
 629         return retval == usage;
 630 }
 631
 632 void r600_polygon_offset_update(struct r600_pipe_context *rctx)
 633 {
 634         struct r600_pipe_state state;
 635
 636         state.id = R600_PIPE_STATE_POLYGON_OFFSET;
 637         state.nregs = 0;
 638         if (rctx->rasterizer && rctx->framebuffer.zsbuf) {
 639                 float offset_units = rctx->rasterizer->offset_units;
 640                 unsigned offset_db_fmt_cntl = 0, depth;
 641
 642                 switch (rctx->framebuffer.zsbuf->texture->format) {
 643                 case PIPE_FORMAT_Z24X8_UNORM:
 644                 case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
 645                         depth = -24;
 646                         offset_units *= 2.0f;
 647                         break;
 648                 case PIPE_FORMAT_Z32_FLOAT:
 649                 case PIPE_FORMAT_Z32_FLOAT_S8X24_USCALED:
 650                         depth = -23;
 651                         offset_units *= 1.0f;
 652                         offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
 653                         break;
 654                 case PIPE_FORMAT_Z16_UNORM:
 655                         depth = -16;
 656                         offset_units *= 4.0f;
 657                         break;
 658                 default:
 659                         return;
 660                 }
 661                 /* FIXME some of those reg can be computed with cso */
 662                 offset_db_fmt_cntl |= S_028DF8_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
 663                 r600_pipe_state_add_reg(&state,
 664                                 R_028E00_PA_SU_POLY_OFFSET_FRONT_SCALE,
 665                                 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
 666                 r600_pipe_state_add_reg(&state,
 667                                 R_028E04_PA_SU_POLY_OFFSET_FRONT_OFFSET,
 668                                 fui(offset_units), 0xFFFFFFFF, NULL);
 669                 r600_pipe_state_add_reg(&state,
 670                                 R_028E08_PA_SU_POLY_OFFSET_BACK_SCALE,
 671                                 fui(rctx->rasterizer->offset_scale), 0xFFFFFFFF, NULL);
 672                 r600_pipe_state_add_reg(&state,
 673                                 R_028E0C_PA_SU_POLY_OFFSET_BACK_OFFSET,
 674                                 fui(offset_units), 0xFFFFFFFF, NULL);
 675                 r600_pipe_state_add_reg(&state,
 676                                 R_028DF8_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
 677                                 offset_db_fmt_cntl, 0xFFFFFFFF, NULL);
 678                 r600_context_pipe_state_set(&rctx->ctx, &state);
 679         }
 680 }
 681
 682 static void r600_set_blend_color(struct pipe_context *ctx,
 683                                         const struct pipe_blend_color *state)
 684 {
 685         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 686         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
 687
 688         if (rstate == NULL)
 689                 return;
 690
 691         rstate->id = R600_PIPE_STATE_BLEND_COLOR;
 692         r600_pipe_state_add_reg(rstate, R_028414_CB_BLEND_RED, fui(state->color[0]), 0xFFFFFFFF, NULL);
 693         r600_pipe_state_add_reg(rstate, R_028418_CB_BLEND_GREEN, fui(state->color[1]), 0xFFFFFFFF, NULL);
 694         r600_pipe_state_add_reg(rstate, R_02841C_CB_BLEND_BLUE, fui(state->color[2]), 0xFFFFFFFF, NULL);
 695         r600_pipe_state_add_reg(rstate, R_028420_CB_BLEND_ALPHA, fui(state->color[3]), 0xFFFFFFFF, NULL);
 696         free(rctx->states[R600_PIPE_STATE_BLEND_COLOR]);
 697         rctx->states[R600_PIPE_STATE_BLEND_COLOR] = rstate;
 698         r600_context_pipe_state_set(&rctx->ctx, rstate);
 699 }
 700
 701 static void *r600_create_blend_state(struct pipe_context *ctx,
 702                                         const struct pipe_blend_state *state)
 703 {
 704         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 705         struct r600_pipe_blend *blend = CALLOC_STRUCT(r600_pipe_blend);
 706         struct r600_pipe_state *rstate;
 707         u32 color_control = 0, target_mask;
 708
 709         if (blend == NULL) {
 710                 return NULL;
 711         }
 712         rstate = &blend->rstate;
 713
 714         rstate->id = R600_PIPE_STATE_BLEND;
 715
 716         target_mask = 0;
 717
 718         /* R600 does not support per-MRT blends */
 719         if (rctx->family > CHIP_R600)
 720                 color_control |= S_028808_PER_MRT_BLEND(1);
 721         if (state->logicop_enable) {
 722                 color_control |= (state->logicop_func << 16) | (state->logicop_func << 20);
 723         } else {
 724                 color_control |= (0xcc << 16);
 725         }
 726         /* we pretend 8 buffer are used, CB_SHADER_MASK will disable unused one */
 727         if (state->independent_blend_enable) {
 728                 for (int i = 0; i < 8; i++) {
 729                         if (state->rt[i].blend_enable) {
 730                                 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
 731                         }
 732                         target_mask |= (state->rt[i].colormask << (4 * i));
 733                 }
 734         } else {
 735                 for (int i = 0; i < 8; i++) {
 736                         if (state->rt[0].blend_enable) {
 737                                 color_control |= S_028808_TARGET_BLEND_ENABLE(1 << i);
 738                         }
 739                         target_mask |= (state->rt[0].colormask << (4 * i));
 740                 }
 741         }
 742         blend->cb_target_mask = target_mask;
 743         /* MULTIWRITE_ENABLE is controlled by r600_pipe_shader_ps(). */
 744         r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
 745                                 color_control, 0xFFFFFFFD, NULL);
 746
 747         for (int i = 0; i < 8; i++) {
 748                 /* state->rt entries > 0 only written if independent blending */
 749                 const int j = state->independent_blend_enable ? i : 0;
 750
 751                 unsigned eqRGB = state->rt[j].rgb_func;
 752                 unsigned srcRGB = state->rt[j].rgb_src_factor;
 753                 unsigned dstRGB = state->rt[j].rgb_dst_factor;
 754
 755                 unsigned eqA = state->rt[j].alpha_func;
 756                 unsigned srcA = state->rt[j].alpha_src_factor;
 757                 unsigned dstA = state->rt[j].alpha_dst_factor;
 758                 uint32_t bc = 0;
 759
 760                 if (!state->rt[j].blend_enable)
 761                         continue;
 762
 763                 bc |= S_028804_COLOR_COMB_FCN(r600_translate_blend_function(eqRGB));
 764                 bc |= S_028804_COLOR_SRCBLEND(r600_translate_blend_factor(srcRGB));
 765                 bc |= S_028804_COLOR_DESTBLEND(r600_translate_blend_factor(dstRGB));
 766
 767                 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
 768                         bc |= S_028804_SEPARATE_ALPHA_BLEND(1);
 769                         bc |= S_028804_ALPHA_COMB_FCN(r600_translate_blend_function(eqA));
 770                         bc |= S_028804_ALPHA_SRCBLEND(r600_translate_blend_factor(srcA));
 771                         bc |= S_028804_ALPHA_DESTBLEND(r600_translate_blend_factor(dstA));
 772                 }
 773
 774                 /* R600 does not support per-MRT blends */
 775                 if (rctx->family > CHIP_R600)
 776                         r600_pipe_state_add_reg(rstate, R_028780_CB_BLEND0_CONTROL + i * 4, bc, 0xFFFFFFFF, NULL);
 777                 if (i == 0)
 778                         r600_pipe_state_add_reg(rstate, R_028804_CB_BLEND_CONTROL, bc, 0xFFFFFFFF, NULL);
 779         }
 780         return rstate;
 781 }
 782
 783 static void *r600_create_dsa_state(struct pipe_context *ctx,
 784                                    const struct pipe_depth_stencil_alpha_state *state)
 785 {
 786         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 787         struct r600_pipe_dsa *dsa = CALLOC_STRUCT(r600_pipe_dsa);
 788         unsigned db_depth_control, alpha_test_control, alpha_ref, db_shader_control;
 789         unsigned stencil_ref_mask, stencil_ref_mask_bf, db_render_override, db_render_control;
 790         struct r600_pipe_state *rstate;
 791
 792         if (dsa == NULL) {
 793                 return NULL;
 794         }
 795
 796         rstate = &dsa->rstate;
 797
 798         rstate->id = R600_PIPE_STATE_DSA;
 799         /* depth TODO some of those db_shader_control field depend on shader adjust mask & add it to shader */
 800         db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
 801         stencil_ref_mask = 0;
 802         stencil_ref_mask_bf = 0;
 803         db_depth_control = S_028800_Z_ENABLE(state->depth.enabled) |
 804                 S_028800_Z_WRITE_ENABLE(state->depth.writemask) |
 805                 S_028800_ZFUNC(state->depth.func);
 806
 807         /* stencil */
 808         if (state->stencil[0].enabled) {
 809                 db_depth_control |= S_028800_STENCIL_ENABLE(1);
 810                 db_depth_control |= S_028800_STENCILFUNC(r600_translate_ds_func(state->stencil[0].func));
 811                 db_depth_control |= S_028800_STENCILFAIL(r600_translate_stencil_op(state->stencil[0].fail_op));
 812                 db_depth_control |= S_028800_STENCILZPASS(r600_translate_stencil_op(state->stencil[0].zpass_op));
 813                 db_depth_control |= S_028800_STENCILZFAIL(r600_translate_stencil_op(state->stencil[0].zfail_op));
 814
 815
 816                 stencil_ref_mask = S_028430_STENCILMASK(state->stencil[0].valuemask) |
 817                         S_028430_STENCILWRITEMASK(state->stencil[0].writemask);
 818                 if (state->stencil[1].enabled) {
 819                         db_depth_control |= S_028800_BACKFACE_ENABLE(1);
 820                         db_depth_control |= S_028800_STENCILFUNC_BF(r600_translate_ds_func(state->stencil[1].func));
 821                         db_depth_control |= S_028800_STENCILFAIL_BF(r600_translate_stencil_op(state->stencil[1].fail_op));
 822                         db_depth_control |= S_028800_STENCILZPASS_BF(r600_translate_stencil_op(state->stencil[1].zpass_op));
 823                         db_depth_control |= S_028800_STENCILZFAIL_BF(r600_translate_stencil_op(state->stencil[1].zfail_op));
 824                         stencil_ref_mask_bf = S_028434_STENCILMASK_BF(state->stencil[1].valuemask) |
 825                                 S_028434_STENCILWRITEMASK_BF(state->stencil[1].writemask);
 826                 }
 827         }
 828
 829         /* alpha */
 830         alpha_test_control = 0;
 831         alpha_ref = 0;
 832         if (state->alpha.enabled) {
 833                 alpha_test_control = S_028410_ALPHA_FUNC(state->alpha.func);
 834                 alpha_test_control |= S_028410_ALPHA_TEST_ENABLE(1);
 835                 alpha_ref = fui(state->alpha.ref_value);
 836         }
 837         dsa->alpha_ref = alpha_ref;
 838
 839         /* misc */
 840         db_render_control = 0;
 841         db_render_override = S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_DISABLE) |
 842                 S_028D10_FORCE_HIS_ENABLE0(V_028D10_FORCE_DISABLE) |
 843                 S_028D10_FORCE_HIS_ENABLE1(V_028D10_FORCE_DISABLE);
 844         /* TODO db_render_override depends on query */
 845         r600_pipe_state_add_reg(rstate, R_028028_DB_STENCIL_CLEAR, 0x00000000, 0xFFFFFFFF, NULL);
 846         r600_pipe_state_add_reg(rstate, R_02802C_DB_DEPTH_CLEAR, 0x3F800000, 0xFFFFFFFF, NULL);
 847         r600_pipe_state_add_reg(rstate, R_028410_SX_ALPHA_TEST_CONTROL, alpha_test_control, 0xFFFFFFFF, NULL);
 848         r600_pipe_state_add_reg(rstate,
 849                                 R_028430_DB_STENCILREFMASK, stencil_ref_mask,
 850                                 0xFFFFFFFF & C_028430_STENCILREF, NULL);
 851         r600_pipe_state_add_reg(rstate,
 852                                 R_028434_DB_STENCILREFMASK_BF, stencil_ref_mask_bf,
 853                                 0xFFFFFFFF & C_028434_STENCILREF_BF, NULL);
 854         r600_pipe_state_add_reg(rstate, R_0286E0_SPI_FOG_FUNC_SCALE, 0x00000000, 0xFFFFFFFF, NULL);
 855         r600_pipe_state_add_reg(rstate, R_0286E4_SPI_FOG_FUNC_BIAS, 0x00000000, 0xFFFFFFFF, NULL);
 856         r600_pipe_state_add_reg(rstate, R_0286DC_SPI_FOG_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
 857         r600_pipe_state_add_reg(rstate, R_028800_DB_DEPTH_CONTROL, db_depth_control, 0xFFFFFFFF, NULL);
 858         /* The DB_SHADER_CONTROL mask is 0xFFFFFFBC since Z_EXPORT_ENABLE,
 859          * STENCIL_EXPORT_ENABLE and KILL_ENABLE are controlled by
 860          * r600_pipe_shader_ps().*/
 861         r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL, db_shader_control, 0xFFFFFFBC, NULL);
 862         r600_pipe_state_add_reg(rstate, R_028D0C_DB_RENDER_CONTROL, db_render_control, 0xFFFFFFFF, NULL);
 863         r600_pipe_state_add_reg(rstate, R_028D10_DB_RENDER_OVERRIDE, db_render_override, 0xFFFFFFFF, NULL);
 864         r600_pipe_state_add_reg(rstate, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 0x00000000, 0xFFFFFFFF, NULL);
 865         r600_pipe_state_add_reg(rstate, R_028D30_DB_PRELOAD_CONTROL, 0x00000000, 0xFFFFFFFF, NULL);
 866         r600_pipe_state_add_reg(rstate, R_028D44_DB_ALPHA_TO_MASK, 0x0000AA00, 0xFFFFFFFF, NULL);
 867
 868         return rstate;
 869 }
 870
 871 static void *r600_create_rs_state(struct pipe_context *ctx,
 872                                         const struct pipe_rasterizer_state *state)
 873 {
 874         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
 875         struct r600_pipe_rasterizer *rs = CALLOC_STRUCT(r600_pipe_rasterizer);
 876         struct r600_pipe_state *rstate;
 877         unsigned tmp;
 878         unsigned prov_vtx = 1, polygon_dual_mode;
 879         unsigned clip_rule;
 880
 881         if (rs == NULL) {
 882                 return NULL;
 883         }
 884
 885         rstate = &rs->rstate;
 886         rs->clamp_vertex_color = state->clamp_vertex_color;
 887         rs->clamp_fragment_color = state->clamp_fragment_color;
 888         rs->flatshade = state->flatshade;
 889         rs->sprite_coord_enable = state->sprite_coord_enable;
 890
 891         clip_rule = state->scissor ? 0xAAAA : 0xFFFF;
 892         /* offset */
 893         rs->offset_units = state->offset_units;
 894         rs->offset_scale = state->offset_scale * 12.0f;
 895
 896         rstate->id = R600_PIPE_STATE_RASTERIZER;
 897         if (state->flatshade_first)
 898                 prov_vtx = 0;
 899         tmp = S_0286D4_FLAT_SHADE_ENA(1);
 900         if (state->sprite_coord_enable) {
 901                 tmp |= S_0286D4_PNT_SPRITE_ENA(1) |
 902                         S_0286D4_PNT_SPRITE_OVRD_X(2) |
 903                         S_0286D4_PNT_SPRITE_OVRD_Y(3) |
 904                         S_0286D4_PNT_SPRITE_OVRD_Z(0) |
 905                         S_0286D4_PNT_SPRITE_OVRD_W(1);
 906                 if (state->sprite_coord_mode != PIPE_SPRITE_COORD_UPPER_LEFT) {
 907                         tmp |= S_0286D4_PNT_SPRITE_TOP_1(1);
 908                 }
 909         }
 910         r600_pipe_state_add_reg(rstate, R_0286D4_SPI_INTERP_CONTROL_0, tmp, 0xFFFFFFFF, NULL);
 911
 912         polygon_dual_mode = (state->fill_front != PIPE_POLYGON_MODE_FILL ||
 913                                 state->fill_back != PIPE_POLYGON_MODE_FILL);
 914         r600_pipe_state_add_reg(rstate, R_028814_PA_SU_SC_MODE_CNTL,
 915                 S_028814_PROVOKING_VTX_LAST(prov_vtx) |
 916                 S_028814_CULL_FRONT((state->cull_face & PIPE_FACE_FRONT) ? 1 : 0) |
 917                 S_028814_CULL_BACK((state->cull_face & PIPE_FACE_BACK) ? 1 : 0) |
 918                 S_028814_FACE(!state->front_ccw) |
 919                 S_028814_POLY_OFFSET_FRONT_ENABLE(state->offset_tri) |
 920                 S_028814_POLY_OFFSET_BACK_ENABLE(state->offset_tri) |
 921                 S_028814_POLY_OFFSET_PARA_ENABLE(state->offset_tri) |
 922                 S_028814_POLY_MODE(polygon_dual_mode) |
 923                 S_028814_POLYMODE_FRONT_PTYPE(r600_translate_fill(state->fill_front)) |
 924                 S_028814_POLYMODE_BACK_PTYPE(r600_translate_fill(state->fill_back)), 0xFFFFFFFF, NULL);
 925         r600_pipe_state_add_reg(rstate, R_02881C_PA_CL_VS_OUT_CNTL,
 926                         S_02881C_USE_VTX_POINT_SIZE(state->point_size_per_vertex) |
 927                         S_02881C_VS_OUT_MISC_VEC_ENA(state->point_size_per_vertex), 0xFFFFFFFF, NULL);
 928         r600_pipe_state_add_reg(rstate, R_028820_PA_CL_NANINF_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
 929         /* point size 12.4 fixed point */
 930         tmp = (unsigned)(state->point_size * 8.0);
 931         r600_pipe_state_add_reg(rstate, R_028A00_PA_SU_POINT_SIZE, S_028A00_HEIGHT(tmp) | S_028A00_WIDTH(tmp), 0xFFFFFFFF, NULL);
 932         r600_pipe_state_add_reg(rstate, R_028A04_PA_SU_POINT_MINMAX, 0x80000000, 0xFFFFFFFF, NULL);
 933
 934         tmp = (unsigned)state->line_width * 8;
 935         r600_pipe_state_add_reg(rstate, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp), 0xFFFFFFFF, NULL);
 936
 937         r600_pipe_state_add_reg(rstate, R_028A0C_PA_SC_LINE_STIPPLE, 0x00000005, 0xFFFFFFFF, NULL);
 938         r600_pipe_state_add_reg(rstate, R_028A48_PA_SC_MPASS_PS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
 939         r600_pipe_state_add_reg(rstate, R_028C00_PA_SC_LINE_CNTL, 0x00000400, 0xFFFFFFFF, NULL);
 940
 941         r600_pipe_state_add_reg(rstate, R_028C08_PA_SU_VTX_CNTL,
 942                                 S_028C08_PIX_CENTER_HALF(state->gl_rasterization_rules),
 943                                 0xFFFFFFFF, NULL);
 944
 945         r600_pipe_state_add_reg(rstate, R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
 946         r600_pipe_state_add_reg(rstate, R_028C10_PA_CL_GB_VERT_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
 947         r600_pipe_state_add_reg(rstate, R_028C14_PA_CL_GB_HORZ_CLIP_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
 948         r600_pipe_state_add_reg(rstate, R_028C18_PA_CL_GB_HORZ_DISC_ADJ, 0x3F800000, 0xFFFFFFFF, NULL);
 949         r600_pipe_state_add_reg(rstate, R_028DFC_PA_SU_POLY_OFFSET_CLAMP, 0x00000000, 0xFFFFFFFF, NULL);
 950         r600_pipe_state_add_reg(rstate, R_02820C_PA_SC_CLIPRECT_RULE, clip_rule, 0xFFFFFFFF, NULL);
 951
 952         return rstate;
 953 }
 954
 955 static void *r600_create_sampler_state(struct pipe_context *ctx,
 956                                         const struct pipe_sampler_state *state)
 957 {
 958         struct r600_pipe_sampler_state *ss = CALLOC_STRUCT(r600_pipe_sampler_state);
 959         struct r600_pipe_state *rstate;
 960         union util_color uc;
 961         unsigned aniso_flag_offset = state->max_anisotropy > 1 ? 4 : 0;
 962
 963         if (ss == NULL) {
 964                 return NULL;
 965         }
 966
 967         ss->seamless_cube_map = state->seamless_cube_map;
 968         rstate = &ss->rstate;
 969         rstate->id = R600_PIPE_STATE_SAMPLER;
 970         util_pack_color(state->border_color, PIPE_FORMAT_B8G8R8A8_UNORM, &uc);
 971         r600_pipe_state_add_reg_noblock(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
 972                                         S_03C000_CLAMP_X(r600_tex_wrap(state->wrap_s)) |
 973                                         S_03C000_CLAMP_Y(r600_tex_wrap(state->wrap_t)) |
 974                                         S_03C000_CLAMP_Z(r600_tex_wrap(state->wrap_r)) |
 975                                         S_03C000_XY_MAG_FILTER(r600_tex_filter(state->mag_img_filter) | aniso_flag_offset) |
 976                                         S_03C000_XY_MIN_FILTER(r600_tex_filter(state->min_img_filter) | aniso_flag_offset) |
 977                                         S_03C000_MIP_FILTER(r600_tex_mipfilter(state->min_mip_filter)) |
 978                                         S_03C000_MAX_ANISO(r600_tex_aniso_filter(state->max_anisotropy)) |
 979                                         S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state->compare_func)) |
 980                                         S_03C000_BORDER_COLOR_TYPE(uc.ui ? V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0xFFFFFFFF, NULL);
 981         r600_pipe_state_add_reg_noblock(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
 982                                         S_03C004_MIN_LOD(S_FIXED(CLAMP(state->min_lod, 0, 15), 6)) |
 983                                         S_03C004_MAX_LOD(S_FIXED(CLAMP(state->max_lod, 0, 15), 6)) |
 984                                         S_03C004_LOD_BIAS(S_FIXED(CLAMP(state->lod_bias, -16, 16), 6)), 0xFFFFFFFF, NULL);
 985         r600_pipe_state_add_reg_noblock(rstate, R_03C008_SQ_TEX_SAMPLER_WORD2_0, S_03C008_TYPE(1), 0xFFFFFFFF, NULL);
 986         if (uc.ui) {
 987                 r600_pipe_state_add_reg_noblock(rstate, R_00A400_TD_PS_SAMPLER0_BORDER_RED, fui(state->border_color[0]), 0xFFFFFFFF, NULL);
 988                 r600_pipe_state_add_reg_noblock(rstate, R_00A404_TD_PS_SAMPLER0_BORDER_GREEN, fui(state->border_color[1]), 0xFFFFFFFF, NULL);
 989                 r600_pipe_state_add_reg_noblock(rstate, R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, fui(state->border_color[2]), 0xFFFFFFFF, NULL);
 990                 r600_pipe_state_add_reg_noblock(rstate, R_00A40C_TD_PS_SAMPLER0_BORDER_ALPHA, fui(state->border_color[3]), 0xFFFFFFFF, NULL);
 991         }
 992         return rstate;
 993 }
 994
 995 static struct pipe_sampler_view *r600_create_sampler_view(struct pipe_context *ctx,
 996                                                         struct pipe_resource *texture,
 997                                                         const struct pipe_sampler_view *state)
 998 {
 999         struct r600_pipe_sampler_view *resource = CALLOC_STRUCT(r600_pipe_sampler_view);
1000         struct r600_pipe_resource_state *rstate;
1001         const struct util_format_description *desc;
1002         struct r600_resource_texture *tmp;
1003         struct r600_resource *rbuffer;
1004         unsigned format, endian;
1005         uint32_t word4 = 0, yuv_format = 0, pitch = 0;
1006         unsigned char swizzle[4], array_mode = 0, tile_type = 0;
1007         struct r600_bo *bo[2];
1008         unsigned width, height, depth, offset_level, last_level;
1009
1010         if (resource == NULL)
1011                 return NULL;
1012         rstate = &resource->state;
1013
1014         /* initialize base object */
1015         resource->base = *state;
1016         resource->base.texture = NULL;
1017         pipe_reference(NULL, &texture->reference);
1018         resource->base.texture = texture;
1019         resource->base.reference.count = 1;
1020         resource->base.context = ctx;
1021
1022         swizzle[0] = state->swizzle_r;
1023         swizzle[1] = state->swizzle_g;
1024         swizzle[2] = state->swizzle_b;
1025         swizzle[3] = state->swizzle_a;
1026         format = r600_translate_texformat(ctx->screen, state->format,
1027                                           swizzle,
1028                                           &word4, &yuv_format);
1029         if (format == ~0) {
1030                 format = 0;
1031         }
1032         desc = util_format_description(state->format);
1033         if (desc == NULL) {
1034                 R600_ERR("unknown format %d\n", state->format);
1035         }
1036         tmp = (struct r600_resource_texture *)texture;
1037         if (tmp->depth && !tmp->is_flushing_texture) {
1038                 r600_texture_depth_flush(ctx, texture, TRUE);
1039                 tmp = tmp->flushed_depth_texture;
1040         }
1041         endian = r600_colorformat_endian_swap(format);
1042
1043         if (tmp->force_int_type) {
1044                 word4 &= C_038010_NUM_FORMAT_ALL;
1045                 word4 |= S_038010_NUM_FORMAT_ALL(V_038010_SQ_NUM_FORMAT_INT);
1046         }
1047         rbuffer = &tmp->resource;
1048         bo[0] = rbuffer->bo;
1049         bo[1] = rbuffer->bo;
1050
1051         offset_level = state->u.tex.first_level;
1052         last_level = state->u.tex.last_level - offset_level;
1053         width = u_minify(texture->width0, offset_level);
1054         height = u_minify(texture->height0, offset_level);
1055         depth = u_minify(texture->depth0, offset_level);
1056
1057         pitch = align(tmp->pitch_in_blocks[offset_level] *
1058                       util_format_get_blockwidth(state->format), 8);
1059         array_mode = tmp->array_mode[offset_level];
1060         tile_type = tmp->tile_type;
1061
1062         if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
1063                 height = 1;
1064                 depth = texture->array_size;
1065         } else if (texture->target == PIPE_TEXTURE_2D_ARRAY) {
1066                 depth = texture->array_size;
1067         }
1068
1069         rstate->bo[0] = bo[0];
1070         rstate->bo[1] = bo[1];
1071
1072         rstate->val[0] = (S_038000_DIM(r600_tex_dim(texture->target)) |
1073                           S_038000_TILE_MODE(array_mode) |
1074                           S_038000_TILE_TYPE(tile_type) |
1075                           S_038000_PITCH((pitch / 8) - 1) |
1076                           S_038000_TEX_WIDTH(width - 1));
1077         rstate->val[1] = (S_038004_TEX_HEIGHT(height - 1) |
1078                           S_038004_TEX_DEPTH(depth - 1) |
1079                           S_038004_DATA_FORMAT(format));
1080         rstate->val[2] = (tmp->offset[offset_level] + r600_bo_offset(bo[0])) >> 8;
1081         rstate->val[3] = (tmp->offset[offset_level+1] + r600_bo_offset(bo[1])) >> 8;
1082         rstate->val[4] = (word4 |
1083                           S_038010_SRF_MODE_ALL(V_038010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
1084                           S_038010_REQUEST_SIZE(1) |
1085                           S_038010_ENDIAN_SWAP(endian) |
1086                           S_038010_BASE_LEVEL(0));
1087         rstate->val[5] = (S_038014_LAST_LEVEL(last_level) |
1088                           S_038014_BASE_ARRAY(state->u.tex.first_layer) |
1089                           S_038014_LAST_ARRAY(state->u.tex.last_layer));
1090         rstate->val[6] = (S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
1091                           S_038018_MAX_ANISO(4 /* max 16 samples */));
1092
1093         return &resource->base;
1094 }
1095
1096 static void r600_set_vs_sampler_view(struct pipe_context *ctx, unsigned count,
1097                                         struct pipe_sampler_view **views)
1098 {
1099         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1100         struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1101
1102         for (int i = 0; i < count; i++) {
1103                 if (resource[i]) {
1104                         r600_context_pipe_state_set_vs_resource(&rctx->ctx, &resource[i]->state,
1105                                                                 i + R600_MAX_CONST_BUFFERS);
1106                 }
1107         }
1108 }
1109
1110 static void r600_set_ps_sampler_view(struct pipe_context *ctx, unsigned count,
1111                                         struct pipe_sampler_view **views)
1112 {
1113         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1114         struct r600_pipe_sampler_view **resource = (struct r600_pipe_sampler_view **)views;
1115         int i;
1116         int has_depth = 0;
1117
1118         for (i = 0; i < count; i++) {
1119                 if (&rctx->ps_samplers.views[i]->base != views[i]) {
1120                         if (resource[i]) {
1121                                 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
1122                                         has_depth = 1;
1123                                 r600_context_pipe_state_set_ps_resource(&rctx->ctx, &resource[i]->state,
1124                                                                         i + R600_MAX_CONST_BUFFERS);
1125                         } else
1126                                 r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
1127                                                                         i + R600_MAX_CONST_BUFFERS);
1128
1129                         pipe_sampler_view_reference(
1130                                 (struct pipe_sampler_view **)&rctx->ps_samplers.views[i],
1131                                 views[i]);
1132
1133                 } else {
1134                         if (resource[i]) {
1135                                 if (((struct r600_resource_texture *)resource[i]->base.texture)->depth)
1136                                         has_depth = 1;
1137                         }
1138                 }
1139         }
1140         for (i = count; i < NUM_TEX_UNITS; i++) {
1141                 if (rctx->ps_samplers.views[i]) {
1142                         r600_context_pipe_state_set_ps_resource(&rctx->ctx, NULL,
1143                                                                 i + R600_MAX_CONST_BUFFERS);
1144                         pipe_sampler_view_reference((struct pipe_sampler_view **)&rctx->ps_samplers.views[i], NULL);
1145                 }
1146         }
1147         rctx->have_depth_texture = has_depth;
1148         rctx->ps_samplers.n_views = count;
1149 }
1150
1151 static void r600_set_seamless_cubemap(struct r600_pipe_context *rctx, boolean enable)
1152 {
1153         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1154         if (rstate == NULL)
1155                 return;
1156
1157         rstate->id = R600_PIPE_STATE_SEAMLESS_CUBEMAP;
1158         r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
1159                                 (enable ? 0 : S_009508_DISABLE_CUBE_WRAP(1)),
1160                                 1, NULL);
1161
1162         free(rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP]);
1163         rctx->states[R600_PIPE_STATE_SEAMLESS_CUBEMAP] = rstate;
1164         r600_context_pipe_state_set(&rctx->ctx, rstate);
1165 }
1166
1167 static void r600_bind_ps_sampler(struct pipe_context *ctx, unsigned count, void **states)
1168 {
1169         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1170         struct r600_pipe_sampler_state **sstates = (struct r600_pipe_sampler_state **)states;
1171         int seamless = -1;
1172
1173         memcpy(rctx->ps_samplers.samplers, states, sizeof(void*) * count);
1174         rctx->ps_samplers.n_samplers = count;
1175
1176         for (int i = 0; i < count; i++) {
1177                 r600_context_pipe_state_set_ps_sampler(&rctx->ctx, &sstates[i]->rstate, i);
1178
1179                 if (sstates[i])
1180                         seamless = sstates[i]->seamless_cube_map;
1181         }
1182
1183         if (seamless != -1)
1184                 r600_set_seamless_cubemap(rctx, seamless);
1185 }
1186
1187 static void r600_bind_vs_sampler(struct pipe_context *ctx, unsigned count, void **states)
1188 {
1189         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1190         struct r600_pipe_sampler_state **sstates = (struct r600_pipe_sampler_state **)states;
1191         int seamless = -1;
1192
1193         for (int i = 0; i < count; i++) {
1194                 r600_context_pipe_state_set_vs_sampler(&rctx->ctx, &sstates[i]->rstate, i);
1195
1196                 if (sstates[i])
1197                         seamless = sstates[i]->seamless_cube_map;
1198         }
1199
1200         if (seamless != -1)
1201                 r600_set_seamless_cubemap(rctx, seamless);
1202 }
1203
1204 static void r600_set_clip_state(struct pipe_context *ctx,
1205                                 const struct pipe_clip_state *state)
1206 {
1207         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1208         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1209
1210         if (rstate == NULL)
1211                 return;
1212
1213         rctx->clip = *state;
1214         rstate->id = R600_PIPE_STATE_CLIP;
1215         for (int i = 0; i < state->nr; i++) {
1216                 r600_pipe_state_add_reg(rstate,
1217                                         R_028E20_PA_CL_UCP0_X + i * 16,
1218                                         fui(state->ucp[i][0]), 0xFFFFFFFF, NULL);
1219                 r600_pipe_state_add_reg(rstate,
1220                                         R_028E24_PA_CL_UCP0_Y + i * 16,
1221                                         fui(state->ucp[i][1]) , 0xFFFFFFFF, NULL);
1222                 r600_pipe_state_add_reg(rstate,
1223                                         R_028E28_PA_CL_UCP0_Z + i * 16,
1224                                         fui(state->ucp[i][2]), 0xFFFFFFFF, NULL);
1225                 r600_pipe_state_add_reg(rstate,
1226                                         R_028E2C_PA_CL_UCP0_W + i * 16,
1227                                         fui(state->ucp[i][3]), 0xFFFFFFFF, NULL);
1228         }
1229         r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
1230                         S_028810_PS_UCP_MODE(3) | ((1 << state->nr) - 1) |
1231                         S_028810_ZCLIP_NEAR_DISABLE(state->depth_clamp) |
1232                         S_028810_ZCLIP_FAR_DISABLE(state->depth_clamp), 0xFFFFFFFF, NULL);
1233
1234         free(rctx->states[R600_PIPE_STATE_CLIP]);
1235         rctx->states[R600_PIPE_STATE_CLIP] = rstate;
1236         r600_context_pipe_state_set(&rctx->ctx, rstate);
1237 }
1238
1239 static void r600_set_polygon_stipple(struct pipe_context *ctx,
1240                                          const struct pipe_poly_stipple *state)
1241 {
1242 }
1243
1244 static void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask)
1245 {
1246 }
1247
1248 static void r600_set_scissor_state(struct pipe_context *ctx,
1249                                         const struct pipe_scissor_state *state)
1250 {
1251         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1252         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1253         u32 tl, br;
1254
1255         if (rstate == NULL)
1256                 return;
1257
1258         rstate->id = R600_PIPE_STATE_SCISSOR;
1259         tl = S_028240_TL_X(state->minx) | S_028240_TL_Y(state->miny) | S_028240_WINDOW_OFFSET_DISABLE(1);
1260         br = S_028244_BR_X(state->maxx) | S_028244_BR_Y(state->maxy);
1261         r600_pipe_state_add_reg(rstate,
1262                                 R_028210_PA_SC_CLIPRECT_0_TL, tl,
1263                                 0xFFFFFFFF, NULL);
1264         r600_pipe_state_add_reg(rstate,
1265                                 R_028214_PA_SC_CLIPRECT_0_BR, br,
1266                                 0xFFFFFFFF, NULL);
1267         r600_pipe_state_add_reg(rstate,
1268                                 R_028218_PA_SC_CLIPRECT_1_TL, tl,
1269                                 0xFFFFFFFF, NULL);
1270         r600_pipe_state_add_reg(rstate,
1271                                 R_02821C_PA_SC_CLIPRECT_1_BR, br,
1272                                 0xFFFFFFFF, NULL);
1273         r600_pipe_state_add_reg(rstate,
1274                                 R_028220_PA_SC_CLIPRECT_2_TL, tl,
1275                                 0xFFFFFFFF, NULL);
1276         r600_pipe_state_add_reg(rstate,
1277                                 R_028224_PA_SC_CLIPRECT_2_BR, br,
1278                                 0xFFFFFFFF, NULL);
1279         r600_pipe_state_add_reg(rstate,
1280                                 R_028228_PA_SC_CLIPRECT_3_TL, tl,
1281                                 0xFFFFFFFF, NULL);
1282         r600_pipe_state_add_reg(rstate,
1283                                 R_02822C_PA_SC_CLIPRECT_3_BR, br,
1284                                 0xFFFFFFFF, NULL);
1285
1286         free(rctx->states[R600_PIPE_STATE_SCISSOR]);
1287         rctx->states[R600_PIPE_STATE_SCISSOR] = rstate;
1288         r600_context_pipe_state_set(&rctx->ctx, rstate);
1289 }
1290
1291 static void r600_set_stencil_ref(struct pipe_context *ctx,
1292                                 const struct pipe_stencil_ref *state)
1293 {
1294         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1295         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1296         u32 tmp;
1297
1298         if (rstate == NULL)
1299                 return;
1300
1301         rctx->stencil_ref = *state;
1302         rstate->id = R600_PIPE_STATE_STENCIL_REF;
1303         tmp = S_028430_STENCILREF(state->ref_value[0]);
1304         r600_pipe_state_add_reg(rstate,
1305                                 R_028430_DB_STENCILREFMASK, tmp,
1306                                 ~C_028430_STENCILREF, NULL);
1307         tmp = S_028434_STENCILREF_BF(state->ref_value[1]);
1308         r600_pipe_state_add_reg(rstate,
1309                                 R_028434_DB_STENCILREFMASK_BF, tmp,
1310                                 ~C_028434_STENCILREF_BF, NULL);
1311
1312         free(rctx->states[R600_PIPE_STATE_STENCIL_REF]);
1313         rctx->states[R600_PIPE_STATE_STENCIL_REF] = rstate;
1314         r600_context_pipe_state_set(&rctx->ctx, rstate);
1315 }
1316
1317 static void r600_set_viewport_state(struct pipe_context *ctx,
1318                                         const struct pipe_viewport_state *state)
1319 {
1320         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1321         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1322
1323         if (rstate == NULL)
1324                 return;
1325
1326         rctx->viewport = *state;
1327         rstate->id = R600_PIPE_STATE_VIEWPORT;
1328         r600_pipe_state_add_reg(rstate, R_0282D0_PA_SC_VPORT_ZMIN_0, 0x00000000, 0xFFFFFFFF, NULL);
1329         r600_pipe_state_add_reg(rstate, R_0282D4_PA_SC_VPORT_ZMAX_0, 0x3F800000, 0xFFFFFFFF, NULL);
1330         r600_pipe_state_add_reg(rstate, R_02843C_PA_CL_VPORT_XSCALE_0, fui(state->scale[0]), 0xFFFFFFFF, NULL);
1331         r600_pipe_state_add_reg(rstate, R_028444_PA_CL_VPORT_YSCALE_0, fui(state->scale[1]), 0xFFFFFFFF, NULL);
1332         r600_pipe_state_add_reg(rstate, R_02844C_PA_CL_VPORT_ZSCALE_0, fui(state->scale[2]), 0xFFFFFFFF, NULL);
1333         r600_pipe_state_add_reg(rstate, R_028440_PA_CL_VPORT_XOFFSET_0, fui(state->translate[0]), 0xFFFFFFFF, NULL);
1334         r600_pipe_state_add_reg(rstate, R_028448_PA_CL_VPORT_YOFFSET_0, fui(state->translate[1]), 0xFFFFFFFF, NULL);
1335         r600_pipe_state_add_reg(rstate, R_028450_PA_CL_VPORT_ZOFFSET_0, fui(state->translate[2]), 0xFFFFFFFF, NULL);
1336         r600_pipe_state_add_reg(rstate, R_028818_PA_CL_VTE_CNTL, 0x0000043F, 0xFFFFFFFF, NULL);
1337
1338         free(rctx->states[R600_PIPE_STATE_VIEWPORT]);
1339         rctx->states[R600_PIPE_STATE_VIEWPORT] = rstate;
1340         r600_context_pipe_state_set(&rctx->ctx, rstate);
1341 }
1342
1343 static void r600_cb(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1344                         const struct pipe_framebuffer_state *state, int cb)
1345 {
1346         struct r600_resource_texture *rtex;
1347         struct r600_resource *rbuffer;
1348         struct r600_surface *surf;
1349         unsigned level = state->cbufs[cb]->u.tex.level;
1350         unsigned pitch, slice;
1351         unsigned color_info;
1352         unsigned format, swap, ntype, endian;
1353         unsigned offset;
1354         const struct util_format_description *desc;
1355         struct r600_bo *bo[3];
1356         int i;
1357
1358         surf = (struct r600_surface *)state->cbufs[cb];
1359         rtex = (struct r600_resource_texture*)state->cbufs[cb]->texture;
1360
1361         if (rtex->depth)
1362                 rctx->have_depth_fb = TRUE;
1363
1364         if (rtex->depth && !rtex->is_flushing_texture) {
1365                 r600_texture_depth_flush(&rctx->context, state->cbufs[cb]->texture, TRUE);
1366                 rtex = rtex->flushed_depth_texture;
1367         }
1368
1369         rbuffer = &rtex->resource;
1370         bo[0] = rbuffer->bo;
1371         bo[1] = rbuffer->bo;
1372         bo[2] = rbuffer->bo;
1373
1374         /* XXX quite sure for dx10+ hw don't need any offset hacks */
1375         offset = r600_texture_get_offset(rtex,
1376                                          level, state->cbufs[cb]->u.tex.first_layer);
1377         pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1378         slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
1379         desc = util_format_description(surf->base.format);
1380
1381         for (i = 0; i < 4; i++) {
1382                 if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
1383                         break;
1384                 }
1385         }
1386         ntype = V_0280A0_NUMBER_UNORM;
1387         if (desc->colorspace == UTIL_FORMAT_COLORSPACE_SRGB)
1388                 ntype = V_0280A0_NUMBER_SRGB;
1389         else if (desc->channel[i].type == UTIL_FORMAT_TYPE_SIGNED)
1390                 ntype = V_0280A0_NUMBER_SNORM;
1391
1392         format = r600_translate_colorformat(surf->base.format);
1393         swap = r600_translate_colorswap(surf->base.format);
1394         if(rbuffer->b.b.b.usage == PIPE_USAGE_STAGING) {
1395                 endian = ENDIAN_NONE;
1396         } else {
1397                 endian = r600_colorformat_endian_swap(format);
1398         }
1399
1400         /* disable when gallium grows int textures */
1401         if ((format == FMT_32_32_32_32 || format == FMT_16_16_16_16) && rtex->force_int_type)
1402                 ntype = V_0280A0_NUMBER_UINT;
1403
1404         color_info = S_0280A0_FORMAT(format) |
1405                 S_0280A0_COMP_SWAP(swap) |
1406                 S_0280A0_ARRAY_MODE(rtex->array_mode[level]) |
1407                 S_0280A0_BLEND_CLAMP(1) |
1408                 S_0280A0_NUMBER_TYPE(ntype) |
1409                 S_0280A0_ENDIAN(endian);
1410
1411         /* EXPORT_NORM is an optimzation that can be enabled for better
1412          * performance in certain cases
1413          */
1414         if (rctx->chip_class == R600) {
1415                 /* EXPORT_NORM can be enabled if:
1416                  * - 11-bit or smaller UNORM/SNORM/SRGB
1417                  * - BLEND_CLAMP is enabled
1418                  * - BLEND_FLOAT32 is disabled
1419                  */
1420                 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1421                     (desc->channel[i].size < 12 &&
1422                      desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1423                      ntype != V_0280A0_NUMBER_UINT &&
1424                      ntype != V_0280A0_NUMBER_SINT) &&
1425                     G_0280A0_BLEND_CLAMP(color_info) &&
1426                     !G_0280A0_BLEND_FLOAT32(color_info))
1427                         color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1428         } else {
1429                 /* EXPORT_NORM can be enabled if:
1430                  * - 11-bit or smaller UNORM/SNORM/SRGB
1431                  * - 16-bit or smaller FLOAT
1432                  */
1433                 if (desc->colorspace != UTIL_FORMAT_COLORSPACE_ZS &&
1434                     ((desc->channel[i].size < 12 &&
1435                       desc->channel[i].type != UTIL_FORMAT_TYPE_FLOAT &&
1436                       ntype != V_0280A0_NUMBER_UINT && ntype != V_0280A0_NUMBER_SINT) ||
1437                     (desc->channel[i].size < 17 &&
1438                      desc->channel[i].type == UTIL_FORMAT_TYPE_FLOAT)))
1439                         color_info |= S_0280A0_SOURCE_FORMAT(V_0280A0_EXPORT_NORM);
1440         }
1441
1442         r600_pipe_state_add_reg(rstate,
1443                                 R_028040_CB_COLOR0_BASE + cb * 4,
1444                                 (offset + r600_bo_offset(bo[0])) >> 8, 0xFFFFFFFF, bo[0]);
1445         r600_pipe_state_add_reg(rstate,
1446                                 R_0280A0_CB_COLOR0_INFO + cb * 4,
1447                                 color_info, 0xFFFFFFFF, bo[0]);
1448         r600_pipe_state_add_reg(rstate,
1449                                 R_028060_CB_COLOR0_SIZE + cb * 4,
1450                                 S_028060_PITCH_TILE_MAX(pitch) |
1451                                 S_028060_SLICE_TILE_MAX(slice),
1452                                 0xFFFFFFFF, NULL);
1453         r600_pipe_state_add_reg(rstate,
1454                                 R_028080_CB_COLOR0_VIEW + cb * 4,
1455                                 0x00000000, 0xFFFFFFFF, NULL);
1456         r600_pipe_state_add_reg(rstate,
1457                                 R_0280E0_CB_COLOR0_FRAG + cb * 4,
1458                                 r600_bo_offset(bo[1]) >> 8, 0xFFFFFFFF, bo[1]);
1459         r600_pipe_state_add_reg(rstate,
1460                                 R_0280C0_CB_COLOR0_TILE + cb * 4,
1461                                 r600_bo_offset(bo[2]) >> 8, 0xFFFFFFFF, bo[2]);
1462         r600_pipe_state_add_reg(rstate,
1463                                 R_028100_CB_COLOR0_MASK + cb * 4,
1464                                 0x00000000, 0xFFFFFFFF, NULL);
1465 }
1466
1467 static void r600_db(struct r600_pipe_context *rctx, struct r600_pipe_state *rstate,
1468                         const struct pipe_framebuffer_state *state)
1469 {
1470         struct r600_resource_texture *rtex;
1471         struct r600_resource *rbuffer;
1472         struct r600_surface *surf;
1473         unsigned level;
1474         unsigned pitch, slice, format;
1475         unsigned offset;
1476
1477         if (state->zsbuf == NULL)
1478                 return;
1479
1480         level = state->zsbuf->u.tex.level;
1481
1482         surf = (struct r600_surface *)state->zsbuf;
1483         rtex = (struct r600_resource_texture*)state->zsbuf->texture;
1484
1485         rbuffer = &rtex->resource;
1486
1487         /* XXX quite sure for dx10+ hw don't need any offset hacks */
1488         offset = r600_texture_get_offset((struct r600_resource_texture *)state->zsbuf->texture,
1489                                          level, state->zsbuf->u.tex.first_layer);
1490         pitch = rtex->pitch_in_blocks[level] / 8 - 1;
1491         slice = rtex->pitch_in_blocks[level] * surf->aligned_height / 64 - 1;
1492         format = r600_translate_dbformat(state->zsbuf->texture->format);
1493
1494         r600_pipe_state_add_reg(rstate, R_02800C_DB_DEPTH_BASE,
1495                                 (offset + r600_bo_offset(rbuffer->bo)) >> 8, 0xFFFFFFFF, rbuffer->bo);
1496         r600_pipe_state_add_reg(rstate, R_028000_DB_DEPTH_SIZE,
1497                                 S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice),
1498                                 0xFFFFFFFF, NULL);
1499         r600_pipe_state_add_reg(rstate, R_028004_DB_DEPTH_VIEW, 0x00000000, 0xFFFFFFFF, NULL);
1500         r600_pipe_state_add_reg(rstate, R_028010_DB_DEPTH_INFO,
1501                                 S_028010_ARRAY_MODE(rtex->array_mode[level]) | S_028010_FORMAT(format),
1502                                 0xFFFFFFFF, rbuffer->bo);
1503         r600_pipe_state_add_reg(rstate, R_028D34_DB_PREFETCH_LIMIT,
1504                                 (surf->aligned_height / 8) - 1, 0xFFFFFFFF, NULL);
1505 }
1506
1507 static void r600_set_framebuffer_state(struct pipe_context *ctx,
1508                                         const struct pipe_framebuffer_state *state)
1509 {
1510         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1511         struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
1512         u32 shader_mask, tl, br, shader_control, target_mask;
1513
1514         if (rstate == NULL)
1515                 return;
1516
1517         r600_context_flush_dest_caches(&rctx->ctx);
1518         rctx->ctx.num_dest_buffers = state->nr_cbufs;
1519
1520         /* unreference old buffer and reference new one */
1521         rstate->id = R600_PIPE_STATE_FRAMEBUFFER;
1522
1523         util_copy_framebuffer_state(&rctx->framebuffer, state);
1524
1525         /* build states */
1526         rctx->have_depth_fb = 0;
1527         for (int i = 0; i < state->nr_cbufs; i++) {
1528                 r600_cb(rctx, rstate, state, i);
1529         }
1530         if (state->zsbuf) {
1531                 r600_db(rctx, rstate, state);
1532                 rctx->ctx.num_dest_buffers++;
1533         }
1534
1535         target_mask = 0x00000000;
1536         target_mask = 0xFFFFFFFF;
1537         shader_mask = 0;
1538         shader_control = 0;
1539         for (int i = 0; i < state->nr_cbufs; i++) {
1540                 target_mask ^= 0xf << (i * 4);
1541                 shader_mask |= 0xf << (i * 4);
1542                 shader_control |= 1 << i;
1543         }
1544         tl = S_028240_TL_X(0) | S_028240_TL_Y(0) | S_028240_WINDOW_OFFSET_DISABLE(1);
1545         br = S_028244_BR_X(state->width) | S_028244_BR_Y(state->height);
1546
1547         r600_pipe_state_add_reg(rstate,
1548                                 R_028030_PA_SC_SCREEN_SCISSOR_TL, tl,
1549                                 0xFFFFFFFF, NULL);
1550         r600_pipe_state_add_reg(rstate,
1551                                 R_028034_PA_SC_SCREEN_SCISSOR_BR, br,
1552                                 0xFFFFFFFF, NULL);
1553         r600_pipe_state_add_reg(rstate,
1554                                 R_028204_PA_SC_WINDOW_SCISSOR_TL, tl,
1555                                 0xFFFFFFFF, NULL);
1556         r600_pipe_state_add_reg(rstate,
1557                                 R_028208_PA_SC_WINDOW_SCISSOR_BR, br,
1558                                 0xFFFFFFFF, NULL);
1559         r600_pipe_state_add_reg(rstate,
1560                                 R_028240_PA_SC_GENERIC_SCISSOR_TL, tl,
1561                                 0xFFFFFFFF, NULL);
1562         r600_pipe_state_add_reg(rstate,
1563                                 R_028244_PA_SC_GENERIC_SCISSOR_BR, br,
1564                                 0xFFFFFFFF, NULL);
1565         r600_pipe_state_add_reg(rstate,
1566                                 R_028250_PA_SC_VPORT_SCISSOR_0_TL, tl,
1567                                 0xFFFFFFFF, NULL);
1568         r600_pipe_state_add_reg(rstate,
1569                                 R_028254_PA_SC_VPORT_SCISSOR_0_BR, br,
1570                                 0xFFFFFFFF, NULL);
1571         r600_pipe_state_add_reg(rstate,
1572                                 R_028200_PA_SC_WINDOW_OFFSET, 0x00000000,
1573                                 0xFFFFFFFF, NULL);
1574         if (rctx->chip_class >= R700) {
1575                 r600_pipe_state_add_reg(rstate,
1576                                         R_028230_PA_SC_EDGERULE, 0xAAAAAAAA,
1577                                         0xFFFFFFFF, NULL);
1578         }
1579
1580         r600_pipe_state_add_reg(rstate, R_0287A0_CB_SHADER_CONTROL,
1581                                 shader_control, 0xFFFFFFFF, NULL);
1582         r600_pipe_state_add_reg(rstate, R_028238_CB_TARGET_MASK,
1583                                 0x00000000, target_mask, NULL);
1584         r600_pipe_state_add_reg(rstate, R_02823C_CB_SHADER_MASK,
1585                                 shader_mask, 0xFFFFFFFF, NULL);
1586         r600_pipe_state_add_reg(rstate, R_028C04_PA_SC_AA_CONFIG,
1587                                 0x00000000, 0xFFFFFFFF, NULL);
1588         r600_pipe_state_add_reg(rstate, R_028C1C_PA_SC_AA_SAMPLE_LOCS_MCTX,
1589                                 0x00000000, 0xFFFFFFFF, NULL);
1590         r600_pipe_state_add_reg(rstate, R_028C20_PA_SC_AA_SAMPLE_LOCS_8S_WD1_MCTX,
1591                                 0x00000000, 0xFFFFFFFF, NULL);
1592         r600_pipe_state_add_reg(rstate, R_028C30_CB_CLRCMP_CONTROL,
1593                                 0x01000000, 0xFFFFFFFF, NULL);
1594         r600_pipe_state_add_reg(rstate, R_028C34_CB_CLRCMP_SRC,
1595                                 0x00000000, 0xFFFFFFFF, NULL);
1596         r600_pipe_state_add_reg(rstate, R_028C38_CB_CLRCMP_DST,
1597                                 0x000000FF, 0xFFFFFFFF, NULL);
1598         r600_pipe_state_add_reg(rstate, R_028C3C_CB_CLRCMP_MSK,
1599                                 0xFFFFFFFF, 0xFFFFFFFF, NULL);
1600         r600_pipe_state_add_reg(rstate, R_028C48_PA_SC_AA_MASK,
1601                                 0xFFFFFFFF, 0xFFFFFFFF, NULL);
1602
1603         free(rctx->states[R600_PIPE_STATE_FRAMEBUFFER]);
1604         rctx->states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
1605         r600_context_pipe_state_set(&rctx->ctx, rstate);
1606
1607         if (state->zsbuf) {
1608                 r600_polygon_offset_update(rctx);
1609         }
1610 }
1611
1612 static void r600_texture_barrier(struct pipe_context *ctx)
1613 {
1614         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1615
1616         r600_context_flush_all(&rctx->ctx, S_0085F0_TC_ACTION_ENA(1) | S_0085F0_CB_ACTION_ENA(1) |
1617                         S_0085F0_CB0_DEST_BASE_ENA(1) | S_0085F0_CB1_DEST_BASE_ENA(1) |
1618                         S_0085F0_CB2_DEST_BASE_ENA(1) | S_0085F0_CB3_DEST_BASE_ENA(1) |
1619                         S_0085F0_CB4_DEST_BASE_ENA(1) | S_0085F0_CB5_DEST_BASE_ENA(1) |
1620                         S_0085F0_CB6_DEST_BASE_ENA(1) | S_0085F0_CB7_DEST_BASE_ENA(1));
1621 }
1622
1623 void r600_init_state_functions(struct r600_pipe_context *rctx)
1624 {
1625         rctx->context.create_blend_state = r600_create_blend_state;
1626         rctx->context.create_depth_stencil_alpha_state = r600_create_dsa_state;
1627         rctx->context.create_fs_state = r600_create_shader_state;
1628         rctx->context.create_rasterizer_state = r600_create_rs_state;
1629         rctx->context.create_sampler_state = r600_create_sampler_state;
1630         rctx->context.create_sampler_view = r600_create_sampler_view;
1631         rctx->context.create_vertex_elements_state = r600_create_vertex_elements;
1632         rctx->context.create_vs_state = r600_create_shader_state;
1633         rctx->context.bind_blend_state = r600_bind_blend_state;
1634         rctx->context.bind_depth_stencil_alpha_state = r600_bind_dsa_state;
1635         rctx->context.bind_fragment_sampler_states = r600_bind_ps_sampler;
1636         rctx->context.bind_fs_state = r600_bind_ps_shader;
1637         rctx->context.bind_rasterizer_state = r600_bind_rs_state;
1638         rctx->context.bind_vertex_elements_state = r600_bind_vertex_elements;
1639         rctx->context.bind_vertex_sampler_states = r600_bind_vs_sampler;
1640         rctx->context.bind_vs_state = r600_bind_vs_shader;
1641         rctx->context.delete_blend_state = r600_delete_state;
1642         rctx->context.delete_depth_stencil_alpha_state = r600_delete_state;
1643         rctx->context.delete_fs_state = r600_delete_ps_shader;
1644         rctx->context.delete_rasterizer_state = r600_delete_rs_state;
1645         rctx->context.delete_sampler_state = r600_delete_state;
1646         rctx->context.delete_vertex_elements_state = r600_delete_vertex_element;
1647         rctx->context.delete_vs_state = r600_delete_vs_shader;
1648         rctx->context.set_blend_color = r600_set_blend_color;
1649         rctx->context.set_clip_state = r600_set_clip_state;
1650         rctx->context.set_constant_buffer = r600_set_constant_buffer;
1651         rctx->context.set_fragment_sampler_views = r600_set_ps_sampler_view;
1652         rctx->context.set_framebuffer_state = r600_set_framebuffer_state;
1653         rctx->context.set_polygon_stipple = r600_set_polygon_stipple;
1654         rctx->context.set_sample_mask = r600_set_sample_mask;
1655         rctx->context.set_scissor_state = r600_set_scissor_state;
1656         rctx->context.set_stencil_ref = r600_set_stencil_ref;
1657         rctx->context.set_vertex_buffers = r600_set_vertex_buffers;
1658         rctx->context.set_index_buffer = r600_set_index_buffer;
1659         rctx->context.set_vertex_sampler_views = r600_set_vs_sampler_view;
1660         rctx->context.set_viewport_state = r600_set_viewport_state;
1661         rctx->context.sampler_view_destroy = r600_sampler_view_destroy;
1662         rctx->context.redefine_user_buffer = u_default_redefine_user_buffer;
1663         rctx->context.texture_barrier = r600_texture_barrier;
1664 }
1665
1666 void r600_adjust_gprs(struct r600_pipe_context *rctx)
1667 {
1668         struct r600_pipe_state rstate;
1669         unsigned num_ps_gprs = rctx->default_ps_gprs;
1670         unsigned num_vs_gprs = rctx->default_vs_gprs;
1671         unsigned tmp;
1672         int diff;
1673
1674         if (rctx->chip_class >= EVERGREEN)
1675                 return;
1676
1677         if (!rctx->ps_shader && !rctx->vs_shader)
1678                 return;
1679
1680         if (rctx->ps_shader->shader.bc.ngpr > rctx->default_ps_gprs)
1681         {
1682                 diff = rctx->ps_shader->shader.bc.ngpr - rctx->default_ps_gprs;
1683                 num_vs_gprs -= diff;
1684                 num_ps_gprs += diff;
1685         }
1686
1687         if (rctx->vs_shader->shader.bc.ngpr > rctx->default_vs_gprs)
1688         {
1689                 diff = rctx->vs_shader->shader.bc.ngpr - rctx->default_vs_gprs;
1690                 num_ps_gprs -= diff;
1691                 num_vs_gprs += diff;
1692         }
1693
1694         tmp = 0;
1695         tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1696         tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1697         rstate.nregs = 0;
1698         r600_pipe_state_add_reg(&rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0x0FFFFFFF, NULL);
1699
1700         r600_context_pipe_state_set(&rctx->ctx, &rstate);
1701 }
1702
1703 void r600_init_config(struct r600_pipe_context *rctx)
1704 {
1705         int ps_prio;
1706         int vs_prio;
1707         int gs_prio;
1708         int es_prio;
1709         int num_ps_gprs;
1710         int num_vs_gprs;
1711         int num_gs_gprs;
1712         int num_es_gprs;
1713         int num_temp_gprs;
1714         int num_ps_threads;
1715         int num_vs_threads;
1716         int num_gs_threads;
1717         int num_es_threads;
1718         int num_ps_stack_entries;
1719         int num_vs_stack_entries;
1720         int num_gs_stack_entries;
1721         int num_es_stack_entries;
1722         enum radeon_family family;
1723         struct r600_pipe_state *rstate = &rctx->config;
1724         u32 tmp;
1725
1726         family = rctx->family;
1727         ps_prio = 0;
1728         vs_prio = 1;
1729         gs_prio = 2;
1730         es_prio = 3;
1731         switch (family) {
1732         case CHIP_R600:
1733                 num_ps_gprs = 192;
1734                 num_vs_gprs = 56;
1735                 num_temp_gprs = 4;
1736                 num_gs_gprs = 0;
1737                 num_es_gprs = 0;
1738                 num_ps_threads = 136;
1739                 num_vs_threads = 48;
1740                 num_gs_threads = 4;
1741                 num_es_threads = 4;
1742                 num_ps_stack_entries = 128;
1743                 num_vs_stack_entries = 128;
1744                 num_gs_stack_entries = 0;
1745                 num_es_stack_entries = 0;
1746                 break;
1747         case CHIP_RV630:
1748         case CHIP_RV635:
1749                 num_ps_gprs = 84;
1750                 num_vs_gprs = 36;
1751                 num_temp_gprs = 4;
1752                 num_gs_gprs = 0;
1753                 num_es_gprs = 0;
1754                 num_ps_threads = 144;
1755                 num_vs_threads = 40;
1756                 num_gs_threads = 4;
1757                 num_es_threads = 4;
1758                 num_ps_stack_entries = 40;
1759                 num_vs_stack_entries = 40;
1760                 num_gs_stack_entries = 32;
1761                 num_es_stack_entries = 16;
1762                 break;
1763         case CHIP_RV610:
1764         case CHIP_RV620:
1765         case CHIP_RS780:
1766         case CHIP_RS880:
1767         default:
1768                 num_ps_gprs = 84;
1769                 num_vs_gprs = 36;
1770                 num_temp_gprs = 4;
1771                 num_gs_gprs = 0;
1772                 num_es_gprs = 0;
1773                 num_ps_threads = 136;
1774                 num_vs_threads = 48;
1775                 num_gs_threads = 4;
1776                 num_es_threads = 4;
1777                 num_ps_stack_entries = 40;
1778                 num_vs_stack_entries = 40;
1779                 num_gs_stack_entries = 32;
1780                 num_es_stack_entries = 16;
1781                 break;
1782         case CHIP_RV670:
1783                 num_ps_gprs = 144;
1784                 num_vs_gprs = 40;
1785                 num_temp_gprs = 4;
1786                 num_gs_gprs = 0;
1787                 num_es_gprs = 0;
1788                 num_ps_threads = 136;
1789                 num_vs_threads = 48;
1790                 num_gs_threads = 4;
1791                 num_es_threads = 4;
1792                 num_ps_stack_entries = 40;
1793                 num_vs_stack_entries = 40;
1794                 num_gs_stack_entries = 32;
1795                 num_es_stack_entries = 16;
1796                 break;
1797         case CHIP_RV770:
1798                 num_ps_gprs = 192;
1799                 num_vs_gprs = 56;
1800                 num_temp_gprs = 4;
1801                 num_gs_gprs = 0;
1802                 num_es_gprs = 0;
1803                 num_ps_threads = 188;
1804                 num_vs_threads = 60;
1805                 num_gs_threads = 0;
1806                 num_es_threads = 0;
1807                 num_ps_stack_entries = 256;
1808                 num_vs_stack_entries = 256;
1809                 num_gs_stack_entries = 0;
1810                 num_es_stack_entries = 0;
1811                 break;
1812         case CHIP_RV730:
1813         case CHIP_RV740:
1814                 num_ps_gprs = 84;
1815                 num_vs_gprs = 36;
1816                 num_temp_gprs = 4;
1817                 num_gs_gprs = 0;
1818                 num_es_gprs = 0;
1819                 num_ps_threads = 188;
1820                 num_vs_threads = 60;
1821                 num_gs_threads = 0;
1822                 num_es_threads = 0;
1823                 num_ps_stack_entries = 128;
1824                 num_vs_stack_entries = 128;
1825                 num_gs_stack_entries = 0;
1826                 num_es_stack_entries = 0;
1827                 break;
1828         case CHIP_RV710:
1829                 num_ps_gprs = 192;
1830                 num_vs_gprs = 56;
1831                 num_temp_gprs = 4;
1832                 num_gs_gprs = 0;
1833                 num_es_gprs = 0;
1834                 num_ps_threads = 144;
1835                 num_vs_threads = 48;
1836                 num_gs_threads = 0;
1837                 num_es_threads = 0;
1838                 num_ps_stack_entries = 128;
1839                 num_vs_stack_entries = 128;
1840                 num_gs_stack_entries = 0;
1841                 num_es_stack_entries = 0;
1842                 break;
1843         }
1844
1845         rctx->default_ps_gprs = num_ps_gprs;
1846         rctx->default_vs_gprs = num_vs_gprs;
1847
1848         rstate->id = R600_PIPE_STATE_CONFIG;
1849
1850         /* SQ_CONFIG */
1851         tmp = 0;
1852         switch (family) {
1853         case CHIP_RV610:
1854         case CHIP_RV620:
1855         case CHIP_RS780:
1856         case CHIP_RS880:
1857         case CHIP_RV710:
1858                 break;
1859         default:
1860                 tmp |= S_008C00_VC_ENABLE(1);
1861                 break;
1862         }
1863         tmp |= S_008C00_DX9_CONSTS(0);
1864         tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
1865         tmp |= S_008C00_PS_PRIO(ps_prio);
1866         tmp |= S_008C00_VS_PRIO(vs_prio);
1867         tmp |= S_008C00_GS_PRIO(gs_prio);
1868         tmp |= S_008C00_ES_PRIO(es_prio);
1869         r600_pipe_state_add_reg(rstate, R_008C00_SQ_CONFIG, tmp, 0xFFFFFFFF, NULL);
1870
1871         /* SQ_GPR_RESOURCE_MGMT_1 */
1872         tmp = 0;
1873         tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
1874         tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
1875         tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(num_temp_gprs);
1876         r600_pipe_state_add_reg(rstate, R_008C04_SQ_GPR_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1877
1878         /* SQ_GPR_RESOURCE_MGMT_2 */
1879         tmp = 0;
1880         tmp |= S_008C08_NUM_GS_GPRS(num_gs_gprs);
1881         tmp |= S_008C08_NUM_ES_GPRS(num_es_gprs);
1882         r600_pipe_state_add_reg(rstate, R_008C08_SQ_GPR_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1883
1884         /* SQ_THREAD_RESOURCE_MGMT */
1885         tmp = 0;
1886         tmp |= S_008C0C_NUM_PS_THREADS(num_ps_threads);
1887         tmp |= S_008C0C_NUM_VS_THREADS(num_vs_threads);
1888         tmp |= S_008C0C_NUM_GS_THREADS(num_gs_threads);
1889         tmp |= S_008C0C_NUM_ES_THREADS(num_es_threads);
1890         r600_pipe_state_add_reg(rstate, R_008C0C_SQ_THREAD_RESOURCE_MGMT, tmp, 0xFFFFFFFF, NULL);
1891
1892         /* SQ_STACK_RESOURCE_MGMT_1 */
1893         tmp = 0;
1894         tmp |= S_008C10_NUM_PS_STACK_ENTRIES(num_ps_stack_entries);
1895         tmp |= S_008C10_NUM_VS_STACK_ENTRIES(num_vs_stack_entries);
1896         r600_pipe_state_add_reg(rstate, R_008C10_SQ_STACK_RESOURCE_MGMT_1, tmp, 0xFFFFFFFF, NULL);
1897
1898         /* SQ_STACK_RESOURCE_MGMT_2 */
1899         tmp = 0;
1900         tmp |= S_008C14_NUM_GS_STACK_ENTRIES(num_gs_stack_entries);
1901         tmp |= S_008C14_NUM_ES_STACK_ENTRIES(num_es_stack_entries);
1902         r600_pipe_state_add_reg(rstate, R_008C14_SQ_STACK_RESOURCE_MGMT_2, tmp, 0xFFFFFFFF, NULL);
1903
1904         r600_pipe_state_add_reg(rstate, R_009714_VC_ENHANCE, 0x00000000, 0xFFFFFFFF, NULL);
1905         r600_pipe_state_add_reg(rstate, R_028350_SX_MISC, 0x00000000, 0xFFFFFFFF, NULL);
1906
1907         if (rctx->chip_class >= R700) {
1908                 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00004000, 0xFFFFFFFF, NULL);
1909                 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
1910                                         S_009508_DISABLE_CUBE_ANISO(1) |
1911                                         S_009508_SYNC_GRADIENT(1) |
1912                                         S_009508_SYNC_WALKER(1) |
1913                                         S_009508_SYNC_ALIGNER(1), 0xFFFFFFFF, NULL);
1914                 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x00000000, 0xFFFFFFFF, NULL);
1915                 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x00420204, 0xFFFFFFFF, NULL);
1916                 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000000, 0xFFFFFFFF, NULL);
1917                 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00514002, 0xFFFFFFFF, NULL);
1918         } else {
1919                 r600_pipe_state_add_reg(rstate, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0x00000000, 0xFFFFFFFF, NULL);
1920                 r600_pipe_state_add_reg(rstate, R_009508_TA_CNTL_AUX,
1921                                         S_009508_DISABLE_CUBE_ANISO(1) |
1922                                         S_009508_SYNC_GRADIENT(1) |
1923                                         S_009508_SYNC_WALKER(1) |
1924                                         S_009508_SYNC_ALIGNER(1), 0xFFFFFFFF, NULL);
1925                 r600_pipe_state_add_reg(rstate, R_009830_DB_DEBUG, 0x82000000, 0xFFFFFFFF, NULL);
1926                 r600_pipe_state_add_reg(rstate, R_009838_DB_WATERMARKS, 0x01020204, 0xFFFFFFFF, NULL);
1927                 r600_pipe_state_add_reg(rstate, R_0286C8_SPI_THREAD_GROUPING, 0x00000001, 0xFFFFFFFF, NULL);
1928                 r600_pipe_state_add_reg(rstate, R_028A4C_PA_SC_MODE_CNTL, 0x00004012, 0xFFFFFFFF, NULL);
1929         }
1930         r600_pipe_state_add_reg(rstate, R_0288A8_SQ_ESGS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1931         r600_pipe_state_add_reg(rstate, R_0288AC_SQ_GSVS_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1932         r600_pipe_state_add_reg(rstate, R_0288B0_SQ_ESTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1933         r600_pipe_state_add_reg(rstate, R_0288B4_SQ_GSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1934         r600_pipe_state_add_reg(rstate, R_0288B8_SQ_VSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1935         r600_pipe_state_add_reg(rstate, R_0288BC_SQ_PSTMP_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1936         r600_pipe_state_add_reg(rstate, R_0288C0_SQ_FBUF_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1937         r600_pipe_state_add_reg(rstate, R_0288C4_SQ_REDUC_RING_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1938         r600_pipe_state_add_reg(rstate, R_0288C8_SQ_GS_VERT_ITEMSIZE, 0x00000000, 0xFFFFFFFF, NULL);
1939         r600_pipe_state_add_reg(rstate, R_028A10_VGT_OUTPUT_PATH_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1940         r600_pipe_state_add_reg(rstate, R_028A14_VGT_HOS_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1941         r600_pipe_state_add_reg(rstate, R_028A18_VGT_HOS_MAX_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1942         r600_pipe_state_add_reg(rstate, R_028A1C_VGT_HOS_MIN_TESS_LEVEL, 0x00000000, 0xFFFFFFFF, NULL);
1943         r600_pipe_state_add_reg(rstate, R_028A20_VGT_HOS_REUSE_DEPTH, 0x00000000, 0xFFFFFFFF, NULL);
1944         r600_pipe_state_add_reg(rstate, R_028A24_VGT_GROUP_PRIM_TYPE, 0x00000000, 0xFFFFFFFF, NULL);
1945         r600_pipe_state_add_reg(rstate, R_028A28_VGT_GROUP_FIRST_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1946         r600_pipe_state_add_reg(rstate, R_028A2C_VGT_GROUP_DECR, 0x00000000, 0xFFFFFFFF, NULL);
1947         r600_pipe_state_add_reg(rstate, R_028A30_VGT_GROUP_VECT_0_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1948         r600_pipe_state_add_reg(rstate, R_028A34_VGT_GROUP_VECT_1_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1949         r600_pipe_state_add_reg(rstate, R_028A38_VGT_GROUP_VECT_0_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1950         r600_pipe_state_add_reg(rstate, R_028A3C_VGT_GROUP_VECT_1_FMT_CNTL, 0x00000000, 0xFFFFFFFF, NULL);
1951         r600_pipe_state_add_reg(rstate, R_028A40_VGT_GS_MODE, 0x00000000, 0xFFFFFFFF, NULL);
1952         r600_pipe_state_add_reg(rstate, R_028AB0_VGT_STRMOUT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1953         r600_pipe_state_add_reg(rstate, R_028AB4_VGT_REUSE_OFF, 0x00000001, 0xFFFFFFFF, NULL);
1954         r600_pipe_state_add_reg(rstate, R_028AB8_VGT_VTX_CNT_EN, 0x00000000, 0xFFFFFFFF, NULL);
1955         r600_pipe_state_add_reg(rstate, R_028B20_VGT_STRMOUT_BUFFER_EN, 0x00000000, 0xFFFFFFFF, NULL);
1956
1957         r600_pipe_state_add_reg(rstate, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX, 0x00000000, 0xFFFFFFFF, NULL);
1958         r600_pipe_state_add_reg(rstate, R_028A84_VGT_PRIMITIVEID_EN, 0x00000000, 0xFFFFFFFF, NULL);
1959         r600_pipe_state_add_reg(rstate, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, 0x00000000, 0xFFFFFFFF, NULL);
1960         r600_pipe_state_add_reg(rstate, R_028AA0_VGT_INSTANCE_STEP_RATE_0, 0x00000000, 0xFFFFFFFF, NULL);
1961         r600_pipe_state_add_reg(rstate, R_028AA4_VGT_INSTANCE_STEP_RATE_1, 0x00000000, 0xFFFFFFFF, NULL);
1962         r600_context_pipe_state_set(&rctx->ctx, rstate);
1963 }
1964
1965 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader)
1966 {
1967         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
1968         struct r600_pipe_state *rstate = &shader->rstate;
1969         struct r600_shader *rshader = &shader->shader;
1970         unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z, spi_ps_in_control_1, db_shader_control;
1971         int pos_index = -1, face_index = -1;
1972
1973         rstate->nregs = 0;
1974
1975         for (i = 0; i < rshader->ninput; i++) {
1976                 if (rshader->input[i].name == TGSI_SEMANTIC_POSITION)
1977                         pos_index = i;
1978                 if (rshader->input[i].name == TGSI_SEMANTIC_FACE)
1979                         face_index = i;
1980         }
1981
1982         db_shader_control = 0;
1983         for (i = 0; i < rshader->noutput; i++) {
1984                 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION)
1985                         db_shader_control |= S_02880C_Z_EXPORT_ENABLE(1);
1986                 if (rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1987                         db_shader_control |= S_02880C_STENCIL_REF_EXPORT_ENABLE(1);
1988         }
1989         if (rshader->uses_kill)
1990                 db_shader_control |= S_02880C_KILL_ENABLE(1);
1991
1992         exports_ps = 0;
1993         num_cout = 0;
1994         for (i = 0; i < rshader->noutput; i++) {
1995                 if (rshader->output[i].name == TGSI_SEMANTIC_POSITION ||
1996                     rshader->output[i].name == TGSI_SEMANTIC_STENCIL)
1997                         exports_ps |= 1;
1998                 else if (rshader->output[i].name == TGSI_SEMANTIC_COLOR) {
1999                         num_cout++;
2000                 }
2001         }
2002         exports_ps |= S_028854_EXPORT_COLORS(num_cout);
2003         if (!exports_ps) {
2004                 /* always at least export 1 component per pixel */
2005                 exports_ps = 2;
2006         }
2007
2008         spi_ps_in_control_0 = S_0286CC_NUM_INTERP(rshader->ninput) |
2009                                 S_0286CC_PERSP_GRADIENT_ENA(1);
2010         spi_input_z = 0;
2011         if (pos_index != -1) {
2012                 spi_ps_in_control_0 |= (S_0286CC_POSITION_ENA(1) |
2013                                         S_0286CC_POSITION_CENTROID(rshader->input[pos_index].centroid) |
2014                                         S_0286CC_POSITION_ADDR(rshader->input[pos_index].gpr) |
2015                                         S_0286CC_BARYC_SAMPLE_CNTL(1));
2016                 spi_input_z |= 1;
2017         }
2018
2019         spi_ps_in_control_1 = 0;
2020         if (face_index != -1) {
2021                 spi_ps_in_control_1 |= S_0286D0_FRONT_FACE_ENA(1) |
2022                         S_0286D0_FRONT_FACE_ADDR(rshader->input[face_index].gpr);
2023         }
2024
2025         r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0, spi_ps_in_control_0, 0xFFFFFFFF, NULL);
2026         r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1, spi_ps_in_control_1, 0xFFFFFFFF, NULL);
2027         r600_pipe_state_add_reg(rstate, R_0286D8_SPI_INPUT_Z, spi_input_z, 0xFFFFFFFF, NULL);
2028         r600_pipe_state_add_reg(rstate,
2029                                 R_028840_SQ_PGM_START_PS,
2030                                 r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
2031         r600_pipe_state_add_reg(rstate,
2032                                 R_028850_SQ_PGM_RESOURCES_PS,
2033                                 S_028868_NUM_GPRS(rshader->bc.ngpr) |
2034                                 S_028868_STACK_SIZE(rshader->bc.nstack),
2035                                 0xFFFFFFFF, NULL);
2036         r600_pipe_state_add_reg(rstate,
2037                                 R_028854_SQ_PGM_EXPORTS_PS,
2038                                 exports_ps, 0xFFFFFFFF, NULL);
2039         r600_pipe_state_add_reg(rstate,
2040                                 R_0288CC_SQ_PGM_CF_OFFSET_PS,
2041                                 0x00000000, 0xFFFFFFFF, NULL);
2042         r600_pipe_state_add_reg(rstate, R_028808_CB_COLOR_CONTROL,
2043                                 S_028808_MULTIWRITE_ENABLE(!!rshader->fs_write_all),
2044                                 S_028808_MULTIWRITE_ENABLE(1),
2045                                 NULL);
2046         /* only set some bits here, the other bits are set in the dsa state */
2047         r600_pipe_state_add_reg(rstate, R_02880C_DB_SHADER_CONTROL,
2048                                 db_shader_control,
2049                                 S_02880C_Z_EXPORT_ENABLE(1) |
2050                                 S_02880C_STENCIL_REF_EXPORT_ENABLE(1) |
2051                                 S_02880C_KILL_ENABLE(1),
2052                                 NULL);
2053
2054         r600_pipe_state_add_reg(rstate,
2055                                 R_03E200_SQ_LOOP_CONST_0, 0x01000FFF,
2056                                 0xFFFFFFFF, NULL);
2057 }
2058
2059 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader)
2060 {
2061         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2062         struct r600_pipe_state *rstate = &shader->rstate;
2063         struct r600_shader *rshader = &shader->shader;
2064         unsigned spi_vs_out_id[10];
2065         unsigned i, tmp;
2066
2067         /* clear previous register */
2068         rstate->nregs = 0;
2069
2070         /* so far never got proper semantic id from tgsi */
2071         /* FIXME better to move this in config things so they get emited
2072          * only one time per cs
2073          */
2074         for (i = 0; i < 10; i++) {
2075                 spi_vs_out_id[i] = 0;
2076         }
2077         for (i = 0; i < 32; i++) {
2078                 tmp = i << ((i & 3) * 8);
2079                 spi_vs_out_id[i / 4] |= tmp;
2080         }
2081         for (i = 0; i < 10; i++) {
2082                 r600_pipe_state_add_reg(rstate,
2083                                         R_028614_SPI_VS_OUT_ID_0 + i * 4,
2084                                         spi_vs_out_id[i], 0xFFFFFFFF, NULL);
2085         }
2086
2087         r600_pipe_state_add_reg(rstate,
2088                         R_0286C4_SPI_VS_OUT_CONFIG,
2089                         S_0286C4_VS_EXPORT_COUNT(rshader->noutput - 2),
2090                         0xFFFFFFFF, NULL);
2091         r600_pipe_state_add_reg(rstate,
2092                         R_028868_SQ_PGM_RESOURCES_VS,
2093                         S_028868_NUM_GPRS(rshader->bc.ngpr) |
2094                         S_028868_STACK_SIZE(rshader->bc.nstack),
2095                         0xFFFFFFFF, NULL);
2096         r600_pipe_state_add_reg(rstate,
2097                         R_0288D0_SQ_PGM_CF_OFFSET_VS,
2098                         0x00000000, 0xFFFFFFFF, NULL);
2099         r600_pipe_state_add_reg(rstate,
2100                         R_028858_SQ_PGM_START_VS,
2101                         r600_bo_offset(shader->bo) >> 8, 0xFFFFFFFF, shader->bo);
2102
2103         r600_pipe_state_add_reg(rstate,
2104                                 R_03E200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF,
2105                                 0xFFFFFFFF, NULL);
2106 }
2107
2108 void r600_fetch_shader(struct pipe_context *ctx,
2109                        struct r600_vertex_element *ve)
2110 {
2111         struct r600_pipe_state *rstate;
2112         struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
2113
2114         rstate = &ve->rstate;
2115         rstate->id = R600_PIPE_STATE_FETCH_SHADER;
2116         rstate->nregs = 0;
2117         r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_RESOURCES_FS,
2118                                 0x00000000, 0xFFFFFFFF, NULL);
2119         r600_pipe_state_add_reg(rstate, R_0288DC_SQ_PGM_CF_OFFSET_FS,
2120                                 0x00000000, 0xFFFFFFFF, NULL);
2121         r600_pipe_state_add_reg(rstate, R_028894_SQ_PGM_START_FS,
2122                                 r600_bo_offset(ve->fetch_shader) >> 8,
2123                                 0xFFFFFFFF, ve->fetch_shader);
2124 }
2125
2126 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx)
2127 {
2128         struct pipe_depth_stencil_alpha_state dsa;
2129         struct r600_pipe_state *rstate;
2130         boolean quirk = false;
2131
2132         if (rctx->family == CHIP_RV610 || rctx->family == CHIP_RV630 ||
2133                 rctx->family == CHIP_RV620 || rctx->family == CHIP_RV635)
2134                 quirk = true;
2135
2136         memset(&dsa, 0, sizeof(dsa));
2137
2138         if (quirk) {
2139                 dsa.depth.enabled = 1;
2140                 dsa.depth.func = PIPE_FUNC_LEQUAL;
2141                 dsa.stencil[0].enabled = 1;
2142                 dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
2143                 dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
2144                 dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
2145                 dsa.stencil[0].writemask = 0xff;
2146         }
2147
2148         rstate = rctx->context.create_depth_stencil_alpha_state(&rctx->context, &dsa);
2149         r600_pipe_state_add_reg(rstate,
2150                                 R_02880C_DB_SHADER_CONTROL,
2151                                 0x0,
2152                                 S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
2153         r600_pipe_state_add_reg(rstate,
2154                                 R_028D0C_DB_RENDER_CONTROL,
2155                                 S_028D0C_DEPTH_COPY_ENABLE(1) |
2156                                 S_028D0C_STENCIL_COPY_ENABLE(1) |
2157                                 S_028D0C_COPY_CENTROID(1),
2158                                 S_028D0C_DEPTH_COPY_ENABLE(1) |
2159                                 S_028D0C_STENCIL_COPY_ENABLE(1) |
2160                                 S_028D0C_COPY_CENTROID(1), NULL);
2161         return rstate;
2162 }
2163
2164 void r600_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
2165                                     struct r600_pipe_resource_state *rstate)
2166 {
2167         rstate->id = R600_PIPE_STATE_RESOURCE;
2168
2169         rstate->bo[0] = NULL;
2170         rstate->val[0] = 0;
2171         rstate->val[1] = 0;
2172         rstate->val[2] = 0;
2173         rstate->val[3] = 0;
2174         rstate->val[4] = 0;
2175         rstate->val[5] = 0;
2176         rstate->val[6] = 0xc0000000;
2177 }
2178
2179 void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
2180                                    struct r600_resource *rbuffer,
2181                                    unsigned offset, unsigned stride)
2182 {
2183         rstate->val[0] = offset;
2184         rstate->bo[0] = rbuffer->bo;
2185         rstate->val[1] = rbuffer->bo_size - offset - 1;
2186         rstate->val[2] = S_038008_ENDIAN_SWAP(r600_endian_swap(32)) |
2187                          S_038008_STRIDE(stride);
2188 }