src/gallium/drivers/r600/r600_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef R600_PIPE_H
  27 #define R600_PIPE_H
  28
  29 #include "util/u_slab.h"
  30 #include "r600.h"
  31 #include "r600_llvm.h"
  32 #include "r600_public.h"
  33 #include "r600_shader.h"
  34 #include "r600_resource.h"
  35 #include "evergreen_compute.h"
  36
  37 #define R600_MAX_CONST_BUFFERS 2
  38 #define R600_MAX_CONST_BUFFER_SIZE 4096
  39
  40 #ifdef PIPE_ARCH_BIG_ENDIAN
  41 #define R600_BIG_ENDIAN 1
  42 #else
  43 #define R600_BIG_ENDIAN 0
  44 #endif
  45
  46 enum r600_atom_flags {
  47         /* When set, atoms are added at the beginning of the dirty list
  48          * instead of the end. */
  49         EMIT_EARLY = (1 << 0)
  50 };
  51
  52 /* This encapsulates a state or an operation which can emitted into the GPU
  53  * command stream. It's not limited to states only, it can be used for anything
  54  * that wants to write commands into the CS (e.g. cache flushes). */
  55 struct r600_atom {
  56         void (*emit)(struct r600_context *ctx, struct r600_atom *state);
  57
  58         unsigned                num_dw;
  59         enum r600_atom_flags    flags;
  60         bool                    dirty;
  61
  62         struct list_head        head;
  63 };
  64
  65 /* This is an atom containing GPU commands that never change.
  66  * This is supposed to be copied directly into the CS. */
  67 struct r600_command_buffer {
  68         struct r600_atom atom;
  69         uint32_t *buf;
  70         unsigned max_num_dw;
  71         unsigned pkt_flags;
  72 };
  73
  74 struct r600_surface_sync_cmd {
  75         struct r600_atom atom;
  76         unsigned flush_flags; /* CP_COHER_CNTL */
  77 };
  78
  79 struct r600_db_misc_state {
  80         struct r600_atom atom;
  81         bool occlusion_query_enabled;
  82         bool flush_depthstencil_through_cb;
  83         bool copy_depth, copy_stencil;
  84 };
  85
  86 struct r600_cb_misc_state {
  87         struct r600_atom atom;
  88         unsigned cb_color_control; /* this comes from blend state */
  89         unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
  90         unsigned nr_cbufs;
  91         unsigned nr_ps_color_outputs;
  92         bool multiwrite;
  93         bool dual_src_blend;
  94 };
  95
  96 struct r600_alphatest_state {
  97         struct r600_atom atom;
  98         unsigned sx_alpha_test_control; /* this comes from dsa state */
  99         unsigned sx_alpha_ref; /* this comes from dsa state */
 100         bool bypass;
 101         bool cb0_export_16bpc; /* from set_framebuffer_state */
 102 };
 103
 104 struct r600_cs_shader_state {
 105         struct r600_atom atom;
 106         struct r600_pipe_compute *shader;
 107 };
 108
 109 enum r600_pipe_state_id {
 110         R600_PIPE_STATE_BLEND = 0,
 111         R600_PIPE_STATE_BLEND_COLOR,
 112         R600_PIPE_STATE_CONFIG,
 113         R600_PIPE_STATE_SEAMLESS_CUBEMAP,
 114         R600_PIPE_STATE_CLIP,
 115         R600_PIPE_STATE_SCISSOR,
 116         R600_PIPE_STATE_VIEWPORT,
 117         R600_PIPE_STATE_RASTERIZER,
 118         R600_PIPE_STATE_VGT,
 119         R600_PIPE_STATE_FRAMEBUFFER,
 120         R600_PIPE_STATE_DSA,
 121         R600_PIPE_STATE_STENCIL_REF,
 122         R600_PIPE_STATE_PS_SHADER,
 123         R600_PIPE_STATE_VS_SHADER,
 124         R600_PIPE_STATE_CONSTANT,
 125         R600_PIPE_STATE_SAMPLER,
 126         R600_PIPE_STATE_RESOURCE,
 127         R600_PIPE_STATE_POLYGON_OFFSET,
 128         R600_PIPE_STATE_FETCH_SHADER,
 129         R600_PIPE_STATE_SPI,
 130         R600_PIPE_NSTATES
 131 };
 132
 133 struct compute_memory_pool;
 134 void compute_memory_pool_delete(struct compute_memory_pool* pool);
 135 struct compute_memory_pool* compute_memory_pool_new(
 136         struct r600_screen *rscreen);
 137
 138 struct r600_pipe_fences {
 139         struct r600_resource            *bo;
 140         unsigned                        *data;
 141         unsigned                        next_index;
 142         /* linked list of preallocated blocks */
 143         struct list_head                blocks;
 144         /* linked list of freed fences */
 145         struct list_head                pool;
 146         pipe_mutex                      mutex;
 147 };
 148
 149 struct r600_screen {
 150         struct pipe_screen              screen;
 151         struct radeon_winsys            *ws;
 152         unsigned                        family;
 153         enum chip_class                 chip_class;
 154         struct radeon_info              info;
 155         bool                            has_streamout;
 156         struct r600_tiling_info         tiling_info;
 157         struct r600_pipe_fences         fences;
 158
 159         bool                            use_surface_alloc;
 160
 161         /*for compute global memory binding, we allocate stuff here, instead of
 162          * buffers.
 163          * XXX: Not sure if this is the best place for global_pool.  Also,
 164          * it's not thread safe, so it won't work with multiple contexts. */
 165         struct compute_memory_pool *global_pool;
 166 };
 167
 168 struct r600_pipe_sampler_view {
 169         struct pipe_sampler_view        base;
 170         struct r600_resource            *tex_resource;
 171         uint32_t                        tex_resource_words[8];
 172 };
 173
 174 struct r600_pipe_rasterizer {
 175         struct r600_pipe_state          rstate;
 176         boolean                         flatshade;
 177         boolean                         two_side;
 178         unsigned                        sprite_coord_enable;
 179         unsigned                        clip_plane_enable;
 180         unsigned                        pa_sc_line_stipple;
 181         unsigned                        pa_cl_clip_cntl;
 182         float                           offset_units;
 183         float                           offset_scale;
 184         bool                            scissor_enable;
 185 };
 186
 187 struct r600_pipe_blend {
 188         struct r600_pipe_state          rstate;
 189         unsigned                        cb_target_mask;
 190         unsigned                        cb_color_control;
 191         bool                            dual_src_blend;
 192 };
 193
 194 struct r600_pipe_dsa {
 195         struct r600_pipe_state          rstate;
 196         unsigned                        alpha_ref;
 197         ubyte                           valuemask[2];
 198         ubyte                           writemask[2];
 199         unsigned                        sx_alpha_test_control;
 200 };
 201
 202 struct r600_vertex_element
 203 {
 204         unsigned                        count;
 205         struct pipe_vertex_element      elements[PIPE_MAX_ATTRIBS];
 206         struct r600_resource            *fetch_shader;
 207         unsigned                        fs_size;
 208         struct r600_pipe_state          rstate;
 209 };
 210
 211 struct r600_pipe_shader;
 212
 213 struct r600_pipe_shader_selector {
 214         struct r600_pipe_shader *current;
 215
 216         struct tgsi_token       *tokens;
 217         struct pipe_stream_output_info  so;
 218
 219         unsigned        num_shaders;
 220
 221         /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
 222         unsigned        type;
 223
 224         unsigned        nr_ps_max_color_exports;
 225 };
 226
 227 struct r600_pipe_shader {
 228         struct r600_pipe_shader_selector *selector;
 229         struct r600_pipe_shader *next_variant;
 230         struct r600_shader              shader;
 231         struct r600_pipe_state          rstate;
 232         struct r600_resource            *bo;
 233         struct r600_resource            *bo_fetch;
 234         struct r600_vertex_element      vertex_elements;
 235         unsigned        sprite_coord_enable;
 236         unsigned        flatshade;
 237         unsigned        pa_cl_vs_out_cntl;
 238         unsigned        nr_ps_color_outputs;
 239         unsigned        key;
 240         unsigned                db_shader_control;
 241         unsigned                ps_depth_export;
 242 };
 243
 244 struct r600_pipe_sampler_state {
 245         struct r600_pipe_state          rstate;
 246         boolean seamless_cube_map;
 247 };
 248
 249 /* needed for blitter save */
 250 #define NUM_TEX_UNITS 16
 251
 252 struct r600_samplerview_state
 253 {
 254         struct r600_atom                atom;
 255         struct r600_pipe_sampler_view   *views[NUM_TEX_UNITS];
 256         uint32_t                        enabled_mask;
 257         uint32_t                        dirty_mask;
 258         uint32_t                        depth_texture_mask; /* which textures are depth */
 259 };
 260
 261 struct r600_textures_info {
 262         struct r600_samplerview_state   views;
 263
 264         struct r600_pipe_sampler_state  *samplers[NUM_TEX_UNITS];
 265         unsigned                        n_samplers;
 266         bool                            samplers_dirty;
 267         bool                            is_array_sampler[NUM_TEX_UNITS];
 268 };
 269
 270 struct r600_fence {
 271         struct pipe_reference           reference;
 272         unsigned                        index; /* in the shared bo */
 273         struct r600_resource            *sleep_bo;
 274         struct list_head                head;
 275 };
 276
 277 #define FENCE_BLOCK_SIZE 16
 278
 279 struct r600_fence_block {
 280         struct r600_fence               fences[FENCE_BLOCK_SIZE];
 281         struct list_head                head;
 282 };
 283
 284 #define R600_CONSTANT_ARRAY_SIZE 256
 285 #define R600_RESOURCE_ARRAY_SIZE 160
 286
 287 struct r600_stencil_ref
 288 {
 289         ubyte ref_value[2];
 290         ubyte valuemask[2];
 291         ubyte writemask[2];
 292 };
 293
 294 struct r600_constbuf_state
 295 {
 296         struct r600_atom                atom;
 297         struct pipe_constant_buffer     cb[PIPE_MAX_CONSTANT_BUFFERS];
 298         uint32_t                        enabled_mask;
 299         uint32_t                        dirty_mask;
 300 };
 301
 302 struct r600_vertexbuf_state
 303 {
 304         struct r600_atom                atom;
 305         struct pipe_vertex_buffer       vb[PIPE_MAX_ATTRIBS];
 306         uint32_t                        enabled_mask; /* non-NULL buffers */
 307         uint32_t                        dirty_mask;
 308 };
 309
 310 struct r600_context {
 311         struct pipe_context             context;
 312         struct blitter_context          *blitter;
 313         enum radeon_family              family;
 314         enum chip_class                 chip_class;
 315         boolean                         has_vertex_cache;
 316         unsigned                        r6xx_num_clause_temp_gprs;
 317         void                            *custom_dsa_flush;
 318         struct r600_screen              *screen;
 319         struct radeon_winsys            *ws;
 320         struct r600_pipe_state          *states[R600_PIPE_NSTATES];
 321         struct r600_vertex_element      *vertex_elements;
 322         struct pipe_framebuffer_state   framebuffer;
 323         unsigned                        compute_cb_target_mask;
 324         unsigned                        db_shader_control;
 325         unsigned                        pa_sc_line_stipple;
 326         unsigned                        pa_cl_clip_cntl;
 327         /* for saving when using blitter */
 328         struct pipe_stencil_ref         stencil_ref;
 329         struct pipe_viewport_state      viewport;
 330         struct pipe_clip_state          clip;
 331         struct r600_pipe_shader_selector        *ps_shader;
 332         struct r600_pipe_shader_selector        *vs_shader;
 333         struct r600_pipe_rasterizer     *rasterizer;
 334         struct r600_pipe_state          vgt;
 335         struct r600_pipe_state          spi;
 336         struct pipe_query               *current_render_cond;
 337         unsigned                        current_render_cond_mode;
 338         struct pipe_query               *saved_render_cond;
 339         unsigned                        saved_render_cond_mode;
 340         /* shader information */
 341         boolean                         two_side;
 342         boolean                         spi_dirty;
 343         unsigned                        sprite_coord_enable;
 344         boolean                         flatshade;
 345         boolean                         export_16bpc;
 346         unsigned                        nr_cbufs;
 347
 348         struct u_upload_mgr             *uploader;
 349         struct util_slab_mempool        pool_transfers;
 350
 351         unsigned default_ps_gprs, default_vs_gprs;
 352
 353         /* States based on r600_atom. */
 354         struct list_head                dirty_states;
 355         struct r600_command_buffer      start_cs_cmd; /* invariant state mostly */
 356         /** Compute specific registers initializations.  The start_cs_cmd atom
 357          *  must be emitted before start_compute_cs_cmd. */
 358         struct r600_command_buffer      start_compute_cs_cmd;
 359         struct r600_surface_sync_cmd    surface_sync_cmd;
 360         struct r600_atom                r6xx_flush_and_inv_cmd;
 361         struct r600_alphatest_state     alphatest_state;
 362         struct r600_cb_misc_state       cb_misc_state;
 363         struct r600_db_misc_state       db_misc_state;
 364         /** Vertex buffers for fetch shaders */
 365         struct r600_vertexbuf_state     vertex_buffer_state;
 366         /** Vertex buffers for compute shaders */
 367         struct r600_vertexbuf_state     cs_vertex_buffer_state;
 368         struct r600_constbuf_state      vs_constbuf_state;
 369         struct r600_constbuf_state      ps_constbuf_state;
 370         struct r600_textures_info       vs_samplers;
 371         struct r600_textures_info       ps_samplers;
 372         struct r600_cs_shader_state     cs_shader_state;
 373
 374         struct radeon_winsys_cs *cs;
 375
 376         struct r600_range       *range;
 377         unsigned                nblocks;
 378         struct r600_block       **blocks;
 379         struct list_head        dirty;
 380         struct list_head        enable_list;
 381         unsigned                pm4_dirty_cdwords;
 382         unsigned                ctx_pm4_ndwords;
 383
 384         /* The list of active queries. Only one query of each type can be active. */
 385         int                     num_occlusion_queries;
 386
 387         /* Manage queries in two separate groups:
 388          * The timer ones and the others (streamout, occlusion).
 389          *
 390          * We do this because we should only suspend non-timer queries for u_blitter,
 391          * and later if the non-timer queries are suspended, the context flush should
 392          * only suspend and resume the timer queries. */
 393         struct list_head        active_timer_queries;
 394         unsigned                num_cs_dw_timer_queries_suspend;
 395         struct list_head        active_nontimer_queries;
 396         unsigned                num_cs_dw_nontimer_queries_suspend;
 397
 398         unsigned                num_cs_dw_streamout_end;
 399
 400         unsigned                backend_mask;
 401         unsigned                max_db; /* for OQ */
 402         unsigned                flags;
 403         boolean                 predicate_drawing;
 404
 405         unsigned                num_so_targets;
 406         struct r600_so_target   *so_targets[PIPE_MAX_SO_BUFFERS];
 407         boolean                 streamout_start;
 408         unsigned                streamout_append_bitmask;
 409
 410         /* There is no scissor enable bit on r6xx, so we must use a workaround.
 411          * These track the current scissor state. */
 412         bool                    scissor_enable;
 413         struct pipe_scissor_state scissor_state;
 414
 415         /* With rasterizer discard, there doesn't have to be a pixel shader.
 416          * In that case, we bind this one: */
 417         void                    *dummy_pixel_shader;
 418
 419         boolean                 dual_src_blend;
 420
 421         /* Index buffer. */
 422         struct pipe_index_buffer index_buffer;
 423 };
 424
 425 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
 426 {
 427         atom->emit(rctx, atom);
 428         atom->dirty = false;
 429         if (atom->head.next && atom->head.prev)
 430                 LIST_DELINIT(&atom->head);
 431 }
 432
 433 static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state)
 434 {
 435         if (!state->dirty) {
 436                 if (state->flags & EMIT_EARLY) {
 437                         LIST_ADD(&state->head, &rctx->dirty_states);
 438                 } else {
 439                         LIST_ADDTAIL(&state->head, &rctx->dirty_states);
 440                 }
 441                 state->dirty = true;
 442         }
 443 }
 444
 445 /* evergreen_state.c */
 446 void evergreen_init_state_functions(struct r600_context *rctx);
 447 void evergreen_init_atom_start_cs(struct r600_context *rctx);
 448 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 449 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 450 void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
 451 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
 452 void evergreen_polygon_offset_update(struct r600_context *rctx);
 453 boolean evergreen_is_format_supported(struct pipe_screen *screen,
 454                                       enum pipe_format format,
 455                                       enum pipe_texture_target target,
 456                                       unsigned sample_count,
 457                                       unsigned usage);
 458 void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
 459                          const struct pipe_framebuffer_state *state, int cb);
 460
 461
 462 void evergreen_update_dual_export_state(struct r600_context * rctx);
 463
 464 /* r600_blit.c */
 465 void r600_copy_buffer(struct pipe_context *ctx, struct
 466                       pipe_resource *dst, unsigned dstx,
 467                       struct pipe_resource *src, const struct pipe_box *src_box);
 468 void r600_init_blit_functions(struct r600_context *rctx);
 469 void r600_blit_uncompress_depth(struct pipe_context *ctx,
 470                 struct r600_resource_texture *texture,
 471                 struct r600_resource_texture *staging,
 472                 unsigned first_level, unsigned last_level,
 473                 unsigned first_layer, unsigned last_layer);
 474 void r600_flush_depth_textures(struct r600_context *rctx,
 475                                struct r600_samplerview_state *textures);
 476 /* r600_buffer.c */
 477 bool r600_init_resource(struct r600_screen *rscreen,
 478                         struct r600_resource *res,
 479                         unsigned size, unsigned alignment,
 480                         unsigned bind, unsigned usage);
 481 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 482                                          const struct pipe_resource *templ);
 483
 484 /* r600_pipe.c */
 485 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 486                 unsigned flags);
 487
 488 /* r600_query.c */
 489 void r600_init_query_functions(struct r600_context *rctx);
 490 void r600_suspend_nontimer_queries(struct r600_context *ctx);
 491 void r600_resume_nontimer_queries(struct r600_context *ctx);
 492 void r600_suspend_timer_queries(struct r600_context *ctx);
 493 void r600_resume_timer_queries(struct r600_context *ctx);
 494
 495 /* r600_resource.c */
 496 void r600_init_context_resource_functions(struct r600_context *r600);
 497
 498 /* r600_shader.c */
 499 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 500 #ifdef HAVE_OPENCL
 501 int r600_compute_shader_create(struct pipe_context * ctx,
 502         LLVMModuleRef mod,  struct r600_bytecode * bytecode);
 503 #endif
 504 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 505
 506 /* r600_state.c */
 507 void r600_set_scissor_state(struct r600_context *rctx,
 508                             const struct pipe_scissor_state *state);
 509 void r600_update_sampler_states(struct r600_context *rctx);
 510 void r600_init_state_functions(struct r600_context *rctx);
 511 void r600_init_atom_start_cs(struct r600_context *rctx);
 512 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 513 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 514 void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
 515 void *r600_create_db_flush_dsa(struct r600_context *rctx);
 516 void r600_polygon_offset_update(struct r600_context *rctx);
 517 void r600_adjust_gprs(struct r600_context *rctx);
 518 boolean r600_is_format_supported(struct pipe_screen *screen,
 519                                  enum pipe_format format,
 520                                  enum pipe_texture_target target,
 521                                  unsigned sample_count,
 522                                  unsigned usage);
 523 void r600_update_dual_export_state(struct r600_context * rctx);
 524
 525 /* r600_texture.c */
 526 void r600_init_screen_texture_functions(struct pipe_screen *screen);
 527 void r600_init_surface_functions(struct r600_context *r600);
 528 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
 529                                   const unsigned char *swizzle_view,
 530                                   uint32_t *word4_p, uint32_t *yuv_format_p);
 531 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
 532                                         unsigned level, unsigned layer);
 533
 534 /* r600_translate.c */
 535 void r600_translate_index_buffer(struct r600_context *r600,
 536                                  struct pipe_index_buffer *ib,
 537                                  unsigned count);
 538
 539 /* r600_state_common.c */
 540 void r600_init_atom(struct r600_atom *atom,
 541                     void (*emit)(struct r600_context *ctx, struct r600_atom *state),
 542                     unsigned num_dw, enum r600_atom_flags flags);
 543 void r600_init_common_atoms(struct r600_context *rctx);
 544 unsigned r600_get_cb_flush_flags(struct r600_context *rctx);
 545 void r600_texture_barrier(struct pipe_context *ctx);
 546 void r600_set_index_buffer(struct pipe_context *ctx,
 547                            const struct pipe_index_buffer *ib);
 548 void r600_vertex_buffers_dirty(struct r600_context *rctx);
 549 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 550                              const struct pipe_vertex_buffer *input);
 551 void r600_sampler_views_dirty(struct r600_context *rctx,
 552                               struct r600_samplerview_state *state);
 553 void r600_set_sampler_views(struct r600_context *rctx,
 554                             struct r600_textures_info *dst,
 555                             unsigned count,
 556                             struct pipe_sampler_view **views);
 557 void *r600_create_vertex_elements(struct pipe_context *ctx,
 558                                   unsigned count,
 559                                   const struct pipe_vertex_element *elements);
 560 void r600_delete_vertex_element(struct pipe_context *ctx, void *state);
 561 void r600_bind_blend_state(struct pipe_context *ctx, void *state);
 562 void r600_set_blend_color(struct pipe_context *ctx,
 563                           const struct pipe_blend_color *state);
 564 void r600_bind_dsa_state(struct pipe_context *ctx, void *state);
 565 void r600_set_max_scissor(struct r600_context *rctx);
 566 void r600_bind_rs_state(struct pipe_context *ctx, void *state);
 567 void r600_delete_rs_state(struct pipe_context *ctx, void *state);
 568 void r600_sampler_view_destroy(struct pipe_context *ctx,
 569                                struct pipe_sampler_view *state);
 570 void r600_delete_state(struct pipe_context *ctx, void *state);
 571 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
 572 void *r600_create_shader_state_ps(struct pipe_context *ctx,
 573                    const struct pipe_shader_state *state);
 574 void *r600_create_shader_state_vs(struct pipe_context *ctx,
 575                    const struct pipe_shader_state *state);
 576 void r600_bind_ps_shader(struct pipe_context *ctx, void *state);
 577 void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
 578 void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
 579 void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
 580 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
 581 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 582                               struct pipe_constant_buffer *cb);
 583 struct pipe_stream_output_target *
 584 r600_create_so_target(struct pipe_context *ctx,
 585                       struct pipe_resource *buffer,
 586                       unsigned buffer_offset,
 587                       unsigned buffer_size);
 588 void r600_so_target_destroy(struct pipe_context *ctx,
 589                             struct pipe_stream_output_target *target);
 590 void r600_set_so_targets(struct pipe_context *ctx,
 591                          unsigned num_targets,
 592                          struct pipe_stream_output_target **targets,
 593                          unsigned append_bitmask);
 594 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
 595                                const struct pipe_stencil_ref *state);
 596 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 597 uint32_t r600_translate_stencil_op(int s_op);
 598 uint32_t r600_translate_fill(uint32_t func);
 599 unsigned r600_tex_wrap(unsigned wrap);
 600 unsigned r600_tex_filter(unsigned filter);
 601 unsigned r600_tex_mipfilter(unsigned filter);
 602 unsigned r600_tex_compare(unsigned compare);
 603
 604 /*
 605  * Helpers for building command buffers
 606  */
 607
 608 #define PKT3_SET_CONFIG_REG     0x68
 609 #define PKT3_SET_CONTEXT_REG    0x69
 610 #define PKT3_SET_CTL_CONST      0x6F
 611 #define PKT3_SET_LOOP_CONST                    0x6C
 612
 613 #define R600_CONFIG_REG_OFFSET  0x08000
 614 #define R600_CONTEXT_REG_OFFSET 0x28000
 615 #define R600_CTL_CONST_OFFSET   0x3CFF0
 616 #define R600_LOOP_CONST_OFFSET                 0X0003E200
 617 #define EG_LOOP_CONST_OFFSET               0x0003A200
 618
 619 #define PKT_TYPE_S(x)                   (((x) & 0x3) << 30)
 620 #define PKT_COUNT_S(x)                  (((x) & 0x3FFF) << 16)
 621 #define PKT3_IT_OPCODE_S(x)             (((x) & 0xFF) << 8)
 622 #define PKT3_PREDICATE(x)               (((x) >> 0) & 0x1)
 623 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
 624
 625 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
 626
 627 /*Evergreen Compute packet3*/
 628 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
 629
 630 static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value)
 631 {
 632         cb->buf[cb->atom.num_dw++] = value;
 633 }
 634
 635 static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 636 {
 637         assert(reg < R600_CONTEXT_REG_OFFSET);
 638         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 639         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
 640         cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
 641 }
 642
 643 /**
 644  * Needs cb->pkt_flags set to  RADEON_CP_PACKET3_COMPUTE_MODE for compute
 645  * shaders.
 646  */
 647 static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 648 {
 649         assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
 650         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 651         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
 652         cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
 653 }
 654
 655 /**
 656  * Needs cb->pkt_flags set to  RADEON_CP_PACKET3_COMPUTE_MODE for compute
 657  * shaders.
 658  */
 659 static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 660 {
 661         assert(reg >= R600_CTL_CONST_OFFSET);
 662         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 663         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
 664         cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
 665 }
 666
 667 static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 668 {
 669         assert(reg >= R600_LOOP_CONST_OFFSET);
 670         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 671         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
 672         cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
 673 }
 674
 675 /**
 676  * Needs cb->pkt_flags set to  RADEON_CP_PACKET3_COMPUTE_MODE for compute
 677  * shaders.
 678  */
 679 static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 680 {
 681         assert(reg >= EG_LOOP_CONST_OFFSET);
 682         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 683         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
 684         cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
 685 }
 686
 687 static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 688 {
 689         r600_store_config_reg_seq(cb, reg, 1);
 690         r600_store_value(cb, value);
 691 }
 692
 693 static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 694 {
 695         r600_store_context_reg_seq(cb, reg, 1);
 696         r600_store_value(cb, value);
 697 }
 698
 699 static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 700 {
 701         r600_store_ctl_const_seq(cb, reg, 1);
 702         r600_store_value(cb, value);
 703 }
 704
 705 static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 706 {
 707         r600_store_loop_const_seq(cb, reg, 1);
 708         r600_store_value(cb, value);
 709 }
 710
 711 static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 712 {
 713         eg_store_loop_const_seq(cb, reg, 1);
 714         r600_store_value(cb, value);
 715 }
 716
 717 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags);
 718 void r600_release_command_buffer(struct r600_command_buffer *cb);
 719
 720 /*
 721  * Helpers for emitting state into a command stream directly.
 722  */
 723
 724 static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo,
 725                                              enum radeon_bo_usage usage)
 726 {
 727         assert(usage);
 728         return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4;
 729 }
 730
 731 static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value)
 732 {
 733         cs->buf[cs->cdw++] = value;
 734 }
 735
 736 static INLINE void r600_write_array(struct radeon_winsys_cs *cs, unsigned num, unsigned *ptr)
 737 {
 738         assert(cs->cdw+num <= RADEON_MAX_CMDBUF_DWORDS);
 739         memcpy(&cs->buf[cs->cdw], ptr, num * sizeof(ptr[0]));
 740         cs->cdw += num;
 741 }
 742
 743 static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 744 {
 745         assert(reg < R600_CONTEXT_REG_OFFSET);
 746         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 747         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
 748         cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
 749 }
 750
 751 static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 752 {
 753         assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
 754         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 755         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
 756         cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
 757 }
 758
 759 static INLINE void r600_write_compute_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 760 {
 761         r600_write_context_reg_seq(cs, reg, num);
 762         /* Set the compute bit on the packet header */
 763         cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
 764 }
 765
 766 static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 767 {
 768         assert(reg >= R600_CTL_CONST_OFFSET);
 769         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 770         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
 771         cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
 772 }
 773
 774 static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 775 {
 776         r600_write_config_reg_seq(cs, reg, 1);
 777         r600_write_value(cs, value);
 778 }
 779
 780 static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 781 {
 782         r600_write_context_reg_seq(cs, reg, 1);
 783         r600_write_value(cs, value);
 784 }
 785
 786 static INLINE void r600_write_compute_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 787 {
 788         r600_write_compute_context_reg_seq(cs, reg, 1);
 789         r600_write_value(cs, value);
 790 }
 791
 792 static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 793 {
 794         r600_write_ctl_const_seq(cs, reg, 1);
 795         r600_write_value(cs, value);
 796 }
 797
 798 /*
 799  * common helpers
 800  */
 801 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
 802 {
 803         return value * (1 << frac_bits);
 804 }
 805 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
 806
 807 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 808 {
 809         if (filter <= 1)   return 0;
 810         if (filter <= 2)   return 1;
 811         if (filter <= 4)   return 2;
 812         if (filter <= 8)   return 3;
 813          /* else */        return 4;
 814 }
 815
 816 /* 12.4 fixed-point */
 817 static INLINE unsigned r600_pack_float_12p4(float x)
 818 {
 819         return x <= 0    ? 0 :
 820                x >= 4096 ? 0xffff : x * 16;
 821 }
 822
 823 static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource)
 824 {
 825         struct r600_screen *rscreen = (struct r600_screen*)screen;
 826         struct r600_resource *rresource = (struct r600_resource*)resource;
 827
 828         return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);
 829 }
 830
 831 #endif