src/gallium/drivers/r600/r600_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef R600_PIPE_H
  27 #define R600_PIPE_H
  28
  29 #include "util/u_slab.h"
  30 #include "r600.h"
  31 #include "r600_llvm.h"
  32 #include "r600_public.h"
  33 #include "r600_shader.h"
  34 #include "r600_resource.h"
  35 #include "evergreen_compute.h"
  36
  37 #define R600_MAX_CONST_BUFFERS 2
  38 #define R600_MAX_CONST_BUFFER_SIZE 4096
  39
  40 #ifdef PIPE_ARCH_BIG_ENDIAN
  41 #define R600_BIG_ENDIAN 1
  42 #else
  43 #define R600_BIG_ENDIAN 0
  44 #endif
  45
  46 enum r600_atom_flags {
  47         /* When set, atoms are added at the beginning of the dirty list
  48          * instead of the end. */
  49         EMIT_EARLY = (1 << 0)
  50 };
  51
  52 /* This encapsulates a state or an operation which can emitted into the GPU
  53  * command stream. It's not limited to states only, it can be used for anything
  54  * that wants to write commands into the CS (e.g. cache flushes). */
  55 struct r600_atom {
  56         void (*emit)(struct r600_context *ctx, struct r600_atom *state);
  57
  58         unsigned                num_dw;
  59         enum r600_atom_flags    flags;
  60         bool                    dirty;
  61
  62         struct list_head        head;
  63 };
  64
  65 /* This is an atom containing GPU commands that never change.
  66  * This is supposed to be copied directly into the CS. */
  67 struct r600_command_buffer {
  68         struct r600_atom atom;
  69         uint32_t *buf;
  70         unsigned max_num_dw;
  71         unsigned pkt_flags;
  72 };
  73
  74 struct r600_surface_sync_cmd {
  75         struct r600_atom atom;
  76         unsigned flush_flags; /* CP_COHER_CNTL */
  77 };
  78
  79 struct r600_db_misc_state {
  80         struct r600_atom atom;
  81         bool occlusion_query_enabled;
  82         bool flush_depthstencil_through_cb;
  83 };
  84
  85 struct r600_cb_misc_state {
  86         struct r600_atom atom;
  87         unsigned cb_color_control; /* this comes from blend state */
  88         unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
  89         unsigned nr_cbufs;
  90         unsigned nr_ps_color_outputs;
  91         bool multiwrite;
  92         bool dual_src_blend;
  93 };
  94
  95 struct r600_alphatest_state {
  96         struct r600_atom atom;
  97         unsigned sx_alpha_test_control; /* this comes from dsa state */
  98         unsigned sx_alpha_ref; /* this comes from dsa state */
  99         bool bypass;
 100         bool cb0_export_16bpc; /* from set_framebuffer_state */
 101 };
 102
 103 enum r600_pipe_state_id {
 104         R600_PIPE_STATE_BLEND = 0,
 105         R600_PIPE_STATE_BLEND_COLOR,
 106         R600_PIPE_STATE_CONFIG,
 107         R600_PIPE_STATE_SEAMLESS_CUBEMAP,
 108         R600_PIPE_STATE_CLIP,
 109         R600_PIPE_STATE_SCISSOR,
 110         R600_PIPE_STATE_VIEWPORT,
 111         R600_PIPE_STATE_RASTERIZER,
 112         R600_PIPE_STATE_VGT,
 113         R600_PIPE_STATE_FRAMEBUFFER,
 114         R600_PIPE_STATE_DSA,
 115         R600_PIPE_STATE_STENCIL_REF,
 116         R600_PIPE_STATE_PS_SHADER,
 117         R600_PIPE_STATE_VS_SHADER,
 118         R600_PIPE_STATE_CONSTANT,
 119         R600_PIPE_STATE_SAMPLER,
 120         R600_PIPE_STATE_RESOURCE,
 121         R600_PIPE_STATE_POLYGON_OFFSET,
 122         R600_PIPE_STATE_FETCH_SHADER,
 123         R600_PIPE_STATE_SPI,
 124         R600_PIPE_NSTATES
 125 };
 126
 127 struct compute_memory_pool;
 128 void compute_memory_pool_delete(struct compute_memory_pool* pool);
 129 struct compute_memory_pool* compute_memory_pool_new(
 130         struct r600_screen *rscreen);
 131
 132 struct r600_pipe_fences {
 133         struct r600_resource            *bo;
 134         unsigned                        *data;
 135         unsigned                        next_index;
 136         /* linked list of preallocated blocks */
 137         struct list_head                blocks;
 138         /* linked list of freed fences */
 139         struct list_head                pool;
 140         pipe_mutex                      mutex;
 141 };
 142
 143 struct r600_screen {
 144         struct pipe_screen              screen;
 145         struct radeon_winsys            *ws;
 146         unsigned                        family;
 147         enum chip_class                 chip_class;
 148         struct radeon_info              info;
 149         bool                            has_streamout;
 150         struct r600_tiling_info         tiling_info;
 151         struct r600_pipe_fences         fences;
 152
 153         bool                            use_surface_alloc;
 154
 155         /*for compute global memory binding, we allocate stuff here, instead of
 156          * buffers.
 157          * XXX: Not sure if this is the best place for global_pool.  Also,
 158          * it's not thread safe, so it won't work with multiple contexts. */
 159         struct compute_memory_pool *global_pool;
 160 };
 161
 162 struct r600_pipe_sampler_view {
 163         struct pipe_sampler_view        base;
 164         struct r600_resource            *tex_resource;
 165         uint32_t                        tex_resource_words[8];
 166 };
 167
 168 struct r600_pipe_rasterizer {
 169         struct r600_pipe_state          rstate;
 170         boolean                         flatshade;
 171         boolean                         two_side;
 172         unsigned                        sprite_coord_enable;
 173         unsigned                        clip_plane_enable;
 174         unsigned                        pa_sc_line_stipple;
 175         unsigned                        pa_cl_clip_cntl;
 176         float                           offset_units;
 177         float                           offset_scale;
 178         bool                            scissor_enable;
 179 };
 180
 181 struct r600_pipe_blend {
 182         struct r600_pipe_state          rstate;
 183         unsigned                        cb_target_mask;
 184         unsigned                        cb_color_control;
 185         bool                            dual_src_blend;
 186 };
 187
 188 struct r600_pipe_dsa {
 189         struct r600_pipe_state          rstate;
 190         unsigned                        alpha_ref;
 191         ubyte                           valuemask[2];
 192         ubyte                           writemask[2];
 193         unsigned                        sx_alpha_test_control;
 194 };
 195
 196 struct r600_vertex_element
 197 {
 198         unsigned                        count;
 199         struct pipe_vertex_element      elements[PIPE_MAX_ATTRIBS];
 200         struct r600_resource            *fetch_shader;
 201         unsigned                        fs_size;
 202         struct r600_pipe_state          rstate;
 203 };
 204
 205 struct r600_pipe_shader;
 206
 207 struct r600_pipe_shader_selector {
 208         struct r600_pipe_shader *current;
 209
 210         struct tgsi_token       *tokens;
 211         struct pipe_stream_output_info  so;
 212
 213         unsigned        num_shaders;
 214
 215         /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
 216         unsigned        type;
 217
 218         unsigned        nr_ps_max_color_exports;
 219 };
 220
 221 struct r600_pipe_shader {
 222         struct r600_pipe_shader_selector *selector;
 223         struct r600_pipe_shader *next_variant;
 224         struct r600_shader              shader;
 225         struct r600_pipe_state          rstate;
 226         struct r600_resource            *bo;
 227         struct r600_resource            *bo_fetch;
 228         struct r600_vertex_element      vertex_elements;
 229         unsigned        sprite_coord_enable;
 230         unsigned        flatshade;
 231         unsigned        pa_cl_vs_out_cntl;
 232         unsigned        nr_ps_color_outputs;
 233         unsigned        key;
 234         unsigned                db_shader_control;
 235         unsigned                ps_depth_export;
 236 };
 237
 238 struct r600_pipe_sampler_state {
 239         struct r600_pipe_state          rstate;
 240         boolean seamless_cube_map;
 241 };
 242
 243 /* needed for blitter save */
 244 #define NUM_TEX_UNITS 16
 245
 246 struct r600_samplerview_state
 247 {
 248         struct r600_atom                atom;
 249         struct r600_pipe_sampler_view   *views[NUM_TEX_UNITS];
 250         uint32_t                        enabled_mask;
 251         uint32_t                        dirty_mask;
 252         uint32_t                        depth_texture_mask; /* which textures are depth */
 253 };
 254
 255 struct r600_textures_info {
 256         struct r600_samplerview_state   views;
 257
 258         struct r600_pipe_sampler_state  *samplers[NUM_TEX_UNITS];
 259         unsigned                        n_samplers;
 260         bool                            samplers_dirty;
 261         bool                            is_array_sampler[NUM_TEX_UNITS];
 262 };
 263
 264 struct r600_fence {
 265         struct pipe_reference           reference;
 266         unsigned                        index; /* in the shared bo */
 267         struct r600_resource            *sleep_bo;
 268         struct list_head                head;
 269 };
 270
 271 #define FENCE_BLOCK_SIZE 16
 272
 273 struct r600_fence_block {
 274         struct r600_fence               fences[FENCE_BLOCK_SIZE];
 275         struct list_head                head;
 276 };
 277
 278 #define R600_CONSTANT_ARRAY_SIZE 256
 279 #define R600_RESOURCE_ARRAY_SIZE 160
 280
 281 struct r600_stencil_ref
 282 {
 283         ubyte ref_value[2];
 284         ubyte valuemask[2];
 285         ubyte writemask[2];
 286 };
 287
 288 struct r600_constbuf_state
 289 {
 290         struct r600_atom                atom;
 291         struct pipe_constant_buffer     cb[PIPE_MAX_CONSTANT_BUFFERS];
 292         uint32_t                        enabled_mask;
 293         uint32_t                        dirty_mask;
 294 };
 295
 296 struct r600_vertexbuf_state
 297 {
 298         struct r600_atom                atom;
 299         struct pipe_vertex_buffer       vb[PIPE_MAX_ATTRIBS];
 300         uint32_t                        enabled_mask; /* non-NULL buffers */
 301         uint32_t                        dirty_mask;
 302 };
 303
 304 struct r600_context {
 305         struct pipe_context             context;
 306         struct blitter_context          *blitter;
 307         enum radeon_family              family;
 308         enum chip_class                 chip_class;
 309         boolean                         has_vertex_cache;
 310         unsigned                        r6xx_num_clause_temp_gprs;
 311         void                            *custom_dsa_flush;
 312         struct r600_screen              *screen;
 313         struct radeon_winsys            *ws;
 314         struct r600_pipe_state          *states[R600_PIPE_NSTATES];
 315         struct r600_vertex_element      *vertex_elements;
 316         struct pipe_framebuffer_state   framebuffer;
 317         unsigned                        compute_cb_target_mask;
 318         unsigned                        db_shader_control;
 319         unsigned                        pa_sc_line_stipple;
 320         unsigned                        pa_cl_clip_cntl;
 321         /* for saving when using blitter */
 322         struct pipe_stencil_ref         stencil_ref;
 323         struct pipe_viewport_state      viewport;
 324         struct pipe_clip_state          clip;
 325         struct r600_pipe_shader_selector        *ps_shader;
 326         struct r600_pipe_shader_selector        *vs_shader;
 327         struct r600_pipe_compute        *cs_shader;
 328         struct r600_pipe_rasterizer     *rasterizer;
 329         struct r600_pipe_state          vgt;
 330         struct r600_pipe_state          spi;
 331         struct pipe_query               *current_render_cond;
 332         unsigned                        current_render_cond_mode;
 333         struct pipe_query               *saved_render_cond;
 334         unsigned                        saved_render_cond_mode;
 335         /* shader information */
 336         boolean                         two_side;
 337         boolean                         spi_dirty;
 338         unsigned                        sprite_coord_enable;
 339         boolean                         flatshade;
 340         boolean                         export_16bpc;
 341         unsigned                        nr_cbufs;
 342
 343         struct u_upload_mgr             *uploader;
 344         struct util_slab_mempool        pool_transfers;
 345
 346         unsigned default_ps_gprs, default_vs_gprs;
 347
 348         /* States based on r600_atom. */
 349         struct list_head                dirty_states;
 350         struct r600_command_buffer      start_cs_cmd; /* invariant state mostly */
 351         /** Compute specific registers initializations.  The start_cs_cmd atom
 352          *  must be emitted before start_compute_cs_cmd. */
 353         struct r600_command_buffer      start_compute_cs_cmd;
 354         struct r600_surface_sync_cmd    surface_sync_cmd;
 355         struct r600_atom                r6xx_flush_and_inv_cmd;
 356         struct r600_alphatest_state     alphatest_state;
 357         struct r600_cb_misc_state       cb_misc_state;
 358         struct r600_db_misc_state       db_misc_state;
 359         /** Vertex buffers for fetch shaders */
 360         struct r600_vertexbuf_state     vertex_buffer_state;
 361         /** Vertex buffers for compute shaders */
 362         struct r600_vertexbuf_state     cs_vertex_buffer_state;
 363         struct r600_constbuf_state      vs_constbuf_state;
 364         struct r600_constbuf_state      ps_constbuf_state;
 365         struct r600_textures_info       vs_samplers;
 366         struct r600_textures_info       ps_samplers;
 367
 368         struct radeon_winsys_cs *cs;
 369
 370         struct r600_range       *range;
 371         unsigned                nblocks;
 372         struct r600_block       **blocks;
 373         struct list_head        dirty;
 374         struct list_head        enable_list;
 375         unsigned                pm4_dirty_cdwords;
 376         unsigned                ctx_pm4_ndwords;
 377
 378         /* The list of active queries. Only one query of each type can be active. */
 379         int                     num_occlusion_queries;
 380
 381         /* Manage queries in two separate groups:
 382          * The timer ones and the others (streamout, occlusion).
 383          *
 384          * We do this because we should only suspend non-timer queries for u_blitter,
 385          * and later if the non-timer queries are suspended, the context flush should
 386          * only suspend and resume the timer queries. */
 387         struct list_head        active_timer_queries;
 388         unsigned                num_cs_dw_timer_queries_suspend;
 389         struct list_head        active_nontimer_queries;
 390         unsigned                num_cs_dw_nontimer_queries_suspend;
 391
 392         unsigned                num_cs_dw_streamout_end;
 393
 394         unsigned                backend_mask;
 395         unsigned                max_db; /* for OQ */
 396         unsigned                flags;
 397         boolean                 predicate_drawing;
 398
 399         unsigned                num_so_targets;
 400         struct r600_so_target   *so_targets[PIPE_MAX_SO_BUFFERS];
 401         boolean                 streamout_start;
 402         unsigned                streamout_append_bitmask;
 403
 404         /* There is no scissor enable bit on r6xx, so we must use a workaround.
 405          * These track the current scissor state. */
 406         bool                    scissor_enable;
 407         struct pipe_scissor_state scissor_state;
 408
 409         /* With rasterizer discard, there doesn't have to be a pixel shader.
 410          * In that case, we bind this one: */
 411         void                    *dummy_pixel_shader;
 412
 413         boolean                 dual_src_blend;
 414
 415         /* Index buffer. */
 416         struct pipe_index_buffer index_buffer;
 417 };
 418
 419 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
 420 {
 421         atom->emit(rctx, atom);
 422         atom->dirty = false;
 423         if (atom->head.next && atom->head.prev)
 424                 LIST_DELINIT(&atom->head);
 425 }
 426
 427 static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state)
 428 {
 429         if (!state->dirty) {
 430                 if (state->flags & EMIT_EARLY) {
 431                         LIST_ADD(&state->head, &rctx->dirty_states);
 432                 } else {
 433                         LIST_ADDTAIL(&state->head, &rctx->dirty_states);
 434                 }
 435                 state->dirty = true;
 436         }
 437 }
 438
 439 /* evergreen_state.c */
 440 void evergreen_init_state_functions(struct r600_context *rctx);
 441 void evergreen_init_atom_start_cs(struct r600_context *rctx);
 442 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 443 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 444 void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
 445 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
 446 void evergreen_polygon_offset_update(struct r600_context *rctx);
 447 boolean evergreen_is_format_supported(struct pipe_screen *screen,
 448                                       enum pipe_format format,
 449                                       enum pipe_texture_target target,
 450                                       unsigned sample_count,
 451                                       unsigned usage);
 452 void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
 453                          const struct pipe_framebuffer_state *state, int cb);
 454
 455
 456 void evergreen_update_dual_export_state(struct r600_context * rctx);
 457
 458 /* r600_blit.c */
 459 void r600_init_blit_functions(struct r600_context *rctx);
 460 void r600_blit_uncompress_depth(struct pipe_context *ctx,
 461                 struct r600_resource_texture *texture,
 462                 struct r600_resource_texture *staging,
 463                 unsigned first_level, unsigned last_level,
 464                 unsigned first_layer, unsigned last_layer);
 465 void r600_flush_depth_textures(struct r600_context *rctx,
 466                                struct r600_samplerview_state *textures);
 467 /* r600_buffer.c */
 468 bool r600_init_resource(struct r600_screen *rscreen,
 469                         struct r600_resource *res,
 470                         unsigned size, unsigned alignment,
 471                         unsigned bind, unsigned usage);
 472 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 473                                          const struct pipe_resource *templ);
 474
 475 /* r600_pipe.c */
 476 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 477                 unsigned flags);
 478
 479 /* r600_query.c */
 480 void r600_init_query_functions(struct r600_context *rctx);
 481 void r600_suspend_nontimer_queries(struct r600_context *ctx);
 482 void r600_resume_nontimer_queries(struct r600_context *ctx);
 483 void r600_suspend_timer_queries(struct r600_context *ctx);
 484 void r600_resume_timer_queries(struct r600_context *ctx);
 485
 486 /* r600_resource.c */
 487 void r600_init_context_resource_functions(struct r600_context *r600);
 488
 489 /* r600_shader.c */
 490 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 491 #ifdef HAVE_OPENCL
 492 int r600_compute_shader_create(struct pipe_context * ctx,
 493         LLVMModuleRef mod,  struct r600_bytecode * bytecode);
 494 #endif
 495 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 496
 497 /* r600_state.c */
 498 void r600_set_scissor_state(struct r600_context *rctx,
 499                             const struct pipe_scissor_state *state);
 500 void r600_update_sampler_states(struct r600_context *rctx);
 501 void r600_init_state_functions(struct r600_context *rctx);
 502 void r600_init_atom_start_cs(struct r600_context *rctx);
 503 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 504 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 505 void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
 506 void *r600_create_db_flush_dsa(struct r600_context *rctx);
 507 void r600_polygon_offset_update(struct r600_context *rctx);
 508 void r600_adjust_gprs(struct r600_context *rctx);
 509 boolean r600_is_format_supported(struct pipe_screen *screen,
 510                                  enum pipe_format format,
 511                                  enum pipe_texture_target target,
 512                                  unsigned sample_count,
 513                                  unsigned usage);
 514 void r600_update_dual_export_state(struct r600_context * rctx);
 515
 516 /* r600_texture.c */
 517 void r600_init_screen_texture_functions(struct pipe_screen *screen);
 518 void r600_init_surface_functions(struct r600_context *r600);
 519 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
 520                                   const unsigned char *swizzle_view,
 521                                   uint32_t *word4_p, uint32_t *yuv_format_p);
 522 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
 523                                         unsigned level, unsigned layer);
 524
 525 /* r600_translate.c */
 526 void r600_translate_index_buffer(struct r600_context *r600,
 527                                  struct pipe_index_buffer *ib,
 528                                  unsigned count);
 529
 530 /* r600_state_common.c */
 531 void r600_init_atom(struct r600_atom *atom,
 532                     void (*emit)(struct r600_context *ctx, struct r600_atom *state),
 533                     unsigned num_dw, enum r600_atom_flags flags);
 534 void r600_init_common_atoms(struct r600_context *rctx);
 535 unsigned r600_get_cb_flush_flags(struct r600_context *rctx);
 536 void r600_texture_barrier(struct pipe_context *ctx);
 537 void r600_set_index_buffer(struct pipe_context *ctx,
 538                            const struct pipe_index_buffer *ib);
 539 void r600_vertex_buffers_dirty(struct r600_context *rctx);
 540 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 541                              const struct pipe_vertex_buffer *input);
 542 void r600_sampler_views_dirty(struct r600_context *rctx,
 543                               struct r600_samplerview_state *state);
 544 void r600_set_sampler_views(struct r600_context *rctx,
 545                             struct r600_textures_info *dst,
 546                             unsigned count,
 547                             struct pipe_sampler_view **views);
 548 void *r600_create_vertex_elements(struct pipe_context *ctx,
 549                                   unsigned count,
 550                                   const struct pipe_vertex_element *elements);
 551 void r600_delete_vertex_element(struct pipe_context *ctx, void *state);
 552 void r600_bind_blend_state(struct pipe_context *ctx, void *state);
 553 void r600_set_blend_color(struct pipe_context *ctx,
 554                           const struct pipe_blend_color *state);
 555 void r600_bind_dsa_state(struct pipe_context *ctx, void *state);
 556 void r600_set_max_scissor(struct r600_context *rctx);
 557 void r600_bind_rs_state(struct pipe_context *ctx, void *state);
 558 void r600_delete_rs_state(struct pipe_context *ctx, void *state);
 559 void r600_sampler_view_destroy(struct pipe_context *ctx,
 560                                struct pipe_sampler_view *state);
 561 void r600_delete_state(struct pipe_context *ctx, void *state);
 562 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
 563 void *r600_create_shader_state_ps(struct pipe_context *ctx,
 564                    const struct pipe_shader_state *state);
 565 void *r600_create_shader_state_vs(struct pipe_context *ctx,
 566                    const struct pipe_shader_state *state);
 567 void r600_bind_ps_shader(struct pipe_context *ctx, void *state);
 568 void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
 569 void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
 570 void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
 571 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
 572 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 573                               struct pipe_constant_buffer *cb);
 574 struct pipe_stream_output_target *
 575 r600_create_so_target(struct pipe_context *ctx,
 576                       struct pipe_resource *buffer,
 577                       unsigned buffer_offset,
 578                       unsigned buffer_size);
 579 void r600_so_target_destroy(struct pipe_context *ctx,
 580                             struct pipe_stream_output_target *target);
 581 void r600_set_so_targets(struct pipe_context *ctx,
 582                          unsigned num_targets,
 583                          struct pipe_stream_output_target **targets,
 584                          unsigned append_bitmask);
 585 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
 586                                const struct pipe_stencil_ref *state);
 587 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 588 uint32_t r600_translate_stencil_op(int s_op);
 589 uint32_t r600_translate_fill(uint32_t func);
 590 unsigned r600_tex_wrap(unsigned wrap);
 591 unsigned r600_tex_filter(unsigned filter);
 592 unsigned r600_tex_mipfilter(unsigned filter);
 593 unsigned r600_tex_compare(unsigned compare);
 594
 595 /*
 596  * Helpers for building command buffers
 597  */
 598
 599 #define PKT3_SET_CONFIG_REG     0x68
 600 #define PKT3_SET_CONTEXT_REG    0x69
 601 #define PKT3_SET_CTL_CONST      0x6F
 602 #define PKT3_SET_LOOP_CONST                    0x6C
 603
 604 #define R600_CONFIG_REG_OFFSET  0x08000
 605 #define R600_CONTEXT_REG_OFFSET 0x28000
 606 #define R600_CTL_CONST_OFFSET   0x3CFF0
 607 #define R600_LOOP_CONST_OFFSET                 0X0003E200
 608 #define EG_LOOP_CONST_OFFSET               0x0003A200
 609
 610 #define PKT_TYPE_S(x)                   (((x) & 0x3) << 30)
 611 #define PKT_COUNT_S(x)                  (((x) & 0x3FFF) << 16)
 612 #define PKT3_IT_OPCODE_S(x)             (((x) & 0xFF) << 8)
 613 #define PKT3_PREDICATE(x)               (((x) >> 0) & 0x1)
 614 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
 615
 616 static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value)
 617 {
 618         cb->buf[cb->atom.num_dw++] = value;
 619 }
 620
 621 static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 622 {
 623         assert(reg < R600_CONTEXT_REG_OFFSET);
 624         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 625         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
 626         cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
 627 }
 628
 629 /**
 630  * Needs cb->pkt_flags set to  RADEON_CP_PACKET3_COMPUTE_MODE for compute
 631  * shaders.
 632  */
 633 static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 634 {
 635         assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
 636         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 637         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
 638         cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
 639 }
 640
 641 /**
 642  * Needs cb->pkt_flags set to  RADEON_CP_PACKET3_COMPUTE_MODE for compute
 643  * shaders.
 644  */
 645 static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 646 {
 647         assert(reg >= R600_CTL_CONST_OFFSET);
 648         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 649         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
 650         cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
 651 }
 652
 653 static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 654 {
 655         assert(reg >= R600_LOOP_CONST_OFFSET);
 656         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 657         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
 658         cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
 659 }
 660
 661 /**
 662  * Needs cb->pkt_flags set to  RADEON_CP_PACKET3_COMPUTE_MODE for compute
 663  * shaders.
 664  */
 665 static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 666 {
 667         assert(reg >= EG_LOOP_CONST_OFFSET);
 668         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 669         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
 670         cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
 671 }
 672
 673 static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 674 {
 675         r600_store_config_reg_seq(cb, reg, 1);
 676         r600_store_value(cb, value);
 677 }
 678
 679 static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 680 {
 681         r600_store_context_reg_seq(cb, reg, 1);
 682         r600_store_value(cb, value);
 683 }
 684
 685 static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 686 {
 687         r600_store_ctl_const_seq(cb, reg, 1);
 688         r600_store_value(cb, value);
 689 }
 690
 691 static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 692 {
 693         r600_store_loop_const_seq(cb, reg, 1);
 694         r600_store_value(cb, value);
 695 }
 696
 697 static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 698 {
 699         eg_store_loop_const_seq(cb, reg, 1);
 700         r600_store_value(cb, value);
 701 }
 702
 703 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags);
 704 void r600_release_command_buffer(struct r600_command_buffer *cb);
 705
 706 /*
 707  * Helpers for emitting state into a command stream directly.
 708  */
 709
 710 static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo,
 711                                              enum radeon_bo_usage usage)
 712 {
 713         assert(usage);
 714         return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4;
 715 }
 716
 717 static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value)
 718 {
 719         cs->buf[cs->cdw++] = value;
 720 }
 721
 722 static INLINE void r600_write_array(struct radeon_winsys_cs *cs, unsigned num, unsigned *ptr)
 723 {
 724         assert(cs->cdw+num <= RADEON_MAX_CMDBUF_DWORDS);
 725         memcpy(&cs->buf[cs->cdw], ptr, num * sizeof(ptr[0]));
 726         cs->cdw += num;
 727 }
 728
 729 static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 730 {
 731         assert(reg < R600_CONTEXT_REG_OFFSET);
 732         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 733         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
 734         cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
 735 }
 736
 737 static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 738 {
 739         assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
 740         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 741         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
 742         cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
 743 }
 744
 745 static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 746 {
 747         assert(reg >= R600_CTL_CONST_OFFSET);
 748         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 749         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
 750         cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
 751 }
 752
 753 static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 754 {
 755         r600_write_config_reg_seq(cs, reg, 1);
 756         r600_write_value(cs, value);
 757 }
 758
 759 static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 760 {
 761         r600_write_context_reg_seq(cs, reg, 1);
 762         r600_write_value(cs, value);
 763 }
 764
 765 static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 766 {
 767         r600_write_ctl_const_seq(cs, reg, 1);
 768         r600_write_value(cs, value);
 769 }
 770
 771 /*
 772  * common helpers
 773  */
 774 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
 775 {
 776         return value * (1 << frac_bits);
 777 }
 778 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
 779
 780 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 781 {
 782         if (filter <= 1)   return 0;
 783         if (filter <= 2)   return 1;
 784         if (filter <= 4)   return 2;
 785         if (filter <= 8)   return 3;
 786          /* else */        return 4;
 787 }
 788
 789 /* 12.4 fixed-point */
 790 static INLINE unsigned r600_pack_float_12p4(float x)
 791 {
 792         return x <= 0    ? 0 :
 793                x >= 4096 ? 0xffff : x * 16;
 794 }
 795
 796 static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource)
 797 {
 798         struct r600_screen *rscreen = (struct r600_screen*)screen;
 799         struct r600_resource *rresource = (struct r600_resource*)resource;
 800
 801         return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);
 802 }
 803
 804 #endif