src/gallium/drivers/r600/r600_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef R600_PIPE_H
  27 #define R600_PIPE_H
  28
  29 #include "util/u_slab.h"
  30 #include "r600.h"
  31 #include "r600_llvm.h"
  32 #include "r600_public.h"
  33 #include "r600_shader.h"
  34 #include "r600_resource.h"
  35 #include "evergreen_compute.h"
  36
  37 #define R600_MAX_CONST_BUFFERS 2
  38 #define R600_MAX_CONST_BUFFER_SIZE 4096
  39
  40 #ifdef PIPE_ARCH_BIG_ENDIAN
  41 #define R600_BIG_ENDIAN 1
  42 #else
  43 #define R600_BIG_ENDIAN 0
  44 #endif
  45
  46 enum r600_atom_flags {
  47         /* When set, atoms are added at the beginning of the dirty list
  48          * instead of the end. */
  49         EMIT_EARLY = (1 << 0)
  50 };
  51
  52 /* This encapsulates a state or an operation which can emitted into the GPU
  53  * command stream. It's not limited to states only, it can be used for anything
  54  * that wants to write commands into the CS (e.g. cache flushes). */
  55 struct r600_atom {
  56         void (*emit)(struct r600_context *ctx, struct r600_atom *state);
  57
  58         unsigned                num_dw;
  59         enum r600_atom_flags    flags;
  60         bool                    dirty;
  61
  62         struct list_head        head;
  63 };
  64
  65 /* This is an atom containing GPU commands that never change.
  66  * This is supposed to be copied directly into the CS. */
  67 struct r600_command_buffer {
  68         struct r600_atom atom;
  69         uint32_t *buf;
  70         unsigned max_num_dw;
  71         unsigned pkt_flags;
  72 };
  73
  74 struct r600_surface_sync_cmd {
  75         struct r600_atom atom;
  76         unsigned flush_flags; /* CP_COHER_CNTL */
  77 };
  78
  79 struct r600_db_misc_state {
  80         struct r600_atom atom;
  81         bool occlusion_query_enabled;
  82         bool flush_depthstencil_through_cb;
  83 };
  84
  85 struct r600_cb_misc_state {
  86         struct r600_atom atom;
  87         unsigned cb_color_control; /* this comes from blend state */
  88         unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
  89         unsigned nr_cbufs;
  90         unsigned nr_ps_color_outputs;
  91         bool multiwrite;
  92         bool dual_src_blend;
  93 };
  94
  95 struct r600_alphatest_state {
  96         struct r600_atom atom;
  97         unsigned sx_alpha_test_control; /* this comes from dsa state */
  98         unsigned sx_alpha_ref; /* this comes from dsa state */
  99         bool bypass;
 100         bool cb0_export_16bpc; /* from set_framebuffer_state */
 101 };
 102
 103 struct r600_cs_shader_state {
 104         struct r600_atom atom;
 105         struct r600_pipe_compute *shader;
 106 };
 107
 108 enum r600_pipe_state_id {
 109         R600_PIPE_STATE_BLEND = 0,
 110         R600_PIPE_STATE_BLEND_COLOR,
 111         R600_PIPE_STATE_CONFIG,
 112         R600_PIPE_STATE_SEAMLESS_CUBEMAP,
 113         R600_PIPE_STATE_CLIP,
 114         R600_PIPE_STATE_SCISSOR,
 115         R600_PIPE_STATE_VIEWPORT,
 116         R600_PIPE_STATE_RASTERIZER,
 117         R600_PIPE_STATE_VGT,
 118         R600_PIPE_STATE_FRAMEBUFFER,
 119         R600_PIPE_STATE_DSA,
 120         R600_PIPE_STATE_STENCIL_REF,
 121         R600_PIPE_STATE_PS_SHADER,
 122         R600_PIPE_STATE_VS_SHADER,
 123         R600_PIPE_STATE_CONSTANT,
 124         R600_PIPE_STATE_SAMPLER,
 125         R600_PIPE_STATE_RESOURCE,
 126         R600_PIPE_STATE_POLYGON_OFFSET,
 127         R600_PIPE_STATE_FETCH_SHADER,
 128         R600_PIPE_STATE_SPI,
 129         R600_PIPE_NSTATES
 130 };
 131
 132 struct compute_memory_pool;
 133 void compute_memory_pool_delete(struct compute_memory_pool* pool);
 134 struct compute_memory_pool* compute_memory_pool_new(
 135         struct r600_screen *rscreen);
 136
 137 struct r600_pipe_fences {
 138         struct r600_resource            *bo;
 139         unsigned                        *data;
 140         unsigned                        next_index;
 141         /* linked list of preallocated blocks */
 142         struct list_head                blocks;
 143         /* linked list of freed fences */
 144         struct list_head                pool;
 145         pipe_mutex                      mutex;
 146 };
 147
 148 struct r600_screen {
 149         struct pipe_screen              screen;
 150         struct radeon_winsys            *ws;
 151         unsigned                        family;
 152         enum chip_class                 chip_class;
 153         struct radeon_info              info;
 154         bool                            has_streamout;
 155         struct r600_tiling_info         tiling_info;
 156         struct r600_pipe_fences         fences;
 157
 158         bool                            use_surface_alloc;
 159
 160         /*for compute global memory binding, we allocate stuff here, instead of
 161          * buffers.
 162          * XXX: Not sure if this is the best place for global_pool.  Also,
 163          * it's not thread safe, so it won't work with multiple contexts. */
 164         struct compute_memory_pool *global_pool;
 165 };
 166
 167 struct r600_pipe_sampler_view {
 168         struct pipe_sampler_view        base;
 169         struct r600_resource            *tex_resource;
 170         uint32_t                        tex_resource_words[8];
 171 };
 172
 173 struct r600_pipe_rasterizer {
 174         struct r600_pipe_state          rstate;
 175         boolean                         flatshade;
 176         boolean                         two_side;
 177         unsigned                        sprite_coord_enable;
 178         unsigned                        clip_plane_enable;
 179         unsigned                        pa_sc_line_stipple;
 180         unsigned                        pa_cl_clip_cntl;
 181         float                           offset_units;
 182         float                           offset_scale;
 183         bool                            scissor_enable;
 184 };
 185
 186 struct r600_pipe_blend {
 187         struct r600_pipe_state          rstate;
 188         unsigned                        cb_target_mask;
 189         unsigned                        cb_color_control;
 190         bool                            dual_src_blend;
 191 };
 192
 193 struct r600_pipe_dsa {
 194         struct r600_pipe_state          rstate;
 195         unsigned                        alpha_ref;
 196         ubyte                           valuemask[2];
 197         ubyte                           writemask[2];
 198         unsigned                        sx_alpha_test_control;
 199 };
 200
 201 struct r600_vertex_element
 202 {
 203         unsigned                        count;
 204         struct pipe_vertex_element      elements[PIPE_MAX_ATTRIBS];
 205         struct r600_resource            *fetch_shader;
 206         unsigned                        fs_size;
 207         struct r600_pipe_state          rstate;
 208 };
 209
 210 struct r600_pipe_shader;
 211
 212 struct r600_pipe_shader_selector {
 213         struct r600_pipe_shader *current;
 214
 215         struct tgsi_token       *tokens;
 216         struct pipe_stream_output_info  so;
 217
 218         unsigned        num_shaders;
 219
 220         /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
 221         unsigned        type;
 222
 223         unsigned        nr_ps_max_color_exports;
 224 };
 225
 226 struct r600_pipe_shader {
 227         struct r600_pipe_shader_selector *selector;
 228         struct r600_pipe_shader *next_variant;
 229         struct r600_shader              shader;
 230         struct r600_pipe_state          rstate;
 231         struct r600_resource            *bo;
 232         struct r600_resource            *bo_fetch;
 233         struct r600_vertex_element      vertex_elements;
 234         unsigned        sprite_coord_enable;
 235         unsigned        flatshade;
 236         unsigned        pa_cl_vs_out_cntl;
 237         unsigned        nr_ps_color_outputs;
 238         unsigned        key;
 239         unsigned                db_shader_control;
 240         unsigned                ps_depth_export;
 241 };
 242
 243 struct r600_pipe_sampler_state {
 244         struct r600_pipe_state          rstate;
 245         boolean seamless_cube_map;
 246 };
 247
 248 /* needed for blitter save */
 249 #define NUM_TEX_UNITS 16
 250
 251 struct r600_samplerview_state
 252 {
 253         struct r600_atom                atom;
 254         struct r600_pipe_sampler_view   *views[NUM_TEX_UNITS];
 255         uint32_t                        enabled_mask;
 256         uint32_t                        dirty_mask;
 257         uint32_t                        depth_texture_mask; /* which textures are depth */
 258 };
 259
 260 struct r600_textures_info {
 261         struct r600_samplerview_state   views;
 262
 263         struct r600_pipe_sampler_state  *samplers[NUM_TEX_UNITS];
 264         unsigned                        n_samplers;
 265         bool                            samplers_dirty;
 266         bool                            is_array_sampler[NUM_TEX_UNITS];
 267 };
 268
 269 struct r600_fence {
 270         struct pipe_reference           reference;
 271         unsigned                        index; /* in the shared bo */
 272         struct r600_resource            *sleep_bo;
 273         struct list_head                head;
 274 };
 275
 276 #define FENCE_BLOCK_SIZE 16
 277
 278 struct r600_fence_block {
 279         struct r600_fence               fences[FENCE_BLOCK_SIZE];
 280         struct list_head                head;
 281 };
 282
 283 #define R600_CONSTANT_ARRAY_SIZE 256
 284 #define R600_RESOURCE_ARRAY_SIZE 160
 285
 286 struct r600_stencil_ref
 287 {
 288         ubyte ref_value[2];
 289         ubyte valuemask[2];
 290         ubyte writemask[2];
 291 };
 292
 293 struct r600_constbuf_state
 294 {
 295         struct r600_atom                atom;
 296         struct pipe_constant_buffer     cb[PIPE_MAX_CONSTANT_BUFFERS];
 297         uint32_t                        enabled_mask;
 298         uint32_t                        dirty_mask;
 299 };
 300
 301 struct r600_vertexbuf_state
 302 {
 303         struct r600_atom                atom;
 304         struct pipe_vertex_buffer       vb[PIPE_MAX_ATTRIBS];
 305         uint32_t                        enabled_mask; /* non-NULL buffers */
 306         uint32_t                        dirty_mask;
 307 };
 308
 309 struct r600_context {
 310         struct pipe_context             context;
 311         struct blitter_context          *blitter;
 312         enum radeon_family              family;
 313         enum chip_class                 chip_class;
 314         boolean                         has_vertex_cache;
 315         unsigned                        r6xx_num_clause_temp_gprs;
 316         void                            *custom_dsa_flush;
 317         struct r600_screen              *screen;
 318         struct radeon_winsys            *ws;
 319         struct r600_pipe_state          *states[R600_PIPE_NSTATES];
 320         struct r600_vertex_element      *vertex_elements;
 321         struct pipe_framebuffer_state   framebuffer;
 322         unsigned                        compute_cb_target_mask;
 323         unsigned                        db_shader_control;
 324         unsigned                        pa_sc_line_stipple;
 325         unsigned                        pa_cl_clip_cntl;
 326         /* for saving when using blitter */
 327         struct pipe_stencil_ref         stencil_ref;
 328         struct pipe_viewport_state      viewport;
 329         struct pipe_clip_state          clip;
 330         struct r600_pipe_shader_selector        *ps_shader;
 331         struct r600_pipe_shader_selector        *vs_shader;
 332         struct r600_pipe_rasterizer     *rasterizer;
 333         struct r600_pipe_state          vgt;
 334         struct r600_pipe_state          spi;
 335         struct pipe_query               *current_render_cond;
 336         unsigned                        current_render_cond_mode;
 337         struct pipe_query               *saved_render_cond;
 338         unsigned                        saved_render_cond_mode;
 339         /* shader information */
 340         boolean                         two_side;
 341         boolean                         spi_dirty;
 342         unsigned                        sprite_coord_enable;
 343         boolean                         flatshade;
 344         boolean                         export_16bpc;
 345         unsigned                        nr_cbufs;
 346
 347         struct u_upload_mgr             *uploader;
 348         struct util_slab_mempool        pool_transfers;
 349
 350         unsigned default_ps_gprs, default_vs_gprs;
 351
 352         /* States based on r600_atom. */
 353         struct list_head                dirty_states;
 354         struct r600_command_buffer      start_cs_cmd; /* invariant state mostly */
 355         /** Compute specific registers initializations.  The start_cs_cmd atom
 356          *  must be emitted before start_compute_cs_cmd. */
 357         struct r600_command_buffer      start_compute_cs_cmd;
 358         struct r600_surface_sync_cmd    surface_sync_cmd;
 359         struct r600_atom                r6xx_flush_and_inv_cmd;
 360         struct r600_alphatest_state     alphatest_state;
 361         struct r600_cb_misc_state       cb_misc_state;
 362         struct r600_db_misc_state       db_misc_state;
 363         /** Vertex buffers for fetch shaders */
 364         struct r600_vertexbuf_state     vertex_buffer_state;
 365         /** Vertex buffers for compute shaders */
 366         struct r600_vertexbuf_state     cs_vertex_buffer_state;
 367         struct r600_constbuf_state      vs_constbuf_state;
 368         struct r600_constbuf_state      ps_constbuf_state;
 369         struct r600_textures_info       vs_samplers;
 370         struct r600_textures_info       ps_samplers;
 371         struct r600_cs_shader_state     cs_shader_state;
 372
 373         struct radeon_winsys_cs *cs;
 374
 375         struct r600_range       *range;
 376         unsigned                nblocks;
 377         struct r600_block       **blocks;
 378         struct list_head        dirty;
 379         struct list_head        enable_list;
 380         unsigned                pm4_dirty_cdwords;
 381         unsigned                ctx_pm4_ndwords;
 382
 383         /* The list of active queries. Only one query of each type can be active. */
 384         int                     num_occlusion_queries;
 385
 386         /* Manage queries in two separate groups:
 387          * The timer ones and the others (streamout, occlusion).
 388          *
 389          * We do this because we should only suspend non-timer queries for u_blitter,
 390          * and later if the non-timer queries are suspended, the context flush should
 391          * only suspend and resume the timer queries. */
 392         struct list_head        active_timer_queries;
 393         unsigned                num_cs_dw_timer_queries_suspend;
 394         struct list_head        active_nontimer_queries;
 395         unsigned                num_cs_dw_nontimer_queries_suspend;
 396
 397         unsigned                num_cs_dw_streamout_end;
 398
 399         unsigned                backend_mask;
 400         unsigned                max_db; /* for OQ */
 401         unsigned                flags;
 402         boolean                 predicate_drawing;
 403
 404         unsigned                num_so_targets;
 405         struct r600_so_target   *so_targets[PIPE_MAX_SO_BUFFERS];
 406         boolean                 streamout_start;
 407         unsigned                streamout_append_bitmask;
 408
 409         /* There is no scissor enable bit on r6xx, so we must use a workaround.
 410          * These track the current scissor state. */
 411         bool                    scissor_enable;
 412         struct pipe_scissor_state scissor_state;
 413
 414         /* With rasterizer discard, there doesn't have to be a pixel shader.
 415          * In that case, we bind this one: */
 416         void                    *dummy_pixel_shader;
 417
 418         boolean                 dual_src_blend;
 419
 420         /* Index buffer. */
 421         struct pipe_index_buffer index_buffer;
 422 };
 423
 424 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
 425 {
 426         atom->emit(rctx, atom);
 427         atom->dirty = false;
 428         if (atom->head.next && atom->head.prev)
 429                 LIST_DELINIT(&atom->head);
 430 }
 431
 432 static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state)
 433 {
 434         if (!state->dirty) {
 435                 if (state->flags & EMIT_EARLY) {
 436                         LIST_ADD(&state->head, &rctx->dirty_states);
 437                 } else {
 438                         LIST_ADDTAIL(&state->head, &rctx->dirty_states);
 439                 }
 440                 state->dirty = true;
 441         }
 442 }
 443
 444 /* evergreen_state.c */
 445 void evergreen_init_state_functions(struct r600_context *rctx);
 446 void evergreen_init_atom_start_cs(struct r600_context *rctx);
 447 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 448 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 449 void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
 450 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
 451 void evergreen_polygon_offset_update(struct r600_context *rctx);
 452 boolean evergreen_is_format_supported(struct pipe_screen *screen,
 453                                       enum pipe_format format,
 454                                       enum pipe_texture_target target,
 455                                       unsigned sample_count,
 456                                       unsigned usage);
 457 void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
 458                          const struct pipe_framebuffer_state *state, int cb);
 459
 460
 461 void evergreen_update_dual_export_state(struct r600_context * rctx);
 462
 463 /* r600_blit.c */
 464 void r600_copy_buffer(struct pipe_context *ctx, struct
 465                       pipe_resource *dst, unsigned dstx,
 466                       struct pipe_resource *src, const struct pipe_box *src_box);
 467 void r600_init_blit_functions(struct r600_context *rctx);
 468 void r600_blit_uncompress_depth(struct pipe_context *ctx,
 469                 struct r600_resource_texture *texture,
 470                 struct r600_resource_texture *staging,
 471                 unsigned first_level, unsigned last_level,
 472                 unsigned first_layer, unsigned last_layer);
 473 void r600_flush_depth_textures(struct r600_context *rctx,
 474                                struct r600_samplerview_state *textures);
 475 /* r600_buffer.c */
 476 bool r600_init_resource(struct r600_screen *rscreen,
 477                         struct r600_resource *res,
 478                         unsigned size, unsigned alignment,
 479                         unsigned bind, unsigned usage);
 480 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 481                                          const struct pipe_resource *templ);
 482
 483 /* r600_pipe.c */
 484 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 485                 unsigned flags);
 486
 487 /* r600_query.c */
 488 void r600_init_query_functions(struct r600_context *rctx);
 489 void r600_suspend_nontimer_queries(struct r600_context *ctx);
 490 void r600_resume_nontimer_queries(struct r600_context *ctx);
 491 void r600_suspend_timer_queries(struct r600_context *ctx);
 492 void r600_resume_timer_queries(struct r600_context *ctx);
 493
 494 /* r600_resource.c */
 495 void r600_init_context_resource_functions(struct r600_context *r600);
 496
 497 /* r600_shader.c */
 498 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 499 #ifdef HAVE_OPENCL
 500 int r600_compute_shader_create(struct pipe_context * ctx,
 501         LLVMModuleRef mod,  struct r600_bytecode * bytecode);
 502 #endif
 503 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 504
 505 /* r600_state.c */
 506 void r600_set_scissor_state(struct r600_context *rctx,
 507                             const struct pipe_scissor_state *state);
 508 void r600_update_sampler_states(struct r600_context *rctx);
 509 void r600_init_state_functions(struct r600_context *rctx);
 510 void r600_init_atom_start_cs(struct r600_context *rctx);
 511 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 512 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 513 void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
 514 void *r600_create_db_flush_dsa(struct r600_context *rctx);
 515 void r600_polygon_offset_update(struct r600_context *rctx);
 516 void r600_adjust_gprs(struct r600_context *rctx);
 517 boolean r600_is_format_supported(struct pipe_screen *screen,
 518                                  enum pipe_format format,
 519                                  enum pipe_texture_target target,
 520                                  unsigned sample_count,
 521                                  unsigned usage);
 522 void r600_update_dual_export_state(struct r600_context * rctx);
 523
 524 /* r600_texture.c */
 525 void r600_init_screen_texture_functions(struct pipe_screen *screen);
 526 void r600_init_surface_functions(struct r600_context *r600);
 527 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
 528                                   const unsigned char *swizzle_view,
 529                                   uint32_t *word4_p, uint32_t *yuv_format_p);
 530 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
 531                                         unsigned level, unsigned layer);
 532
 533 /* r600_translate.c */
 534 void r600_translate_index_buffer(struct r600_context *r600,
 535                                  struct pipe_index_buffer *ib,
 536                                  unsigned count);
 537
 538 /* r600_state_common.c */
 539 void r600_init_atom(struct r600_atom *atom,
 540                     void (*emit)(struct r600_context *ctx, struct r600_atom *state),
 541                     unsigned num_dw, enum r600_atom_flags flags);
 542 void r600_init_common_atoms(struct r600_context *rctx);
 543 unsigned r600_get_cb_flush_flags(struct r600_context *rctx);
 544 void r600_texture_barrier(struct pipe_context *ctx);
 545 void r600_set_index_buffer(struct pipe_context *ctx,
 546                            const struct pipe_index_buffer *ib);
 547 void r600_vertex_buffers_dirty(struct r600_context *rctx);
 548 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 549                              const struct pipe_vertex_buffer *input);
 550 void r600_sampler_views_dirty(struct r600_context *rctx,
 551                               struct r600_samplerview_state *state);
 552 void r600_set_sampler_views(struct r600_context *rctx,
 553                             struct r600_textures_info *dst,
 554                             unsigned count,
 555                             struct pipe_sampler_view **views);
 556 void *r600_create_vertex_elements(struct pipe_context *ctx,
 557                                   unsigned count,
 558                                   const struct pipe_vertex_element *elements);
 559 void r600_delete_vertex_element(struct pipe_context *ctx, void *state);
 560 void r600_bind_blend_state(struct pipe_context *ctx, void *state);
 561 void r600_set_blend_color(struct pipe_context *ctx,
 562                           const struct pipe_blend_color *state);
 563 void r600_bind_dsa_state(struct pipe_context *ctx, void *state);
 564 void r600_set_max_scissor(struct r600_context *rctx);
 565 void r600_bind_rs_state(struct pipe_context *ctx, void *state);
 566 void r600_delete_rs_state(struct pipe_context *ctx, void *state);
 567 void r600_sampler_view_destroy(struct pipe_context *ctx,
 568                                struct pipe_sampler_view *state);
 569 void r600_delete_state(struct pipe_context *ctx, void *state);
 570 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
 571 void *r600_create_shader_state_ps(struct pipe_context *ctx,
 572                    const struct pipe_shader_state *state);
 573 void *r600_create_shader_state_vs(struct pipe_context *ctx,
 574                    const struct pipe_shader_state *state);
 575 void r600_bind_ps_shader(struct pipe_context *ctx, void *state);
 576 void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
 577 void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
 578 void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
 579 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
 580 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 581                               struct pipe_constant_buffer *cb);
 582 struct pipe_stream_output_target *
 583 r600_create_so_target(struct pipe_context *ctx,
 584                       struct pipe_resource *buffer,
 585                       unsigned buffer_offset,
 586                       unsigned buffer_size);
 587 void r600_so_target_destroy(struct pipe_context *ctx,
 588                             struct pipe_stream_output_target *target);
 589 void r600_set_so_targets(struct pipe_context *ctx,
 590                          unsigned num_targets,
 591                          struct pipe_stream_output_target **targets,
 592                          unsigned append_bitmask);
 593 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
 594                                const struct pipe_stencil_ref *state);
 595 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 596 uint32_t r600_translate_stencil_op(int s_op);
 597 uint32_t r600_translate_fill(uint32_t func);
 598 unsigned r600_tex_wrap(unsigned wrap);
 599 unsigned r600_tex_filter(unsigned filter);
 600 unsigned r600_tex_mipfilter(unsigned filter);
 601 unsigned r600_tex_compare(unsigned compare);
 602
 603 /*
 604  * Helpers for building command buffers
 605  */
 606
 607 #define PKT3_SET_CONFIG_REG     0x68
 608 #define PKT3_SET_CONTEXT_REG    0x69
 609 #define PKT3_SET_CTL_CONST      0x6F
 610 #define PKT3_SET_LOOP_CONST                    0x6C
 611
 612 #define R600_CONFIG_REG_OFFSET  0x08000
 613 #define R600_CONTEXT_REG_OFFSET 0x28000
 614 #define R600_CTL_CONST_OFFSET   0x3CFF0
 615 #define R600_LOOP_CONST_OFFSET                 0X0003E200
 616 #define EG_LOOP_CONST_OFFSET               0x0003A200
 617
 618 #define PKT_TYPE_S(x)                   (((x) & 0x3) << 30)
 619 #define PKT_COUNT_S(x)                  (((x) & 0x3FFF) << 16)
 620 #define PKT3_IT_OPCODE_S(x)             (((x) & 0xFF) << 8)
 621 #define PKT3_PREDICATE(x)               (((x) >> 0) & 0x1)
 622 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
 623
 624 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
 625
 626 /*Evergreen Compute packet3*/
 627 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
 628
 629 static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value)
 630 {
 631         cb->buf[cb->atom.num_dw++] = value;
 632 }
 633
 634 static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 635 {
 636         assert(reg < R600_CONTEXT_REG_OFFSET);
 637         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 638         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
 639         cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
 640 }
 641
 642 /**
 643  * Needs cb->pkt_flags set to  RADEON_CP_PACKET3_COMPUTE_MODE for compute
 644  * shaders.
 645  */
 646 static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 647 {
 648         assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
 649         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 650         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
 651         cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
 652 }
 653
 654 /**
 655  * Needs cb->pkt_flags set to  RADEON_CP_PACKET3_COMPUTE_MODE for compute
 656  * shaders.
 657  */
 658 static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 659 {
 660         assert(reg >= R600_CTL_CONST_OFFSET);
 661         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 662         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
 663         cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
 664 }
 665
 666 static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 667 {
 668         assert(reg >= R600_LOOP_CONST_OFFSET);
 669         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 670         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
 671         cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
 672 }
 673
 674 /**
 675  * Needs cb->pkt_flags set to  RADEON_CP_PACKET3_COMPUTE_MODE for compute
 676  * shaders.
 677  */
 678 static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 679 {
 680         assert(reg >= EG_LOOP_CONST_OFFSET);
 681         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 682         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
 683         cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
 684 }
 685
 686 static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 687 {
 688         r600_store_config_reg_seq(cb, reg, 1);
 689         r600_store_value(cb, value);
 690 }
 691
 692 static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 693 {
 694         r600_store_context_reg_seq(cb, reg, 1);
 695         r600_store_value(cb, value);
 696 }
 697
 698 static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 699 {
 700         r600_store_ctl_const_seq(cb, reg, 1);
 701         r600_store_value(cb, value);
 702 }
 703
 704 static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 705 {
 706         r600_store_loop_const_seq(cb, reg, 1);
 707         r600_store_value(cb, value);
 708 }
 709
 710 static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 711 {
 712         eg_store_loop_const_seq(cb, reg, 1);
 713         r600_store_value(cb, value);
 714 }
 715
 716 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags);
 717 void r600_release_command_buffer(struct r600_command_buffer *cb);
 718
 719 /*
 720  * Helpers for emitting state into a command stream directly.
 721  */
 722
 723 static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo,
 724                                              enum radeon_bo_usage usage)
 725 {
 726         assert(usage);
 727         return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4;
 728 }
 729
 730 static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value)
 731 {
 732         cs->buf[cs->cdw++] = value;
 733 }
 734
 735 static INLINE void r600_write_array(struct radeon_winsys_cs *cs, unsigned num, unsigned *ptr)
 736 {
 737         assert(cs->cdw+num <= RADEON_MAX_CMDBUF_DWORDS);
 738         memcpy(&cs->buf[cs->cdw], ptr, num * sizeof(ptr[0]));
 739         cs->cdw += num;
 740 }
 741
 742 static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 743 {
 744         assert(reg < R600_CONTEXT_REG_OFFSET);
 745         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 746         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
 747         cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
 748 }
 749
 750 static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 751 {
 752         assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
 753         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 754         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
 755         cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
 756 }
 757
 758 static INLINE void r600_write_compute_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 759 {
 760         r600_write_context_reg_seq(cs, reg, num);
 761         /* Set the compute bit on the packet header */
 762         cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
 763 }
 764
 765 static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 766 {
 767         assert(reg >= R600_CTL_CONST_OFFSET);
 768         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 769         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
 770         cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
 771 }
 772
 773 static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 774 {
 775         r600_write_config_reg_seq(cs, reg, 1);
 776         r600_write_value(cs, value);
 777 }
 778
 779 static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 780 {
 781         r600_write_context_reg_seq(cs, reg, 1);
 782         r600_write_value(cs, value);
 783 }
 784
 785 static INLINE void r600_write_compute_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 786 {
 787         r600_write_compute_context_reg_seq(cs, reg, 1);
 788         r600_write_value(cs, value);
 789 }
 790
 791 static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 792 {
 793         r600_write_ctl_const_seq(cs, reg, 1);
 794         r600_write_value(cs, value);
 795 }
 796
 797 /*
 798  * common helpers
 799  */
 800 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
 801 {
 802         return value * (1 << frac_bits);
 803 }
 804 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
 805
 806 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 807 {
 808         if (filter <= 1)   return 0;
 809         if (filter <= 2)   return 1;
 810         if (filter <= 4)   return 2;
 811         if (filter <= 8)   return 3;
 812          /* else */        return 4;
 813 }
 814
 815 /* 12.4 fixed-point */
 816 static INLINE unsigned r600_pack_float_12p4(float x)
 817 {
 818         return x <= 0    ? 0 :
 819                x >= 4096 ? 0xffff : x * 16;
 820 }
 821
 822 static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource)
 823 {
 824         struct r600_screen *rscreen = (struct r600_screen*)screen;
 825         struct r600_resource *rresource = (struct r600_resource*)resource;
 826
 827         return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);
 828 }
 829
 830 #endif