r600g: rework state emission of vertex buffers
[profile/ivi/mesa.git] / src / gallium / drivers / r600 / r600_pipe.h
1 /*
2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * on the rights to use, copy, modify, merge, publish, distribute, sub
8  * license, and/or sell copies of the Software, and to permit persons to whom
9  * the Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *      Jerome Glisse
25  */
26 #ifndef R600_PIPE_H
27 #define R600_PIPE_H
28
29 #include "util/u_slab.h"
30 #include "r600.h"
31 #include "r600_shader.h"
32 #include "r600_resource.h"
33
34 #define R600_MAX_CONST_BUFFERS 2
35 #define R600_MAX_CONST_BUFFER_SIZE 4096
36
37 #ifdef PIPE_ARCH_BIG_ENDIAN
38 #define R600_BIG_ENDIAN 1
39 #else
40 #define R600_BIG_ENDIAN 0
41 #endif
42
43 enum r600_atom_flags {
44         /* When set, atoms are added at the beginning of the dirty list
45          * instead of the end. */
46         EMIT_EARLY = (1 << 0)
47 };
48
49 /* This encapsulates a state or an operation which can emitted into the GPU
50  * command stream. It's not limited to states only, it can be used for anything
51  * that wants to write commands into the CS (e.g. cache flushes). */
52 struct r600_atom {
53         void (*emit)(struct r600_context *ctx, struct r600_atom *state);
54
55         unsigned                num_dw;
56         enum r600_atom_flags    flags;
57         bool                    dirty;
58
59         struct list_head        head;
60 };
61
62 /* This is an atom containing GPU commands that never change.
63  * This is supposed to be copied directly into the CS. */
64 struct r600_command_buffer {
65         struct r600_atom atom;
66         uint32_t *buf;
67         unsigned max_num_dw;
68 };
69
70 struct r600_surface_sync_cmd {
71         struct r600_atom atom;
72         unsigned flush_flags; /* CP_COHER_CNTL */
73 };
74
75 struct r600_db_misc_state {
76         struct r600_atom atom;
77         bool occlusion_query_enabled;
78         bool flush_depthstencil_enabled;
79 };
80
81 enum r600_pipe_state_id {
82         R600_PIPE_STATE_BLEND = 0,
83         R600_PIPE_STATE_BLEND_COLOR,
84         R600_PIPE_STATE_CONFIG,
85         R600_PIPE_STATE_SEAMLESS_CUBEMAP,
86         R600_PIPE_STATE_CLIP,
87         R600_PIPE_STATE_SCISSOR,
88         R600_PIPE_STATE_VIEWPORT,
89         R600_PIPE_STATE_RASTERIZER,
90         R600_PIPE_STATE_VGT,
91         R600_PIPE_STATE_FRAMEBUFFER,
92         R600_PIPE_STATE_DSA,
93         R600_PIPE_STATE_STENCIL_REF,
94         R600_PIPE_STATE_PS_SHADER,
95         R600_PIPE_STATE_VS_SHADER,
96         R600_PIPE_STATE_CONSTANT,
97         R600_PIPE_STATE_SAMPLER,
98         R600_PIPE_STATE_RESOURCE,
99         R600_PIPE_STATE_POLYGON_OFFSET,
100         R600_PIPE_STATE_FETCH_SHADER,
101         R600_PIPE_NSTATES
102 };
103
104 struct r600_pipe_fences {
105         struct r600_resource            *bo;
106         unsigned                        *data;
107         unsigned                        next_index;
108         /* linked list of preallocated blocks */
109         struct list_head                blocks;
110         /* linked list of freed fences */
111         struct list_head                pool;
112         pipe_mutex                      mutex;
113 };
114
115 struct r600_screen {
116         struct pipe_screen              screen;
117         struct radeon_winsys            *ws;
118         unsigned                        family;
119         enum chip_class                 chip_class;
120         struct radeon_info              info;
121         struct r600_tiling_info         tiling_info;
122         struct util_slab_mempool        pool_buffers;
123         struct r600_pipe_fences         fences;
124
125         unsigned                        num_contexts;
126         bool                            use_surface_alloc;
127
128         /* for thread-safe write accessing to num_contexts */
129         pipe_mutex                      mutex_num_contexts;
130 };
131
132 struct r600_pipe_sampler_view {
133         struct pipe_sampler_view        base;
134         struct r600_pipe_resource_state         state;
135 };
136
137 struct r600_pipe_rasterizer {
138         struct r600_pipe_state          rstate;
139         boolean                         flatshade;
140         boolean                         two_side;
141         unsigned                        sprite_coord_enable;
142         unsigned                        clip_plane_enable;
143         unsigned                        pa_sc_line_stipple;
144         unsigned                        pa_cl_clip_cntl;
145         float                           offset_units;
146         float                           offset_scale;
147         bool                            scissor_enable;
148 };
149
150 struct r600_pipe_blend {
151         struct r600_pipe_state          rstate;
152         unsigned                        cb_target_mask;
153         unsigned                        cb_color_control;
154 };
155
156 struct r600_pipe_dsa {
157         struct r600_pipe_state          rstate;
158         unsigned                        alpha_ref;
159         ubyte                           valuemask[2];
160         ubyte                           writemask[2];
161         bool                            is_flush;
162 };
163
164 struct r600_vertex_element
165 {
166         unsigned                        count;
167         struct pipe_vertex_element      elements[PIPE_MAX_ATTRIBS];
168         struct u_vbuf_elements          *vmgr_elements;
169         struct r600_resource            *fetch_shader;
170         unsigned                        fs_size;
171         struct r600_pipe_state          rstate;
172 };
173
174 struct r600_pipe_shader {
175         struct r600_shader              shader;
176         struct r600_pipe_state          rstate;
177         struct r600_resource            *bo;
178         struct r600_resource            *bo_fetch;
179         struct r600_vertex_element      vertex_elements;
180         struct tgsi_token               *tokens;
181         unsigned        sprite_coord_enable;
182         unsigned        flatshade;
183         unsigned        pa_cl_vs_out_cntl;
184         struct pipe_stream_output_info  so;
185 };
186
187 struct r600_pipe_sampler_state {
188         struct r600_pipe_state          rstate;
189         boolean seamless_cube_map;
190 };
191
192 /* needed for blitter save */
193 #define NUM_TEX_UNITS 16
194
195 struct r600_textures_info {
196         struct r600_pipe_sampler_view   *views[NUM_TEX_UNITS];
197         struct r600_pipe_sampler_state  *samplers[NUM_TEX_UNITS];
198         unsigned                        n_views;
199         unsigned                        n_samplers;
200         bool                            samplers_dirty;
201         bool                            is_array_sampler[NUM_TEX_UNITS];
202 };
203
204 struct r600_fence {
205         struct pipe_reference           reference;
206         unsigned                        index; /* in the shared bo */
207         struct r600_resource            *sleep_bo;
208         struct list_head                head;
209 };
210
211 #define FENCE_BLOCK_SIZE 16
212
213 struct r600_fence_block {
214         struct r600_fence               fences[FENCE_BLOCK_SIZE];
215         struct list_head                head;
216 };
217
218 #define R600_CONSTANT_ARRAY_SIZE 256
219 #define R600_RESOURCE_ARRAY_SIZE 160
220
221 struct r600_stencil_ref
222 {
223         ubyte ref_value[2];
224         ubyte valuemask[2];
225         ubyte writemask[2];
226 };
227
228 struct r600_context {
229         struct pipe_context             context;
230         struct blitter_context          *blitter;
231         enum radeon_family              family;
232         enum chip_class                 chip_class;
233         boolean                         has_vertex_cache;
234         unsigned                        r6xx_num_clause_temp_gprs;
235         void                            *custom_dsa_flush;
236         struct r600_screen              *screen;
237         struct radeon_winsys            *ws;
238         struct r600_pipe_state          *states[R600_PIPE_NSTATES];
239         struct r600_vertex_element      *vertex_elements;
240         struct pipe_framebuffer_state   framebuffer;
241         unsigned                        cb_target_mask;
242         unsigned                        cb_color_control;
243         unsigned                        pa_sc_line_stipple;
244         unsigned                        pa_cl_clip_cntl;
245         /* for saving when using blitter */
246         struct pipe_stencil_ref         stencil_ref;
247         struct pipe_viewport_state      viewport;
248         struct pipe_clip_state          clip;
249         struct r600_pipe_shader         *ps_shader;
250         struct r600_pipe_shader         *vs_shader;
251         struct r600_pipe_state          vs_const_buffer;
252         struct r600_pipe_resource_state         vs_const_buffer_resource[R600_MAX_CONST_BUFFERS];
253         struct r600_pipe_state          ps_const_buffer;
254         struct r600_pipe_resource_state         ps_const_buffer_resource[R600_MAX_CONST_BUFFERS];
255         struct r600_pipe_rasterizer     *rasterizer;
256         struct r600_pipe_state          vgt;
257         struct r600_pipe_state          spi;
258         struct pipe_query               *current_render_cond;
259         unsigned                        current_render_cond_mode;
260         struct pipe_query               *saved_render_cond;
261         unsigned                        saved_render_cond_mode;
262         /* shader information */
263         boolean                         two_side;
264         unsigned                        sprite_coord_enable;
265         boolean                         export_16bpc;
266         unsigned                        alpha_ref;
267         boolean                         alpha_ref_dirty;
268         unsigned                        nr_cbufs;
269         struct r600_textures_info       vs_samplers;
270         struct r600_textures_info       ps_samplers;
271
272         struct u_vbuf                   *vbuf_mgr;
273         struct util_slab_mempool        pool_transfers;
274         boolean                         have_depth_texture, have_depth_fb;
275
276         unsigned default_ps_gprs, default_vs_gprs;
277
278         /* States based on r600_atom. */
279         struct list_head                dirty_states;
280         struct r600_command_buffer      start_cs_cmd; /* invariant state mostly */
281         struct r600_surface_sync_cmd    surface_sync_cmd;
282         struct r600_atom                r6xx_flush_and_inv_cmd;
283         struct r600_db_misc_state       db_misc_state;
284         struct r600_atom                vertex_buffer_state;
285
286         /* Below are variables from the old r600_context.
287          */
288         struct radeon_winsys_cs *cs;
289
290         struct r600_range       *range;
291         unsigned                nblocks;
292         struct r600_block       **blocks;
293         struct list_head        dirty;
294         struct list_head        resource_dirty;
295         struct list_head        enable_list;
296         unsigned                pm4_dirty_cdwords;
297         unsigned                ctx_pm4_ndwords;
298
299         /* The list of active queries. Only one query of each type can be active. */
300         int                     num_occlusion_queries;
301
302         /* Manage queries in two separate groups:
303          * The timer ones and the others (streamout, occlusion).
304          *
305          * We do this because we should only suspend non-timer queries for u_blitter,
306          * and later if the non-timer queries are suspended, the context flush should
307          * only suspend and resume the timer queries. */
308         struct list_head        active_timer_queries;
309         unsigned                num_cs_dw_timer_queries_suspend;
310         struct list_head        active_nontimer_queries;
311         unsigned                num_cs_dw_nontimer_queries_suspend;
312
313         unsigned                num_cs_dw_streamout_end;
314
315         unsigned                backend_mask;
316         unsigned                max_db; /* for OQ */
317         unsigned                flags;
318         boolean                 predicate_drawing;
319         struct r600_range       ps_resources;
320         struct r600_range       vs_resources;
321         int                     num_ps_resources, num_vs_resources;
322
323         unsigned                num_so_targets;
324         struct r600_so_target   *so_targets[PIPE_MAX_SO_BUFFERS];
325         boolean                 streamout_start;
326         unsigned                streamout_append_bitmask;
327
328         /* There is no scissor enable bit on r6xx, so we must use a workaround.
329          * These track the current scissor state. */
330         bool                    scissor_enable;
331         struct pipe_scissor_state scissor_state;
332
333         /* With rasterizer discard, there doesn't have to be a pixel shader.
334          * In that case, we bind this one: */
335         void                    *dummy_pixel_shader;
336
337         bool                    vertex_buffers_dirty;
338 };
339
340 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
341 {
342         atom->emit(rctx, atom);
343         atom->dirty = false;
344         if (atom->head.next && atom->head.prev)
345                 LIST_DELINIT(&atom->head);
346 }
347
348 static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state)
349 {
350         if (!state->dirty) {
351                 if (state->flags & EMIT_EARLY) {
352                         LIST_ADD(&state->head, &rctx->dirty_states);
353                 } else {
354                         LIST_ADDTAIL(&state->head, &rctx->dirty_states);
355                 }
356                 state->dirty = true;
357         }
358 }
359
360 /* evergreen_state.c */
361 void evergreen_init_state_functions(struct r600_context *rctx);
362 void evergreen_init_atom_start_cs(struct r600_context *rctx);
363 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
364 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
365 void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
366 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
367 void evergreen_polygon_offset_update(struct r600_context *rctx);
368 void evergreen_pipe_init_buffer_resource(struct r600_context *rctx,
369                                          struct r600_pipe_resource_state *rstate);
370 void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx,
371                                         struct r600_pipe_resource_state *rstate,
372                                         struct r600_resource *rbuffer,
373                                         unsigned offset, unsigned stride,
374                                         enum radeon_bo_usage usage);
375 boolean evergreen_is_format_supported(struct pipe_screen *screen,
376                                       enum pipe_format format,
377                                       enum pipe_texture_target target,
378                                       unsigned sample_count,
379                                       unsigned usage);
380
381 /* r600_blit.c */
382 void r600_init_blit_functions(struct r600_context *rctx);
383 void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
384 void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
385 void r600_flush_depth_textures(struct r600_context *rctx);
386
387 /* r600_buffer.c */
388 bool r600_init_resource(struct r600_screen *rscreen,
389                         struct r600_resource *res,
390                         unsigned size, unsigned alignment,
391                         unsigned bind, unsigned usage);
392 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
393                                          const struct pipe_resource *templ);
394 struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen,
395                                               void *ptr, unsigned bytes,
396                                               unsigned bind);
397 void r600_upload_index_buffer(struct r600_context *rctx,
398                               struct pipe_index_buffer *ib, unsigned count);
399
400
401 /* r600_pipe.c */
402 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
403                 unsigned flags);
404
405 /* r600_query.c */
406 void r600_init_query_functions(struct r600_context *rctx);
407 void r600_suspend_nontimer_queries(struct r600_context *ctx);
408 void r600_resume_nontimer_queries(struct r600_context *ctx);
409 void r600_suspend_timer_queries(struct r600_context *ctx);
410 void r600_resume_timer_queries(struct r600_context *ctx);
411
412 /* r600_resource.c */
413 void r600_init_context_resource_functions(struct r600_context *r600);
414
415 /* r600_shader.c */
416 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader);
417 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
418 int r600_find_vs_semantic_index(struct r600_shader *vs,
419                                 struct r600_shader *ps, int id);
420
421 /* r600_state.c */
422 void r600_set_scissor_state(struct r600_context *rctx,
423                             const struct pipe_scissor_state *state);
424 void r600_update_sampler_states(struct r600_context *rctx);
425 void r600_init_state_functions(struct r600_context *rctx);
426 void r600_init_atom_start_cs(struct r600_context *rctx);
427 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
428 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
429 void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
430 void *r600_create_db_flush_dsa(struct r600_context *rctx);
431 void r600_polygon_offset_update(struct r600_context *rctx);
432 void r600_pipe_init_buffer_resource(struct r600_context *rctx,
433                                     struct r600_pipe_resource_state *rstate);
434 void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
435                                    struct r600_resource *rbuffer,
436                                    unsigned offset, unsigned stride,
437                                    enum radeon_bo_usage usage);
438 void r600_adjust_gprs(struct r600_context *rctx);
439 boolean r600_is_format_supported(struct pipe_screen *screen,
440                                  enum pipe_format format,
441                                  enum pipe_texture_target target,
442                                  unsigned sample_count,
443                                  unsigned usage);
444
445 /* r600_texture.c */
446 void r600_init_screen_texture_functions(struct pipe_screen *screen);
447 void r600_init_surface_functions(struct r600_context *r600);
448 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
449                                   const unsigned char *swizzle_view,
450                                   uint32_t *word4_p, uint32_t *yuv_format_p);
451 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
452                                         unsigned level, unsigned layer);
453
454 /* r600_translate.c */
455 void r600_translate_index_buffer(struct r600_context *r600,
456                                  struct pipe_index_buffer *ib,
457                                  unsigned count);
458
459 /* r600_state_common.c */
460 void r600_init_atom(struct r600_atom *atom,
461                     void (*emit)(struct r600_context *ctx, struct r600_atom *state),
462                     unsigned num_dw, enum r600_atom_flags flags);
463 void r600_init_common_atoms(struct r600_context *rctx);
464 unsigned r600_get_cb_flush_flags(struct r600_context *rctx);
465 void r600_texture_barrier(struct pipe_context *ctx);
466 void r600_set_index_buffer(struct pipe_context *ctx,
467                            const struct pipe_index_buffer *ib);
468 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
469                              const struct pipe_vertex_buffer *buffers);
470 void *r600_create_vertex_elements(struct pipe_context *ctx,
471                                   unsigned count,
472                                   const struct pipe_vertex_element *elements);
473 void r600_delete_vertex_element(struct pipe_context *ctx, void *state);
474 void r600_bind_blend_state(struct pipe_context *ctx, void *state);
475 void r600_set_blend_color(struct pipe_context *ctx,
476                           const struct pipe_blend_color *state);
477 void r600_bind_dsa_state(struct pipe_context *ctx, void *state);
478 void r600_set_max_scissor(struct r600_context *rctx);
479 void r600_bind_rs_state(struct pipe_context *ctx, void *state);
480 void r600_delete_rs_state(struct pipe_context *ctx, void *state);
481 void r600_sampler_view_destroy(struct pipe_context *ctx,
482                                struct pipe_sampler_view *state);
483 void r600_delete_state(struct pipe_context *ctx, void *state);
484 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
485 void *r600_create_shader_state(struct pipe_context *ctx,
486                                const struct pipe_shader_state *state);
487 void r600_bind_ps_shader(struct pipe_context *ctx, void *state);
488 void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
489 void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
490 void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
491 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
492                               struct pipe_resource *buffer);
493 struct pipe_stream_output_target *
494 r600_create_so_target(struct pipe_context *ctx,
495                       struct pipe_resource *buffer,
496                       unsigned buffer_offset,
497                       unsigned buffer_size);
498 void r600_so_target_destroy(struct pipe_context *ctx,
499                             struct pipe_stream_output_target *target);
500 void r600_set_so_targets(struct pipe_context *ctx,
501                          unsigned num_targets,
502                          struct pipe_stream_output_target **targets,
503                          unsigned append_bitmask);
504 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
505                                const struct pipe_stencil_ref *state);
506 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
507 uint32_t r600_translate_stencil_op(int s_op);
508 uint32_t r600_translate_fill(uint32_t func);
509 unsigned r600_tex_wrap(unsigned wrap);
510 unsigned r600_tex_filter(unsigned filter);
511 unsigned r600_tex_mipfilter(unsigned filter);
512 unsigned r600_tex_compare(unsigned compare);
513
514 /*
515  * Helpers for building command buffers
516  */
517
518 #define PKT3_SET_CONFIG_REG     0x68
519 #define PKT3_SET_CONTEXT_REG    0x69
520 #define PKT3_SET_CTL_CONST      0x6F
521 #define PKT3_SET_LOOP_CONST                    0x6C
522
523 #define R600_CONFIG_REG_OFFSET  0x08000
524 #define R600_CONTEXT_REG_OFFSET 0x28000
525 #define R600_CTL_CONST_OFFSET   0x3CFF0
526 #define R600_LOOP_CONST_OFFSET                 0X0003E200
527 #define EG_LOOP_CONST_OFFSET               0x0003A200
528
529 #define PKT_TYPE_S(x)                   (((x) & 0x3) << 30)
530 #define PKT_COUNT_S(x)                  (((x) & 0x3FFF) << 16)
531 #define PKT3_IT_OPCODE_S(x)             (((x) & 0xFF) << 8)
532 #define PKT3_PREDICATE(x)               (((x) >> 0) & 0x1)
533 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
534
535 static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value)
536 {
537         cb->buf[cb->atom.num_dw++] = value;
538 }
539
540 static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
541 {
542         assert(reg < R600_CONTEXT_REG_OFFSET);
543         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
544         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
545         cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
546 }
547
548 static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
549 {
550         assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
551         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
552         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
553         cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
554 }
555
556 static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
557 {
558         assert(reg >= R600_CTL_CONST_OFFSET);
559         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
560         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
561         cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
562 }
563
564 static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
565 {
566         assert(reg >= R600_LOOP_CONST_OFFSET);
567         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
568         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
569         cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
570 }
571
572 static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
573 {
574         assert(reg >= EG_LOOP_CONST_OFFSET);
575         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
576         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
577         cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
578 }
579
580 static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
581 {
582         r600_store_config_reg_seq(cb, reg, 1);
583         r600_store_value(cb, value);
584 }
585
586 static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
587 {
588         r600_store_context_reg_seq(cb, reg, 1);
589         r600_store_value(cb, value);
590 }
591
592 static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
593 {
594         r600_store_ctl_const_seq(cb, reg, 1);
595         r600_store_value(cb, value);
596 }
597
598 static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
599 {
600         r600_store_loop_const_seq(cb, reg, 1);
601         r600_store_value(cb, value);
602 }
603
604 static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
605 {
606         eg_store_loop_const_seq(cb, reg, 1);
607         r600_store_value(cb, value);
608 }
609
610 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags);
611 void r600_release_command_buffer(struct r600_command_buffer *cb);
612
613 /*
614  * Helpers for emitting state into a command stream directly.
615  */
616
617 static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo,
618                                              enum radeon_bo_usage usage)
619 {
620         assert(usage);
621         return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4;
622 }
623
624 static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value)
625 {
626         cs->buf[cs->cdw++] = value;
627 }
628
629 static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
630 {
631         assert(reg < R600_CONTEXT_REG_OFFSET);
632         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
633         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
634         cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
635 }
636
637 static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
638 {
639         assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
640         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
641         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
642         cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
643 }
644
645 static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
646 {
647         assert(reg >= R600_CTL_CONST_OFFSET);
648         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
649         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
650         cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
651 }
652
653 static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
654 {
655         r600_write_config_reg_seq(cs, reg, 1);
656         r600_write_value(cs, value);
657 }
658
659 static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
660 {
661         r600_write_context_reg_seq(cs, reg, 1);
662         r600_write_value(cs, value);
663 }
664
665 static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
666 {
667         r600_write_ctl_const_seq(cs, reg, 1);
668         r600_write_value(cs, value);
669 }
670
671 /*
672  * common helpers
673  */
674 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
675 {
676         return value * (1 << frac_bits);
677 }
678 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
679
680 static inline unsigned r600_tex_aniso_filter(unsigned filter)
681 {
682         if (filter <= 1)   return 0;
683         if (filter <= 2)   return 1;
684         if (filter <= 4)   return 2;
685         if (filter <= 8)   return 3;
686          /* else */        return 4;
687 }
688
689 /* 12.4 fixed-point */
690 static INLINE unsigned r600_pack_float_12p4(float x)
691 {
692         return x <= 0    ? 0 :
693                x >= 4096 ? 0xffff : x * 16;
694 }
695
696 static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource)
697 {
698         struct r600_screen *rscreen = (struct r600_screen*)screen;
699         struct r600_resource *rresource = (struct r600_resource*)resource;
700
701         return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);
702 }
703
704 #endif