2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "../../winsys/radeon/drm/radeon_winsys.h"
31 #include "pipe/p_state.h"
32 #include "pipe/p_screen.h"
33 #include "pipe/p_context.h"
34 #include "util/u_math.h"
35 #include "util/u_slab.h"
36 #include "util/u_vbuf.h"
38 #include "r600_public.h"
39 #include "r600_shader.h"
40 #include "r600_resource.h"
42 #define R600_MAX_CONST_BUFFERS 2
43 #define R600_MAX_CONST_BUFFER_SIZE 4096
45 #ifdef PIPE_ARCH_BIG_ENDIAN
46 #define R600_BIG_ENDIAN 1
48 #define R600_BIG_ENDIAN 0
51 enum r600_pipe_state_id {
52 R600_PIPE_STATE_BLEND = 0,
53 R600_PIPE_STATE_BLEND_COLOR,
54 R600_PIPE_STATE_CONFIG,
55 R600_PIPE_STATE_SEAMLESS_CUBEMAP,
57 R600_PIPE_STATE_SCISSOR,
58 R600_PIPE_STATE_VIEWPORT,
59 R600_PIPE_STATE_RASTERIZER,
61 R600_PIPE_STATE_FRAMEBUFFER,
63 R600_PIPE_STATE_STENCIL_REF,
64 R600_PIPE_STATE_PS_SHADER,
65 R600_PIPE_STATE_VS_SHADER,
66 R600_PIPE_STATE_CONSTANT,
67 R600_PIPE_STATE_SAMPLER,
68 R600_PIPE_STATE_RESOURCE,
69 R600_PIPE_STATE_POLYGON_OFFSET,
70 R600_PIPE_STATE_FETCH_SHADER,
74 struct r600_pipe_fences {
75 struct r600_resource *bo;
78 /* linked list of preallocated blocks */
79 struct list_head blocks;
80 /* linked list of freed fences */
81 struct list_head pool;
86 struct pipe_screen screen;
87 struct radeon_winsys *ws;
89 enum chip_class chip_class;
90 struct radeon_info info;
91 struct r600_tiling_info tiling_info;
92 struct util_slab_mempool pool_buffers;
93 struct r600_pipe_fences fences;
95 unsigned num_contexts;
97 /* for thread-safe write accessing to num_contexts */
98 pipe_mutex mutex_num_contexts;
101 struct r600_pipe_sampler_view {
102 struct pipe_sampler_view base;
103 struct r600_pipe_resource_state state;
106 struct r600_pipe_rasterizer {
107 struct r600_pipe_state rstate;
110 unsigned sprite_coord_enable;
111 unsigned clip_plane_enable;
116 struct r600_pipe_blend {
117 struct r600_pipe_state rstate;
118 unsigned cb_target_mask;
121 struct r600_pipe_dsa {
122 struct r600_pipe_state rstate;
126 struct r600_vertex_element
129 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS];
130 struct u_vbuf_elements *vmgr_elements;
131 struct r600_resource *fetch_shader;
133 struct r600_pipe_state rstate;
134 /* if offset is to big for fetch instructio we need to alterate
135 * offset of vertex buffer, record here the offset need to add
137 unsigned vbuffer_need_offset;
138 unsigned vbuffer_offset[PIPE_MAX_ATTRIBS];
141 struct r600_pipe_shader {
142 struct r600_shader shader;
143 struct r600_pipe_state rstate;
144 struct r600_resource *bo;
145 struct r600_resource *bo_fetch;
146 struct r600_vertex_element vertex_elements;
147 struct tgsi_token *tokens;
148 unsigned sprite_coord_enable;
149 struct pipe_stream_output_info so;
152 struct r600_pipe_sampler_state {
153 struct r600_pipe_state rstate;
154 boolean seamless_cube_map;
157 /* needed for blitter save */
158 #define NUM_TEX_UNITS 16
160 struct r600_textures_info {
161 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
162 struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS];
166 bool is_array_sampler[NUM_TEX_UNITS];
170 struct pipe_reference reference;
171 unsigned index; /* in the shared bo */
172 struct list_head head;
175 #define FENCE_BLOCK_SIZE 16
177 struct r600_fence_block {
178 struct r600_fence fences[FENCE_BLOCK_SIZE];
179 struct list_head head;
182 #define R600_CONSTANT_ARRAY_SIZE 256
183 #define R600_RESOURCE_ARRAY_SIZE 160
185 struct r600_pipe_context {
186 struct pipe_context context;
187 struct blitter_context *blitter;
188 enum radeon_family family;
189 enum chip_class chip_class;
190 void *custom_dsa_flush;
191 struct r600_screen *screen;
192 struct radeon_winsys *ws;
193 struct r600_pipe_state *states[R600_PIPE_NSTATES];
194 struct r600_context ctx;
195 struct r600_vertex_element *vertex_elements;
196 struct r600_pipe_resource_state fs_resource[PIPE_MAX_ATTRIBS];
197 struct pipe_framebuffer_state framebuffer;
198 unsigned cb_target_mask;
199 /* for saving when using blitter */
200 struct pipe_stencil_ref stencil_ref;
201 struct pipe_viewport_state viewport;
202 struct pipe_clip_state clip;
203 struct r600_pipe_state config;
204 struct r600_pipe_shader *ps_shader;
205 struct r600_pipe_shader *vs_shader;
206 struct r600_pipe_state vs_const_buffer;
207 struct r600_pipe_resource_state vs_const_buffer_resource[R600_MAX_CONST_BUFFERS];
208 struct r600_pipe_state ps_const_buffer;
209 struct r600_pipe_resource_state ps_const_buffer_resource[R600_MAX_CONST_BUFFERS];
210 struct r600_pipe_rasterizer *rasterizer;
211 struct r600_pipe_state vgt;
212 struct r600_pipe_state spi;
213 struct pipe_query *current_render_cond;
214 unsigned current_render_cond_mode;
215 struct pipe_query *saved_render_cond;
216 unsigned saved_render_cond_mode;
217 /* shader information */
219 unsigned user_clip_plane_enable;
220 unsigned clip_dist_enable;
221 unsigned sprite_coord_enable;
222 boolean export_16bpc;
224 boolean alpha_ref_dirty;
226 struct r600_textures_info vs_samplers;
227 struct r600_textures_info ps_samplers;
229 struct u_vbuf *vbuf_mgr;
230 struct util_slab_mempool pool_transfers;
231 boolean have_depth_texture, have_depth_fb;
233 unsigned default_ps_gprs, default_vs_gprs;
236 /* evergreen_state.c */
237 void evergreen_init_state_functions(struct r600_pipe_context *rctx);
238 void evergreen_init_config(struct r600_pipe_context *rctx);
239 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
240 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
241 void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
242 void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx);
243 void evergreen_polygon_offset_update(struct r600_pipe_context *rctx);
244 void evergreen_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
245 struct r600_pipe_resource_state *rstate);
246 void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx,
247 struct r600_pipe_resource_state *rstate,
248 struct r600_resource *rbuffer,
249 unsigned offset, unsigned stride,
250 enum radeon_bo_usage usage);
251 boolean evergreen_is_format_supported(struct pipe_screen *screen,
252 enum pipe_format format,
253 enum pipe_texture_target target,
254 unsigned sample_count,
258 void r600_init_blit_functions(struct r600_pipe_context *rctx);
259 void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
260 void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
261 void r600_flush_depth_textures(struct r600_pipe_context *rctx);
264 bool r600_init_resource(struct r600_screen *rscreen,
265 struct r600_resource *res,
266 unsigned size, unsigned alignment,
267 unsigned bind, unsigned usage);
268 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
269 const struct pipe_resource *templ);
270 struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen,
271 void *ptr, unsigned bytes,
273 void r600_upload_index_buffer(struct r600_pipe_context *rctx,
274 struct pipe_index_buffer *ib, unsigned count);
278 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
282 void r600_init_query_functions(struct r600_pipe_context *rctx);
284 /* r600_resource.c */
285 void r600_init_context_resource_functions(struct r600_pipe_context *r600);
288 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader);
289 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
290 int r600_find_vs_semantic_index(struct r600_shader *vs,
291 struct r600_shader *ps, int id);
294 void r600_update_sampler_states(struct r600_pipe_context *rctx);
295 void r600_init_state_functions(struct r600_pipe_context *rctx);
296 void r600_init_config(struct r600_pipe_context *rctx);
297 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
298 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
299 void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
300 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx);
301 void r600_polygon_offset_update(struct r600_pipe_context *rctx);
302 void r600_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
303 struct r600_pipe_resource_state *rstate);
304 void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
305 struct r600_resource *rbuffer,
306 unsigned offset, unsigned stride,
307 enum radeon_bo_usage usage);
308 void r600_adjust_gprs(struct r600_pipe_context *rctx);
309 boolean r600_is_format_supported(struct pipe_screen *screen,
310 enum pipe_format format,
311 enum pipe_texture_target target,
312 unsigned sample_count,
316 void r600_init_screen_texture_functions(struct pipe_screen *screen);
317 void r600_init_surface_functions(struct r600_pipe_context *r600);
318 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
319 const unsigned char *swizzle_view,
320 uint32_t *word4_p, uint32_t *yuv_format_p);
321 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
322 unsigned level, unsigned layer);
324 /* r600_translate.c */
325 void r600_translate_index_buffer(struct r600_pipe_context *r600,
326 struct pipe_index_buffer *ib,
329 /* r600_state_common.c */
330 void r600_set_index_buffer(struct pipe_context *ctx,
331 const struct pipe_index_buffer *ib);
332 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
333 const struct pipe_vertex_buffer *buffers);
334 void *r600_create_vertex_elements(struct pipe_context *ctx,
336 const struct pipe_vertex_element *elements);
337 void r600_delete_vertex_element(struct pipe_context *ctx, void *state);
338 void r600_bind_blend_state(struct pipe_context *ctx, void *state);
339 void r600_bind_dsa_state(struct pipe_context *ctx, void *state);
340 void r600_bind_rs_state(struct pipe_context *ctx, void *state);
341 void r600_delete_rs_state(struct pipe_context *ctx, void *state);
342 void r600_sampler_view_destroy(struct pipe_context *ctx,
343 struct pipe_sampler_view *state);
344 void r600_delete_state(struct pipe_context *ctx, void *state);
345 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
346 void *r600_create_shader_state(struct pipe_context *ctx,
347 const struct pipe_shader_state *state);
348 void r600_bind_ps_shader(struct pipe_context *ctx, void *state);
349 void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
350 void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
351 void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
352 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
353 struct pipe_resource *buffer);
354 struct pipe_stream_output_target *
355 r600_create_so_target(struct pipe_context *ctx,
356 struct pipe_resource *buffer,
357 unsigned buffer_offset,
358 unsigned buffer_size);
359 void r600_so_target_destroy(struct pipe_context *ctx,
360 struct pipe_stream_output_target *target);
361 void r600_set_so_targets(struct pipe_context *ctx,
362 unsigned num_targets,
363 struct pipe_stream_output_target **targets,
364 unsigned append_bitmask);
367 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
372 static INLINE u32 S_FIXED(float value, u32 frac_bits)
374 return value * (1 << frac_bits);
376 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
378 static inline unsigned r600_tex_aniso_filter(unsigned filter)
380 if (filter <= 1) return 0;
381 if (filter <= 2) return 1;
382 if (filter <= 4) return 2;
383 if (filter <= 8) return 3;