src/gallium/drivers/r600/r600_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef R600_PIPE_H
  27 #define R600_PIPE_H
  28
  29 #include "util/u_slab.h"
  30 #include "r600.h"
  31 #include "r600_llvm.h"
  32 #include "r600_public.h"
  33 #include "r600_shader.h"
  34 #include "r600_resource.h"
  35 #include "evergreen_compute.h"
  36
  37 #define R600_MAX_CONST_BUFFERS 2
  38 #define R600_MAX_CONST_BUFFER_SIZE 4096
  39
  40 #ifdef PIPE_ARCH_BIG_ENDIAN
  41 #define R600_BIG_ENDIAN 1
  42 #else
  43 #define R600_BIG_ENDIAN 0
  44 #endif
  45
  46 enum r600_atom_flags {
  47         /* When set, atoms are added at the beginning of the dirty list
  48          * instead of the end. */
  49         EMIT_EARLY = (1 << 0)
  50 };
  51
  52 /* This encapsulates a state or an operation which can emitted into the GPU
  53  * command stream. It's not limited to states only, it can be used for anything
  54  * that wants to write commands into the CS (e.g. cache flushes). */
  55 struct r600_atom {
  56         void (*emit)(struct r600_context *ctx, struct r600_atom *state);
  57
  58         unsigned                num_dw;
  59         enum r600_atom_flags    flags;
  60         bool                    dirty;
  61
  62         struct list_head        head;
  63 };
  64
  65 /* This is an atom containing GPU commands that never change.
  66  * This is supposed to be copied directly into the CS. */
  67 struct r600_command_buffer {
  68         struct r600_atom atom;
  69         uint32_t *buf;
  70         unsigned max_num_dw;
  71         unsigned pkt_flags;
  72 };
  73
  74 struct r600_surface_sync_cmd {
  75         struct r600_atom atom;
  76         unsigned flush_flags; /* CP_COHER_CNTL */
  77 };
  78
  79 struct r600_db_misc_state {
  80         struct r600_atom atom;
  81         bool occlusion_query_enabled;
  82         bool flush_depthstencil_enabled;
  83 };
  84
  85 enum r600_pipe_state_id {
  86         R600_PIPE_STATE_BLEND = 0,
  87         R600_PIPE_STATE_BLEND_COLOR,
  88         R600_PIPE_STATE_CONFIG,
  89         R600_PIPE_STATE_SEAMLESS_CUBEMAP,
  90         R600_PIPE_STATE_CLIP,
  91         R600_PIPE_STATE_SCISSOR,
  92         R600_PIPE_STATE_VIEWPORT,
  93         R600_PIPE_STATE_RASTERIZER,
  94         R600_PIPE_STATE_VGT,
  95         R600_PIPE_STATE_FRAMEBUFFER,
  96         R600_PIPE_STATE_DSA,
  97         R600_PIPE_STATE_STENCIL_REF,
  98         R600_PIPE_STATE_PS_SHADER,
  99         R600_PIPE_STATE_VS_SHADER,
 100         R600_PIPE_STATE_CONSTANT,
 101         R600_PIPE_STATE_SAMPLER,
 102         R600_PIPE_STATE_RESOURCE,
 103         R600_PIPE_STATE_POLYGON_OFFSET,
 104         R600_PIPE_STATE_FETCH_SHADER,
 105         R600_PIPE_STATE_SPI,
 106         R600_PIPE_NSTATES
 107 };
 108
 109 struct compute_memory_pool;
 110 void compute_memory_pool_delete(struct compute_memory_pool* pool);
 111 struct compute_memory_pool* compute_memory_pool_new(
 112         struct r600_screen *rscreen);
 113
 114 struct r600_pipe_fences {
 115         struct r600_resource            *bo;
 116         unsigned                        *data;
 117         unsigned                        next_index;
 118         /* linked list of preallocated blocks */
 119         struct list_head                blocks;
 120         /* linked list of freed fences */
 121         struct list_head                pool;
 122         pipe_mutex                      mutex;
 123 };
 124
 125 struct r600_screen {
 126         struct pipe_screen              screen;
 127         struct radeon_winsys            *ws;
 128         unsigned                        family;
 129         enum chip_class                 chip_class;
 130         struct radeon_info              info;
 131         bool                            has_streamout;
 132         struct r600_tiling_info         tiling_info;
 133         struct r600_pipe_fences         fences;
 134
 135         bool                            use_surface_alloc;
 136         int                             glsl_feature_level;
 137
 138         /*for compute global memory binding, we allocate stuff here, instead of
 139          * buffers.
 140          * XXX: Not sure if this is the best place for global_pool.  Also,
 141          * it's not thread safe, so it won't work with multiple contexts. */
 142         struct compute_memory_pool *global_pool;
 143 };
 144
 145 struct r600_pipe_sampler_view {
 146         struct pipe_sampler_view        base;
 147         struct r600_pipe_resource_state         state;
 148 };
 149
 150 struct r600_pipe_rasterizer {
 151         struct r600_pipe_state          rstate;
 152         boolean                         flatshade;
 153         boolean                         two_side;
 154         unsigned                        sprite_coord_enable;
 155         unsigned                        clip_plane_enable;
 156         unsigned                        pa_sc_line_stipple;
 157         unsigned                        pa_cl_clip_cntl;
 158         float                           offset_units;
 159         float                           offset_scale;
 160         bool                            scissor_enable;
 161 };
 162
 163 struct r600_pipe_blend {
 164         struct r600_pipe_state          rstate;
 165         unsigned                        cb_target_mask;
 166         unsigned                        cb_color_control;
 167         bool                            dual_src_blend;
 168 };
 169
 170 struct r600_pipe_dsa {
 171         struct r600_pipe_state          rstate;
 172         unsigned                        alpha_ref;
 173         ubyte                           valuemask[2];
 174         ubyte                           writemask[2];
 175         bool                            is_flush;
 176         unsigned                        sx_alpha_test_control;
 177 };
 178
 179 struct r600_vertex_element
 180 {
 181         unsigned                        count;
 182         struct pipe_vertex_element      elements[PIPE_MAX_ATTRIBS];
 183         struct r600_resource            *fetch_shader;
 184         unsigned                        fs_size;
 185         struct r600_pipe_state          rstate;
 186 };
 187
 188 struct r600_pipe_shader;
 189
 190 struct r600_pipe_shader_selector {
 191         struct r600_pipe_shader *current;
 192
 193         struct tgsi_token       *tokens;
 194         struct pipe_stream_output_info  so;
 195
 196         unsigned        num_shaders;
 197
 198         /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
 199         unsigned        type;
 200
 201         unsigned        nr_ps_max_color_exports;
 202 };
 203
 204 struct r600_pipe_shader {
 205         struct r600_pipe_shader_selector *selector;
 206         struct r600_pipe_shader *next_variant;
 207         struct r600_shader              shader;
 208         struct r600_pipe_state          rstate;
 209         struct r600_resource            *bo;
 210         struct r600_resource            *bo_fetch;
 211         struct r600_vertex_element      vertex_elements;
 212         unsigned        sprite_coord_enable;
 213         unsigned        flatshade;
 214         unsigned        pa_cl_vs_out_cntl;
 215         unsigned        ps_cb_shader_mask;
 216         unsigned        key;
 217         unsigned                db_shader_control;
 218         unsigned                ps_depth_export;
 219 };
 220
 221 struct r600_pipe_sampler_state {
 222         struct r600_pipe_state          rstate;
 223         boolean seamless_cube_map;
 224 };
 225
 226 /* needed for blitter save */
 227 #define NUM_TEX_UNITS 16
 228
 229 struct r600_textures_info {
 230         struct r600_pipe_sampler_view   *views[NUM_TEX_UNITS];
 231         struct r600_pipe_sampler_state  *samplers[NUM_TEX_UNITS];
 232         unsigned                        n_views;
 233         unsigned                        n_samplers;
 234         bool                            samplers_dirty;
 235         bool                            is_array_sampler[NUM_TEX_UNITS];
 236 };
 237
 238 struct r600_fence {
 239         struct pipe_reference           reference;
 240         unsigned                        index; /* in the shared bo */
 241         struct r600_resource            *sleep_bo;
 242         struct list_head                head;
 243 };
 244
 245 #define FENCE_BLOCK_SIZE 16
 246
 247 struct r600_fence_block {
 248         struct r600_fence               fences[FENCE_BLOCK_SIZE];
 249         struct list_head                head;
 250 };
 251
 252 #define R600_CONSTANT_ARRAY_SIZE 256
 253 #define R600_RESOURCE_ARRAY_SIZE 160
 254
 255 struct r600_stencil_ref
 256 {
 257         ubyte ref_value[2];
 258         ubyte valuemask[2];
 259         ubyte writemask[2];
 260 };
 261
 262 struct r600_constbuf_state
 263 {
 264         struct r600_atom                atom;
 265         struct pipe_constant_buffer     cb[PIPE_MAX_CONSTANT_BUFFERS];
 266         uint32_t                        enabled_mask;
 267         uint32_t                        dirty_mask;
 268 };
 269
 270 struct r600_context {
 271         struct pipe_context             context;
 272         struct blitter_context          *blitter;
 273         enum radeon_family              family;
 274         enum chip_class                 chip_class;
 275         boolean                         has_vertex_cache;
 276         unsigned                        r6xx_num_clause_temp_gprs;
 277         void                            *custom_dsa_flush;
 278         struct r600_screen              *screen;
 279         struct radeon_winsys            *ws;
 280         struct r600_pipe_state          *states[R600_PIPE_NSTATES];
 281         struct r600_vertex_element      *vertex_elements;
 282         struct pipe_framebuffer_state   framebuffer;
 283         unsigned                        cb_target_mask;
 284         unsigned                        fb_cb_shader_mask;
 285         unsigned                        sx_alpha_test_control;
 286         unsigned                        cb_shader_mask;
 287         unsigned                        db_shader_control;
 288         unsigned                        cb_color_control;
 289         unsigned                        pa_sc_line_stipple;
 290         unsigned                        pa_cl_clip_cntl;
 291         /* for saving when using blitter */
 292         struct pipe_stencil_ref         stencil_ref;
 293         struct pipe_viewport_state      viewport;
 294         struct pipe_clip_state          clip;
 295         struct r600_pipe_shader_selector        *ps_shader;
 296         struct r600_pipe_shader_selector        *vs_shader;
 297         struct r600_pipe_compute        *cs_shader;
 298         struct r600_pipe_rasterizer     *rasterizer;
 299         struct r600_pipe_state          vgt;
 300         struct r600_pipe_state          spi;
 301         struct pipe_query               *current_render_cond;
 302         unsigned                        current_render_cond_mode;
 303         struct pipe_query               *saved_render_cond;
 304         unsigned                        saved_render_cond_mode;
 305         /* shader information */
 306         boolean                         two_side;
 307         boolean                         spi_dirty;
 308         unsigned                        sprite_coord_enable;
 309         boolean                         flatshade;
 310         boolean                         export_16bpc;
 311         unsigned                        alpha_ref;
 312         boolean                         alpha_ref_dirty;
 313         unsigned                        nr_cbufs;
 314         struct r600_textures_info       vs_samplers;
 315         struct r600_textures_info       ps_samplers;
 316
 317         struct u_upload_mgr             *uploader;
 318         struct util_slab_mempool        pool_transfers;
 319         boolean                         have_depth_texture, have_depth_fb;
 320
 321         unsigned default_ps_gprs, default_vs_gprs;
 322
 323         /* States based on r600_atom. */
 324         struct list_head                dirty_states;
 325         struct r600_command_buffer      start_cs_cmd; /* invariant state mostly */
 326         /** Compute specific registers initializations.  The start_cs_cmd atom
 327          *  must be emitted before start_compute_cs_cmd. */
 328         struct r600_command_buffer      start_compute_cs_cmd;
 329         struct r600_surface_sync_cmd    surface_sync_cmd;
 330         struct r600_atom                r6xx_flush_and_inv_cmd;
 331         struct r600_db_misc_state       db_misc_state;
 332         struct r600_atom                vertex_buffer_state;
 333         struct r600_constbuf_state      vs_constbuf_state;
 334         struct r600_constbuf_state      ps_constbuf_state;
 335
 336         struct radeon_winsys_cs *cs;
 337
 338         struct r600_range       *range;
 339         unsigned                nblocks;
 340         struct r600_block       **blocks;
 341         struct list_head        dirty;
 342         struct list_head        resource_dirty;
 343         struct list_head        enable_list;
 344         unsigned                pm4_dirty_cdwords;
 345         unsigned                ctx_pm4_ndwords;
 346
 347         /* The list of active queries. Only one query of each type can be active. */
 348         int                     num_occlusion_queries;
 349
 350         /* Manage queries in two separate groups:
 351          * The timer ones and the others (streamout, occlusion).
 352          *
 353          * We do this because we should only suspend non-timer queries for u_blitter,
 354          * and later if the non-timer queries are suspended, the context flush should
 355          * only suspend and resume the timer queries. */
 356         struct list_head        active_timer_queries;
 357         unsigned                num_cs_dw_timer_queries_suspend;
 358         struct list_head        active_nontimer_queries;
 359         unsigned                num_cs_dw_nontimer_queries_suspend;
 360
 361         unsigned                num_cs_dw_streamout_end;
 362
 363         unsigned                backend_mask;
 364         unsigned                max_db; /* for OQ */
 365         unsigned                flags;
 366         boolean                 predicate_drawing;
 367         struct r600_range       ps_resources;
 368         struct r600_range       vs_resources;
 369         int                     num_ps_resources, num_vs_resources;
 370
 371         unsigned                num_so_targets;
 372         struct r600_so_target   *so_targets[PIPE_MAX_SO_BUFFERS];
 373         boolean                 streamout_start;
 374         unsigned                streamout_append_bitmask;
 375
 376         /* There is no scissor enable bit on r6xx, so we must use a workaround.
 377          * These track the current scissor state. */
 378         bool                    scissor_enable;
 379         struct pipe_scissor_state scissor_state;
 380
 381         /* With rasterizer discard, there doesn't have to be a pixel shader.
 382          * In that case, we bind this one: */
 383         void                    *dummy_pixel_shader;
 384
 385         boolean                 dual_src_blend;
 386
 387         /* Vertex and index buffers. */
 388         bool                    vertex_buffers_dirty;
 389         struct pipe_index_buffer index_buffer;
 390         struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
 391         unsigned                nr_vertex_buffers;
 392 };
 393
 394 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
 395 {
 396         atom->emit(rctx, atom);
 397         atom->dirty = false;
 398         if (atom->head.next && atom->head.prev)
 399                 LIST_DELINIT(&atom->head);
 400 }
 401
 402 static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state)
 403 {
 404         if (!state->dirty) {
 405                 if (state->flags & EMIT_EARLY) {
 406                         LIST_ADD(&state->head, &rctx->dirty_states);
 407                 } else {
 408                         LIST_ADDTAIL(&state->head, &rctx->dirty_states);
 409                 }
 410                 state->dirty = true;
 411         }
 412 }
 413
 414 /* evergreen_state.c */
 415 void evergreen_init_state_functions(struct r600_context *rctx);
 416 void evergreen_init_atom_start_cs(struct r600_context *rctx);
 417 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 418 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 419 void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
 420 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
 421 void evergreen_polygon_offset_update(struct r600_context *rctx);
 422 boolean evergreen_is_format_supported(struct pipe_screen *screen,
 423                                       enum pipe_format format,
 424                                       enum pipe_texture_target target,
 425                                       unsigned sample_count,
 426                                       unsigned usage);
 427 void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
 428                          const struct pipe_framebuffer_state *state, int cb);
 429
 430
 431 void evergreen_update_dual_export_state(struct r600_context * rctx);
 432
 433 /* r600_blit.c */
 434 void r600_init_blit_functions(struct r600_context *rctx);
 435 void r600_blit_uncompress_depth(struct pipe_context *ctx,
 436                 struct r600_resource_texture *texture,
 437                 struct r600_resource_texture *staging);
 438 void r600_flush_depth_textures(struct r600_context *rctx);
 439
 440 /* r600_buffer.c */
 441 bool r600_init_resource(struct r600_screen *rscreen,
 442                         struct r600_resource *res,
 443                         unsigned size, unsigned alignment,
 444                         unsigned bind, unsigned usage);
 445 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 446                                          const struct pipe_resource *templ);
 447
 448 /* r600_pipe.c */
 449 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 450                 unsigned flags);
 451
 452 /* r600_query.c */
 453 void r600_init_query_functions(struct r600_context *rctx);
 454 void r600_suspend_nontimer_queries(struct r600_context *ctx);
 455 void r600_resume_nontimer_queries(struct r600_context *ctx);
 456 void r600_suspend_timer_queries(struct r600_context *ctx);
 457 void r600_resume_timer_queries(struct r600_context *ctx);
 458
 459 /* r600_resource.c */
 460 void r600_init_context_resource_functions(struct r600_context *r600);
 461
 462 /* r600_shader.c */
 463 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 464 #ifdef HAVE_OPENCL
 465 int r600_compute_shader_create(struct pipe_context * ctx,
 466         LLVMModuleRef mod,  struct r600_bytecode * bytecode);
 467 #endif
 468 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 469
 470 /* r600_state.c */
 471 void r600_set_scissor_state(struct r600_context *rctx,
 472                             const struct pipe_scissor_state *state);
 473 void r600_update_sampler_states(struct r600_context *rctx);
 474 void r600_init_state_functions(struct r600_context *rctx);
 475 void r600_init_atom_start_cs(struct r600_context *rctx);
 476 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 477 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 478 void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
 479 void *r600_create_db_flush_dsa(struct r600_context *rctx);
 480 void r600_polygon_offset_update(struct r600_context *rctx);
 481 void r600_adjust_gprs(struct r600_context *rctx);
 482 boolean r600_is_format_supported(struct pipe_screen *screen,
 483                                  enum pipe_format format,
 484                                  enum pipe_texture_target target,
 485                                  unsigned sample_count,
 486                                  unsigned usage);
 487 void r600_update_dual_export_state(struct r600_context * rctx);
 488
 489 /* r600_texture.c */
 490 void r600_init_screen_texture_functions(struct pipe_screen *screen);
 491 void r600_init_surface_functions(struct r600_context *r600);
 492 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
 493                                   const unsigned char *swizzle_view,
 494                                   uint32_t *word4_p, uint32_t *yuv_format_p);
 495 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
 496                                         unsigned level, unsigned layer);
 497
 498 /* r600_translate.c */
 499 void r600_translate_index_buffer(struct r600_context *r600,
 500                                  struct pipe_index_buffer *ib,
 501                                  unsigned count);
 502
 503 /* r600_state_common.c */
 504 void r600_init_atom(struct r600_atom *atom,
 505                     void (*emit)(struct r600_context *ctx, struct r600_atom *state),
 506                     unsigned num_dw, enum r600_atom_flags flags);
 507 void r600_init_common_atoms(struct r600_context *rctx);
 508 unsigned r600_get_cb_flush_flags(struct r600_context *rctx);
 509 void r600_texture_barrier(struct pipe_context *ctx);
 510 void r600_set_index_buffer(struct pipe_context *ctx,
 511                            const struct pipe_index_buffer *ib);
 512 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 513                              const struct pipe_vertex_buffer *buffers);
 514 void *r600_create_vertex_elements(struct pipe_context *ctx,
 515                                   unsigned count,
 516                                   const struct pipe_vertex_element *elements);
 517 void r600_delete_vertex_element(struct pipe_context *ctx, void *state);
 518 void r600_bind_blend_state(struct pipe_context *ctx, void *state);
 519 void r600_set_blend_color(struct pipe_context *ctx,
 520                           const struct pipe_blend_color *state);
 521 void r600_bind_dsa_state(struct pipe_context *ctx, void *state);
 522 void r600_set_max_scissor(struct r600_context *rctx);
 523 void r600_bind_rs_state(struct pipe_context *ctx, void *state);
 524 void r600_delete_rs_state(struct pipe_context *ctx, void *state);
 525 void r600_sampler_view_destroy(struct pipe_context *ctx,
 526                                struct pipe_sampler_view *state);
 527 void r600_delete_state(struct pipe_context *ctx, void *state);
 528 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
 529 void *r600_create_shader_state_ps(struct pipe_context *ctx,
 530                    const struct pipe_shader_state *state);
 531 void *r600_create_shader_state_vs(struct pipe_context *ctx,
 532                    const struct pipe_shader_state *state);
 533 void r600_bind_ps_shader(struct pipe_context *ctx, void *state);
 534 void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
 535 void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
 536 void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
 537 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
 538 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 539                               struct pipe_constant_buffer *cb);
 540 struct pipe_stream_output_target *
 541 r600_create_so_target(struct pipe_context *ctx,
 542                       struct pipe_resource *buffer,
 543                       unsigned buffer_offset,
 544                       unsigned buffer_size);
 545 void r600_so_target_destroy(struct pipe_context *ctx,
 546                             struct pipe_stream_output_target *target);
 547 void r600_set_so_targets(struct pipe_context *ctx,
 548                          unsigned num_targets,
 549                          struct pipe_stream_output_target **targets,
 550                          unsigned append_bitmask);
 551 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
 552                                const struct pipe_stencil_ref *state);
 553 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 554 uint32_t r600_translate_stencil_op(int s_op);
 555 uint32_t r600_translate_fill(uint32_t func);
 556 unsigned r600_tex_wrap(unsigned wrap);
 557 unsigned r600_tex_filter(unsigned filter);
 558 unsigned r600_tex_mipfilter(unsigned filter);
 559 unsigned r600_tex_compare(unsigned compare);
 560
 561 /*
 562  * Helpers for building command buffers
 563  */
 564
 565 #define PKT3_SET_CONFIG_REG     0x68
 566 #define PKT3_SET_CONTEXT_REG    0x69
 567 #define PKT3_SET_CTL_CONST      0x6F
 568 #define PKT3_SET_LOOP_CONST                    0x6C
 569
 570 #define R600_CONFIG_REG_OFFSET  0x08000
 571 #define R600_CONTEXT_REG_OFFSET 0x28000
 572 #define R600_CTL_CONST_OFFSET   0x3CFF0
 573 #define R600_LOOP_CONST_OFFSET                 0X0003E200
 574 #define EG_LOOP_CONST_OFFSET               0x0003A200
 575
 576 #define PKT_TYPE_S(x)                   (((x) & 0x3) << 30)
 577 #define PKT_COUNT_S(x)                  (((x) & 0x3FFF) << 16)
 578 #define PKT3_IT_OPCODE_S(x)             (((x) & 0xFF) << 8)
 579 #define PKT3_PREDICATE(x)               (((x) >> 0) & 0x1)
 580 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
 581
 582 static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value)
 583 {
 584         cb->buf[cb->atom.num_dw++] = value;
 585 }
 586
 587 static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 588 {
 589         assert(reg < R600_CONTEXT_REG_OFFSET);
 590         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 591         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
 592         cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
 593 }
 594
 595 /**
 596  * Needs cb->pkt_flags set to  RADEON_CP_PACKET3_COMPUTE_MODE for compute
 597  * shaders.
 598  */
 599 static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 600 {
 601         assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
 602         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 603         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
 604         cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
 605 }
 606
 607 /**
 608  * Needs cb->pkt_flags set to  RADEON_CP_PACKET3_COMPUTE_MODE for compute
 609  * shaders.
 610  */
 611 static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 612 {
 613         assert(reg >= R600_CTL_CONST_OFFSET);
 614         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 615         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
 616         cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
 617 }
 618
 619 static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 620 {
 621         assert(reg >= R600_LOOP_CONST_OFFSET);
 622         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 623         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
 624         cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
 625 }
 626
 627 /**
 628  * Needs cb->pkt_flags set to  RADEON_CP_PACKET3_COMPUTE_MODE for compute
 629  * shaders.
 630  */
 631 static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 632 {
 633         assert(reg >= EG_LOOP_CONST_OFFSET);
 634         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 635         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
 636         cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
 637 }
 638
 639 static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 640 {
 641         r600_store_config_reg_seq(cb, reg, 1);
 642         r600_store_value(cb, value);
 643 }
 644
 645 static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 646 {
 647         r600_store_context_reg_seq(cb, reg, 1);
 648         r600_store_value(cb, value);
 649 }
 650
 651 static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 652 {
 653         r600_store_ctl_const_seq(cb, reg, 1);
 654         r600_store_value(cb, value);
 655 }
 656
 657 static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 658 {
 659         r600_store_loop_const_seq(cb, reg, 1);
 660         r600_store_value(cb, value);
 661 }
 662
 663 static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 664 {
 665         eg_store_loop_const_seq(cb, reg, 1);
 666         r600_store_value(cb, value);
 667 }
 668
 669 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags);
 670 void r600_release_command_buffer(struct r600_command_buffer *cb);
 671
 672 /*
 673  * Helpers for emitting state into a command stream directly.
 674  */
 675
 676 static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo,
 677                                              enum radeon_bo_usage usage)
 678 {
 679         assert(usage);
 680         return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4;
 681 }
 682
 683 static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value)
 684 {
 685         cs->buf[cs->cdw++] = value;
 686 }
 687
 688 static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 689 {
 690         assert(reg < R600_CONTEXT_REG_OFFSET);
 691         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 692         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
 693         cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
 694 }
 695
 696 static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 697 {
 698         assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
 699         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 700         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
 701         cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
 702 }
 703
 704 static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 705 {
 706         assert(reg >= R600_CTL_CONST_OFFSET);
 707         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 708         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
 709         cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
 710 }
 711
 712 static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 713 {
 714         r600_write_config_reg_seq(cs, reg, 1);
 715         r600_write_value(cs, value);
 716 }
 717
 718 static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 719 {
 720         r600_write_context_reg_seq(cs, reg, 1);
 721         r600_write_value(cs, value);
 722 }
 723
 724 static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 725 {
 726         r600_write_ctl_const_seq(cs, reg, 1);
 727         r600_write_value(cs, value);
 728 }
 729
 730 /*
 731  * common helpers
 732  */
 733 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
 734 {
 735         return value * (1 << frac_bits);
 736 }
 737 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
 738
 739 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 740 {
 741         if (filter <= 1)   return 0;
 742         if (filter <= 2)   return 1;
 743         if (filter <= 4)   return 2;
 744         if (filter <= 8)   return 3;
 745          /* else */        return 4;
 746 }
 747
 748 /* 12.4 fixed-point */
 749 static INLINE unsigned r600_pack_float_12p4(float x)
 750 {
 751         return x <= 0    ? 0 :
 752                x >= 4096 ? 0xffff : x * 16;
 753 }
 754
 755 static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource)
 756 {
 757         struct r600_screen *rscreen = (struct r600_screen*)screen;
 758         struct r600_resource *rresource = (struct r600_resource*)resource;
 759
 760         return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);
 761 }
 762
 763 #endif