2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "util/u_slab.h"
31 #include "r600_shader.h"
32 #include "r600_resource.h"
34 #define R600_MAX_CONST_BUFFERS 2
35 #define R600_MAX_CONST_BUFFER_SIZE 4096
37 #ifdef PIPE_ARCH_BIG_ENDIAN
38 #define R600_BIG_ENDIAN 1
40 #define R600_BIG_ENDIAN 0
43 enum r600_atom_flags {
44 /* When set, atoms are added at the beginning of the dirty list
45 * instead of the end. */
49 /* This encapsulates a state or an operation which can emitted into the GPU
50 * command stream. It's not limited to states only, it can be used for anything
51 * that wants to write commands into the CS (e.g. cache flushes). */
53 void (*emit)(struct r600_context *ctx, struct r600_atom *state);
56 enum r600_atom_flags flags;
59 struct list_head head;
62 /* This is an atom containing GPU commands that never change.
63 * This is supposed to be copied directly into the CS. */
64 struct r600_command_buffer {
65 struct r600_atom atom;
70 struct r600_surface_sync_cmd {
71 struct r600_atom atom;
72 unsigned flush_flags; /* CP_COHER_CNTL */
75 struct r600_db_misc_state {
76 struct r600_atom atom;
77 bool occlusion_query_enabled;
78 bool flush_depthstencil_enabled;
81 enum r600_pipe_state_id {
82 R600_PIPE_STATE_BLEND = 0,
83 R600_PIPE_STATE_BLEND_COLOR,
84 R600_PIPE_STATE_CONFIG,
85 R600_PIPE_STATE_SEAMLESS_CUBEMAP,
87 R600_PIPE_STATE_SCISSOR,
88 R600_PIPE_STATE_VIEWPORT,
89 R600_PIPE_STATE_RASTERIZER,
91 R600_PIPE_STATE_FRAMEBUFFER,
93 R600_PIPE_STATE_STENCIL_REF,
94 R600_PIPE_STATE_PS_SHADER,
95 R600_PIPE_STATE_VS_SHADER,
96 R600_PIPE_STATE_CONSTANT,
97 R600_PIPE_STATE_SAMPLER,
98 R600_PIPE_STATE_RESOURCE,
99 R600_PIPE_STATE_POLYGON_OFFSET,
100 R600_PIPE_STATE_FETCH_SHADER,
104 struct r600_pipe_fences {
105 struct r600_resource *bo;
108 /* linked list of preallocated blocks */
109 struct list_head blocks;
110 /* linked list of freed fences */
111 struct list_head pool;
116 struct pipe_screen screen;
117 struct radeon_winsys *ws;
119 enum chip_class chip_class;
120 struct radeon_info info;
121 struct r600_tiling_info tiling_info;
122 struct util_slab_mempool pool_buffers;
123 struct r600_pipe_fences fences;
125 unsigned num_contexts;
126 bool use_surface_alloc;
128 /* for thread-safe write accessing to num_contexts */
129 pipe_mutex mutex_num_contexts;
132 struct r600_pipe_sampler_view {
133 struct pipe_sampler_view base;
134 struct r600_pipe_resource_state state;
137 struct r600_pipe_rasterizer {
138 struct r600_pipe_state rstate;
141 unsigned sprite_coord_enable;
142 unsigned clip_plane_enable;
143 unsigned pa_sc_line_stipple;
144 unsigned pa_cl_clip_cntl;
150 struct r600_pipe_blend {
151 struct r600_pipe_state rstate;
152 unsigned cb_target_mask;
153 unsigned cb_color_control;
156 struct r600_pipe_dsa {
157 struct r600_pipe_state rstate;
164 struct r600_vertex_element
167 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS];
168 struct u_vbuf_elements *vmgr_elements;
169 struct r600_resource *fetch_shader;
171 struct r600_pipe_state rstate;
172 /* if offset is to big for fetch instructio we need to alterate
173 * offset of vertex buffer, record here the offset need to add
175 unsigned vbuffer_need_offset;
176 unsigned vbuffer_offset[PIPE_MAX_ATTRIBS];
179 struct r600_pipe_shader {
180 struct r600_shader shader;
181 struct r600_pipe_state rstate;
182 struct r600_resource *bo;
183 struct r600_resource *bo_fetch;
184 struct r600_vertex_element vertex_elements;
185 struct tgsi_token *tokens;
186 unsigned sprite_coord_enable;
188 unsigned pa_cl_vs_out_cntl;
189 struct pipe_stream_output_info so;
192 struct r600_pipe_sampler_state {
193 struct r600_pipe_state rstate;
194 boolean seamless_cube_map;
197 /* needed for blitter save */
198 #define NUM_TEX_UNITS 16
200 struct r600_textures_info {
201 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
202 struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS];
206 bool is_array_sampler[NUM_TEX_UNITS];
210 struct pipe_reference reference;
211 unsigned index; /* in the shared bo */
212 struct r600_resource *sleep_bo;
213 struct list_head head;
216 #define FENCE_BLOCK_SIZE 16
218 struct r600_fence_block {
219 struct r600_fence fences[FENCE_BLOCK_SIZE];
220 struct list_head head;
223 #define R600_CONSTANT_ARRAY_SIZE 256
224 #define R600_RESOURCE_ARRAY_SIZE 160
226 struct r600_stencil_ref
233 struct r600_context {
234 struct pipe_context context;
235 struct blitter_context *blitter;
236 enum radeon_family family;
237 enum chip_class chip_class;
238 boolean has_vertex_cache;
239 unsigned r6xx_num_clause_temp_gprs;
240 void *custom_dsa_flush;
241 struct r600_screen *screen;
242 struct radeon_winsys *ws;
243 struct r600_pipe_state *states[R600_PIPE_NSTATES];
244 struct r600_vertex_element *vertex_elements;
245 struct r600_pipe_resource_state fs_resource[PIPE_MAX_ATTRIBS];
246 struct pipe_framebuffer_state framebuffer;
247 unsigned cb_target_mask;
248 unsigned cb_color_control;
249 unsigned pa_sc_line_stipple;
250 unsigned pa_cl_clip_cntl;
251 /* for saving when using blitter */
252 struct pipe_stencil_ref stencil_ref;
253 struct pipe_viewport_state viewport;
254 struct pipe_clip_state clip;
255 struct r600_pipe_shader *ps_shader;
256 struct r600_pipe_shader *vs_shader;
257 struct r600_pipe_state vs_const_buffer;
258 struct r600_pipe_resource_state vs_const_buffer_resource[R600_MAX_CONST_BUFFERS];
259 struct r600_pipe_state ps_const_buffer;
260 struct r600_pipe_resource_state ps_const_buffer_resource[R600_MAX_CONST_BUFFERS];
261 struct r600_pipe_rasterizer *rasterizer;
262 struct r600_pipe_state vgt;
263 struct r600_pipe_state spi;
264 struct pipe_query *current_render_cond;
265 unsigned current_render_cond_mode;
266 struct pipe_query *saved_render_cond;
267 unsigned saved_render_cond_mode;
268 /* shader information */
270 unsigned sprite_coord_enable;
271 boolean export_16bpc;
273 boolean alpha_ref_dirty;
275 struct r600_textures_info vs_samplers;
276 struct r600_textures_info ps_samplers;
278 struct u_vbuf *vbuf_mgr;
279 struct util_slab_mempool pool_transfers;
280 boolean have_depth_texture, have_depth_fb;
282 unsigned default_ps_gprs, default_vs_gprs;
284 /* States based on r600_atom. */
285 struct list_head dirty_states;
286 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
287 struct r600_surface_sync_cmd surface_sync_cmd;
288 struct r600_atom r6xx_flush_and_inv_cmd;
289 struct r600_db_misc_state db_misc_state;
291 /* Below are variables from the old r600_context.
293 struct radeon_winsys_cs *cs;
295 struct r600_range *range;
297 struct r600_block **blocks;
298 struct list_head dirty;
299 struct list_head resource_dirty;
300 struct list_head enable_list;
301 unsigned pm4_dirty_cdwords;
302 unsigned ctx_pm4_ndwords;
304 /* The list of active queries. Only one query of each type can be active. */
305 int num_occlusion_queries;
307 /* Manage queries in two separate groups:
308 * The timer ones and the others (streamout, occlusion).
310 * We do this because we should only suspend non-timer queries for u_blitter,
311 * and later if the non-timer queries are suspended, the context flush should
312 * only suspend and resume the timer queries. */
313 struct list_head active_timer_queries;
314 unsigned num_cs_dw_timer_queries_suspend;
315 struct list_head active_nontimer_queries;
316 unsigned num_cs_dw_nontimer_queries_suspend;
318 unsigned num_cs_dw_streamout_end;
320 unsigned backend_mask;
321 unsigned max_db; /* for OQ */
323 boolean predicate_drawing;
324 struct r600_range ps_resources;
325 struct r600_range vs_resources;
326 struct r600_range fs_resources;
327 int num_ps_resources, num_vs_resources, num_fs_resources;
329 unsigned num_so_targets;
330 struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS];
331 boolean streamout_start;
332 unsigned streamout_append_bitmask;
334 /* There is no scissor enable bit on r6xx, so we must use a workaround.
335 * These track the current scissor state. */
337 struct pipe_scissor_state scissor_state;
339 /* With rasterizer discard, there doesn't have to be a pixel shader.
340 * In that case, we bind this one: */
341 void *dummy_pixel_shader;
344 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
346 atom->emit(rctx, atom);
348 if (atom->head.next && atom->head.prev)
349 LIST_DELINIT(&atom->head);
352 static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state)
355 if (state->flags & EMIT_EARLY) {
356 LIST_ADD(&state->head, &rctx->dirty_states);
358 LIST_ADDTAIL(&state->head, &rctx->dirty_states);
364 /* evergreen_state.c */
365 void evergreen_init_state_functions(struct r600_context *rctx);
366 void evergreen_init_atom_start_cs(struct r600_context *rctx);
367 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
368 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
369 void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
370 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
371 void evergreen_polygon_offset_update(struct r600_context *rctx);
372 void evergreen_pipe_init_buffer_resource(struct r600_context *rctx,
373 struct r600_pipe_resource_state *rstate);
374 void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx,
375 struct r600_pipe_resource_state *rstate,
376 struct r600_resource *rbuffer,
377 unsigned offset, unsigned stride,
378 enum radeon_bo_usage usage);
379 boolean evergreen_is_format_supported(struct pipe_screen *screen,
380 enum pipe_format format,
381 enum pipe_texture_target target,
382 unsigned sample_count,
386 void r600_init_blit_functions(struct r600_context *rctx);
387 void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
388 void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
389 void r600_flush_depth_textures(struct r600_context *rctx);
392 bool r600_init_resource(struct r600_screen *rscreen,
393 struct r600_resource *res,
394 unsigned size, unsigned alignment,
395 unsigned bind, unsigned usage);
396 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
397 const struct pipe_resource *templ);
398 struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen,
399 void *ptr, unsigned bytes,
401 void r600_upload_index_buffer(struct r600_context *rctx,
402 struct pipe_index_buffer *ib, unsigned count);
406 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
410 void r600_init_query_functions(struct r600_context *rctx);
411 void r600_suspend_nontimer_queries(struct r600_context *ctx);
412 void r600_resume_nontimer_queries(struct r600_context *ctx);
413 void r600_suspend_timer_queries(struct r600_context *ctx);
414 void r600_resume_timer_queries(struct r600_context *ctx);
416 /* r600_resource.c */
417 void r600_init_context_resource_functions(struct r600_context *r600);
420 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader);
421 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
422 int r600_find_vs_semantic_index(struct r600_shader *vs,
423 struct r600_shader *ps, int id);
426 void r600_set_scissor_state(struct r600_context *rctx,
427 const struct pipe_scissor_state *state);
428 void r600_update_sampler_states(struct r600_context *rctx);
429 void r600_init_state_functions(struct r600_context *rctx);
430 void r600_init_atom_start_cs(struct r600_context *rctx);
431 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
432 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
433 void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
434 void *r600_create_db_flush_dsa(struct r600_context *rctx);
435 void r600_polygon_offset_update(struct r600_context *rctx);
436 void r600_pipe_init_buffer_resource(struct r600_context *rctx,
437 struct r600_pipe_resource_state *rstate);
438 void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
439 struct r600_resource *rbuffer,
440 unsigned offset, unsigned stride,
441 enum radeon_bo_usage usage);
442 void r600_adjust_gprs(struct r600_context *rctx);
443 boolean r600_is_format_supported(struct pipe_screen *screen,
444 enum pipe_format format,
445 enum pipe_texture_target target,
446 unsigned sample_count,
450 void r600_init_screen_texture_functions(struct pipe_screen *screen);
451 void r600_init_surface_functions(struct r600_context *r600);
452 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
453 const unsigned char *swizzle_view,
454 uint32_t *word4_p, uint32_t *yuv_format_p);
455 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
456 unsigned level, unsigned layer);
458 /* r600_translate.c */
459 void r600_translate_index_buffer(struct r600_context *r600,
460 struct pipe_index_buffer *ib,
463 /* r600_state_common.c */
464 void r600_init_atom(struct r600_atom *atom,
465 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
466 unsigned num_dw, enum r600_atom_flags flags);
467 void r600_init_common_atoms(struct r600_context *rctx);
468 unsigned r600_get_cb_flush_flags(struct r600_context *rctx);
469 void r600_texture_barrier(struct pipe_context *ctx);
470 void r600_set_index_buffer(struct pipe_context *ctx,
471 const struct pipe_index_buffer *ib);
472 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
473 const struct pipe_vertex_buffer *buffers);
474 void *r600_create_vertex_elements(struct pipe_context *ctx,
476 const struct pipe_vertex_element *elements);
477 void r600_delete_vertex_element(struct pipe_context *ctx, void *state);
478 void r600_bind_blend_state(struct pipe_context *ctx, void *state);
479 void r600_set_blend_color(struct pipe_context *ctx,
480 const struct pipe_blend_color *state);
481 void r600_bind_dsa_state(struct pipe_context *ctx, void *state);
482 void r600_set_max_scissor(struct r600_context *rctx);
483 void r600_bind_rs_state(struct pipe_context *ctx, void *state);
484 void r600_delete_rs_state(struct pipe_context *ctx, void *state);
485 void r600_sampler_view_destroy(struct pipe_context *ctx,
486 struct pipe_sampler_view *state);
487 void r600_delete_state(struct pipe_context *ctx, void *state);
488 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
489 void *r600_create_shader_state(struct pipe_context *ctx,
490 const struct pipe_shader_state *state);
491 void r600_bind_ps_shader(struct pipe_context *ctx, void *state);
492 void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
493 void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
494 void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
495 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
496 struct pipe_resource *buffer);
497 struct pipe_stream_output_target *
498 r600_create_so_target(struct pipe_context *ctx,
499 struct pipe_resource *buffer,
500 unsigned buffer_offset,
501 unsigned buffer_size);
502 void r600_so_target_destroy(struct pipe_context *ctx,
503 struct pipe_stream_output_target *target);
504 void r600_set_so_targets(struct pipe_context *ctx,
505 unsigned num_targets,
506 struct pipe_stream_output_target **targets,
507 unsigned append_bitmask);
508 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
509 const struct pipe_stencil_ref *state);
510 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
511 uint32_t r600_translate_stencil_op(int s_op);
512 uint32_t r600_translate_fill(uint32_t func);
513 unsigned r600_tex_wrap(unsigned wrap);
514 unsigned r600_tex_filter(unsigned filter);
515 unsigned r600_tex_mipfilter(unsigned filter);
516 unsigned r600_tex_compare(unsigned compare);
519 * Helpers for building command buffers
522 #define PKT3_SET_CONFIG_REG 0x68
523 #define PKT3_SET_CONTEXT_REG 0x69
524 #define PKT3_SET_CTL_CONST 0x6F
525 #define PKT3_SET_LOOP_CONST 0x6C
527 #define R600_CONFIG_REG_OFFSET 0x08000
528 #define R600_CONTEXT_REG_OFFSET 0x28000
529 #define R600_CTL_CONST_OFFSET 0x3CFF0
530 #define R600_LOOP_CONST_OFFSET 0X0003E200
531 #define EG_LOOP_CONST_OFFSET 0x0003A200
533 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
534 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
535 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
536 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
537 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
539 static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value)
541 cb->buf[cb->atom.num_dw++] = value;
544 static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
546 assert(reg < R600_CONTEXT_REG_OFFSET);
547 assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
548 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
549 cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
552 static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
554 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
555 assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
556 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
557 cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
560 static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
562 assert(reg >= R600_CTL_CONST_OFFSET);
563 assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
564 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
565 cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
568 static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
570 assert(reg >= R600_LOOP_CONST_OFFSET);
571 assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
572 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
573 cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
576 static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
578 assert(reg >= EG_LOOP_CONST_OFFSET);
579 assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
580 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
581 cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
584 static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
586 r600_store_config_reg_seq(cb, reg, 1);
587 r600_store_value(cb, value);
590 static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
592 r600_store_context_reg_seq(cb, reg, 1);
593 r600_store_value(cb, value);
596 static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
598 r600_store_ctl_const_seq(cb, reg, 1);
599 r600_store_value(cb, value);
602 static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
604 r600_store_loop_const_seq(cb, reg, 1);
605 r600_store_value(cb, value);
608 static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
610 eg_store_loop_const_seq(cb, reg, 1);
611 r600_store_value(cb, value);
614 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags);
615 void r600_release_command_buffer(struct r600_command_buffer *cb);
618 * Helpers for emitting state into a command stream directly.
621 static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo,
622 enum radeon_bo_usage usage)
625 return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4;
628 static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value)
630 cs->buf[cs->cdw++] = value;
633 static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
635 assert(reg < R600_CONTEXT_REG_OFFSET);
636 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
637 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
638 cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
641 static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
643 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
644 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
645 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
646 cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
649 static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
651 assert(reg >= R600_CTL_CONST_OFFSET);
652 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
653 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
654 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
657 static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
659 r600_write_config_reg_seq(cs, reg, 1);
660 r600_write_value(cs, value);
663 static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
665 r600_write_context_reg_seq(cs, reg, 1);
666 r600_write_value(cs, value);
669 static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
671 r600_write_ctl_const_seq(cs, reg, 1);
672 r600_write_value(cs, value);
678 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
680 return value * (1 << frac_bits);
682 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
684 static inline unsigned r600_tex_aniso_filter(unsigned filter)
686 if (filter <= 1) return 0;
687 if (filter <= 2) return 1;
688 if (filter <= 4) return 2;
689 if (filter <= 8) return 3;
693 /* 12.4 fixed-point */
694 static INLINE unsigned r600_pack_float_12p4(float x)
697 x >= 4096 ? 0xffff : x * 16;
700 static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource)
702 struct r600_screen *rscreen = (struct r600_screen*)screen;
703 struct r600_resource *rresource = (struct r600_resource*)resource;
705 return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);