src/gallium/drivers/r600/r600_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef R600_PIPE_H
  27 #define R600_PIPE_H
  28
  29 #include "../../winsys/radeon/drm/radeon_winsys.h"
  30
  31 #include "pipe/p_state.h"
  32 #include "pipe/p_screen.h"
  33 #include "pipe/p_context.h"
  34 #include "util/u_math.h"
  35 #include "util/u_slab.h"
  36 #include "util/u_vbuf.h"
  37 #include "r600.h"
  38 #include "r600_public.h"
  39 #include "r600_shader.h"
  40 #include "r600_resource.h"
  41
  42 #define R600_MAX_CONST_BUFFERS 2
  43 #define R600_MAX_CONST_BUFFER_SIZE 4096
  44
  45 #ifdef PIPE_ARCH_BIG_ENDIAN
  46 #define R600_BIG_ENDIAN 1
  47 #else
  48 #define R600_BIG_ENDIAN 0
  49 #endif
  50
  51 enum r600_atom_flags {
  52         /* When set, atoms are added at the beginning of the dirty list
  53          * instead of the end. */
  54         EMIT_EARLY = (1 << 0)
  55 };
  56
  57 /* This encapsulates a state or an operation which can emitted into the GPU
  58  * command stream. It's not limited to states only, it can be used for anything
  59  * that wants to write commands into the CS (e.g. cache flushes). */
  60 struct r600_atom {
  61         void (*emit)(struct r600_context *ctx, struct r600_atom *state);
  62
  63         unsigned                num_dw;
  64         enum r600_atom_flags    flags;
  65         bool                    dirty;
  66
  67         struct list_head        head;
  68 };
  69
  70 /* This is an atom containing GPU commands that never change.
  71  * This is supposed to be copied directly into the CS. */
  72 struct r600_command_buffer {
  73         struct r600_atom atom;
  74         uint32_t *buf;
  75         unsigned max_num_dw;
  76 };
  77
  78 struct r600_atom_surface_sync {
  79         struct r600_atom atom;
  80         unsigned flush_flags; /* CP_COHER_CNTL */
  81 };
  82
  83 struct r600_atom_db_misc_state {
  84         struct r600_atom atom;
  85         bool occlusion_query_enabled;
  86         bool flush_depthstencil_enabled;
  87 };
  88
  89 enum r600_pipe_state_id {
  90         R600_PIPE_STATE_BLEND = 0,
  91         R600_PIPE_STATE_BLEND_COLOR,
  92         R600_PIPE_STATE_CONFIG,
  93         R600_PIPE_STATE_SEAMLESS_CUBEMAP,
  94         R600_PIPE_STATE_CLIP,
  95         R600_PIPE_STATE_SCISSOR,
  96         R600_PIPE_STATE_VIEWPORT,
  97         R600_PIPE_STATE_RASTERIZER,
  98         R600_PIPE_STATE_VGT,
  99         R600_PIPE_STATE_FRAMEBUFFER,
 100         R600_PIPE_STATE_DSA,
 101         R600_PIPE_STATE_STENCIL_REF,
 102         R600_PIPE_STATE_PS_SHADER,
 103         R600_PIPE_STATE_VS_SHADER,
 104         R600_PIPE_STATE_CONSTANT,
 105         R600_PIPE_STATE_SAMPLER,
 106         R600_PIPE_STATE_RESOURCE,
 107         R600_PIPE_STATE_POLYGON_OFFSET,
 108         R600_PIPE_STATE_FETCH_SHADER,
 109         R600_PIPE_NSTATES
 110 };
 111
 112 struct r600_pipe_fences {
 113         struct r600_resource            *bo;
 114         unsigned                        *data;
 115         unsigned                        next_index;
 116         /* linked list of preallocated blocks */
 117         struct list_head                blocks;
 118         /* linked list of freed fences */
 119         struct list_head                pool;
 120         pipe_mutex                      mutex;
 121 };
 122
 123 struct r600_screen {
 124         struct pipe_screen              screen;
 125         struct radeon_winsys            *ws;
 126         unsigned                        family;
 127         enum chip_class                 chip_class;
 128         struct radeon_info              info;
 129         struct r600_tiling_info         tiling_info;
 130         struct util_slab_mempool        pool_buffers;
 131         struct r600_pipe_fences         fences;
 132
 133         unsigned                        num_contexts;
 134         bool                            use_surface_alloc;
 135
 136         /* for thread-safe write accessing to num_contexts */
 137         pipe_mutex                      mutex_num_contexts;
 138 };
 139
 140 struct r600_pipe_sampler_view {
 141         struct pipe_sampler_view        base;
 142         struct r600_pipe_resource_state         state;
 143 };
 144
 145 struct r600_pipe_rasterizer {
 146         struct r600_pipe_state          rstate;
 147         boolean                         flatshade;
 148         boolean                         two_side;
 149         unsigned                        sprite_coord_enable;
 150         unsigned                        clip_plane_enable;
 151         unsigned                        pa_sc_line_stipple;
 152         unsigned                        pa_cl_clip_cntl;
 153         float                           offset_units;
 154         float                           offset_scale;
 155         bool                            scissor_enable;
 156 };
 157
 158 struct r600_pipe_blend {
 159         struct r600_pipe_state          rstate;
 160         unsigned                        cb_target_mask;
 161         unsigned                        cb_color_control;
 162 };
 163
 164 struct r600_pipe_dsa {
 165         struct r600_pipe_state          rstate;
 166         unsigned                        alpha_ref;
 167         ubyte                           valuemask[2];
 168         ubyte                           writemask[2];
 169         bool                            is_flush;
 170 };
 171
 172 struct r600_vertex_element
 173 {
 174         unsigned                        count;
 175         struct pipe_vertex_element      elements[PIPE_MAX_ATTRIBS];
 176         struct u_vbuf_elements          *vmgr_elements;
 177         struct r600_resource            *fetch_shader;
 178         unsigned                        fs_size;
 179         struct r600_pipe_state          rstate;
 180         /* if offset is to big for fetch instructio we need to alterate
 181          * offset of vertex buffer, record here the offset need to add
 182          */
 183         unsigned                        vbuffer_need_offset;
 184         unsigned                        vbuffer_offset[PIPE_MAX_ATTRIBS];
 185 };
 186
 187 struct r600_pipe_shader {
 188         struct r600_shader              shader;
 189         struct r600_pipe_state          rstate;
 190         struct r600_resource            *bo;
 191         struct r600_resource            *bo_fetch;
 192         struct r600_vertex_element      vertex_elements;
 193         struct tgsi_token               *tokens;
 194         unsigned        sprite_coord_enable;
 195         unsigned        flatshade;
 196         unsigned        pa_cl_vs_out_cntl;
 197         struct pipe_stream_output_info  so;
 198 };
 199
 200 struct r600_pipe_sampler_state {
 201         struct r600_pipe_state          rstate;
 202         boolean seamless_cube_map;
 203 };
 204
 205 /* needed for blitter save */
 206 #define NUM_TEX_UNITS 16
 207
 208 struct r600_textures_info {
 209         struct r600_pipe_sampler_view   *views[NUM_TEX_UNITS];
 210         struct r600_pipe_sampler_state  *samplers[NUM_TEX_UNITS];
 211         unsigned                        n_views;
 212         unsigned                        n_samplers;
 213         bool                            samplers_dirty;
 214         bool                            is_array_sampler[NUM_TEX_UNITS];
 215 };
 216
 217 struct r600_fence {
 218         struct pipe_reference           reference;
 219         unsigned                        index; /* in the shared bo */
 220         struct r600_resource            *sleep_bo;
 221         struct list_head                head;
 222 };
 223
 224 #define FENCE_BLOCK_SIZE 16
 225
 226 struct r600_fence_block {
 227         struct r600_fence               fences[FENCE_BLOCK_SIZE];
 228         struct list_head                head;
 229 };
 230
 231 #define R600_CONSTANT_ARRAY_SIZE 256
 232 #define R600_RESOURCE_ARRAY_SIZE 160
 233
 234 struct r600_stencil_ref
 235 {
 236         ubyte ref_value[2];
 237         ubyte valuemask[2];
 238         ubyte writemask[2];
 239 };
 240
 241 struct r600_context {
 242         struct pipe_context             context;
 243         struct blitter_context          *blitter;
 244         enum radeon_family              family;
 245         enum chip_class                 chip_class;
 246         unsigned                        r6xx_num_clause_temp_gprs;
 247         void                            *custom_dsa_flush;
 248         struct r600_screen              *screen;
 249         struct radeon_winsys            *ws;
 250         struct r600_pipe_state          *states[R600_PIPE_NSTATES];
 251         struct r600_vertex_element      *vertex_elements;
 252         struct r600_pipe_resource_state fs_resource[PIPE_MAX_ATTRIBS];
 253         struct pipe_framebuffer_state   framebuffer;
 254         unsigned                        cb_target_mask;
 255         unsigned                        cb_color_control;
 256         unsigned                        pa_sc_line_stipple;
 257         unsigned                        pa_cl_clip_cntl;
 258         /* for saving when using blitter */
 259         struct pipe_stencil_ref         stencil_ref;
 260         struct pipe_viewport_state      viewport;
 261         struct pipe_clip_state          clip;
 262         struct r600_pipe_shader         *ps_shader;
 263         struct r600_pipe_shader         *vs_shader;
 264         struct r600_pipe_state          vs_const_buffer;
 265         struct r600_pipe_resource_state         vs_const_buffer_resource[R600_MAX_CONST_BUFFERS];
 266         struct r600_pipe_state          ps_const_buffer;
 267         struct r600_pipe_resource_state         ps_const_buffer_resource[R600_MAX_CONST_BUFFERS];
 268         struct r600_pipe_rasterizer     *rasterizer;
 269         struct r600_pipe_state          vgt;
 270         struct r600_pipe_state          spi;
 271         struct pipe_query               *current_render_cond;
 272         unsigned                        current_render_cond_mode;
 273         struct pipe_query               *saved_render_cond;
 274         unsigned                        saved_render_cond_mode;
 275         /* shader information */
 276         boolean                         two_side;
 277         unsigned                        sprite_coord_enable;
 278         boolean                         export_16bpc;
 279         unsigned                        alpha_ref;
 280         boolean                         alpha_ref_dirty;
 281         unsigned                        nr_cbufs;
 282         struct r600_textures_info       vs_samplers;
 283         struct r600_textures_info       ps_samplers;
 284
 285         struct u_vbuf                   *vbuf_mgr;
 286         struct util_slab_mempool        pool_transfers;
 287         boolean                         have_depth_texture, have_depth_fb;
 288
 289         unsigned default_ps_gprs, default_vs_gprs;
 290
 291         /* States based on r600_state. */
 292         struct list_head                dirty_states;
 293         struct r600_command_buffer      atom_start_cs; /* invariant state mostly */
 294         struct r600_atom_surface_sync   atom_surface_sync;
 295         struct r600_atom                atom_r6xx_flush_and_inv;
 296         struct r600_atom_db_misc_state  atom_db_misc_state;
 297
 298         /* Below are variables from the old r600_context.
 299          */
 300         struct radeon_winsys_cs *cs;
 301
 302         struct r600_range       *range;
 303         unsigned                nblocks;
 304         struct r600_block       **blocks;
 305         struct list_head        dirty;
 306         struct list_head        resource_dirty;
 307         struct list_head        enable_list;
 308         unsigned                pm4_dirty_cdwords;
 309         unsigned                ctx_pm4_ndwords;
 310
 311         /* The list of active queries. Only one query of each type can be active. */
 312         int                     num_occlusion_queries;
 313
 314         /* Manage queries in two separate groups:
 315          * The timer ones and the others (streamout, occlusion).
 316          *
 317          * We do this because we should only suspend non-timer queries for u_blitter,
 318          * and later if the non-timer queries are suspended, the context flush should
 319          * only suspend and resume the timer queries. */
 320         struct list_head        active_timer_queries;
 321         unsigned                num_cs_dw_timer_queries_suspend;
 322         struct list_head        active_nontimer_queries;
 323         unsigned                num_cs_dw_nontimer_queries_suspend;
 324
 325         unsigned                num_cs_dw_streamout_end;
 326
 327         unsigned                backend_mask;
 328         unsigned                max_db; /* for OQ */
 329         unsigned                flags;
 330         boolean                 predicate_drawing;
 331         struct r600_range       ps_resources;
 332         struct r600_range       vs_resources;
 333         struct r600_range       fs_resources;
 334         int                     num_ps_resources, num_vs_resources, num_fs_resources;
 335
 336         unsigned                num_so_targets;
 337         struct r600_so_target   *so_targets[PIPE_MAX_SO_BUFFERS];
 338         boolean                 streamout_start;
 339         unsigned                streamout_append_bitmask;
 340
 341         /* There is no scissor enable bit on r6xx, so we must use a workaround.
 342          * These track the current scissor state. */
 343         bool                    scissor_enable;
 344         struct pipe_scissor_state scissor_state;
 345 };
 346
 347 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
 348 {
 349         atom->emit(rctx, atom);
 350         atom->dirty = false;
 351         if (atom->head.next && atom->head.prev)
 352                 LIST_DELINIT(&atom->head);
 353 }
 354
 355 static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state)
 356 {
 357         if (!state->dirty) {
 358                 if (state->flags & EMIT_EARLY) {
 359                         LIST_ADD(&state->head, &rctx->dirty_states);
 360                 } else {
 361                         LIST_ADDTAIL(&state->head, &rctx->dirty_states);
 362                 }
 363                 state->dirty = true;
 364         }
 365 }
 366
 367 /* evergreen_state.c */
 368 void evergreen_init_state_functions(struct r600_context *rctx);
 369 void evergreen_init_atom_start_cs(struct r600_context *rctx);
 370 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 371 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 372 void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
 373 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
 374 void evergreen_polygon_offset_update(struct r600_context *rctx);
 375 void evergreen_pipe_init_buffer_resource(struct r600_context *rctx,
 376                                          struct r600_pipe_resource_state *rstate);
 377 void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx,
 378                                         struct r600_pipe_resource_state *rstate,
 379                                         struct r600_resource *rbuffer,
 380                                         unsigned offset, unsigned stride,
 381                                         enum radeon_bo_usage usage);
 382 boolean evergreen_is_format_supported(struct pipe_screen *screen,
 383                                       enum pipe_format format,
 384                                       enum pipe_texture_target target,
 385                                       unsigned sample_count,
 386                                       unsigned usage);
 387
 388 /* r600_blit.c */
 389 void r600_init_blit_functions(struct r600_context *rctx);
 390 void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
 391 void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
 392 void r600_flush_depth_textures(struct r600_context *rctx);
 393
 394 /* r600_buffer.c */
 395 bool r600_init_resource(struct r600_screen *rscreen,
 396                         struct r600_resource *res,
 397                         unsigned size, unsigned alignment,
 398                         unsigned bind, unsigned usage);
 399 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 400                                          const struct pipe_resource *templ);
 401 struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen,
 402                                               void *ptr, unsigned bytes,
 403                                               unsigned bind);
 404 void r600_upload_index_buffer(struct r600_context *rctx,
 405                               struct pipe_index_buffer *ib, unsigned count);
 406
 407
 408 /* r600_pipe.c */
 409 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 410                 unsigned flags);
 411
 412 /* r600_query.c */
 413 void r600_init_query_functions(struct r600_context *rctx);
 414 void r600_suspend_nontimer_queries(struct r600_context *ctx);
 415 void r600_resume_nontimer_queries(struct r600_context *ctx);
 416 void r600_suspend_timer_queries(struct r600_context *ctx);
 417 void r600_resume_timer_queries(struct r600_context *ctx);
 418
 419 /* r600_resource.c */
 420 void r600_init_context_resource_functions(struct r600_context *r600);
 421
 422 /* r600_shader.c */
 423 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 424 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 425 int r600_find_vs_semantic_index(struct r600_shader *vs,
 426                                 struct r600_shader *ps, int id);
 427
 428 /* r600_state.c */
 429 void r600_set_scissor_state(struct r600_context *rctx,
 430                             const struct pipe_scissor_state *state);
 431 void r600_update_sampler_states(struct r600_context *rctx);
 432 void r600_init_state_functions(struct r600_context *rctx);
 433 void r600_init_atom_start_cs(struct r600_context *rctx);
 434 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 435 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 436 void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
 437 void *r600_create_db_flush_dsa(struct r600_context *rctx);
 438 void r600_polygon_offset_update(struct r600_context *rctx);
 439 void r600_pipe_init_buffer_resource(struct r600_context *rctx,
 440                                     struct r600_pipe_resource_state *rstate);
 441 void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
 442                                    struct r600_resource *rbuffer,
 443                                    unsigned offset, unsigned stride,
 444                                    enum radeon_bo_usage usage);
 445 void r600_adjust_gprs(struct r600_context *rctx);
 446 boolean r600_is_format_supported(struct pipe_screen *screen,
 447                                  enum pipe_format format,
 448                                  enum pipe_texture_target target,
 449                                  unsigned sample_count,
 450                                  unsigned usage);
 451
 452 /* r600_texture.c */
 453 void r600_init_screen_texture_functions(struct pipe_screen *screen);
 454 void r600_init_surface_functions(struct r600_context *r600);
 455 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
 456                                   const unsigned char *swizzle_view,
 457                                   uint32_t *word4_p, uint32_t *yuv_format_p);
 458 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
 459                                         unsigned level, unsigned layer);
 460
 461 /* r600_translate.c */
 462 void r600_translate_index_buffer(struct r600_context *r600,
 463                                  struct pipe_index_buffer *ib,
 464                                  unsigned count);
 465
 466 /* r600_state_common.c */
 467 void r600_init_atom(struct r600_atom *atom,
 468                     void (*emit)(struct r600_context *ctx, struct r600_atom *state),
 469                     unsigned num_dw, enum r600_atom_flags flags);
 470 void r600_init_common_atoms(struct r600_context *rctx);
 471 unsigned r600_get_cb_flush_flags(struct r600_context *rctx);
 472 void r600_texture_barrier(struct pipe_context *ctx);
 473 void r600_set_index_buffer(struct pipe_context *ctx,
 474                            const struct pipe_index_buffer *ib);
 475 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 476                              const struct pipe_vertex_buffer *buffers);
 477 void *r600_create_vertex_elements(struct pipe_context *ctx,
 478                                   unsigned count,
 479                                   const struct pipe_vertex_element *elements);
 480 void r600_delete_vertex_element(struct pipe_context *ctx, void *state);
 481 void r600_bind_blend_state(struct pipe_context *ctx, void *state);
 482 void r600_set_blend_color(struct pipe_context *ctx,
 483                           const struct pipe_blend_color *state);
 484 void r600_bind_dsa_state(struct pipe_context *ctx, void *state);
 485 void r600_set_max_scissor(struct r600_context *rctx);
 486 void r600_bind_rs_state(struct pipe_context *ctx, void *state);
 487 void r600_delete_rs_state(struct pipe_context *ctx, void *state);
 488 void r600_sampler_view_destroy(struct pipe_context *ctx,
 489                                struct pipe_sampler_view *state);
 490 void r600_delete_state(struct pipe_context *ctx, void *state);
 491 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
 492 void *r600_create_shader_state(struct pipe_context *ctx,
 493                                const struct pipe_shader_state *state);
 494 void r600_bind_ps_shader(struct pipe_context *ctx, void *state);
 495 void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
 496 void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
 497 void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
 498 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 499                               struct pipe_resource *buffer);
 500 struct pipe_stream_output_target *
 501 r600_create_so_target(struct pipe_context *ctx,
 502                       struct pipe_resource *buffer,
 503                       unsigned buffer_offset,
 504                       unsigned buffer_size);
 505 void r600_so_target_destroy(struct pipe_context *ctx,
 506                             struct pipe_stream_output_target *target);
 507 void r600_set_so_targets(struct pipe_context *ctx,
 508                          unsigned num_targets,
 509                          struct pipe_stream_output_target **targets,
 510                          unsigned append_bitmask);
 511 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
 512                                const struct pipe_stencil_ref *state);
 513 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 514 uint32_t r600_translate_stencil_op(int s_op);
 515 uint32_t r600_translate_fill(uint32_t func);
 516 unsigned r600_tex_wrap(unsigned wrap);
 517 unsigned r600_tex_filter(unsigned filter);
 518 unsigned r600_tex_mipfilter(unsigned filter);
 519 unsigned r600_tex_compare(unsigned compare);
 520
 521 /*
 522  * Helpers for building command buffers
 523  */
 524
 525 #define PKT3_SET_CONFIG_REG     0x68
 526 #define PKT3_SET_CONTEXT_REG    0x69
 527 #define PKT3_SET_CTL_CONST      0x6F
 528 #define PKT3_SET_LOOP_CONST                    0x6C
 529
 530 #define R600_CONFIG_REG_OFFSET  0x08000
 531 #define R600_CONTEXT_REG_OFFSET 0x28000
 532 #define R600_CTL_CONST_OFFSET   0x3CFF0
 533 #define R600_LOOP_CONST_OFFSET                 0X0003E200
 534 #define EG_LOOP_CONST_OFFSET               0x0003A200
 535
 536 #define PKT_TYPE_S(x)                   (((x) & 0x3) << 30)
 537 #define PKT_COUNT_S(x)                  (((x) & 0x3FFF) << 16)
 538 #define PKT3_IT_OPCODE_S(x)             (((x) & 0xFF) << 8)
 539 #define PKT3_PREDICATE(x)               (((x) >> 0) & 0x1)
 540 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
 541
 542 static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value)
 543 {
 544         cb->buf[cb->atom.num_dw++] = value;
 545 }
 546
 547 static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 548 {
 549         assert(reg < R600_CONTEXT_REG_OFFSET);
 550         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 551         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
 552         cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
 553 }
 554
 555 static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 556 {
 557         assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
 558         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 559         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
 560         cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
 561 }
 562
 563 static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 564 {
 565         assert(reg >= R600_CTL_CONST_OFFSET);
 566         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 567         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
 568         cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
 569 }
 570
 571 static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 572 {
 573         assert(reg >= R600_LOOP_CONST_OFFSET);
 574         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 575         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
 576         cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
 577 }
 578
 579 static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 580 {
 581         assert(reg >= EG_LOOP_CONST_OFFSET);
 582         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 583         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
 584         cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
 585 }
 586
 587 static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 588 {
 589         r600_store_config_reg_seq(cb, reg, 1);
 590         r600_store_value(cb, value);
 591 }
 592
 593 static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 594 {
 595         r600_store_context_reg_seq(cb, reg, 1);
 596         r600_store_value(cb, value);
 597 }
 598
 599 static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 600 {
 601         r600_store_ctl_const_seq(cb, reg, 1);
 602         r600_store_value(cb, value);
 603 }
 604
 605 static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 606 {
 607         r600_store_loop_const_seq(cb, reg, 1);
 608         r600_store_value(cb, value);
 609 }
 610
 611 static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 612 {
 613         eg_store_loop_const_seq(cb, reg, 1);
 614         r600_store_value(cb, value);
 615 }
 616
 617 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags);
 618 void r600_release_command_buffer(struct r600_command_buffer *cb);
 619
 620 /*
 621  * Helpers for emitting state into a command stream directly.
 622  */
 623
 624 static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value)
 625 {
 626         cs->buf[cs->cdw++] = value;
 627 }
 628
 629 static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 630 {
 631         assert(reg < R600_CONTEXT_REG_OFFSET);
 632         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 633         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
 634         cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
 635 }
 636
 637 static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 638 {
 639         assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
 640         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 641         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
 642         cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
 643 }
 644
 645 static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 646 {
 647         assert(reg >= R600_CTL_CONST_OFFSET);
 648         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 649         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
 650         cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
 651 }
 652
 653 static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 654 {
 655         r600_write_config_reg_seq(cs, reg, 1);
 656         r600_write_value(cs, value);
 657 }
 658
 659 static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 660 {
 661         r600_write_context_reg_seq(cs, reg, 1);
 662         r600_write_value(cs, value);
 663 }
 664
 665 static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 666 {
 667         r600_write_ctl_const_seq(cs, reg, 1);
 668         r600_write_value(cs, value);
 669 }
 670
 671 /*
 672  * common helpers
 673  */
 674 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
 675 {
 676         return value * (1 << frac_bits);
 677 }
 678 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
 679
 680 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 681 {
 682         if (filter <= 1)   return 0;
 683         if (filter <= 2)   return 1;
 684         if (filter <= 4)   return 2;
 685         if (filter <= 8)   return 3;
 686          /* else */        return 4;
 687 }
 688
 689 /* 12.4 fixed-point */
 690 static INLINE unsigned r600_pack_float_12p4(float x)
 691 {
 692         return x <= 0    ? 0 :
 693                x >= 4096 ? 0xffff : x * 16;
 694 }
 695
 696 #endif