r600g: rework and consolidate stencilref state setting
[profile/ivi/mesa.git] / src / gallium / drivers / r600 / r600_pipe.h
1 /*
2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * on the rights to use, copy, modify, merge, publish, distribute, sub
8  * license, and/or sell copies of the Software, and to permit persons to whom
9  * the Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors:
24  *      Jerome Glisse
25  */
26 #ifndef R600_PIPE_H
27 #define R600_PIPE_H
28
29 #include "../../winsys/radeon/drm/radeon_winsys.h"
30
31 #include "pipe/p_state.h"
32 #include "pipe/p_screen.h"
33 #include "pipe/p_context.h"
34 #include "util/u_math.h"
35 #include "util/u_slab.h"
36 #include "util/u_vbuf.h"
37 #include "r600.h"
38 #include "r600_public.h"
39 #include "r600_shader.h"
40 #include "r600_resource.h"
41
42 #define R600_MAX_CONST_BUFFERS 2
43 #define R600_MAX_CONST_BUFFER_SIZE 4096
44
45 #ifdef PIPE_ARCH_BIG_ENDIAN
46 #define R600_BIG_ENDIAN 1
47 #else
48 #define R600_BIG_ENDIAN 0
49 #endif
50
51 enum r600_pipe_state_id {
52         R600_PIPE_STATE_BLEND = 0,
53         R600_PIPE_STATE_BLEND_COLOR,
54         R600_PIPE_STATE_CONFIG,
55         R600_PIPE_STATE_SEAMLESS_CUBEMAP,
56         R600_PIPE_STATE_CLIP,
57         R600_PIPE_STATE_SCISSOR,
58         R600_PIPE_STATE_VIEWPORT,
59         R600_PIPE_STATE_RASTERIZER,
60         R600_PIPE_STATE_VGT,
61         R600_PIPE_STATE_FRAMEBUFFER,
62         R600_PIPE_STATE_DSA,
63         R600_PIPE_STATE_STENCIL_REF,
64         R600_PIPE_STATE_PS_SHADER,
65         R600_PIPE_STATE_VS_SHADER,
66         R600_PIPE_STATE_CONSTANT,
67         R600_PIPE_STATE_SAMPLER,
68         R600_PIPE_STATE_RESOURCE,
69         R600_PIPE_STATE_POLYGON_OFFSET,
70         R600_PIPE_STATE_FETCH_SHADER,
71         R600_PIPE_NSTATES
72 };
73
74 struct r600_pipe_fences {
75         struct r600_resource            *bo;
76         unsigned                        *data;
77         unsigned                        next_index;
78         /* linked list of preallocated blocks */
79         struct list_head                blocks;
80         /* linked list of freed fences */
81         struct list_head                pool;
82         pipe_mutex                      mutex;
83 };
84
85 struct r600_screen {
86         struct pipe_screen              screen;
87         struct radeon_winsys            *ws;
88         unsigned                        family;
89         enum chip_class                 chip_class;
90         struct radeon_info              info;
91         struct r600_tiling_info         tiling_info;
92         struct util_slab_mempool        pool_buffers;
93         struct r600_pipe_fences         fences;
94
95         unsigned                        num_contexts;
96
97         /* for thread-safe write accessing to num_contexts */
98         pipe_mutex                      mutex_num_contexts;
99 };
100
101 struct r600_pipe_sampler_view {
102         struct pipe_sampler_view        base;
103         struct r600_pipe_resource_state         state;
104 };
105
106 struct r600_pipe_rasterizer {
107         struct r600_pipe_state          rstate;
108         boolean                         flatshade;
109         boolean                         two_side;
110         unsigned                        sprite_coord_enable;
111         unsigned                        clip_plane_enable;
112         float                           offset_units;
113         float                           offset_scale;
114 };
115
116 struct r600_pipe_blend {
117         struct r600_pipe_state          rstate;
118         unsigned                        cb_target_mask;
119 };
120
121 struct r600_pipe_dsa {
122         struct r600_pipe_state          rstate;
123         unsigned                        alpha_ref;
124         ubyte                           valuemask[2];
125         ubyte                           writemask[2];
126 };
127
128 struct r600_vertex_element
129 {
130         unsigned                        count;
131         struct pipe_vertex_element      elements[PIPE_MAX_ATTRIBS];
132         struct u_vbuf_elements          *vmgr_elements;
133         struct r600_resource            *fetch_shader;
134         unsigned                        fs_size;
135         struct r600_pipe_state          rstate;
136         /* if offset is to big for fetch instructio we need to alterate
137          * offset of vertex buffer, record here the offset need to add
138          */
139         unsigned                        vbuffer_need_offset;
140         unsigned                        vbuffer_offset[PIPE_MAX_ATTRIBS];
141 };
142
143 struct r600_pipe_shader {
144         struct r600_shader              shader;
145         struct r600_pipe_state          rstate;
146         struct r600_resource            *bo;
147         struct r600_resource            *bo_fetch;
148         struct r600_vertex_element      vertex_elements;
149         struct tgsi_token               *tokens;
150         unsigned        sprite_coord_enable;
151         unsigned        flatshade;
152         struct pipe_stream_output_info  so;
153 };
154
155 struct r600_pipe_sampler_state {
156         struct r600_pipe_state          rstate;
157         boolean seamless_cube_map;
158 };
159
160 /* needed for blitter save */
161 #define NUM_TEX_UNITS 16
162
163 struct r600_textures_info {
164         struct r600_pipe_sampler_view   *views[NUM_TEX_UNITS];
165         struct r600_pipe_sampler_state  *samplers[NUM_TEX_UNITS];
166         unsigned                        n_views;
167         unsigned                        n_samplers;
168         bool                            samplers_dirty;
169         bool                            is_array_sampler[NUM_TEX_UNITS];
170 };
171
172 struct r600_fence {
173         struct pipe_reference           reference;
174         unsigned                        index; /* in the shared bo */
175         struct list_head                head;
176 };
177
178 #define FENCE_BLOCK_SIZE 16
179
180 struct r600_fence_block {
181         struct r600_fence               fences[FENCE_BLOCK_SIZE];
182         struct list_head                head;
183 };
184
185 #define R600_CONSTANT_ARRAY_SIZE 256
186 #define R600_RESOURCE_ARRAY_SIZE 160
187
188 struct r600_stencil_ref
189 {
190         ubyte ref_value[2];
191         ubyte valuemask[2];
192         ubyte writemask[2];
193 };
194
195 struct r600_pipe_context {
196         struct pipe_context             context;
197         struct blitter_context          *blitter;
198         enum radeon_family              family;
199         enum chip_class                 chip_class;
200         unsigned                        r6xx_num_clause_temp_gprs;
201         void                            *custom_dsa_flush;
202         struct r600_screen              *screen;
203         struct radeon_winsys            *ws;
204         struct r600_pipe_state          *states[R600_PIPE_NSTATES];
205         struct r600_context             ctx;
206         struct r600_vertex_element      *vertex_elements;
207         struct r600_pipe_resource_state fs_resource[PIPE_MAX_ATTRIBS];
208         struct pipe_framebuffer_state   framebuffer;
209         unsigned                        cb_target_mask;
210         /* for saving when using blitter */
211         struct pipe_stencil_ref         stencil_ref;
212         struct pipe_viewport_state      viewport;
213         struct pipe_clip_state          clip;
214         struct r600_pipe_state          config;
215         struct r600_pipe_shader         *ps_shader;
216         struct r600_pipe_shader         *vs_shader;
217         struct r600_pipe_state          vs_const_buffer;
218         struct r600_pipe_resource_state         vs_const_buffer_resource[R600_MAX_CONST_BUFFERS];
219         struct r600_pipe_state          ps_const_buffer;
220         struct r600_pipe_resource_state         ps_const_buffer_resource[R600_MAX_CONST_BUFFERS];
221         struct r600_pipe_rasterizer     *rasterizer;
222         struct r600_pipe_state          vgt;
223         struct r600_pipe_state          spi;
224         struct pipe_query               *current_render_cond;
225         unsigned                        current_render_cond_mode;
226         struct pipe_query               *saved_render_cond;
227         unsigned                        saved_render_cond_mode;
228         /* shader information */
229         boolean                         two_side;
230         unsigned                        user_clip_plane_enable;
231         unsigned                        clip_dist_enable;
232         unsigned                        sprite_coord_enable;
233         boolean                         export_16bpc;
234         unsigned                        alpha_ref;
235         boolean                         alpha_ref_dirty;
236         unsigned                        nr_cbufs;
237         struct r600_textures_info       vs_samplers;
238         struct r600_textures_info       ps_samplers;
239
240         struct u_vbuf                   *vbuf_mgr;
241         struct util_slab_mempool        pool_transfers;
242         boolean                         have_depth_texture, have_depth_fb;
243
244         unsigned default_ps_gprs, default_vs_gprs;
245 };
246
247 /* evergreen_state.c */
248 void evergreen_init_state_functions(struct r600_pipe_context *rctx);
249 void evergreen_init_config(struct r600_pipe_context *rctx);
250 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
251 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
252 void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
253 void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx);
254 void evergreen_polygon_offset_update(struct r600_pipe_context *rctx);
255 void evergreen_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
256                                          struct r600_pipe_resource_state *rstate);
257 void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx,
258                                         struct r600_pipe_resource_state *rstate,
259                                         struct r600_resource *rbuffer,
260                                         unsigned offset, unsigned stride,
261                                         enum radeon_bo_usage usage);
262 boolean evergreen_is_format_supported(struct pipe_screen *screen,
263                                       enum pipe_format format,
264                                       enum pipe_texture_target target,
265                                       unsigned sample_count,
266                                       unsigned usage);
267
268 /* r600_blit.c */
269 void r600_init_blit_functions(struct r600_pipe_context *rctx);
270 void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
271 void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
272 void r600_flush_depth_textures(struct r600_pipe_context *rctx);
273
274 /* r600_buffer.c */
275 bool r600_init_resource(struct r600_screen *rscreen,
276                         struct r600_resource *res,
277                         unsigned size, unsigned alignment,
278                         unsigned bind, unsigned usage);
279 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
280                                          const struct pipe_resource *templ);
281 struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen,
282                                               void *ptr, unsigned bytes,
283                                               unsigned bind);
284 void r600_upload_index_buffer(struct r600_pipe_context *rctx,
285                               struct pipe_index_buffer *ib, unsigned count);
286
287
288 /* r600_pipe.c */
289 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
290                 unsigned flags);
291
292 /* r600_query.c */
293 void r600_init_query_functions(struct r600_pipe_context *rctx);
294
295 /* r600_resource.c */
296 void r600_init_context_resource_functions(struct r600_pipe_context *r600);
297
298 /* r600_shader.c */
299 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader);
300 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
301 int r600_find_vs_semantic_index(struct r600_shader *vs,
302                                 struct r600_shader *ps, int id);
303
304 /* r600_state.c */
305 void r600_update_sampler_states(struct r600_pipe_context *rctx);
306 void r600_init_state_functions(struct r600_pipe_context *rctx);
307 void r600_init_config(struct r600_pipe_context *rctx);
308 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
309 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
310 void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
311 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx);
312 void r600_polygon_offset_update(struct r600_pipe_context *rctx);
313 void r600_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
314                                     struct r600_pipe_resource_state *rstate);
315 void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
316                                    struct r600_resource *rbuffer,
317                                    unsigned offset, unsigned stride,
318                                    enum radeon_bo_usage usage);
319 void r600_adjust_gprs(struct r600_pipe_context *rctx);
320 boolean r600_is_format_supported(struct pipe_screen *screen,
321                                  enum pipe_format format,
322                                  enum pipe_texture_target target,
323                                  unsigned sample_count,
324                                  unsigned usage);
325
326 /* r600_texture.c */
327 void r600_init_screen_texture_functions(struct pipe_screen *screen);
328 void r600_init_surface_functions(struct r600_pipe_context *r600);
329 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
330                                   const unsigned char *swizzle_view,
331                                   uint32_t *word4_p, uint32_t *yuv_format_p);
332 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
333                                         unsigned level, unsigned layer);
334
335 /* r600_translate.c */
336 void r600_translate_index_buffer(struct r600_pipe_context *r600,
337                                  struct pipe_index_buffer *ib,
338                                  unsigned count);
339
340 /* r600_state_common.c */
341 void r600_set_index_buffer(struct pipe_context *ctx,
342                            const struct pipe_index_buffer *ib);
343 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
344                              const struct pipe_vertex_buffer *buffers);
345 void *r600_create_vertex_elements(struct pipe_context *ctx,
346                                   unsigned count,
347                                   const struct pipe_vertex_element *elements);
348 void r600_delete_vertex_element(struct pipe_context *ctx, void *state);
349 void r600_bind_blend_state(struct pipe_context *ctx, void *state);
350 void r600_bind_dsa_state(struct pipe_context *ctx, void *state);
351 void r600_bind_rs_state(struct pipe_context *ctx, void *state);
352 void r600_delete_rs_state(struct pipe_context *ctx, void *state);
353 void r600_sampler_view_destroy(struct pipe_context *ctx,
354                                struct pipe_sampler_view *state);
355 void r600_delete_state(struct pipe_context *ctx, void *state);
356 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
357 void *r600_create_shader_state(struct pipe_context *ctx,
358                                const struct pipe_shader_state *state);
359 void r600_bind_ps_shader(struct pipe_context *ctx, void *state);
360 void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
361 void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
362 void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
363 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
364                               struct pipe_resource *buffer);
365 struct pipe_stream_output_target *
366 r600_create_so_target(struct pipe_context *ctx,
367                       struct pipe_resource *buffer,
368                       unsigned buffer_offset,
369                       unsigned buffer_size);
370 void r600_so_target_destroy(struct pipe_context *ctx,
371                             struct pipe_stream_output_target *target);
372 void r600_set_so_targets(struct pipe_context *ctx,
373                          unsigned num_targets,
374                          struct pipe_stream_output_target **targets,
375                          unsigned append_bitmask);
376 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
377                                const struct pipe_stencil_ref *state);
378 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
379
380 /*
381  * common helpers
382  */
383 static INLINE u32 S_FIXED(float value, u32 frac_bits)
384 {
385         return value * (1 << frac_bits);
386 }
387 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
388
389 static inline unsigned r600_tex_aniso_filter(unsigned filter)
390 {
391         if (filter <= 1)   return 0;
392         if (filter <= 2)   return 1;
393         if (filter <= 4)   return 2;
394         if (filter <= 8)   return 3;
395          /* else */        return 4;
396 }
397
398 /* 12.4 fixed-point */
399 static INLINE unsigned r600_pack_float_12p4(float x)
400 {
401         return x <= 0    ? 0 :
402                x >= 4096 ? 0xffff : x * 16;
403 }
404
405 #endif