2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "../../winsys/radeon/drm/radeon_winsys.h"
31 #include "pipe/p_state.h"
32 #include "pipe/p_screen.h"
33 #include "pipe/p_context.h"
34 #include "util/u_math.h"
35 #include "util/u_slab.h"
36 #include "util/u_vbuf.h"
38 #include "r600_public.h"
39 #include "r600_shader.h"
40 #include "r600_resource.h"
42 #define R600_MAX_CONST_BUFFERS 2
43 #define R600_MAX_CONST_BUFFER_SIZE 4096
45 #ifdef PIPE_ARCH_BIG_ENDIAN
46 #define R600_BIG_ENDIAN 1
48 #define R600_BIG_ENDIAN 0
51 enum r600_atom_flags {
52 /* When set, atoms are added at the beginning of the dirty list
53 * instead of the end. */
57 /* This encapsulates a state or an operation which can emitted into the GPU
58 * command stream. It's not limited to states only, it can be used for anything
59 * that wants to write commands into the CS (e.g. cache flushes). */
61 void (*emit)(struct r600_context *ctx, struct r600_atom *state);
64 enum r600_atom_flags flags;
67 struct list_head head;
70 /* This is an atom containing GPU commands that never change.
71 * This is supposed to be copied directly into the CS. */
72 struct r600_command_buffer {
73 struct r600_atom atom;
78 struct r600_atom_surface_sync {
79 struct r600_atom atom;
80 unsigned flush_flags; /* CP_COHER_CNTL */
83 struct r600_atom_db_misc_state {
84 struct r600_atom atom;
85 bool occlusion_query_enabled;
86 bool flush_depthstencil_enabled;
89 struct r600_atom_eg_strmout_config {
90 struct r600_atom atom;
91 bool rasterizer_discard;
95 enum r600_pipe_state_id {
96 R600_PIPE_STATE_BLEND = 0,
97 R600_PIPE_STATE_BLEND_COLOR,
98 R600_PIPE_STATE_CONFIG,
99 R600_PIPE_STATE_SEAMLESS_CUBEMAP,
100 R600_PIPE_STATE_CLIP,
101 R600_PIPE_STATE_SCISSOR,
102 R600_PIPE_STATE_VIEWPORT,
103 R600_PIPE_STATE_RASTERIZER,
105 R600_PIPE_STATE_FRAMEBUFFER,
107 R600_PIPE_STATE_STENCIL_REF,
108 R600_PIPE_STATE_PS_SHADER,
109 R600_PIPE_STATE_VS_SHADER,
110 R600_PIPE_STATE_CONSTANT,
111 R600_PIPE_STATE_SAMPLER,
112 R600_PIPE_STATE_RESOURCE,
113 R600_PIPE_STATE_POLYGON_OFFSET,
114 R600_PIPE_STATE_FETCH_SHADER,
118 struct r600_pipe_fences {
119 struct r600_resource *bo;
122 /* linked list of preallocated blocks */
123 struct list_head blocks;
124 /* linked list of freed fences */
125 struct list_head pool;
130 struct pipe_screen screen;
131 struct radeon_winsys *ws;
133 enum chip_class chip_class;
134 struct radeon_info info;
135 struct r600_tiling_info tiling_info;
136 struct util_slab_mempool pool_buffers;
137 struct r600_pipe_fences fences;
139 unsigned num_contexts;
140 bool use_surface_alloc;
142 /* for thread-safe write accessing to num_contexts */
143 pipe_mutex mutex_num_contexts;
146 struct r600_pipe_sampler_view {
147 struct pipe_sampler_view base;
148 struct r600_pipe_resource_state state;
151 struct r600_pipe_rasterizer {
152 struct r600_pipe_state rstate;
155 unsigned sprite_coord_enable;
156 unsigned clip_plane_enable;
157 unsigned pa_sc_line_stipple;
158 unsigned pa_cl_clip_cntl;
162 bool rasterizer_discard;
165 struct r600_pipe_blend {
166 struct r600_pipe_state rstate;
167 unsigned cb_target_mask;
168 unsigned cb_color_control;
171 struct r600_pipe_dsa {
172 struct r600_pipe_state rstate;
179 struct r600_vertex_element
182 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS];
183 struct u_vbuf_elements *vmgr_elements;
184 struct r600_resource *fetch_shader;
186 struct r600_pipe_state rstate;
187 /* if offset is to big for fetch instructio we need to alterate
188 * offset of vertex buffer, record here the offset need to add
190 unsigned vbuffer_need_offset;
191 unsigned vbuffer_offset[PIPE_MAX_ATTRIBS];
194 struct r600_pipe_shader {
195 struct r600_shader shader;
196 struct r600_pipe_state rstate;
197 struct r600_resource *bo;
198 struct r600_resource *bo_fetch;
199 struct r600_vertex_element vertex_elements;
200 struct tgsi_token *tokens;
201 unsigned sprite_coord_enable;
203 unsigned pa_cl_vs_out_cntl;
204 struct pipe_stream_output_info so;
207 struct r600_pipe_sampler_state {
208 struct r600_pipe_state rstate;
209 boolean seamless_cube_map;
212 /* needed for blitter save */
213 #define NUM_TEX_UNITS 16
215 struct r600_textures_info {
216 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
217 struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS];
221 bool is_array_sampler[NUM_TEX_UNITS];
225 struct pipe_reference reference;
226 unsigned index; /* in the shared bo */
227 struct r600_resource *sleep_bo;
228 struct list_head head;
231 #define FENCE_BLOCK_SIZE 16
233 struct r600_fence_block {
234 struct r600_fence fences[FENCE_BLOCK_SIZE];
235 struct list_head head;
238 #define R600_CONSTANT_ARRAY_SIZE 256
239 #define R600_RESOURCE_ARRAY_SIZE 160
241 struct r600_stencil_ref
248 struct r600_context {
249 struct pipe_context context;
250 struct blitter_context *blitter;
251 enum radeon_family family;
252 enum chip_class chip_class;
253 unsigned r6xx_num_clause_temp_gprs;
254 void *custom_dsa_flush;
255 struct r600_screen *screen;
256 struct radeon_winsys *ws;
257 struct r600_pipe_state *states[R600_PIPE_NSTATES];
258 struct r600_vertex_element *vertex_elements;
259 struct r600_pipe_resource_state fs_resource[PIPE_MAX_ATTRIBS];
260 struct pipe_framebuffer_state framebuffer;
261 unsigned cb_target_mask;
262 unsigned cb_color_control;
263 unsigned pa_sc_line_stipple;
264 unsigned pa_cl_clip_cntl;
265 /* for saving when using blitter */
266 struct pipe_stencil_ref stencil_ref;
267 struct pipe_viewport_state viewport;
268 struct pipe_clip_state clip;
269 struct r600_pipe_shader *ps_shader;
270 struct r600_pipe_shader *vs_shader;
271 struct r600_pipe_state vs_const_buffer;
272 struct r600_pipe_resource_state vs_const_buffer_resource[R600_MAX_CONST_BUFFERS];
273 struct r600_pipe_state ps_const_buffer;
274 struct r600_pipe_resource_state ps_const_buffer_resource[R600_MAX_CONST_BUFFERS];
275 struct r600_pipe_rasterizer *rasterizer;
276 struct r600_pipe_state vgt;
277 struct r600_pipe_state spi;
278 struct pipe_query *current_render_cond;
279 unsigned current_render_cond_mode;
280 struct pipe_query *saved_render_cond;
281 unsigned saved_render_cond_mode;
282 /* shader information */
284 unsigned sprite_coord_enable;
285 boolean export_16bpc;
287 boolean alpha_ref_dirty;
289 struct r600_textures_info vs_samplers;
290 struct r600_textures_info ps_samplers;
292 struct u_vbuf *vbuf_mgr;
293 struct util_slab_mempool pool_transfers;
294 boolean have_depth_texture, have_depth_fb;
296 unsigned default_ps_gprs, default_vs_gprs;
298 /* States based on r600_state. */
299 struct list_head dirty_states;
300 struct r600_command_buffer atom_start_cs; /* invariant state mostly */
301 struct r600_atom_surface_sync atom_surface_sync;
302 struct r600_atom atom_r6xx_flush_and_inv;
303 struct r600_atom_db_misc_state atom_db_misc_state;
304 struct r600_atom_eg_strmout_config atom_eg_strmout_config;
306 /* Below are variables from the old r600_context.
308 struct radeon_winsys_cs *cs;
310 struct r600_range *range;
312 struct r600_block **blocks;
313 struct list_head dirty;
314 struct list_head resource_dirty;
315 struct list_head enable_list;
316 unsigned pm4_dirty_cdwords;
317 unsigned ctx_pm4_ndwords;
319 /* The list of active queries. Only one query of each type can be active. */
320 int num_occlusion_queries;
322 /* Manage queries in two separate groups:
323 * The timer ones and the others (streamout, occlusion).
325 * We do this because we should only suspend non-timer queries for u_blitter,
326 * and later if the non-timer queries are suspended, the context flush should
327 * only suspend and resume the timer queries. */
328 struct list_head active_timer_queries;
329 unsigned num_cs_dw_timer_queries_suspend;
330 struct list_head active_nontimer_queries;
331 unsigned num_cs_dw_nontimer_queries_suspend;
333 unsigned num_cs_dw_streamout_end;
335 unsigned backend_mask;
336 unsigned max_db; /* for OQ */
338 boolean predicate_drawing;
339 struct r600_range ps_resources;
340 struct r600_range vs_resources;
341 struct r600_range fs_resources;
342 int num_ps_resources, num_vs_resources, num_fs_resources;
344 unsigned num_so_targets;
345 struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS];
346 boolean streamout_start;
347 unsigned streamout_append_bitmask;
349 /* There is no scissor enable bit on r6xx, so we must use a workaround.
350 * These track the current scissor state. */
352 struct pipe_scissor_state scissor_state;
355 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
357 atom->emit(rctx, atom);
359 if (atom->head.next && atom->head.prev)
360 LIST_DELINIT(&atom->head);
363 static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state)
366 if (state->flags & EMIT_EARLY) {
367 LIST_ADD(&state->head, &rctx->dirty_states);
369 LIST_ADDTAIL(&state->head, &rctx->dirty_states);
375 /* evergreen_state.c */
376 void evergreen_init_state_functions(struct r600_context *rctx);
377 void evergreen_init_atom_start_cs(struct r600_context *rctx);
378 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
379 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
380 void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
381 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
382 void evergreen_polygon_offset_update(struct r600_context *rctx);
383 void evergreen_pipe_init_buffer_resource(struct r600_context *rctx,
384 struct r600_pipe_resource_state *rstate);
385 void evergreen_pipe_mod_buffer_resource(struct pipe_context *ctx,
386 struct r600_pipe_resource_state *rstate,
387 struct r600_resource *rbuffer,
388 unsigned offset, unsigned stride,
389 enum radeon_bo_usage usage);
390 boolean evergreen_is_format_supported(struct pipe_screen *screen,
391 enum pipe_format format,
392 enum pipe_texture_target target,
393 unsigned sample_count,
395 void evergreen_set_rasterizer_discard(struct pipe_context *ctx, boolean discard);
398 void r600_init_blit_functions(struct r600_context *rctx);
399 void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
400 void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
401 void r600_flush_depth_textures(struct r600_context *rctx);
404 bool r600_init_resource(struct r600_screen *rscreen,
405 struct r600_resource *res,
406 unsigned size, unsigned alignment,
407 unsigned bind, unsigned usage);
408 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
409 const struct pipe_resource *templ);
410 struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen,
411 void *ptr, unsigned bytes,
413 void r600_upload_index_buffer(struct r600_context *rctx,
414 struct pipe_index_buffer *ib, unsigned count);
418 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
422 void r600_init_query_functions(struct r600_context *rctx);
423 void r600_suspend_nontimer_queries(struct r600_context *ctx);
424 void r600_resume_nontimer_queries(struct r600_context *ctx);
425 void r600_suspend_timer_queries(struct r600_context *ctx);
426 void r600_resume_timer_queries(struct r600_context *ctx);
428 /* r600_resource.c */
429 void r600_init_context_resource_functions(struct r600_context *r600);
432 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader);
433 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
434 int r600_find_vs_semantic_index(struct r600_shader *vs,
435 struct r600_shader *ps, int id);
438 void r600_set_scissor_state(struct r600_context *rctx,
439 const struct pipe_scissor_state *state);
440 void r600_update_sampler_states(struct r600_context *rctx);
441 void r600_init_state_functions(struct r600_context *rctx);
442 void r600_init_atom_start_cs(struct r600_context *rctx);
443 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
444 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
445 void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
446 void *r600_create_db_flush_dsa(struct r600_context *rctx);
447 void r600_polygon_offset_update(struct r600_context *rctx);
448 void r600_pipe_init_buffer_resource(struct r600_context *rctx,
449 struct r600_pipe_resource_state *rstate);
450 void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
451 struct r600_resource *rbuffer,
452 unsigned offset, unsigned stride,
453 enum radeon_bo_usage usage);
454 void r600_adjust_gprs(struct r600_context *rctx);
455 boolean r600_is_format_supported(struct pipe_screen *screen,
456 enum pipe_format format,
457 enum pipe_texture_target target,
458 unsigned sample_count,
462 void r600_init_screen_texture_functions(struct pipe_screen *screen);
463 void r600_init_surface_functions(struct r600_context *r600);
464 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
465 const unsigned char *swizzle_view,
466 uint32_t *word4_p, uint32_t *yuv_format_p);
467 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
468 unsigned level, unsigned layer);
470 /* r600_translate.c */
471 void r600_translate_index_buffer(struct r600_context *r600,
472 struct pipe_index_buffer *ib,
475 /* r600_state_common.c */
476 void r600_init_atom(struct r600_atom *atom,
477 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
478 unsigned num_dw, enum r600_atom_flags flags);
479 void r600_init_common_atoms(struct r600_context *rctx);
480 unsigned r600_get_cb_flush_flags(struct r600_context *rctx);
481 void r600_texture_barrier(struct pipe_context *ctx);
482 void r600_set_index_buffer(struct pipe_context *ctx,
483 const struct pipe_index_buffer *ib);
484 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
485 const struct pipe_vertex_buffer *buffers);
486 void *r600_create_vertex_elements(struct pipe_context *ctx,
488 const struct pipe_vertex_element *elements);
489 void r600_delete_vertex_element(struct pipe_context *ctx, void *state);
490 void r600_bind_blend_state(struct pipe_context *ctx, void *state);
491 void r600_set_blend_color(struct pipe_context *ctx,
492 const struct pipe_blend_color *state);
493 void r600_bind_dsa_state(struct pipe_context *ctx, void *state);
494 void r600_set_max_scissor(struct r600_context *rctx);
495 void r600_bind_rs_state(struct pipe_context *ctx, void *state);
496 void r600_delete_rs_state(struct pipe_context *ctx, void *state);
497 void r600_sampler_view_destroy(struct pipe_context *ctx,
498 struct pipe_sampler_view *state);
499 void r600_delete_state(struct pipe_context *ctx, void *state);
500 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
501 void *r600_create_shader_state(struct pipe_context *ctx,
502 const struct pipe_shader_state *state);
503 void r600_bind_ps_shader(struct pipe_context *ctx, void *state);
504 void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
505 void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
506 void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
507 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
508 struct pipe_resource *buffer);
509 struct pipe_stream_output_target *
510 r600_create_so_target(struct pipe_context *ctx,
511 struct pipe_resource *buffer,
512 unsigned buffer_offset,
513 unsigned buffer_size);
514 void r600_so_target_destroy(struct pipe_context *ctx,
515 struct pipe_stream_output_target *target);
516 void r600_set_so_targets(struct pipe_context *ctx,
517 unsigned num_targets,
518 struct pipe_stream_output_target **targets,
519 unsigned append_bitmask);
520 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
521 const struct pipe_stencil_ref *state);
522 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
523 uint32_t r600_translate_stencil_op(int s_op);
524 uint32_t r600_translate_fill(uint32_t func);
525 unsigned r600_tex_wrap(unsigned wrap);
526 unsigned r600_tex_filter(unsigned filter);
527 unsigned r600_tex_mipfilter(unsigned filter);
528 unsigned r600_tex_compare(unsigned compare);
531 * Helpers for building command buffers
534 #define PKT3_SET_CONFIG_REG 0x68
535 #define PKT3_SET_CONTEXT_REG 0x69
536 #define PKT3_SET_CTL_CONST 0x6F
537 #define PKT3_SET_LOOP_CONST 0x6C
539 #define R600_CONFIG_REG_OFFSET 0x08000
540 #define R600_CONTEXT_REG_OFFSET 0x28000
541 #define R600_CTL_CONST_OFFSET 0x3CFF0
542 #define R600_LOOP_CONST_OFFSET 0X0003E200
543 #define EG_LOOP_CONST_OFFSET 0x0003A200
545 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
546 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
547 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
548 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
549 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
551 static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value)
553 cb->buf[cb->atom.num_dw++] = value;
556 static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
558 assert(reg < R600_CONTEXT_REG_OFFSET);
559 assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
560 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
561 cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
564 static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
566 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
567 assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
568 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
569 cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
572 static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
574 assert(reg >= R600_CTL_CONST_OFFSET);
575 assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
576 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
577 cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
580 static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
582 assert(reg >= R600_LOOP_CONST_OFFSET);
583 assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
584 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
585 cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
588 static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
590 assert(reg >= EG_LOOP_CONST_OFFSET);
591 assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
592 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
593 cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
596 static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
598 r600_store_config_reg_seq(cb, reg, 1);
599 r600_store_value(cb, value);
602 static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
604 r600_store_context_reg_seq(cb, reg, 1);
605 r600_store_value(cb, value);
608 static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
610 r600_store_ctl_const_seq(cb, reg, 1);
611 r600_store_value(cb, value);
614 static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
616 r600_store_loop_const_seq(cb, reg, 1);
617 r600_store_value(cb, value);
620 static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
622 eg_store_loop_const_seq(cb, reg, 1);
623 r600_store_value(cb, value);
626 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags);
627 void r600_release_command_buffer(struct r600_command_buffer *cb);
630 * Helpers for emitting state into a command stream directly.
633 static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value)
635 cs->buf[cs->cdw++] = value;
638 static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
640 assert(reg < R600_CONTEXT_REG_OFFSET);
641 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
642 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
643 cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
646 static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
648 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
649 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
650 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
651 cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
654 static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
656 assert(reg >= R600_CTL_CONST_OFFSET);
657 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
658 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
659 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
662 static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
664 r600_write_config_reg_seq(cs, reg, 1);
665 r600_write_value(cs, value);
668 static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
670 r600_write_context_reg_seq(cs, reg, 1);
671 r600_write_value(cs, value);
674 static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
676 r600_write_ctl_const_seq(cs, reg, 1);
677 r600_write_value(cs, value);
683 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
685 return value * (1 << frac_bits);
687 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
689 static inline unsigned r600_tex_aniso_filter(unsigned filter)
691 if (filter <= 1) return 0;
692 if (filter <= 2) return 1;
693 if (filter <= 4) return 2;
694 if (filter <= 8) return 3;
698 /* 12.4 fixed-point */
699 static INLINE unsigned r600_pack_float_12p4(float x)
702 x >= 4096 ? 0xffff : x * 16;