src/gallium/drivers/r600/r600_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef R600_PIPE_H
  27 #define R600_PIPE_H
  28
  29 #include "util/u_slab.h"
  30 #include "r600.h"
  31 #include "r600_llvm.h"
  32 #include "r600_public.h"
  33 #include "r600_shader.h"
  34 #include "r600_resource.h"
  35 #include "evergreen_compute.h"
  36
  37 #define R600_MAX_CONST_BUFFERS 2
  38 #define R600_MAX_CONST_BUFFER_SIZE 4096
  39
  40 #ifdef PIPE_ARCH_BIG_ENDIAN
  41 #define R600_BIG_ENDIAN 1
  42 #else
  43 #define R600_BIG_ENDIAN 0
  44 #endif
  45
  46 enum r600_atom_flags {
  47         /* When set, atoms are added at the beginning of the dirty list
  48          * instead of the end. */
  49         EMIT_EARLY = (1 << 0)
  50 };
  51
  52 /* This encapsulates a state or an operation which can emitted into the GPU
  53  * command stream. It's not limited to states only, it can be used for anything
  54  * that wants to write commands into the CS (e.g. cache flushes). */
  55 struct r600_atom {
  56         void (*emit)(struct r600_context *ctx, struct r600_atom *state);
  57
  58         unsigned                num_dw;
  59         enum r600_atom_flags    flags;
  60         bool                    dirty;
  61
  62         struct list_head        head;
  63 };
  64
  65 /* This is an atom containing GPU commands that never change.
  66  * This is supposed to be copied directly into the CS. */
  67 struct r600_command_buffer {
  68         struct r600_atom atom;
  69         uint32_t *buf;
  70         unsigned max_num_dw;
  71 };
  72
  73 struct r600_surface_sync_cmd {
  74         struct r600_atom atom;
  75         unsigned flush_flags; /* CP_COHER_CNTL */
  76 };
  77
  78 struct r600_db_misc_state {
  79         struct r600_atom atom;
  80         bool occlusion_query_enabled;
  81         bool flush_depthstencil_enabled;
  82 };
  83
  84 enum r600_pipe_state_id {
  85         R600_PIPE_STATE_BLEND = 0,
  86         R600_PIPE_STATE_BLEND_COLOR,
  87         R600_PIPE_STATE_CONFIG,
  88         R600_PIPE_STATE_SEAMLESS_CUBEMAP,
  89         R600_PIPE_STATE_CLIP,
  90         R600_PIPE_STATE_SCISSOR,
  91         R600_PIPE_STATE_VIEWPORT,
  92         R600_PIPE_STATE_RASTERIZER,
  93         R600_PIPE_STATE_VGT,
  94         R600_PIPE_STATE_FRAMEBUFFER,
  95         R600_PIPE_STATE_DSA,
  96         R600_PIPE_STATE_STENCIL_REF,
  97         R600_PIPE_STATE_PS_SHADER,
  98         R600_PIPE_STATE_VS_SHADER,
  99         R600_PIPE_STATE_CONSTANT,
 100         R600_PIPE_STATE_SAMPLER,
 101         R600_PIPE_STATE_RESOURCE,
 102         R600_PIPE_STATE_POLYGON_OFFSET,
 103         R600_PIPE_STATE_FETCH_SHADER,
 104         R600_PIPE_STATE_SPI,
 105         R600_PIPE_NSTATES
 106 };
 107
 108 struct compute_memory_pool;
 109 void compute_memory_pool_delete(struct compute_memory_pool* pool);
 110 struct compute_memory_pool* compute_memory_pool_new(
 111         int64_t initial_size_in_dw,
 112         struct r600_screen *rscreen);
 113
 114 struct r600_pipe_fences {
 115         struct r600_resource            *bo;
 116         unsigned                        *data;
 117         unsigned                        next_index;
 118         /* linked list of preallocated blocks */
 119         struct list_head                blocks;
 120         /* linked list of freed fences */
 121         struct list_head                pool;
 122         pipe_mutex                      mutex;
 123 };
 124
 125 struct r600_screen {
 126         struct pipe_screen              screen;
 127         struct radeon_winsys            *ws;
 128         unsigned                        family;
 129         enum chip_class                 chip_class;
 130         struct radeon_info              info;
 131         struct r600_tiling_info         tiling_info;
 132         struct r600_pipe_fences         fences;
 133
 134         bool                            use_surface_alloc;
 135         int                             glsl_feature_level;
 136
 137         /*for compute global memory binding, we allocate stuff here, instead of
 138          * buffers.
 139          * XXX: Not sure if this is the best place for global_pool.  Also,
 140          * it's not thread safe, so it won't work with multiple contexts. */
 141         struct compute_memory_pool *global_pool;
 142 };
 143
 144 struct r600_pipe_sampler_view {
 145         struct pipe_sampler_view        base;
 146         struct r600_pipe_resource_state         state;
 147 };
 148
 149 struct r600_pipe_rasterizer {
 150         struct r600_pipe_state          rstate;
 151         boolean                         flatshade;
 152         boolean                         two_side;
 153         unsigned                        sprite_coord_enable;
 154         unsigned                        clip_plane_enable;
 155         unsigned                        pa_sc_line_stipple;
 156         unsigned                        pa_cl_clip_cntl;
 157         float                           offset_units;
 158         float                           offset_scale;
 159         bool                            scissor_enable;
 160 };
 161
 162 struct r600_pipe_blend {
 163         struct r600_pipe_state          rstate;
 164         unsigned                        cb_target_mask;
 165         unsigned                        cb_color_control;
 166         bool                            dual_src_blend;
 167 };
 168
 169 struct r600_pipe_dsa {
 170         struct r600_pipe_state          rstate;
 171         unsigned                        alpha_ref;
 172         ubyte                           valuemask[2];
 173         ubyte                           writemask[2];
 174         bool                            is_flush;
 175         unsigned                        sx_alpha_test_control;
 176 };
 177
 178 struct r600_vertex_element
 179 {
 180         unsigned                        count;
 181         struct pipe_vertex_element      elements[PIPE_MAX_ATTRIBS];
 182         struct r600_resource            *fetch_shader;
 183         unsigned                        fs_size;
 184         struct r600_pipe_state          rstate;
 185 };
 186
 187 struct r600_pipe_shader {
 188         struct r600_shader              shader;
 189         struct r600_pipe_state          rstate;
 190         struct r600_resource            *bo;
 191         struct r600_resource            *bo_fetch;
 192         struct r600_vertex_element      vertex_elements;
 193         struct tgsi_token               *tokens;
 194         unsigned        sprite_coord_enable;
 195         unsigned        flatshade;
 196         unsigned        pa_cl_vs_out_cntl;
 197         unsigned        ps_cb_shader_mask;
 198         struct pipe_stream_output_info  so;
 199 };
 200
 201 struct r600_pipe_sampler_state {
 202         struct r600_pipe_state          rstate;
 203         boolean seamless_cube_map;
 204 };
 205
 206 /* needed for blitter save */
 207 #define NUM_TEX_UNITS 16
 208
 209 struct r600_textures_info {
 210         struct r600_pipe_sampler_view   *views[NUM_TEX_UNITS];
 211         struct r600_pipe_sampler_state  *samplers[NUM_TEX_UNITS];
 212         unsigned                        n_views;
 213         unsigned                        n_samplers;
 214         bool                            samplers_dirty;
 215         bool                            is_array_sampler[NUM_TEX_UNITS];
 216 };
 217
 218 struct r600_fence {
 219         struct pipe_reference           reference;
 220         unsigned                        index; /* in the shared bo */
 221         struct r600_resource            *sleep_bo;
 222         struct list_head                head;
 223 };
 224
 225 #define FENCE_BLOCK_SIZE 16
 226
 227 struct r600_fence_block {
 228         struct r600_fence               fences[FENCE_BLOCK_SIZE];
 229         struct list_head                head;
 230 };
 231
 232 #define R600_CONSTANT_ARRAY_SIZE 256
 233 #define R600_RESOURCE_ARRAY_SIZE 160
 234
 235 struct r600_stencil_ref
 236 {
 237         ubyte ref_value[2];
 238         ubyte valuemask[2];
 239         ubyte writemask[2];
 240 };
 241
 242 struct r600_constbuf_state
 243 {
 244         struct r600_atom                atom;
 245         struct pipe_constant_buffer     cb[PIPE_MAX_CONSTANT_BUFFERS];
 246         uint32_t                        enabled_mask;
 247         uint32_t                        dirty_mask;
 248 };
 249
 250 struct r600_context {
 251         struct pipe_context             context;
 252         struct blitter_context          *blitter;
 253         enum radeon_family              family;
 254         enum chip_class                 chip_class;
 255         boolean                         has_vertex_cache;
 256         unsigned                        r6xx_num_clause_temp_gprs;
 257         void                            *custom_dsa_flush;
 258         struct r600_screen              *screen;
 259         struct radeon_winsys            *ws;
 260         struct r600_pipe_state          *states[R600_PIPE_NSTATES];
 261         struct r600_vertex_element      *vertex_elements;
 262         struct pipe_framebuffer_state   framebuffer;
 263         unsigned                        cb_target_mask;
 264         unsigned                        fb_cb_shader_mask;
 265         unsigned                        sx_alpha_test_control;
 266         unsigned                        cb_shader_mask;
 267         unsigned                        cb_color_control;
 268         unsigned                        pa_sc_line_stipple;
 269         unsigned                        pa_cl_clip_cntl;
 270         /* for saving when using blitter */
 271         struct pipe_stencil_ref         stencil_ref;
 272         struct pipe_viewport_state      viewport;
 273         struct pipe_clip_state          clip;
 274         struct r600_pipe_shader         *ps_shader;
 275         struct r600_pipe_shader         *vs_shader;
 276         struct r600_pipe_compute        *cs_shader;
 277         struct r600_pipe_rasterizer     *rasterizer;
 278         struct r600_pipe_state          vgt;
 279         struct r600_pipe_state          spi;
 280         struct pipe_query               *current_render_cond;
 281         unsigned                        current_render_cond_mode;
 282         struct pipe_query               *saved_render_cond;
 283         unsigned                        saved_render_cond_mode;
 284         /* shader information */
 285         boolean                         two_side;
 286         boolean                         spi_dirty;
 287         unsigned                        sprite_coord_enable;
 288         boolean                         flatshade;
 289         boolean                         export_16bpc;
 290         unsigned                        alpha_ref;
 291         boolean                         alpha_ref_dirty;
 292         unsigned                        nr_cbufs;
 293         struct r600_textures_info       vs_samplers;
 294         struct r600_textures_info       ps_samplers;
 295
 296         struct u_upload_mgr             *uploader;
 297         struct util_slab_mempool        pool_transfers;
 298         boolean                         have_depth_texture, have_depth_fb;
 299
 300         unsigned default_ps_gprs, default_vs_gprs;
 301
 302         /* States based on r600_atom. */
 303         struct list_head                dirty_states;
 304         struct r600_command_buffer      start_cs_cmd; /* invariant state mostly */
 305         struct r600_surface_sync_cmd    surface_sync_cmd;
 306         struct r600_atom                r6xx_flush_and_inv_cmd;
 307         struct r600_db_misc_state       db_misc_state;
 308         struct r600_atom                vertex_buffer_state;
 309         struct r600_constbuf_state      vs_constbuf_state;
 310         struct r600_constbuf_state      ps_constbuf_state;
 311
 312         struct radeon_winsys_cs *cs;
 313
 314         struct r600_range       *range;
 315         unsigned                nblocks;
 316         struct r600_block       **blocks;
 317         struct list_head        dirty;
 318         struct list_head        resource_dirty;
 319         struct list_head        enable_list;
 320         unsigned                pm4_dirty_cdwords;
 321         unsigned                ctx_pm4_ndwords;
 322
 323         /* The list of active queries. Only one query of each type can be active. */
 324         int                     num_occlusion_queries;
 325
 326         /* Manage queries in two separate groups:
 327          * The timer ones and the others (streamout, occlusion).
 328          *
 329          * We do this because we should only suspend non-timer queries for u_blitter,
 330          * and later if the non-timer queries are suspended, the context flush should
 331          * only suspend and resume the timer queries. */
 332         struct list_head        active_timer_queries;
 333         unsigned                num_cs_dw_timer_queries_suspend;
 334         struct list_head        active_nontimer_queries;
 335         unsigned                num_cs_dw_nontimer_queries_suspend;
 336
 337         unsigned                num_cs_dw_streamout_end;
 338
 339         unsigned                backend_mask;
 340         unsigned                max_db; /* for OQ */
 341         unsigned                flags;
 342         boolean                 predicate_drawing;
 343         struct r600_range       ps_resources;
 344         struct r600_range       vs_resources;
 345         int                     num_ps_resources, num_vs_resources;
 346
 347         unsigned                num_so_targets;
 348         struct r600_so_target   *so_targets[PIPE_MAX_SO_BUFFERS];
 349         boolean                 streamout_start;
 350         unsigned                streamout_append_bitmask;
 351
 352         /* There is no scissor enable bit on r6xx, so we must use a workaround.
 353          * These track the current scissor state. */
 354         bool                    scissor_enable;
 355         struct pipe_scissor_state scissor_state;
 356
 357         /* With rasterizer discard, there doesn't have to be a pixel shader.
 358          * In that case, we bind this one: */
 359         void                    *dummy_pixel_shader;
 360
 361         boolean                 dual_src_blend;
 362
 363         /* Vertex and index buffers. */
 364         bool                    vertex_buffers_dirty;
 365         struct pipe_index_buffer index_buffer;
 366         struct pipe_vertex_buffer vertex_buffer[PIPE_MAX_ATTRIBS];
 367         unsigned                nr_vertex_buffers;
 368 };
 369
 370 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
 371 {
 372         atom->emit(rctx, atom);
 373         atom->dirty = false;
 374         if (atom->head.next && atom->head.prev)
 375                 LIST_DELINIT(&atom->head);
 376 }
 377
 378 static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state)
 379 {
 380         if (!state->dirty) {
 381                 if (state->flags & EMIT_EARLY) {
 382                         LIST_ADD(&state->head, &rctx->dirty_states);
 383                 } else {
 384                         LIST_ADDTAIL(&state->head, &rctx->dirty_states);
 385                 }
 386                 state->dirty = true;
 387         }
 388 }
 389
 390 /* evergreen_state.c */
 391 void evergreen_init_state_functions(struct r600_context *rctx);
 392 void evergreen_init_atom_start_cs(struct r600_context *rctx);
 393 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 394 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 395 void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
 396 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
 397 void evergreen_polygon_offset_update(struct r600_context *rctx);
 398 boolean evergreen_is_format_supported(struct pipe_screen *screen,
 399                                       enum pipe_format format,
 400                                       enum pipe_texture_target target,
 401                                       unsigned sample_count,
 402                                       unsigned usage);
 403
 404 /* r600_blit.c */
 405 void r600_init_blit_functions(struct r600_context *rctx);
 406 void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
 407 void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
 408 void r600_flush_depth_textures(struct r600_context *rctx);
 409
 410 /* r600_buffer.c */
 411 bool r600_init_resource(struct r600_screen *rscreen,
 412                         struct r600_resource *res,
 413                         unsigned size, unsigned alignment,
 414                         unsigned bind, unsigned usage);
 415 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 416                                          const struct pipe_resource *templ);
 417
 418 /* r600_pipe.c */
 419 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 420                 unsigned flags);
 421
 422 /* r600_query.c */
 423 void r600_init_query_functions(struct r600_context *rctx);
 424 void r600_suspend_nontimer_queries(struct r600_context *ctx);
 425 void r600_resume_nontimer_queries(struct r600_context *ctx);
 426 void r600_suspend_timer_queries(struct r600_context *ctx);
 427 void r600_resume_timer_queries(struct r600_context *ctx);
 428
 429 /* r600_resource.c */
 430 void r600_init_context_resource_functions(struct r600_context *r600);
 431
 432 /* r600_shader.c */
 433 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 434 #ifdef HAVE_OPENCL
 435 int r600_compute_shader_create(struct pipe_context * ctx,
 436         LLVMModuleRef mod,  struct r600_bytecode * bytecode);
 437 #endif
 438 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 439 int r600_find_vs_semantic_index(struct r600_shader *vs,
 440                                 struct r600_shader *ps, int id);
 441
 442 /* r600_state.c */
 443 void r600_set_scissor_state(struct r600_context *rctx,
 444                             const struct pipe_scissor_state *state);
 445 void r600_update_sampler_states(struct r600_context *rctx);
 446 void r600_init_state_functions(struct r600_context *rctx);
 447 void r600_init_atom_start_cs(struct r600_context *rctx);
 448 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 449 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 450 void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
 451 void *r600_create_db_flush_dsa(struct r600_context *rctx);
 452 void r600_polygon_offset_update(struct r600_context *rctx);
 453 void r600_adjust_gprs(struct r600_context *rctx);
 454 boolean r600_is_format_supported(struct pipe_screen *screen,
 455                                  enum pipe_format format,
 456                                  enum pipe_texture_target target,
 457                                  unsigned sample_count,
 458                                  unsigned usage);
 459
 460 /* r600_texture.c */
 461 void r600_init_screen_texture_functions(struct pipe_screen *screen);
 462 void r600_init_surface_functions(struct r600_context *r600);
 463 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
 464                                   const unsigned char *swizzle_view,
 465                                   uint32_t *word4_p, uint32_t *yuv_format_p);
 466 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
 467                                         unsigned level, unsigned layer);
 468
 469 /* r600_translate.c */
 470 void r600_translate_index_buffer(struct r600_context *r600,
 471                                  struct pipe_index_buffer *ib,
 472                                  unsigned count);
 473
 474 /* r600_state_common.c */
 475 void r600_init_atom(struct r600_atom *atom,
 476                     void (*emit)(struct r600_context *ctx, struct r600_atom *state),
 477                     unsigned num_dw, enum r600_atom_flags flags);
 478 void r600_init_common_atoms(struct r600_context *rctx);
 479 unsigned r600_get_cb_flush_flags(struct r600_context *rctx);
 480 void r600_texture_barrier(struct pipe_context *ctx);
 481 void r600_set_index_buffer(struct pipe_context *ctx,
 482                            const struct pipe_index_buffer *ib);
 483 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 484                              const struct pipe_vertex_buffer *buffers);
 485 void *r600_create_vertex_elements(struct pipe_context *ctx,
 486                                   unsigned count,
 487                                   const struct pipe_vertex_element *elements);
 488 void r600_delete_vertex_element(struct pipe_context *ctx, void *state);
 489 void r600_bind_blend_state(struct pipe_context *ctx, void *state);
 490 void r600_set_blend_color(struct pipe_context *ctx,
 491                           const struct pipe_blend_color *state);
 492 void r600_bind_dsa_state(struct pipe_context *ctx, void *state);
 493 void r600_set_max_scissor(struct r600_context *rctx);
 494 void r600_bind_rs_state(struct pipe_context *ctx, void *state);
 495 void r600_delete_rs_state(struct pipe_context *ctx, void *state);
 496 void r600_sampler_view_destroy(struct pipe_context *ctx,
 497                                struct pipe_sampler_view *state);
 498 void r600_delete_state(struct pipe_context *ctx, void *state);
 499 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
 500 void *r600_create_shader_state(struct pipe_context *ctx,
 501                                const struct pipe_shader_state *state);
 502 void r600_bind_ps_shader(struct pipe_context *ctx, void *state);
 503 void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
 504 void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
 505 void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
 506 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
 507 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 508                               struct pipe_constant_buffer *cb);
 509 struct pipe_stream_output_target *
 510 r600_create_so_target(struct pipe_context *ctx,
 511                       struct pipe_resource *buffer,
 512                       unsigned buffer_offset,
 513                       unsigned buffer_size);
 514 void r600_so_target_destroy(struct pipe_context *ctx,
 515                             struct pipe_stream_output_target *target);
 516 void r600_set_so_targets(struct pipe_context *ctx,
 517                          unsigned num_targets,
 518                          struct pipe_stream_output_target **targets,
 519                          unsigned append_bitmask);
 520 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
 521                                const struct pipe_stencil_ref *state);
 522 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 523 uint32_t r600_translate_stencil_op(int s_op);
 524 uint32_t r600_translate_fill(uint32_t func);
 525 unsigned r600_tex_wrap(unsigned wrap);
 526 unsigned r600_tex_filter(unsigned filter);
 527 unsigned r600_tex_mipfilter(unsigned filter);
 528 unsigned r600_tex_compare(unsigned compare);
 529
 530 /*
 531  * Helpers for building command buffers
 532  */
 533
 534 #define PKT3_SET_CONFIG_REG     0x68
 535 #define PKT3_SET_CONTEXT_REG    0x69
 536 #define PKT3_SET_CTL_CONST      0x6F
 537 #define PKT3_SET_LOOP_CONST                    0x6C
 538
 539 #define R600_CONFIG_REG_OFFSET  0x08000
 540 #define R600_CONTEXT_REG_OFFSET 0x28000
 541 #define R600_CTL_CONST_OFFSET   0x3CFF0
 542 #define R600_LOOP_CONST_OFFSET                 0X0003E200
 543 #define EG_LOOP_CONST_OFFSET               0x0003A200
 544
 545 #define PKT_TYPE_S(x)                   (((x) & 0x3) << 30)
 546 #define PKT_COUNT_S(x)                  (((x) & 0x3FFF) << 16)
 547 #define PKT3_IT_OPCODE_S(x)             (((x) & 0xFF) << 8)
 548 #define PKT3_PREDICATE(x)               (((x) >> 0) & 0x1)
 549 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
 550
 551 static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value)
 552 {
 553         cb->buf[cb->atom.num_dw++] = value;
 554 }
 555
 556 static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 557 {
 558         assert(reg < R600_CONTEXT_REG_OFFSET);
 559         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 560         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
 561         cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
 562 }
 563
 564 static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 565 {
 566         assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
 567         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 568         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
 569         cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
 570 }
 571
 572 static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 573 {
 574         assert(reg >= R600_CTL_CONST_OFFSET);
 575         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 576         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
 577         cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
 578 }
 579
 580 static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 581 {
 582         assert(reg >= R600_LOOP_CONST_OFFSET);
 583         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 584         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
 585         cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
 586 }
 587
 588 static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 589 {
 590         assert(reg >= EG_LOOP_CONST_OFFSET);
 591         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 592         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
 593         cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
 594 }
 595
 596 static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 597 {
 598         r600_store_config_reg_seq(cb, reg, 1);
 599         r600_store_value(cb, value);
 600 }
 601
 602 static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 603 {
 604         r600_store_context_reg_seq(cb, reg, 1);
 605         r600_store_value(cb, value);
 606 }
 607
 608 static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 609 {
 610         r600_store_ctl_const_seq(cb, reg, 1);
 611         r600_store_value(cb, value);
 612 }
 613
 614 static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 615 {
 616         r600_store_loop_const_seq(cb, reg, 1);
 617         r600_store_value(cb, value);
 618 }
 619
 620 static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 621 {
 622         eg_store_loop_const_seq(cb, reg, 1);
 623         r600_store_value(cb, value);
 624 }
 625
 626 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags);
 627 void r600_release_command_buffer(struct r600_command_buffer *cb);
 628
 629 /*
 630  * Helpers for emitting state into a command stream directly.
 631  */
 632
 633 static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo,
 634                                              enum radeon_bo_usage usage)
 635 {
 636         assert(usage);
 637         return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4;
 638 }
 639
 640 static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value)
 641 {
 642         cs->buf[cs->cdw++] = value;
 643 }
 644
 645 static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 646 {
 647         assert(reg < R600_CONTEXT_REG_OFFSET);
 648         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 649         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
 650         cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
 651 }
 652
 653 static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 654 {
 655         assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
 656         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 657         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
 658         cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
 659 }
 660
 661 static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 662 {
 663         assert(reg >= R600_CTL_CONST_OFFSET);
 664         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 665         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
 666         cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
 667 }
 668
 669 static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 670 {
 671         r600_write_config_reg_seq(cs, reg, 1);
 672         r600_write_value(cs, value);
 673 }
 674
 675 static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 676 {
 677         r600_write_context_reg_seq(cs, reg, 1);
 678         r600_write_value(cs, value);
 679 }
 680
 681 static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 682 {
 683         r600_write_ctl_const_seq(cs, reg, 1);
 684         r600_write_value(cs, value);
 685 }
 686
 687 /*
 688  * common helpers
 689  */
 690 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
 691 {
 692         return value * (1 << frac_bits);
 693 }
 694 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
 695
 696 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 697 {
 698         if (filter <= 1)   return 0;
 699         if (filter <= 2)   return 1;
 700         if (filter <= 4)   return 2;
 701         if (filter <= 8)   return 3;
 702          /* else */        return 4;
 703 }
 704
 705 /* 12.4 fixed-point */
 706 static INLINE unsigned r600_pack_float_12p4(float x)
 707 {
 708         return x <= 0    ? 0 :
 709                x >= 4096 ? 0xffff : x * 16;
 710 }
 711
 712 static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource)
 713 {
 714         struct r600_screen *rscreen = (struct r600_screen*)screen;
 715         struct r600_resource *rresource = (struct r600_resource*)resource;
 716
 717         return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);
 718 }
 719
 720 #endif