src/gallium/drivers/r600/r600_pipe.h

   1 /*
   2  * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * on the rights to use, copy, modify, merge, publish, distribute, sub
   8  * license, and/or sell copies of the Software, and to permit persons to whom
   9  * the Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  18  * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
  19  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  20  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  21  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Jerome Glisse
  25  */
  26 #ifndef R600_PIPE_H
  27 #define R600_PIPE_H
  28
  29 #include "util/u_blitter.h"
  30 #include "util/u_slab.h"
  31 #include "r600.h"
  32 #include "r600_llvm.h"
  33 #include "r600_public.h"
  34 #include "r600_shader.h"
  35 #include "r600_resource.h"
  36 #include "evergreen_compute.h"
  37
  38 #define R600_MAX_CONST_BUFFERS 2
  39 #define R600_MAX_CONST_BUFFER_SIZE 4096
  40
  41 #ifdef PIPE_ARCH_BIG_ENDIAN
  42 #define R600_BIG_ENDIAN 1
  43 #else
  44 #define R600_BIG_ENDIAN 0
  45 #endif
  46
  47 enum r600_atom_flags {
  48         /* When set, atoms are added at the beginning of the dirty list
  49          * instead of the end. */
  50         EMIT_EARLY = (1 << 0)
  51 };
  52
  53 /* This encapsulates a state or an operation which can emitted into the GPU
  54  * command stream. It's not limited to states only, it can be used for anything
  55  * that wants to write commands into the CS (e.g. cache flushes). */
  56 struct r600_atom {
  57         void (*emit)(struct r600_context *ctx, struct r600_atom *state);
  58
  59         unsigned                num_dw;
  60         enum r600_atom_flags    flags;
  61         bool                    dirty;
  62
  63         struct list_head        head;
  64 };
  65
  66 /* This is an atom containing GPU commands that never change.
  67  * This is supposed to be copied directly into the CS. */
  68 struct r600_command_buffer {
  69         struct r600_atom atom;
  70         uint32_t *buf;
  71         unsigned max_num_dw;
  72         unsigned pkt_flags;
  73 };
  74
  75 struct r600_surface_sync_cmd {
  76         struct r600_atom atom;
  77         unsigned flush_flags; /* CP_COHER_CNTL */
  78 };
  79
  80 struct r600_db_misc_state {
  81         struct r600_atom atom;
  82         bool occlusion_query_enabled;
  83         bool flush_depthstencil_through_cb;
  84         bool copy_depth, copy_stencil;
  85         unsigned copy_sample;
  86         unsigned log_samples;
  87 };
  88
  89 struct r600_cb_misc_state {
  90         struct r600_atom atom;
  91         unsigned cb_color_control; /* this comes from blend state */
  92         unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
  93         unsigned nr_cbufs;
  94         unsigned nr_ps_color_outputs;
  95         bool multiwrite;
  96         bool dual_src_blend;
  97 };
  98
  99 struct r600_alphatest_state {
 100         struct r600_atom atom;
 101         unsigned sx_alpha_test_control; /* this comes from dsa state */
 102         unsigned sx_alpha_ref; /* this comes from dsa state */
 103         bool bypass;
 104         bool cb0_export_16bpc; /* from set_framebuffer_state */
 105 };
 106
 107 struct r600_cs_shader_state {
 108         struct r600_atom atom;
 109         struct r600_pipe_compute *shader;
 110 };
 111
 112 struct r600_sample_mask {
 113         struct r600_atom atom;
 114         uint16_t sample_mask; /* there are only 8 bits on EG, 16 bits on Cayman */
 115 };
 116
 117 enum r600_pipe_state_id {
 118         R600_PIPE_STATE_BLEND = 0,
 119         R600_PIPE_STATE_BLEND_COLOR,
 120         R600_PIPE_STATE_CONFIG,
 121         R600_PIPE_STATE_SEAMLESS_CUBEMAP,
 122         R600_PIPE_STATE_CLIP,
 123         R600_PIPE_STATE_SCISSOR,
 124         R600_PIPE_STATE_VIEWPORT,
 125         R600_PIPE_STATE_RASTERIZER,
 126         R600_PIPE_STATE_VGT,
 127         R600_PIPE_STATE_FRAMEBUFFER,
 128         R600_PIPE_STATE_DSA,
 129         R600_PIPE_STATE_STENCIL_REF,
 130         R600_PIPE_STATE_PS_SHADER,
 131         R600_PIPE_STATE_VS_SHADER,
 132         R600_PIPE_STATE_CONSTANT,
 133         R600_PIPE_STATE_SAMPLER,
 134         R600_PIPE_STATE_RESOURCE,
 135         R600_PIPE_STATE_POLYGON_OFFSET,
 136         R600_PIPE_STATE_FETCH_SHADER,
 137         R600_PIPE_STATE_SPI,
 138         R600_PIPE_NSTATES
 139 };
 140
 141 struct compute_memory_pool;
 142 void compute_memory_pool_delete(struct compute_memory_pool* pool);
 143 struct compute_memory_pool* compute_memory_pool_new(
 144         struct r600_screen *rscreen);
 145
 146 struct r600_pipe_fences {
 147         struct r600_resource            *bo;
 148         unsigned                        *data;
 149         unsigned                        next_index;
 150         /* linked list of preallocated blocks */
 151         struct list_head                blocks;
 152         /* linked list of freed fences */
 153         struct list_head                pool;
 154         pipe_mutex                      mutex;
 155 };
 156
 157 struct r600_screen {
 158         struct pipe_screen              screen;
 159         struct radeon_winsys            *ws;
 160         unsigned                        family;
 161         enum chip_class                 chip_class;
 162         struct radeon_info              info;
 163         bool                            has_streamout;
 164         struct r600_tiling_info         tiling_info;
 165         struct r600_pipe_fences         fences;
 166
 167         /*for compute global memory binding, we allocate stuff here, instead of
 168          * buffers.
 169          * XXX: Not sure if this is the best place for global_pool.  Also,
 170          * it's not thread safe, so it won't work with multiple contexts. */
 171         struct compute_memory_pool *global_pool;
 172 };
 173
 174 struct r600_pipe_sampler_view {
 175         struct pipe_sampler_view        base;
 176         struct r600_resource            *tex_resource;
 177         uint32_t                        tex_resource_words[8];
 178 };
 179
 180 struct r600_pipe_rasterizer {
 181         struct r600_pipe_state          rstate;
 182         boolean                         flatshade;
 183         boolean                         two_side;
 184         unsigned                        sprite_coord_enable;
 185         unsigned                        clip_plane_enable;
 186         unsigned                        pa_sc_line_stipple;
 187         unsigned                        pa_cl_clip_cntl;
 188         float                           offset_units;
 189         float                           offset_scale;
 190         bool                            scissor_enable;
 191         bool                            multisample_enable;
 192 };
 193
 194 struct r600_pipe_blend {
 195         struct r600_pipe_state          rstate;
 196         unsigned                        cb_target_mask;
 197         unsigned                        cb_color_control;
 198         bool                            dual_src_blend;
 199         bool                            alpha_to_one;
 200 };
 201
 202 struct r600_pipe_dsa {
 203         struct r600_pipe_state          rstate;
 204         unsigned                        alpha_ref;
 205         ubyte                           valuemask[2];
 206         ubyte                           writemask[2];
 207         unsigned                        sx_alpha_test_control;
 208 };
 209
 210 struct r600_vertex_element
 211 {
 212         unsigned                        count;
 213         struct pipe_vertex_element      elements[PIPE_MAX_ATTRIBS];
 214         struct r600_resource            *fetch_shader;
 215         unsigned                        fs_size;
 216         struct r600_pipe_state          rstate;
 217 };
 218
 219 struct r600_pipe_shader;
 220
 221 struct r600_pipe_shader_selector {
 222         struct r600_pipe_shader *current;
 223
 224         struct tgsi_token       *tokens;
 225         struct pipe_stream_output_info  so;
 226
 227         unsigned        num_shaders;
 228
 229         /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
 230         unsigned        type;
 231
 232         unsigned        nr_ps_max_color_exports;
 233 };
 234
 235 struct r600_pipe_shader {
 236         struct r600_pipe_shader_selector *selector;
 237         struct r600_pipe_shader *next_variant;
 238         struct r600_shader              shader;
 239         struct r600_pipe_state          rstate;
 240         struct r600_resource            *bo;
 241         struct r600_resource            *bo_fetch;
 242         struct r600_vertex_element      vertex_elements;
 243         unsigned        sprite_coord_enable;
 244         unsigned        flatshade;
 245         unsigned        pa_cl_vs_out_cntl;
 246         unsigned        nr_ps_color_outputs;
 247         unsigned        key;
 248         unsigned                db_shader_control;
 249         unsigned                ps_depth_export;
 250 };
 251
 252 struct r600_pipe_sampler_state {
 253         uint32_t                        tex_sampler_words[3];
 254         uint32_t                        border_color[4];
 255         bool                            border_color_use;
 256         bool                            seamless_cube_map;
 257 };
 258
 259 /* needed for blitter save */
 260 #define NUM_TEX_UNITS 16
 261
 262 struct r600_seamless_cube_map {
 263         struct r600_atom                atom;
 264         bool                            enabled;
 265 };
 266
 267 struct r600_samplerview_state {
 268         struct r600_atom                atom;
 269         struct r600_pipe_sampler_view   *views[NUM_TEX_UNITS];
 270         uint32_t                        enabled_mask;
 271         uint32_t                        dirty_mask;
 272         uint32_t                        compressed_depthtex_mask; /* which textures are depth */
 273         uint32_t                        compressed_colortex_mask;
 274 };
 275
 276 struct r600_textures_info {
 277         struct r600_samplerview_state   views;
 278         struct r600_atom                atom_sampler;
 279         struct r600_pipe_sampler_state  *samplers[NUM_TEX_UNITS];
 280         unsigned                        n_samplers;
 281         bool                            is_array_sampler[NUM_TEX_UNITS];
 282 };
 283
 284 struct r600_fence {
 285         struct pipe_reference           reference;
 286         unsigned                        index; /* in the shared bo */
 287         struct r600_resource            *sleep_bo;
 288         struct list_head                head;
 289 };
 290
 291 #define FENCE_BLOCK_SIZE 16
 292
 293 struct r600_fence_block {
 294         struct r600_fence               fences[FENCE_BLOCK_SIZE];
 295         struct list_head                head;
 296 };
 297
 298 #define R600_CONSTANT_ARRAY_SIZE 256
 299 #define R600_RESOURCE_ARRAY_SIZE 160
 300
 301 struct r600_stencil_ref
 302 {
 303         ubyte ref_value[2];
 304         ubyte valuemask[2];
 305         ubyte writemask[2];
 306 };
 307
 308 struct r600_constbuf_state
 309 {
 310         struct r600_atom                atom;
 311         struct pipe_constant_buffer     cb[PIPE_MAX_CONSTANT_BUFFERS];
 312         uint32_t                        enabled_mask;
 313         uint32_t                        dirty_mask;
 314 };
 315
 316 struct r600_vertexbuf_state
 317 {
 318         struct r600_atom                atom;
 319         struct pipe_vertex_buffer       vb[PIPE_MAX_ATTRIBS];
 320         uint32_t                        enabled_mask; /* non-NULL buffers */
 321         uint32_t                        dirty_mask;
 322 };
 323
 324 struct r600_context {
 325         struct pipe_context             context;
 326         struct blitter_context          *blitter;
 327         enum radeon_family              family;
 328         enum chip_class                 chip_class;
 329         boolean                         has_vertex_cache;
 330         unsigned                        r6xx_num_clause_temp_gprs;
 331         void                            *custom_dsa_flush;
 332         void                            *custom_blend_resolve;
 333         void                            *custom_blend_decompress;
 334
 335         struct r600_screen              *screen;
 336         struct radeon_winsys            *ws;
 337         struct r600_pipe_state          *states[R600_PIPE_NSTATES];
 338         struct r600_vertex_element      *vertex_elements;
 339         struct pipe_framebuffer_state   framebuffer;
 340         unsigned                        compressed_cb_mask;
 341         unsigned                        compute_cb_target_mask;
 342         unsigned                        db_shader_control;
 343         unsigned                        pa_sc_line_stipple;
 344         unsigned                        pa_cl_clip_cntl;
 345         /* for saving when using blitter */
 346         struct pipe_stencil_ref         stencil_ref;
 347         struct pipe_viewport_state      viewport;
 348         struct pipe_clip_state          clip;
 349         struct r600_pipe_shader_selector        *ps_shader;
 350         struct r600_pipe_shader_selector        *vs_shader;
 351         struct r600_pipe_rasterizer     *rasterizer;
 352         struct r600_pipe_state          vgt;
 353         struct r600_pipe_state          spi;
 354         struct pipe_query               *current_render_cond;
 355         unsigned                        current_render_cond_mode;
 356         struct pipe_query               *saved_render_cond;
 357         unsigned                        saved_render_cond_mode;
 358         /* shader information */
 359         boolean                         two_side;
 360         boolean                         spi_dirty;
 361         unsigned                        sprite_coord_enable;
 362         boolean                         flatshade;
 363         boolean                         export_16bpc;
 364         unsigned                        nr_cbufs;
 365         bool                            alpha_to_one;
 366         bool                            multisample_enable;
 367         bool                            cb0_is_integer;
 368
 369         struct u_upload_mgr             *uploader;
 370         struct util_slab_mempool        pool_transfers;
 371
 372         unsigned default_ps_gprs, default_vs_gprs;
 373
 374         /* States based on r600_atom. */
 375         struct list_head                dirty_states;
 376         struct r600_command_buffer      start_cs_cmd; /* invariant state mostly */
 377         /** Compute specific registers initializations.  The start_cs_cmd atom
 378          *  must be emitted before start_compute_cs_cmd. */
 379         struct r600_command_buffer      start_compute_cs_cmd;
 380         struct r600_surface_sync_cmd    surface_sync_cmd;
 381         struct r600_atom                r6xx_flush_and_inv_cmd;
 382         struct r600_alphatest_state     alphatest_state;
 383         struct r600_cb_misc_state       cb_misc_state;
 384         struct r600_db_misc_state       db_misc_state;
 385         /** Vertex buffers for fetch shaders */
 386         struct r600_vertexbuf_state     vertex_buffer_state;
 387         /** Vertex buffers for compute shaders */
 388         struct r600_vertexbuf_state     cs_vertex_buffer_state;
 389         struct r600_constbuf_state      vs_constbuf_state;
 390         struct r600_constbuf_state      ps_constbuf_state;
 391         struct r600_textures_info       vs_samplers;
 392         struct r600_textures_info       ps_samplers;
 393         struct r600_seamless_cube_map   seamless_cube_map;
 394         struct r600_cs_shader_state     cs_shader_state;
 395         struct r600_sample_mask         sample_mask;
 396
 397         /* current external blend state (from state tracker) */
 398         struct r600_pipe_blend          *blend;
 399         /* state with disabled blending - used internally with blend_override */
 400         struct r600_pipe_blend          *no_blend;
 401
 402         /* 1 - override current blend state with no_blend, 0 - use external state */
 403         unsigned        blend_override;
 404
 405         struct radeon_winsys_cs *cs;
 406
 407         struct r600_range       *range;
 408         unsigned                nblocks;
 409         struct r600_block       **blocks;
 410         struct list_head        dirty;
 411         struct list_head        enable_list;
 412         unsigned                pm4_dirty_cdwords;
 413         unsigned                ctx_pm4_ndwords;
 414
 415         /* The list of active queries. Only one query of each type can be active. */
 416         int                     num_occlusion_queries;
 417
 418         /* Manage queries in two separate groups:
 419          * The timer ones and the others (streamout, occlusion).
 420          *
 421          * We do this because we should only suspend non-timer queries for u_blitter,
 422          * and later if the non-timer queries are suspended, the context flush should
 423          * only suspend and resume the timer queries. */
 424         struct list_head        active_timer_queries;
 425         unsigned                num_cs_dw_timer_queries_suspend;
 426         struct list_head        active_nontimer_queries;
 427         unsigned                num_cs_dw_nontimer_queries_suspend;
 428
 429         unsigned                num_cs_dw_streamout_end;
 430
 431         unsigned                backend_mask;
 432         unsigned                max_db; /* for OQ */
 433         unsigned                flags;
 434         boolean                 predicate_drawing;
 435
 436         unsigned                num_so_targets;
 437         struct r600_so_target   *so_targets[PIPE_MAX_SO_BUFFERS];
 438         boolean                 streamout_start;
 439         unsigned                streamout_append_bitmask;
 440
 441         /* There is no scissor enable bit on r6xx, so we must use a workaround.
 442          * These track the current scissor state. */
 443         bool                    scissor_enable;
 444         struct pipe_scissor_state scissor_state;
 445
 446         /* With rasterizer discard, there doesn't have to be a pixel shader.
 447          * In that case, we bind this one: */
 448         void                    *dummy_pixel_shader;
 449
 450         boolean                 dual_src_blend;
 451
 452         /* Index buffer. */
 453         struct pipe_index_buffer index_buffer;
 454
 455         /* Dummy CMASK and FMASK buffers used to get around the R6xx hardware
 456          * bug where valid CMASK and FMASK are required to be present to avoid
 457          * a hardlock in certain operations but aren't actually used
 458          * for anything useful. */
 459         struct r600_resource *dummy_fmask;
 460         struct r600_resource *dummy_cmask;
 461 };
 462
 463 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
 464 {
 465         atom->emit(rctx, atom);
 466         atom->dirty = false;
 467         if (atom->head.next && atom->head.prev)
 468                 LIST_DELINIT(&atom->head);
 469 }
 470
 471 static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state)
 472 {
 473         if (!state->dirty) {
 474                 if (state->flags & EMIT_EARLY) {
 475                         LIST_ADD(&state->head, &rctx->dirty_states);
 476                 } else {
 477                         LIST_ADDTAIL(&state->head, &rctx->dirty_states);
 478                 }
 479                 state->dirty = true;
 480         }
 481 }
 482
 483 /* evergreen_state.c */
 484 void evergreen_init_common_regs(struct r600_command_buffer *cb,
 485                                 enum chip_class ctx_chip_class,
 486                                 enum radeon_family ctx_family,
 487                                 int ctx_drm_minor);
 488
 489 void evergreen_init_state_functions(struct r600_context *rctx);
 490 void evergreen_init_atom_start_cs(struct r600_context *rctx);
 491 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 492 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 493 void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
 494 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
 495 void *evergreen_create_resolve_blend(struct r600_context *rctx);
 496 void *evergreen_create_decompress_blend(struct r600_context *rctx);
 497 void evergreen_polygon_offset_update(struct r600_context *rctx);
 498 boolean evergreen_is_format_supported(struct pipe_screen *screen,
 499                                       enum pipe_format format,
 500                                       enum pipe_texture_target target,
 501                                       unsigned sample_count,
 502                                       unsigned usage);
 503 void evergreen_init_color_surface(struct r600_context *rctx,
 504                                   struct r600_surface *surf);
 505 void evergreen_update_dual_export_state(struct r600_context * rctx);
 506
 507 /* r600_blit.c */
 508 void r600_copy_buffer(struct pipe_context *ctx, struct
 509                       pipe_resource *dst, unsigned dstx,
 510                       struct pipe_resource *src, const struct pipe_box *src_box);
 511 void r600_init_blit_functions(struct r600_context *rctx);
 512 void r600_blit_decompress_depth(struct pipe_context *ctx,
 513                 struct r600_texture *texture,
 514                 struct r600_texture *staging,
 515                 unsigned first_level, unsigned last_level,
 516                 unsigned first_layer, unsigned last_layer,
 517                 unsigned first_sample, unsigned last_sample);
 518 void r600_decompress_depth_textures(struct r600_context *rctx,
 519                                     struct r600_samplerview_state *textures);
 520 void r600_decompress_color_textures(struct r600_context *rctx,
 521                                     struct r600_samplerview_state *textures);
 522
 523 /* r600_buffer.c */
 524 bool r600_init_resource(struct r600_screen *rscreen,
 525                         struct r600_resource *res,
 526                         unsigned size, unsigned alignment,
 527                         unsigned bind, unsigned usage);
 528 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
 529                                          const struct pipe_resource *templ,
 530                                          unsigned alignment);
 531
 532 /* r600_pipe.c */
 533 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
 534                 unsigned flags);
 535
 536 /* r600_query.c */
 537 void r600_init_query_functions(struct r600_context *rctx);
 538 void r600_suspend_nontimer_queries(struct r600_context *ctx);
 539 void r600_resume_nontimer_queries(struct r600_context *ctx);
 540 void r600_suspend_timer_queries(struct r600_context *ctx);
 541 void r600_resume_timer_queries(struct r600_context *ctx);
 542
 543 /* r600_resource.c */
 544 void r600_init_context_resource_functions(struct r600_context *r600);
 545
 546 /* r600_shader.c */
 547 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 548 #ifdef HAVE_OPENCL
 549 int r600_compute_shader_create(struct pipe_context * ctx,
 550         LLVMModuleRef mod,  struct r600_bytecode * bytecode);
 551 #endif
 552 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 553
 554 /* r600_state.c */
 555 void r600_set_scissor_state(struct r600_context *rctx,
 556                             const struct pipe_scissor_state *state);
 557 void r600_init_state_functions(struct r600_context *rctx);
 558 void r600_init_atom_start_cs(struct r600_context *rctx);
 559 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 560 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
 561 void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
 562 void *r600_create_db_flush_dsa(struct r600_context *rctx);
 563 void *r600_create_resolve_blend(struct r600_context *rctx);
 564 void *r700_create_resolve_blend(struct r600_context *rctx);
 565 void *r600_create_decompress_blend(struct r600_context *rctx);
 566 void r600_polygon_offset_update(struct r600_context *rctx);
 567 void r600_adjust_gprs(struct r600_context *rctx);
 568 boolean r600_is_format_supported(struct pipe_screen *screen,
 569                                  enum pipe_format format,
 570                                  enum pipe_texture_target target,
 571                                  unsigned sample_count,
 572                                  unsigned usage);
 573 void r600_update_dual_export_state(struct r600_context * rctx);
 574
 575 /* r600_texture.c */
 576 void r600_init_screen_texture_functions(struct pipe_screen *screen);
 577 void r600_init_surface_functions(struct r600_context *r600);
 578 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
 579                                   const unsigned char *swizzle_view,
 580                                   uint32_t *word4_p, uint32_t *yuv_format_p);
 581 unsigned r600_texture_get_offset(struct r600_texture *rtex,
 582                                         unsigned level, unsigned layer);
 583
 584 /* r600_translate.c */
 585 void r600_translate_index_buffer(struct r600_context *r600,
 586                                  struct pipe_index_buffer *ib,
 587                                  unsigned count);
 588
 589 /* r600_state_common.c */
 590 void r600_init_atom(struct r600_atom *atom,
 591                     void (*emit)(struct r600_context *ctx, struct r600_atom *state),
 592                     unsigned num_dw, enum r600_atom_flags flags);
 593 void r600_init_common_atoms(struct r600_context *rctx);
 594 unsigned r600_get_cb_flush_flags(struct r600_context *rctx);
 595 void r600_texture_barrier(struct pipe_context *ctx);
 596 void r600_set_index_buffer(struct pipe_context *ctx,
 597                            const struct pipe_index_buffer *ib);
 598 void r600_vertex_buffers_dirty(struct r600_context *rctx);
 599 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
 600                              const struct pipe_vertex_buffer *input);
 601 void r600_sampler_views_dirty(struct r600_context *rctx,
 602                               struct r600_samplerview_state *state);
 603 void r600_set_sampler_views(struct pipe_context *pipe,
 604                             unsigned shader,
 605                             unsigned start,
 606                             unsigned count,
 607                             struct pipe_sampler_view **views);
 608 void r600_bind_vs_samplers(struct pipe_context *ctx, unsigned count, void **states);
 609 void r600_bind_ps_samplers(struct pipe_context *ctx, unsigned count, void **states);
 610 void *r600_create_vertex_elements(struct pipe_context *ctx,
 611                                   unsigned count,
 612                                   const struct pipe_vertex_element *elements);
 613 void r600_delete_vertex_element(struct pipe_context *ctx, void *state);
 614 void r600_bind_blend_state(struct pipe_context *ctx, void *state);
 615 void r600_set_blend_color(struct pipe_context *ctx,
 616                           const struct pipe_blend_color *state);
 617 void r600_bind_dsa_state(struct pipe_context *ctx, void *state);
 618 void r600_set_max_scissor(struct r600_context *rctx);
 619 void r600_bind_rs_state(struct pipe_context *ctx, void *state);
 620 void r600_delete_rs_state(struct pipe_context *ctx, void *state);
 621 void r600_sampler_view_destroy(struct pipe_context *ctx,
 622                                struct pipe_sampler_view *state);
 623 void r600_delete_sampler(struct pipe_context *ctx, void *state);
 624 void r600_delete_state(struct pipe_context *ctx, void *state);
 625 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
 626 void *r600_create_shader_state_ps(struct pipe_context *ctx,
 627                    const struct pipe_shader_state *state);
 628 void *r600_create_shader_state_vs(struct pipe_context *ctx,
 629                    const struct pipe_shader_state *state);
 630 void r600_bind_ps_shader(struct pipe_context *ctx, void *state);
 631 void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
 632 void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
 633 void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
 634 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
 635 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
 636                               struct pipe_constant_buffer *cb);
 637 struct pipe_stream_output_target *
 638 r600_create_so_target(struct pipe_context *ctx,
 639                       struct pipe_resource *buffer,
 640                       unsigned buffer_offset,
 641                       unsigned buffer_size);
 642 void r600_so_target_destroy(struct pipe_context *ctx,
 643                             struct pipe_stream_output_target *target);
 644 void r600_set_so_targets(struct pipe_context *ctx,
 645                          unsigned num_targets,
 646                          struct pipe_stream_output_target **targets,
 647                          unsigned append_bitmask);
 648 void r600_set_sample_mask(struct pipe_context *pipe, unsigned sample_mask);
 649 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
 650                                const struct pipe_stencil_ref *state);
 651 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
 652 void r600_draw_rectangle(struct blitter_context *blitter,
 653                          unsigned x1, unsigned y1, unsigned x2, unsigned y2, float depth,
 654                          enum blitter_attrib_type type, const union pipe_color_union *attrib);
 655 uint32_t r600_translate_stencil_op(int s_op);
 656 uint32_t r600_translate_fill(uint32_t func);
 657 unsigned r600_tex_wrap(unsigned wrap);
 658 unsigned r600_tex_filter(unsigned filter);
 659 unsigned r600_tex_mipfilter(unsigned filter);
 660 unsigned r600_tex_compare(unsigned compare);
 661
 662 /*
 663  * Helpers for building command buffers
 664  */
 665
 666 #define PKT3_SET_CONFIG_REG     0x68
 667 #define PKT3_SET_CONTEXT_REG    0x69
 668 #define PKT3_SET_CTL_CONST      0x6F
 669 #define PKT3_SET_LOOP_CONST                    0x6C
 670
 671 #define R600_CONFIG_REG_OFFSET  0x08000
 672 #define R600_CONTEXT_REG_OFFSET 0x28000
 673 #define R600_CTL_CONST_OFFSET   0x3CFF0
 674 #define R600_LOOP_CONST_OFFSET                 0X0003E200
 675 #define EG_LOOP_CONST_OFFSET               0x0003A200
 676
 677 #define PKT_TYPE_S(x)                   (((x) & 0x3) << 30)
 678 #define PKT_COUNT_S(x)                  (((x) & 0x3FFF) << 16)
 679 #define PKT3_IT_OPCODE_S(x)             (((x) & 0xFF) << 8)
 680 #define PKT3_PREDICATE(x)               (((x) >> 0) & 0x1)
 681 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
 682
 683 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
 684
 685 /*Evergreen Compute packet3*/
 686 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
 687
 688 static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value)
 689 {
 690         cb->buf[cb->atom.num_dw++] = value;
 691 }
 692
 693 static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 694 {
 695         assert(reg < R600_CONTEXT_REG_OFFSET);
 696         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 697         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
 698         cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
 699 }
 700
 701 /**
 702  * Needs cb->pkt_flags set to  RADEON_CP_PACKET3_COMPUTE_MODE for compute
 703  * shaders.
 704  */
 705 static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 706 {
 707         assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
 708         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 709         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
 710         cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
 711 }
 712
 713 /**
 714  * Needs cb->pkt_flags set to  RADEON_CP_PACKET3_COMPUTE_MODE for compute
 715  * shaders.
 716  */
 717 static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 718 {
 719         assert(reg >= R600_CTL_CONST_OFFSET);
 720         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 721         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
 722         cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
 723 }
 724
 725 static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 726 {
 727         assert(reg >= R600_LOOP_CONST_OFFSET);
 728         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 729         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
 730         cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
 731 }
 732
 733 /**
 734  * Needs cb->pkt_flags set to  RADEON_CP_PACKET3_COMPUTE_MODE for compute
 735  * shaders.
 736  */
 737 static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
 738 {
 739         assert(reg >= EG_LOOP_CONST_OFFSET);
 740         assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
 741         cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
 742         cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
 743 }
 744
 745 static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 746 {
 747         r600_store_config_reg_seq(cb, reg, 1);
 748         r600_store_value(cb, value);
 749 }
 750
 751 static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 752 {
 753         r600_store_context_reg_seq(cb, reg, 1);
 754         r600_store_value(cb, value);
 755 }
 756
 757 static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 758 {
 759         r600_store_ctl_const_seq(cb, reg, 1);
 760         r600_store_value(cb, value);
 761 }
 762
 763 static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 764 {
 765         r600_store_loop_const_seq(cb, reg, 1);
 766         r600_store_value(cb, value);
 767 }
 768
 769 static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
 770 {
 771         eg_store_loop_const_seq(cb, reg, 1);
 772         r600_store_value(cb, value);
 773 }
 774
 775 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags);
 776 void r600_release_command_buffer(struct r600_command_buffer *cb);
 777
 778 /*
 779  * Helpers for emitting state into a command stream directly.
 780  */
 781
 782 static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo,
 783                                              enum radeon_bo_usage usage)
 784 {
 785         assert(usage);
 786         return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4;
 787 }
 788
 789 static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value)
 790 {
 791         cs->buf[cs->cdw++] = value;
 792 }
 793
 794 static INLINE void r600_write_array(struct radeon_winsys_cs *cs, unsigned num, unsigned *ptr)
 795 {
 796         assert(cs->cdw+num <= RADEON_MAX_CMDBUF_DWORDS);
 797         memcpy(&cs->buf[cs->cdw], ptr, num * sizeof(ptr[0]));
 798         cs->cdw += num;
 799 }
 800
 801 static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 802 {
 803         assert(reg < R600_CONTEXT_REG_OFFSET);
 804         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 805         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
 806         cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
 807 }
 808
 809 static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 810 {
 811         assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
 812         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 813         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
 814         cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
 815 }
 816
 817 static INLINE void r600_write_compute_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 818 {
 819         r600_write_context_reg_seq(cs, reg, num);
 820         /* Set the compute bit on the packet header */
 821         cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
 822 }
 823
 824 static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
 825 {
 826         assert(reg >= R600_CTL_CONST_OFFSET);
 827         assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
 828         cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
 829         cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
 830 }
 831
 832 static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 833 {
 834         r600_write_config_reg_seq(cs, reg, 1);
 835         r600_write_value(cs, value);
 836 }
 837
 838 static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 839 {
 840         r600_write_context_reg_seq(cs, reg, 1);
 841         r600_write_value(cs, value);
 842 }
 843
 844 static INLINE void r600_write_compute_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 845 {
 846         r600_write_compute_context_reg_seq(cs, reg, 1);
 847         r600_write_value(cs, value);
 848 }
 849
 850 static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
 851 {
 852         r600_write_ctl_const_seq(cs, reg, 1);
 853         r600_write_value(cs, value);
 854 }
 855
 856 /*
 857  * common helpers
 858  */
 859 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
 860 {
 861         return value * (1 << frac_bits);
 862 }
 863 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
 864
 865 static inline unsigned r600_tex_aniso_filter(unsigned filter)
 866 {
 867         if (filter <= 1)   return 0;
 868         if (filter <= 2)   return 1;
 869         if (filter <= 4)   return 2;
 870         if (filter <= 8)   return 3;
 871          /* else */        return 4;
 872 }
 873
 874 /* 12.4 fixed-point */
 875 static INLINE unsigned r600_pack_float_12p4(float x)
 876 {
 877         return x <= 0    ? 0 :
 878                x >= 4096 ? 0xffff : x * 16;
 879 }
 880
 881 static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource)
 882 {
 883         struct r600_screen *rscreen = (struct r600_screen*)screen;
 884         struct r600_resource *rresource = (struct r600_resource*)resource;
 885
 886         return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);
 887 }
 888
 889 #endif