2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "util/u_slab.h"
31 #include "r600_llvm.h"
32 #include "r600_public.h"
33 #include "r600_shader.h"
34 #include "r600_resource.h"
35 #include "evergreen_compute.h"
37 #define R600_MAX_CONST_BUFFERS 2
38 #define R600_MAX_CONST_BUFFER_SIZE 4096
40 #ifdef PIPE_ARCH_BIG_ENDIAN
41 #define R600_BIG_ENDIAN 1
43 #define R600_BIG_ENDIAN 0
46 enum r600_atom_flags {
47 /* When set, atoms are added at the beginning of the dirty list
48 * instead of the end. */
52 /* This encapsulates a state or an operation which can emitted into the GPU
53 * command stream. It's not limited to states only, it can be used for anything
54 * that wants to write commands into the CS (e.g. cache flushes). */
56 void (*emit)(struct r600_context *ctx, struct r600_atom *state);
59 enum r600_atom_flags flags;
62 struct list_head head;
65 /* This is an atom containing GPU commands that never change.
66 * This is supposed to be copied directly into the CS. */
67 struct r600_command_buffer {
68 struct r600_atom atom;
74 struct r600_surface_sync_cmd {
75 struct r600_atom atom;
76 unsigned flush_flags; /* CP_COHER_CNTL */
79 struct r600_db_misc_state {
80 struct r600_atom atom;
81 bool occlusion_query_enabled;
82 bool flush_depthstencil_through_cb;
85 struct r600_cb_misc_state {
86 struct r600_atom atom;
87 unsigned cb_color_control; /* this comes from blend state */
88 unsigned blend_colormask; /* 8*4 bits for 8 RGBA colorbuffers */
90 unsigned nr_ps_color_outputs;
95 struct r600_alphatest_state {
96 struct r600_atom atom;
97 unsigned sx_alpha_test_control; /* this comes from dsa state */
98 unsigned sx_alpha_ref; /* this comes from dsa state */
100 bool cb0_export_16bpc; /* from set_framebuffer_state */
103 enum r600_pipe_state_id {
104 R600_PIPE_STATE_BLEND = 0,
105 R600_PIPE_STATE_BLEND_COLOR,
106 R600_PIPE_STATE_CONFIG,
107 R600_PIPE_STATE_SEAMLESS_CUBEMAP,
108 R600_PIPE_STATE_CLIP,
109 R600_PIPE_STATE_SCISSOR,
110 R600_PIPE_STATE_VIEWPORT,
111 R600_PIPE_STATE_RASTERIZER,
113 R600_PIPE_STATE_FRAMEBUFFER,
115 R600_PIPE_STATE_STENCIL_REF,
116 R600_PIPE_STATE_PS_SHADER,
117 R600_PIPE_STATE_VS_SHADER,
118 R600_PIPE_STATE_CONSTANT,
119 R600_PIPE_STATE_SAMPLER,
120 R600_PIPE_STATE_RESOURCE,
121 R600_PIPE_STATE_POLYGON_OFFSET,
122 R600_PIPE_STATE_FETCH_SHADER,
127 struct compute_memory_pool;
128 void compute_memory_pool_delete(struct compute_memory_pool* pool);
129 struct compute_memory_pool* compute_memory_pool_new(
130 struct r600_screen *rscreen);
132 struct r600_pipe_fences {
133 struct r600_resource *bo;
136 /* linked list of preallocated blocks */
137 struct list_head blocks;
138 /* linked list of freed fences */
139 struct list_head pool;
144 struct pipe_screen screen;
145 struct radeon_winsys *ws;
147 enum chip_class chip_class;
148 struct radeon_info info;
150 struct r600_tiling_info tiling_info;
151 struct r600_pipe_fences fences;
153 bool use_surface_alloc;
155 /*for compute global memory binding, we allocate stuff here, instead of
157 * XXX: Not sure if this is the best place for global_pool. Also,
158 * it's not thread safe, so it won't work with multiple contexts. */
159 struct compute_memory_pool *global_pool;
162 struct r600_pipe_sampler_view {
163 struct pipe_sampler_view base;
164 struct r600_resource *tex_resource;
165 uint32_t tex_resource_words[8];
168 struct r600_pipe_rasterizer {
169 struct r600_pipe_state rstate;
172 unsigned sprite_coord_enable;
173 unsigned clip_plane_enable;
174 unsigned pa_sc_line_stipple;
175 unsigned pa_cl_clip_cntl;
181 struct r600_pipe_blend {
182 struct r600_pipe_state rstate;
183 unsigned cb_target_mask;
184 unsigned cb_color_control;
188 struct r600_pipe_dsa {
189 struct r600_pipe_state rstate;
193 unsigned sx_alpha_test_control;
196 struct r600_vertex_element
199 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS];
200 struct r600_resource *fetch_shader;
202 struct r600_pipe_state rstate;
205 struct r600_pipe_shader;
207 struct r600_pipe_shader_selector {
208 struct r600_pipe_shader *current;
210 struct tgsi_token *tokens;
211 struct pipe_stream_output_info so;
213 unsigned num_shaders;
215 /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
218 unsigned nr_ps_max_color_exports;
221 struct r600_pipe_shader {
222 struct r600_pipe_shader_selector *selector;
223 struct r600_pipe_shader *next_variant;
224 struct r600_shader shader;
225 struct r600_pipe_state rstate;
226 struct r600_resource *bo;
227 struct r600_resource *bo_fetch;
228 struct r600_vertex_element vertex_elements;
229 unsigned sprite_coord_enable;
231 unsigned pa_cl_vs_out_cntl;
232 unsigned nr_ps_color_outputs;
234 unsigned db_shader_control;
235 unsigned ps_depth_export;
238 struct r600_pipe_sampler_state {
239 struct r600_pipe_state rstate;
240 boolean seamless_cube_map;
243 /* needed for blitter save */
244 #define NUM_TEX_UNITS 16
246 struct r600_samplerview_state
248 struct r600_atom atom;
249 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
250 uint32_t enabled_mask;
252 uint32_t depth_texture_mask; /* which textures are depth */
255 struct r600_textures_info {
256 struct r600_samplerview_state views;
258 struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS];
261 bool is_array_sampler[NUM_TEX_UNITS];
265 struct pipe_reference reference;
266 unsigned index; /* in the shared bo */
267 struct r600_resource *sleep_bo;
268 struct list_head head;
271 #define FENCE_BLOCK_SIZE 16
273 struct r600_fence_block {
274 struct r600_fence fences[FENCE_BLOCK_SIZE];
275 struct list_head head;
278 #define R600_CONSTANT_ARRAY_SIZE 256
279 #define R600_RESOURCE_ARRAY_SIZE 160
281 struct r600_stencil_ref
288 struct r600_constbuf_state
290 struct r600_atom atom;
291 struct pipe_constant_buffer cb[PIPE_MAX_CONSTANT_BUFFERS];
292 uint32_t enabled_mask;
296 struct r600_vertexbuf_state
298 struct r600_atom atom;
299 struct pipe_vertex_buffer vb[PIPE_MAX_ATTRIBS];
300 uint32_t enabled_mask; /* non-NULL buffers */
304 struct r600_context {
305 struct pipe_context context;
306 struct blitter_context *blitter;
307 enum radeon_family family;
308 enum chip_class chip_class;
309 boolean has_vertex_cache;
310 unsigned r6xx_num_clause_temp_gprs;
311 void *custom_dsa_flush;
312 struct r600_screen *screen;
313 struct radeon_winsys *ws;
314 struct r600_pipe_state *states[R600_PIPE_NSTATES];
315 struct r600_vertex_element *vertex_elements;
316 struct pipe_framebuffer_state framebuffer;
317 unsigned compute_cb_target_mask;
318 unsigned db_shader_control;
319 unsigned pa_sc_line_stipple;
320 unsigned pa_cl_clip_cntl;
321 /* for saving when using blitter */
322 struct pipe_stencil_ref stencil_ref;
323 struct pipe_viewport_state viewport;
324 struct pipe_clip_state clip;
325 struct r600_pipe_shader_selector *ps_shader;
326 struct r600_pipe_shader_selector *vs_shader;
327 struct r600_pipe_compute *cs_shader;
328 struct r600_pipe_rasterizer *rasterizer;
329 struct r600_pipe_state vgt;
330 struct r600_pipe_state spi;
331 struct pipe_query *current_render_cond;
332 unsigned current_render_cond_mode;
333 struct pipe_query *saved_render_cond;
334 unsigned saved_render_cond_mode;
335 /* shader information */
338 unsigned sprite_coord_enable;
340 boolean export_16bpc;
343 struct u_upload_mgr *uploader;
344 struct util_slab_mempool pool_transfers;
346 unsigned default_ps_gprs, default_vs_gprs;
348 /* States based on r600_atom. */
349 struct list_head dirty_states;
350 struct r600_command_buffer start_cs_cmd; /* invariant state mostly */
351 /** Compute specific registers initializations. The start_cs_cmd atom
352 * must be emitted before start_compute_cs_cmd. */
353 struct r600_command_buffer start_compute_cs_cmd;
354 struct r600_surface_sync_cmd surface_sync_cmd;
355 struct r600_atom r6xx_flush_and_inv_cmd;
356 struct r600_alphatest_state alphatest_state;
357 struct r600_cb_misc_state cb_misc_state;
358 struct r600_db_misc_state db_misc_state;
359 /** Vertex buffers for fetch shaders */
360 struct r600_vertexbuf_state vertex_buffer_state;
361 /** Vertex buffers for compute shaders */
362 struct r600_vertexbuf_state cs_vertex_buffer_state;
363 struct r600_constbuf_state vs_constbuf_state;
364 struct r600_constbuf_state ps_constbuf_state;
365 struct r600_textures_info vs_samplers;
366 struct r600_textures_info ps_samplers;
368 struct radeon_winsys_cs *cs;
370 struct r600_range *range;
372 struct r600_block **blocks;
373 struct list_head dirty;
374 struct list_head enable_list;
375 unsigned pm4_dirty_cdwords;
376 unsigned ctx_pm4_ndwords;
378 /* The list of active queries. Only one query of each type can be active. */
379 int num_occlusion_queries;
381 /* Manage queries in two separate groups:
382 * The timer ones and the others (streamout, occlusion).
384 * We do this because we should only suspend non-timer queries for u_blitter,
385 * and later if the non-timer queries are suspended, the context flush should
386 * only suspend and resume the timer queries. */
387 struct list_head active_timer_queries;
388 unsigned num_cs_dw_timer_queries_suspend;
389 struct list_head active_nontimer_queries;
390 unsigned num_cs_dw_nontimer_queries_suspend;
392 unsigned num_cs_dw_streamout_end;
394 unsigned backend_mask;
395 unsigned max_db; /* for OQ */
397 boolean predicate_drawing;
399 unsigned num_so_targets;
400 struct r600_so_target *so_targets[PIPE_MAX_SO_BUFFERS];
401 boolean streamout_start;
402 unsigned streamout_append_bitmask;
404 /* There is no scissor enable bit on r6xx, so we must use a workaround.
405 * These track the current scissor state. */
407 struct pipe_scissor_state scissor_state;
409 /* With rasterizer discard, there doesn't have to be a pixel shader.
410 * In that case, we bind this one: */
411 void *dummy_pixel_shader;
413 boolean dual_src_blend;
416 struct pipe_index_buffer index_buffer;
419 static INLINE void r600_emit_atom(struct r600_context *rctx, struct r600_atom *atom)
421 atom->emit(rctx, atom);
423 if (atom->head.next && atom->head.prev)
424 LIST_DELINIT(&atom->head);
427 static INLINE void r600_atom_dirty(struct r600_context *rctx, struct r600_atom *state)
430 if (state->flags & EMIT_EARLY) {
431 LIST_ADD(&state->head, &rctx->dirty_states);
433 LIST_ADDTAIL(&state->head, &rctx->dirty_states);
439 /* evergreen_state.c */
440 void evergreen_init_state_functions(struct r600_context *rctx);
441 void evergreen_init_atom_start_cs(struct r600_context *rctx);
442 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
443 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
444 void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
445 void *evergreen_create_db_flush_dsa(struct r600_context *rctx);
446 void evergreen_polygon_offset_update(struct r600_context *rctx);
447 boolean evergreen_is_format_supported(struct pipe_screen *screen,
448 enum pipe_format format,
449 enum pipe_texture_target target,
450 unsigned sample_count,
452 void evergreen_cb(struct r600_context *rctx, struct r600_pipe_state *rstate,
453 const struct pipe_framebuffer_state *state, int cb);
456 void evergreen_update_dual_export_state(struct r600_context * rctx);
459 void r600_copy_buffer(struct pipe_context *ctx, struct
460 pipe_resource *dst, unsigned dstx,
461 struct pipe_resource *src, const struct pipe_box *src_box);
462 void r600_init_blit_functions(struct r600_context *rctx);
463 void r600_blit_uncompress_depth(struct pipe_context *ctx,
464 struct r600_resource_texture *texture,
465 struct r600_resource_texture *staging,
466 unsigned first_level, unsigned last_level,
467 unsigned first_layer, unsigned last_layer);
468 void r600_flush_depth_textures(struct r600_context *rctx,
469 struct r600_samplerview_state *textures);
471 bool r600_init_resource(struct r600_screen *rscreen,
472 struct r600_resource *res,
473 unsigned size, unsigned alignment,
474 unsigned bind, unsigned usage);
475 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
476 const struct pipe_resource *templ);
479 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
483 void r600_init_query_functions(struct r600_context *rctx);
484 void r600_suspend_nontimer_queries(struct r600_context *ctx);
485 void r600_resume_nontimer_queries(struct r600_context *ctx);
486 void r600_suspend_timer_queries(struct r600_context *ctx);
487 void r600_resume_timer_queries(struct r600_context *ctx);
489 /* r600_resource.c */
490 void r600_init_context_resource_functions(struct r600_context *r600);
493 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader);
495 int r600_compute_shader_create(struct pipe_context * ctx,
496 LLVMModuleRef mod, struct r600_bytecode * bytecode);
498 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
501 void r600_set_scissor_state(struct r600_context *rctx,
502 const struct pipe_scissor_state *state);
503 void r600_update_sampler_states(struct r600_context *rctx);
504 void r600_init_state_functions(struct r600_context *rctx);
505 void r600_init_atom_start_cs(struct r600_context *rctx);
506 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
507 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
508 void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
509 void *r600_create_db_flush_dsa(struct r600_context *rctx);
510 void r600_polygon_offset_update(struct r600_context *rctx);
511 void r600_adjust_gprs(struct r600_context *rctx);
512 boolean r600_is_format_supported(struct pipe_screen *screen,
513 enum pipe_format format,
514 enum pipe_texture_target target,
515 unsigned sample_count,
517 void r600_update_dual_export_state(struct r600_context * rctx);
520 void r600_init_screen_texture_functions(struct pipe_screen *screen);
521 void r600_init_surface_functions(struct r600_context *r600);
522 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
523 const unsigned char *swizzle_view,
524 uint32_t *word4_p, uint32_t *yuv_format_p);
525 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
526 unsigned level, unsigned layer);
528 /* r600_translate.c */
529 void r600_translate_index_buffer(struct r600_context *r600,
530 struct pipe_index_buffer *ib,
533 /* r600_state_common.c */
534 void r600_init_atom(struct r600_atom *atom,
535 void (*emit)(struct r600_context *ctx, struct r600_atom *state),
536 unsigned num_dw, enum r600_atom_flags flags);
537 void r600_init_common_atoms(struct r600_context *rctx);
538 unsigned r600_get_cb_flush_flags(struct r600_context *rctx);
539 void r600_texture_barrier(struct pipe_context *ctx);
540 void r600_set_index_buffer(struct pipe_context *ctx,
541 const struct pipe_index_buffer *ib);
542 void r600_vertex_buffers_dirty(struct r600_context *rctx);
543 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
544 const struct pipe_vertex_buffer *input);
545 void r600_sampler_views_dirty(struct r600_context *rctx,
546 struct r600_samplerview_state *state);
547 void r600_set_sampler_views(struct r600_context *rctx,
548 struct r600_textures_info *dst,
550 struct pipe_sampler_view **views);
551 void *r600_create_vertex_elements(struct pipe_context *ctx,
553 const struct pipe_vertex_element *elements);
554 void r600_delete_vertex_element(struct pipe_context *ctx, void *state);
555 void r600_bind_blend_state(struct pipe_context *ctx, void *state);
556 void r600_set_blend_color(struct pipe_context *ctx,
557 const struct pipe_blend_color *state);
558 void r600_bind_dsa_state(struct pipe_context *ctx, void *state);
559 void r600_set_max_scissor(struct r600_context *rctx);
560 void r600_bind_rs_state(struct pipe_context *ctx, void *state);
561 void r600_delete_rs_state(struct pipe_context *ctx, void *state);
562 void r600_sampler_view_destroy(struct pipe_context *ctx,
563 struct pipe_sampler_view *state);
564 void r600_delete_state(struct pipe_context *ctx, void *state);
565 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
566 void *r600_create_shader_state_ps(struct pipe_context *ctx,
567 const struct pipe_shader_state *state);
568 void *r600_create_shader_state_vs(struct pipe_context *ctx,
569 const struct pipe_shader_state *state);
570 void r600_bind_ps_shader(struct pipe_context *ctx, void *state);
571 void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
572 void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
573 void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
574 void r600_constant_buffers_dirty(struct r600_context *rctx, struct r600_constbuf_state *state);
575 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
576 struct pipe_constant_buffer *cb);
577 struct pipe_stream_output_target *
578 r600_create_so_target(struct pipe_context *ctx,
579 struct pipe_resource *buffer,
580 unsigned buffer_offset,
581 unsigned buffer_size);
582 void r600_so_target_destroy(struct pipe_context *ctx,
583 struct pipe_stream_output_target *target);
584 void r600_set_so_targets(struct pipe_context *ctx,
585 unsigned num_targets,
586 struct pipe_stream_output_target **targets,
587 unsigned append_bitmask);
588 void r600_set_pipe_stencil_ref(struct pipe_context *ctx,
589 const struct pipe_stencil_ref *state);
590 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
591 uint32_t r600_translate_stencil_op(int s_op);
592 uint32_t r600_translate_fill(uint32_t func);
593 unsigned r600_tex_wrap(unsigned wrap);
594 unsigned r600_tex_filter(unsigned filter);
595 unsigned r600_tex_mipfilter(unsigned filter);
596 unsigned r600_tex_compare(unsigned compare);
599 * Helpers for building command buffers
602 #define PKT3_SET_CONFIG_REG 0x68
603 #define PKT3_SET_CONTEXT_REG 0x69
604 #define PKT3_SET_CTL_CONST 0x6F
605 #define PKT3_SET_LOOP_CONST 0x6C
607 #define R600_CONFIG_REG_OFFSET 0x08000
608 #define R600_CONTEXT_REG_OFFSET 0x28000
609 #define R600_CTL_CONST_OFFSET 0x3CFF0
610 #define R600_LOOP_CONST_OFFSET 0X0003E200
611 #define EG_LOOP_CONST_OFFSET 0x0003A200
613 #define PKT_TYPE_S(x) (((x) & 0x3) << 30)
614 #define PKT_COUNT_S(x) (((x) & 0x3FFF) << 16)
615 #define PKT3_IT_OPCODE_S(x) (((x) & 0xFF) << 8)
616 #define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
617 #define PKT3(op, count, predicate) (PKT_TYPE_S(3) | PKT_COUNT_S(count) | PKT3_IT_OPCODE_S(op) | PKT3_PREDICATE(predicate))
619 #define RADEON_CP_PACKET3_COMPUTE_MODE 0x00000002
621 /*Evergreen Compute packet3*/
622 #define PKT3C(op, count, predicate) (PKT_TYPE_S(3) | PKT3_IT_OPCODE_S(op) | PKT_COUNT_S(count) | PKT3_PREDICATE(predicate) | RADEON_CP_PACKET3_COMPUTE_MODE)
624 static INLINE void r600_store_value(struct r600_command_buffer *cb, unsigned value)
626 cb->buf[cb->atom.num_dw++] = value;
629 static INLINE void r600_store_config_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
631 assert(reg < R600_CONTEXT_REG_OFFSET);
632 assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
633 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
634 cb->buf[cb->atom.num_dw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
638 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
641 static INLINE void r600_store_context_reg_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
643 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
644 assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
645 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0) | cb->pkt_flags;
646 cb->buf[cb->atom.num_dw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
650 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
653 static INLINE void r600_store_ctl_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
655 assert(reg >= R600_CTL_CONST_OFFSET);
656 assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
657 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_CTL_CONST, num, 0) | cb->pkt_flags;
658 cb->buf[cb->atom.num_dw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
661 static INLINE void r600_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
663 assert(reg >= R600_LOOP_CONST_OFFSET);
664 assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
665 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0);
666 cb->buf[cb->atom.num_dw++] = (reg - R600_LOOP_CONST_OFFSET) >> 2;
670 * Needs cb->pkt_flags set to RADEON_CP_PACKET3_COMPUTE_MODE for compute
673 static INLINE void eg_store_loop_const_seq(struct r600_command_buffer *cb, unsigned reg, unsigned num)
675 assert(reg >= EG_LOOP_CONST_OFFSET);
676 assert(cb->atom.num_dw+2+num <= cb->max_num_dw);
677 cb->buf[cb->atom.num_dw++] = PKT3(PKT3_SET_LOOP_CONST, num, 0) | cb->pkt_flags;
678 cb->buf[cb->atom.num_dw++] = (reg - EG_LOOP_CONST_OFFSET) >> 2;
681 static INLINE void r600_store_config_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
683 r600_store_config_reg_seq(cb, reg, 1);
684 r600_store_value(cb, value);
687 static INLINE void r600_store_context_reg(struct r600_command_buffer *cb, unsigned reg, unsigned value)
689 r600_store_context_reg_seq(cb, reg, 1);
690 r600_store_value(cb, value);
693 static INLINE void r600_store_ctl_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
695 r600_store_ctl_const_seq(cb, reg, 1);
696 r600_store_value(cb, value);
699 static INLINE void r600_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
701 r600_store_loop_const_seq(cb, reg, 1);
702 r600_store_value(cb, value);
705 static INLINE void eg_store_loop_const(struct r600_command_buffer *cb, unsigned reg, unsigned value)
707 eg_store_loop_const_seq(cb, reg, 1);
708 r600_store_value(cb, value);
711 void r600_init_command_buffer(struct r600_command_buffer *cb, unsigned num_dw, enum r600_atom_flags flags);
712 void r600_release_command_buffer(struct r600_command_buffer *cb);
715 * Helpers for emitting state into a command stream directly.
718 static INLINE unsigned r600_context_bo_reloc(struct r600_context *ctx, struct r600_resource *rbo,
719 enum radeon_bo_usage usage)
722 return ctx->ws->cs_add_reloc(ctx->cs, rbo->cs_buf, usage, rbo->domains) * 4;
725 static INLINE void r600_write_value(struct radeon_winsys_cs *cs, unsigned value)
727 cs->buf[cs->cdw++] = value;
730 static INLINE void r600_write_array(struct radeon_winsys_cs *cs, unsigned num, unsigned *ptr)
732 assert(cs->cdw+num <= RADEON_MAX_CMDBUF_DWORDS);
733 memcpy(&cs->buf[cs->cdw], ptr, num * sizeof(ptr[0]));
737 static INLINE void r600_write_config_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
739 assert(reg < R600_CONTEXT_REG_OFFSET);
740 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
741 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONFIG_REG, num, 0);
742 cs->buf[cs->cdw++] = (reg - R600_CONFIG_REG_OFFSET) >> 2;
745 static INLINE void r600_write_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
747 assert(reg >= R600_CONTEXT_REG_OFFSET && reg < R600_CTL_CONST_OFFSET);
748 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
749 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CONTEXT_REG, num, 0);
750 cs->buf[cs->cdw++] = (reg - R600_CONTEXT_REG_OFFSET) >> 2;
753 static INLINE void r600_write_compute_context_reg_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
755 r600_write_context_reg_seq(cs, reg, num);
756 /* Set the compute bit on the packet header */
757 cs->buf[cs->cdw - 2] |= RADEON_CP_PACKET3_COMPUTE_MODE;
760 static INLINE void r600_write_ctl_const_seq(struct radeon_winsys_cs *cs, unsigned reg, unsigned num)
762 assert(reg >= R600_CTL_CONST_OFFSET);
763 assert(cs->cdw+2+num <= RADEON_MAX_CMDBUF_DWORDS);
764 cs->buf[cs->cdw++] = PKT3(PKT3_SET_CTL_CONST, num, 0);
765 cs->buf[cs->cdw++] = (reg - R600_CTL_CONST_OFFSET) >> 2;
768 static INLINE void r600_write_config_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
770 r600_write_config_reg_seq(cs, reg, 1);
771 r600_write_value(cs, value);
774 static INLINE void r600_write_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
776 r600_write_context_reg_seq(cs, reg, 1);
777 r600_write_value(cs, value);
780 static INLINE void r600_write_compute_context_reg(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
782 r600_write_compute_context_reg_seq(cs, reg, 1);
783 r600_write_value(cs, value);
786 static INLINE void r600_write_ctl_const(struct radeon_winsys_cs *cs, unsigned reg, unsigned value)
788 r600_write_ctl_const_seq(cs, reg, 1);
789 r600_write_value(cs, value);
795 static INLINE uint32_t S_FIXED(float value, uint32_t frac_bits)
797 return value * (1 << frac_bits);
799 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
801 static inline unsigned r600_tex_aniso_filter(unsigned filter)
803 if (filter <= 1) return 0;
804 if (filter <= 2) return 1;
805 if (filter <= 4) return 2;
806 if (filter <= 8) return 3;
810 /* 12.4 fixed-point */
811 static INLINE unsigned r600_pack_float_12p4(float x)
814 x >= 4096 ? 0xffff : x * 16;
817 static INLINE uint64_t r600_resource_va(struct pipe_screen *screen, struct pipe_resource *resource)
819 struct r600_screen *rscreen = (struct r600_screen*)screen;
820 struct r600_resource *rresource = (struct r600_resource*)resource;
822 return rscreen->ws->buffer_get_virtual_address(rresource->cs_buf);