2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include "../../winsys/radeon/drm/radeon_winsys.h"
31 #include "pipe/p_state.h"
32 #include "pipe/p_screen.h"
33 #include "pipe/p_context.h"
34 #include "util/u_math.h"
35 #include "util/u_slab.h"
36 #include "util/u_vbuf_mgr.h"
38 #include "r600_public.h"
39 #include "r600_shader.h"
40 #include "r600_resource.h"
42 #define R600_MAX_CONST_BUFFERS 1
43 #define R600_MAX_CONST_BUFFER_SIZE 4096
45 #ifdef PIPE_ARCH_BIG_ENDIAN
46 #define R600_BIG_ENDIAN 1
48 #define R600_BIG_ENDIAN 0
51 enum r600_pipe_state_id {
52 R600_PIPE_STATE_BLEND = 0,
53 R600_PIPE_STATE_BLEND_COLOR,
54 R600_PIPE_STATE_CONFIG,
55 R600_PIPE_STATE_SEAMLESS_CUBEMAP,
57 R600_PIPE_STATE_SCISSOR,
58 R600_PIPE_STATE_VIEWPORT,
59 R600_PIPE_STATE_RASTERIZER,
61 R600_PIPE_STATE_FRAMEBUFFER,
63 R600_PIPE_STATE_STENCIL_REF,
64 R600_PIPE_STATE_PS_SHADER,
65 R600_PIPE_STATE_VS_SHADER,
66 R600_PIPE_STATE_CONSTANT,
67 R600_PIPE_STATE_SAMPLER,
68 R600_PIPE_STATE_RESOURCE,
69 R600_PIPE_STATE_POLYGON_OFFSET,
70 R600_PIPE_STATE_FETCH_SHADER,
76 struct pipe_screen screen;
77 struct radeon_winsys *ws;
78 struct radeon *radeon;
80 enum chip_class chip_class;
81 struct radeon_info info;
82 struct r600_tiling_info tiling_info;
83 struct util_slab_mempool pool_buffers;
84 unsigned num_contexts;
86 /* for thread-safe write accessing to num_contexts */
87 pipe_mutex mutex_num_contexts;
90 struct r600_pipe_sampler_view {
91 struct pipe_sampler_view base;
92 struct r600_pipe_resource_state state;
95 struct r600_pipe_rasterizer {
96 struct r600_pipe_state rstate;
97 boolean clamp_vertex_color;
98 boolean clamp_fragment_color;
100 unsigned sprite_coord_enable;
105 struct r600_pipe_blend {
106 struct r600_pipe_state rstate;
107 unsigned cb_target_mask;
110 struct r600_pipe_dsa {
111 struct r600_pipe_state rstate;
115 struct r600_vertex_element
118 struct pipe_vertex_element elements[PIPE_MAX_ATTRIBS];
119 struct u_vbuf_elements *vmgr_elements;
120 struct r600_resource *fetch_shader;
122 struct r600_pipe_state rstate;
123 /* if offset is to big for fetch instructio we need to alterate
124 * offset of vertex buffer, record here the offset need to add
126 unsigned vbuffer_need_offset;
127 unsigned vbuffer_offset[PIPE_MAX_ATTRIBS];
130 struct r600_pipe_shader {
131 struct r600_shader shader;
132 struct r600_pipe_state rstate;
133 struct r600_resource *bo;
134 struct r600_resource *bo_fetch;
135 struct r600_vertex_element vertex_elements;
136 struct tgsi_token *tokens;
139 struct r600_pipe_sampler_state {
140 struct r600_pipe_state rstate;
141 boolean seamless_cube_map;
144 /* needed for blitter save */
145 #define NUM_TEX_UNITS 16
147 struct r600_textures_info {
148 struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
149 struct r600_pipe_sampler_state *samplers[NUM_TEX_UNITS];
153 bool is_array_sampler[NUM_TEX_UNITS];
157 struct pipe_reference reference;
158 struct r600_pipe_context *ctx;
159 unsigned index; /* in the shared bo */
160 struct list_head head;
163 #define FENCE_BLOCK_SIZE 16
165 struct r600_fence_block {
166 struct r600_fence fences[FENCE_BLOCK_SIZE];
167 struct list_head head;
170 struct r600_pipe_fences {
171 struct r600_resource *bo;
174 /* linked list of preallocated blocks */
175 struct list_head blocks;
176 /* linked list of freed fences */
177 struct list_head pool;
180 #define R600_CONSTANT_ARRAY_SIZE 256
181 #define R600_RESOURCE_ARRAY_SIZE 160
183 struct r600_pipe_context {
184 struct pipe_context context;
185 struct blitter_context *blitter;
186 enum radeon_family family;
187 enum chip_class chip_class;
188 void *custom_dsa_flush;
189 struct r600_screen *screen;
190 struct radeon_winsys *ws;
191 struct radeon *radeon;
192 struct r600_pipe_state *states[R600_PIPE_NSTATES];
193 struct r600_context ctx;
194 struct r600_vertex_element *vertex_elements;
195 struct r600_pipe_resource_state fs_resource[PIPE_MAX_ATTRIBS];
196 struct pipe_framebuffer_state framebuffer;
197 struct pipe_index_buffer index_buffer;
198 unsigned cb_target_mask;
199 /* for saving when using blitter */
200 struct pipe_stencil_ref stencil_ref;
201 struct pipe_viewport_state viewport;
202 struct pipe_clip_state clip;
203 struct r600_pipe_state config;
204 struct r600_pipe_shader *ps_shader;
205 struct r600_pipe_shader *vs_shader;
206 struct r600_pipe_state vs_const_buffer;
207 struct r600_pipe_resource_state vs_const_buffer_resource[R600_MAX_CONST_BUFFERS];
208 struct r600_pipe_state ps_const_buffer;
209 struct r600_pipe_resource_state ps_const_buffer_resource[R600_MAX_CONST_BUFFERS];
210 struct r600_pipe_rasterizer *rasterizer;
211 struct r600_pipe_state vgt;
212 struct r600_pipe_state spi;
213 struct pipe_query *current_render_cond;
214 unsigned current_render_cond_mode;
215 struct pipe_query *saved_render_cond;
216 unsigned saved_render_cond_mode;
217 /* shader information */
218 boolean clamp_vertex_color;
219 boolean clamp_fragment_color;
221 unsigned sprite_coord_enable;
223 boolean export_16bpc;
225 boolean alpha_ref_dirty;
227 struct r600_textures_info vs_samplers;
228 struct r600_textures_info ps_samplers;
230 struct r600_pipe_fences fences;
232 struct u_vbuf_mgr *vbuf_mgr;
233 struct util_slab_mempool pool_transfers;
235 boolean have_depth_texture, have_depth_fb;
237 unsigned default_ps_gprs, default_vs_gprs;
241 struct pipe_draw_info info;
242 struct pipe_context *ctx;
244 unsigned index_buffer_offset;
245 struct pipe_resource *index_buffer;
248 /* evergreen_state.c */
249 void evergreen_init_state_functions(struct r600_pipe_context *rctx);
250 void evergreen_init_config(struct r600_pipe_context *rctx);
251 void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
252 void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
253 void evergreen_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
254 void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx);
255 void evergreen_polygon_offset_update(struct r600_pipe_context *rctx);
256 void evergreen_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
257 struct r600_pipe_resource_state *rstate);
258 void evergreen_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
259 struct r600_resource *rbuffer,
260 unsigned offset, unsigned stride,
261 enum radeon_bo_usage usage);
262 boolean evergreen_is_format_supported(struct pipe_screen *screen,
263 enum pipe_format format,
264 enum pipe_texture_target target,
265 unsigned sample_count,
269 void r600_init_blit_functions(struct r600_pipe_context *rctx);
270 void r600_blit_uncompress_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
271 void r600_blit_push_depth(struct pipe_context *ctx, struct r600_resource_texture *texture);
272 void r600_flush_depth_textures(struct r600_pipe_context *rctx);
275 bool r600_init_resource(struct r600_screen *rscreen,
276 struct r600_resource *res,
277 unsigned size, unsigned alignment,
278 unsigned bind, unsigned usage);
279 struct pipe_resource *r600_buffer_create(struct pipe_screen *screen,
280 const struct pipe_resource *templ);
281 struct pipe_resource *r600_user_buffer_create(struct pipe_screen *screen,
282 void *ptr, unsigned bytes,
284 void r600_upload_index_buffer(struct r600_pipe_context *rctx, struct r600_drawl *draw);
288 void r600_flush(struct pipe_context *ctx, struct pipe_fence_handle **fence,
292 void r600_init_query_functions(struct r600_pipe_context *rctx);
294 /* r600_resource.c */
295 void r600_init_context_resource_functions(struct r600_pipe_context *r600);
298 int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader *shader);
299 void r600_pipe_shader_destroy(struct pipe_context *ctx, struct r600_pipe_shader *shader);
300 int r600_find_vs_semantic_index(struct r600_shader *vs,
301 struct r600_shader *ps, int id);
304 void r600_update_sampler_states(struct r600_pipe_context *rctx);
305 void r600_init_state_functions(struct r600_pipe_context *rctx);
306 void r600_init_config(struct r600_pipe_context *rctx);
307 void r600_pipe_shader_ps(struct pipe_context *ctx, struct r600_pipe_shader *shader);
308 void r600_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader *shader);
309 void r600_fetch_shader(struct pipe_context *ctx, struct r600_vertex_element *ve);
310 void *r600_create_db_flush_dsa(struct r600_pipe_context *rctx);
311 void r600_polygon_offset_update(struct r600_pipe_context *rctx);
312 void r600_pipe_init_buffer_resource(struct r600_pipe_context *rctx,
313 struct r600_pipe_resource_state *rstate);
314 void r600_pipe_mod_buffer_resource(struct r600_pipe_resource_state *rstate,
315 struct r600_resource *rbuffer,
316 unsigned offset, unsigned stride,
317 enum radeon_bo_usage usage);
318 void r600_adjust_gprs(struct r600_pipe_context *rctx);
319 boolean r600_is_format_supported(struct pipe_screen *screen,
320 enum pipe_format format,
321 enum pipe_texture_target target,
322 unsigned sample_count,
326 void r600_init_screen_texture_functions(struct pipe_screen *screen);
327 void r600_init_surface_functions(struct r600_pipe_context *r600);
328 uint32_t r600_translate_texformat(struct pipe_screen *screen, enum pipe_format format,
329 const unsigned char *swizzle_view,
330 uint32_t *word4_p, uint32_t *yuv_format_p);
331 unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
332 unsigned level, unsigned layer);
334 /* r600_translate.c */
335 void r600_translate_index_buffer(struct r600_pipe_context *r600,
336 struct pipe_resource **index_buffer,
337 unsigned *index_size,
338 unsigned *start, unsigned count);
340 /* r600_state_common.c */
341 void r600_set_index_buffer(struct pipe_context *ctx,
342 const struct pipe_index_buffer *ib);
343 void r600_set_vertex_buffers(struct pipe_context *ctx, unsigned count,
344 const struct pipe_vertex_buffer *buffers);
345 void *r600_create_vertex_elements(struct pipe_context *ctx,
347 const struct pipe_vertex_element *elements);
348 void r600_delete_vertex_element(struct pipe_context *ctx, void *state);
349 void r600_bind_blend_state(struct pipe_context *ctx, void *state);
350 void r600_bind_dsa_state(struct pipe_context *ctx, void *state);
351 void r600_bind_rs_state(struct pipe_context *ctx, void *state);
352 void r600_delete_rs_state(struct pipe_context *ctx, void *state);
353 void r600_sampler_view_destroy(struct pipe_context *ctx,
354 struct pipe_sampler_view *state);
355 void r600_delete_state(struct pipe_context *ctx, void *state);
356 void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
357 void *r600_create_shader_state(struct pipe_context *ctx,
358 const struct pipe_shader_state *state);
359 void r600_bind_ps_shader(struct pipe_context *ctx, void *state);
360 void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
361 void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
362 void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
363 void r600_set_constant_buffer(struct pipe_context *ctx, uint shader, uint index,
364 struct pipe_resource *buffer);
365 void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info);
370 static INLINE u32 S_FIXED(float value, u32 frac_bits)
372 return value * (1 << frac_bits);
374 #define ALIGN_DIVUP(x, y) (((x) + (y) - 1) / (y))
376 static inline unsigned r600_tex_aniso_filter(unsigned filter)
378 if (filter <= 1) return 0;
379 if (filter <= 2) return 1;
380 if (filter <= 4) return 2;
381 if (filter <= 8) return 3;